1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "OctoSPI IO Manager"]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Octospim {
9 ptr: *mut u8,
10}
11unsafe impl Send for Octospim {}
12unsafe impl Sync for Octospim {}
13impl Octospim {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "control register"]
23 #[inline(always)]
24 pub const fn cr(self) -> crate::common::Reg<regs::Cr, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "OctoSPI IO Manager Port 1 Configuration Register"]
28 #[inline(always)]
29 pub const fn p1cr(self) -> crate::common::Reg<regs::P1cr, crate::common::RW> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
31 }
32 #[doc = "OctoSPI IO Manager Port 2 Configuration Register"]
33 #[inline(always)]
34 pub const fn p2cr(self) -> crate::common::Reg<regs::P2cr, crate::common::RW> {
35 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
36 }
37}
38pub mod regs {
39 #[doc = "control register"]
40 #[repr(transparent)]
41 #[derive(Copy, Clone, Eq, PartialEq)]
42 pub struct Cr(pub u32);
43 impl Cr {
44 #[doc = "Multiplexed mode enable"]
45 #[inline(always)]
46 pub const fn muxen(&self) -> bool {
47 let val = (self.0 >> 0usize) & 0x01;
48 val != 0
49 }
50 #[doc = "Multiplexed mode enable"]
51 #[inline(always)]
52 pub fn set_muxen(&mut self, val: bool) {
53 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
54 }
55 #[doc = "REQ to ACK time"]
56 #[inline(always)]
57 pub const fn req2ack_time(&self) -> u8 {
58 let val = (self.0 >> 16usize) & 0xff;
59 val as u8
60 }
61 #[doc = "REQ to ACK time"]
62 #[inline(always)]
63 pub fn set_req2ack_time(&mut self, val: u8) {
64 self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
65 }
66 }
67 impl Default for Cr {
68 #[inline(always)]
69 fn default() -> Cr {
70 Cr(0)
71 }
72 }
73 impl core::fmt::Debug for Cr {
74 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
75 f.debug_struct("Cr")
76 .field("muxen", &self.muxen())
77 .field("req2ack_time", &self.req2ack_time())
78 .finish()
79 }
80 }
81 #[cfg(feature = "defmt")]
82 impl defmt::Format for Cr {
83 fn format(&self, f: defmt::Formatter) {
84 #[derive(defmt :: Format)]
85 struct Cr {
86 muxen: bool,
87 req2ack_time: u8,
88 }
89 let proxy = Cr {
90 muxen: self.muxen(),
91 req2ack_time: self.req2ack_time(),
92 };
93 defmt::write!(f, "{}", proxy)
94 }
95 }
96 #[doc = "OctoSPI IO Manager Port 1 Configuration Register"]
97 #[repr(transparent)]
98 #[derive(Copy, Clone, Eq, PartialEq)]
99 pub struct P1cr(pub u32);
100 impl P1cr {
101 #[doc = "CLK/CLK Enable for Port"]
102 #[inline(always)]
103 pub const fn clken(&self) -> bool {
104 let val = (self.0 >> 0usize) & 0x01;
105 val != 0
106 }
107 #[doc = "CLK/CLK Enable for Port"]
108 #[inline(always)]
109 pub fn set_clken(&mut self, val: bool) {
110 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
111 }
112 #[doc = "CLK/CLK Source for Port"]
113 #[inline(always)]
114 pub const fn clksrc(&self) -> bool {
115 let val = (self.0 >> 1usize) & 0x01;
116 val != 0
117 }
118 #[doc = "CLK/CLK Source for Port"]
119 #[inline(always)]
120 pub fn set_clksrc(&mut self, val: bool) {
121 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
122 }
123 #[doc = "DQS Enable for Port"]
124 #[inline(always)]
125 pub const fn dqsen(&self) -> bool {
126 let val = (self.0 >> 4usize) & 0x01;
127 val != 0
128 }
129 #[doc = "DQS Enable for Port"]
130 #[inline(always)]
131 pub fn set_dqsen(&mut self, val: bool) {
132 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
133 }
134 #[doc = "DQS Source for Port"]
135 #[inline(always)]
136 pub const fn dqssrc(&self) -> bool {
137 let val = (self.0 >> 5usize) & 0x01;
138 val != 0
139 }
140 #[doc = "DQS Source for Port"]
141 #[inline(always)]
142 pub fn set_dqssrc(&mut self, val: bool) {
143 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
144 }
145 #[doc = "CS Enable for Port"]
146 #[inline(always)]
147 pub const fn ncsen(&self) -> bool {
148 let val = (self.0 >> 8usize) & 0x01;
149 val != 0
150 }
151 #[doc = "CS Enable for Port"]
152 #[inline(always)]
153 pub fn set_ncsen(&mut self, val: bool) {
154 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
155 }
156 #[doc = "CS Source for Port"]
157 #[inline(always)]
158 pub const fn ncssrc(&self) -> bool {
159 let val = (self.0 >> 9usize) & 0x01;
160 val != 0
161 }
162 #[doc = "CS Source for Port"]
163 #[inline(always)]
164 pub fn set_ncssrc(&mut self, val: bool) {
165 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
166 }
167 #[doc = "Enable for Port"]
168 #[inline(always)]
169 pub const fn iolen(&self) -> bool {
170 let val = (self.0 >> 16usize) & 0x01;
171 val != 0
172 }
173 #[doc = "Enable for Port"]
174 #[inline(always)]
175 pub fn set_iolen(&mut self, val: bool) {
176 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
177 }
178 #[doc = "Source for Port"]
179 #[inline(always)]
180 pub const fn iolsrc(&self) -> u8 {
181 let val = (self.0 >> 17usize) & 0x03;
182 val as u8
183 }
184 #[doc = "Source for Port"]
185 #[inline(always)]
186 pub fn set_iolsrc(&mut self, val: u8) {
187 self.0 = (self.0 & !(0x03 << 17usize)) | (((val as u32) & 0x03) << 17usize);
188 }
189 #[doc = "Enable for Port n"]
190 #[inline(always)]
191 pub const fn iohen(&self) -> bool {
192 let val = (self.0 >> 24usize) & 0x01;
193 val != 0
194 }
195 #[doc = "Enable for Port n"]
196 #[inline(always)]
197 pub fn set_iohen(&mut self, val: bool) {
198 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
199 }
200 #[doc = "Source for Port"]
201 #[inline(always)]
202 pub const fn iohsrc(&self) -> u8 {
203 let val = (self.0 >> 25usize) & 0x03;
204 val as u8
205 }
206 #[doc = "Source for Port"]
207 #[inline(always)]
208 pub fn set_iohsrc(&mut self, val: u8) {
209 self.0 = (self.0 & !(0x03 << 25usize)) | (((val as u32) & 0x03) << 25usize);
210 }
211 }
212 impl Default for P1cr {
213 #[inline(always)]
214 fn default() -> P1cr {
215 P1cr(0)
216 }
217 }
218 impl core::fmt::Debug for P1cr {
219 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
220 f.debug_struct("P1cr")
221 .field("clken", &self.clken())
222 .field("clksrc", &self.clksrc())
223 .field("dqsen", &self.dqsen())
224 .field("dqssrc", &self.dqssrc())
225 .field("ncsen", &self.ncsen())
226 .field("ncssrc", &self.ncssrc())
227 .field("iolen", &self.iolen())
228 .field("iolsrc", &self.iolsrc())
229 .field("iohen", &self.iohen())
230 .field("iohsrc", &self.iohsrc())
231 .finish()
232 }
233 }
234 #[cfg(feature = "defmt")]
235 impl defmt::Format for P1cr {
236 fn format(&self, f: defmt::Formatter) {
237 #[derive(defmt :: Format)]
238 struct P1cr {
239 clken: bool,
240 clksrc: bool,
241 dqsen: bool,
242 dqssrc: bool,
243 ncsen: bool,
244 ncssrc: bool,
245 iolen: bool,
246 iolsrc: u8,
247 iohen: bool,
248 iohsrc: u8,
249 }
250 let proxy = P1cr {
251 clken: self.clken(),
252 clksrc: self.clksrc(),
253 dqsen: self.dqsen(),
254 dqssrc: self.dqssrc(),
255 ncsen: self.ncsen(),
256 ncssrc: self.ncssrc(),
257 iolen: self.iolen(),
258 iolsrc: self.iolsrc(),
259 iohen: self.iohen(),
260 iohsrc: self.iohsrc(),
261 };
262 defmt::write!(f, "{}", proxy)
263 }
264 }
265 #[doc = "OctoSPI IO Manager Port 2 Configuration Register"]
266 #[repr(transparent)]
267 #[derive(Copy, Clone, Eq, PartialEq)]
268 pub struct P2cr(pub u32);
269 impl P2cr {
270 #[doc = "CLK/CLK Enable for Port"]
271 #[inline(always)]
272 pub const fn clken(&self) -> bool {
273 let val = (self.0 >> 0usize) & 0x01;
274 val != 0
275 }
276 #[doc = "CLK/CLK Enable for Port"]
277 #[inline(always)]
278 pub fn set_clken(&mut self, val: bool) {
279 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
280 }
281 #[doc = "CLK/CLK Source for Port"]
282 #[inline(always)]
283 pub const fn clksrc(&self) -> bool {
284 let val = (self.0 >> 1usize) & 0x01;
285 val != 0
286 }
287 #[doc = "CLK/CLK Source for Port"]
288 #[inline(always)]
289 pub fn set_clksrc(&mut self, val: bool) {
290 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
291 }
292 #[doc = "DQS Enable for Port"]
293 #[inline(always)]
294 pub const fn dqsen(&self) -> bool {
295 let val = (self.0 >> 4usize) & 0x01;
296 val != 0
297 }
298 #[doc = "DQS Enable for Port"]
299 #[inline(always)]
300 pub fn set_dqsen(&mut self, val: bool) {
301 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
302 }
303 #[doc = "DQS Source for Port"]
304 #[inline(always)]
305 pub const fn dqssrc(&self) -> bool {
306 let val = (self.0 >> 5usize) & 0x01;
307 val != 0
308 }
309 #[doc = "DQS Source for Port"]
310 #[inline(always)]
311 pub fn set_dqssrc(&mut self, val: bool) {
312 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
313 }
314 #[doc = "CS Enable for Port"]
315 #[inline(always)]
316 pub const fn ncsen(&self) -> bool {
317 let val = (self.0 >> 8usize) & 0x01;
318 val != 0
319 }
320 #[doc = "CS Enable for Port"]
321 #[inline(always)]
322 pub fn set_ncsen(&mut self, val: bool) {
323 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
324 }
325 #[doc = "CS Source for Port"]
326 #[inline(always)]
327 pub const fn ncssrc(&self) -> bool {
328 let val = (self.0 >> 9usize) & 0x01;
329 val != 0
330 }
331 #[doc = "CS Source for Port"]
332 #[inline(always)]
333 pub fn set_ncssrc(&mut self, val: bool) {
334 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
335 }
336 #[doc = "Enable for Port"]
337 #[inline(always)]
338 pub const fn iolen(&self) -> bool {
339 let val = (self.0 >> 16usize) & 0x01;
340 val != 0
341 }
342 #[doc = "Enable for Port"]
343 #[inline(always)]
344 pub fn set_iolen(&mut self, val: bool) {
345 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
346 }
347 #[doc = "Source for Port"]
348 #[inline(always)]
349 pub const fn iolsrc(&self) -> u8 {
350 let val = (self.0 >> 17usize) & 0x03;
351 val as u8
352 }
353 #[doc = "Source for Port"]
354 #[inline(always)]
355 pub fn set_iolsrc(&mut self, val: u8) {
356 self.0 = (self.0 & !(0x03 << 17usize)) | (((val as u32) & 0x03) << 17usize);
357 }
358 #[doc = "Enable for Port n"]
359 #[inline(always)]
360 pub const fn iohen(&self) -> bool {
361 let val = (self.0 >> 24usize) & 0x01;
362 val != 0
363 }
364 #[doc = "Enable for Port n"]
365 #[inline(always)]
366 pub fn set_iohen(&mut self, val: bool) {
367 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
368 }
369 #[doc = "Source for Port"]
370 #[inline(always)]
371 pub const fn iohsrc(&self) -> u8 {
372 let val = (self.0 >> 25usize) & 0x03;
373 val as u8
374 }
375 #[doc = "Source for Port"]
376 #[inline(always)]
377 pub fn set_iohsrc(&mut self, val: u8) {
378 self.0 = (self.0 & !(0x03 << 25usize)) | (((val as u32) & 0x03) << 25usize);
379 }
380 }
381 impl Default for P2cr {
382 #[inline(always)]
383 fn default() -> P2cr {
384 P2cr(0)
385 }
386 }
387 impl core::fmt::Debug for P2cr {
388 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
389 f.debug_struct("P2cr")
390 .field("clken", &self.clken())
391 .field("clksrc", &self.clksrc())
392 .field("dqsen", &self.dqsen())
393 .field("dqssrc", &self.dqssrc())
394 .field("ncsen", &self.ncsen())
395 .field("ncssrc", &self.ncssrc())
396 .field("iolen", &self.iolen())
397 .field("iolsrc", &self.iolsrc())
398 .field("iohen", &self.iohen())
399 .field("iohsrc", &self.iohsrc())
400 .finish()
401 }
402 }
403 #[cfg(feature = "defmt")]
404 impl defmt::Format for P2cr {
405 fn format(&self, f: defmt::Formatter) {
406 #[derive(defmt :: Format)]
407 struct P2cr {
408 clken: bool,
409 clksrc: bool,
410 dqsen: bool,
411 dqssrc: bool,
412 ncsen: bool,
413 ncssrc: bool,
414 iolen: bool,
415 iolsrc: u8,
416 iohen: bool,
417 iohsrc: u8,
418 }
419 let proxy = P2cr {
420 clken: self.clken(),
421 clksrc: self.clksrc(),
422 dqsen: self.dqsen(),
423 dqssrc: self.dqssrc(),
424 ncsen: self.ncsen(),
425 ncssrc: self.ncssrc(),
426 iolen: self.iolen(),
427 iolsrc: self.iolsrc(),
428 iohen: self.iohen(),
429 iohsrc: self.iohsrc(),
430 };
431 defmt::write!(f, "{}", proxy)
432 }
433 }
434}
435