1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "Public key accelerator."]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Pka {
9 ptr: *mut u8,
10}
11unsafe impl Send for Pka {}
12unsafe impl Sync for Pka {}
13impl Pka {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "PKA control register."]
23 #[inline(always)]
24 pub const fn cr(self) -> crate::common::Reg<regs::Cr, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "PKA status register."]
28 #[inline(always)]
29 pub const fn sr(self) -> crate::common::Reg<regs::Sr, crate::common::RW> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
31 }
32 #[doc = "PKA clear flag register."]
33 #[inline(always)]
34 pub const fn clrfr(self) -> crate::common::Reg<regs::Clrfr, crate::common::RW> {
35 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
36 }
37 #[doc = "PKA internal memeory."]
38 #[inline(always)]
39 pub const fn ram(self, n: usize) -> crate::common::Reg<u32, crate::common::RW> {
40 assert!(n < 1334usize);
41 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0400usize + n * 4usize) as _) }
42 }
43}
44pub mod regs {
45 #[doc = "PKA clear flag register."]
46 #[repr(transparent)]
47 #[derive(Copy, Clone, Eq, PartialEq)]
48 pub struct Clrfr(pub u32);
49 impl Clrfr {
50 #[doc = "Clear PKA End of Operation flag."]
51 #[inline(always)]
52 pub const fn procendfc(&self) -> bool {
53 let val = (self.0 >> 17usize) & 0x01;
54 val != 0
55 }
56 #[doc = "Clear PKA End of Operation flag."]
57 #[inline(always)]
58 pub fn set_procendfc(&mut self, val: bool) {
59 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
60 }
61 #[doc = "Clear PKA RAM error flag."]
62 #[inline(always)]
63 pub const fn ramerrfc(&self) -> bool {
64 let val = (self.0 >> 19usize) & 0x01;
65 val != 0
66 }
67 #[doc = "Clear PKA RAM error flag."]
68 #[inline(always)]
69 pub fn set_ramerrfc(&mut self, val: bool) {
70 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
71 }
72 #[doc = "Clear address error flag."]
73 #[inline(always)]
74 pub const fn addrerrfc(&self) -> bool {
75 let val = (self.0 >> 20usize) & 0x01;
76 val != 0
77 }
78 #[doc = "Clear address error flag."]
79 #[inline(always)]
80 pub fn set_addrerrfc(&mut self, val: bool) {
81 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
82 }
83 #[doc = "Clear operation error flag."]
84 #[inline(always)]
85 pub const fn operrfc(&self) -> bool {
86 let val = (self.0 >> 21usize) & 0x01;
87 val != 0
88 }
89 #[doc = "Clear operation error flag."]
90 #[inline(always)]
91 pub fn set_operrfc(&mut self, val: bool) {
92 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
93 }
94 }
95 impl Default for Clrfr {
96 #[inline(always)]
97 fn default() -> Clrfr {
98 Clrfr(0)
99 }
100 }
101 impl core::fmt::Debug for Clrfr {
102 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
103 f.debug_struct("Clrfr")
104 .field("procendfc", &self.procendfc())
105 .field("ramerrfc", &self.ramerrfc())
106 .field("addrerrfc", &self.addrerrfc())
107 .field("operrfc", &self.operrfc())
108 .finish()
109 }
110 }
111 #[cfg(feature = "defmt")]
112 impl defmt::Format for Clrfr {
113 fn format(&self, f: defmt::Formatter) {
114 #[derive(defmt :: Format)]
115 struct Clrfr {
116 procendfc: bool,
117 ramerrfc: bool,
118 addrerrfc: bool,
119 operrfc: bool,
120 }
121 let proxy = Clrfr {
122 procendfc: self.procendfc(),
123 ramerrfc: self.ramerrfc(),
124 addrerrfc: self.addrerrfc(),
125 operrfc: self.operrfc(),
126 };
127 defmt::write!(f, "{}", proxy)
128 }
129 }
130 #[doc = "PKA control register."]
131 #[repr(transparent)]
132 #[derive(Copy, Clone, Eq, PartialEq)]
133 pub struct Cr(pub u32);
134 impl Cr {
135 #[doc = "PKA enable. When an illegal operation is selected while EN=1 OPERRF bit is set in PKA_SR. See PKA_CR.MODE bitfield for details. When EN=0 PKA RAM can still be accessed by the application."]
136 #[inline(always)]
137 pub const fn en(&self) -> bool {
138 let val = (self.0 >> 0usize) & 0x01;
139 val != 0
140 }
141 #[doc = "PKA enable. When an illegal operation is selected while EN=1 OPERRF bit is set in PKA_SR. See PKA_CR.MODE bitfield for details. When EN=0 PKA RAM can still be accessed by the application."]
142 #[inline(always)]
143 pub fn set_en(&mut self, val: bool) {
144 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
145 }
146 #[doc = "start the operation Writing 1 to this bit starts the operation which is selected by MODE\\[5:0\\], using the operands and data already written to the PKA RAM. This bit is always read as 0. When an illegal operation is selected while START bit is set no operation is started, and OPERRF bit is set in PKA_SR. START is ignored if PKA is busy."]
147 #[inline(always)]
148 pub const fn start(&self) -> bool {
149 let val = (self.0 >> 1usize) & 0x01;
150 val != 0
151 }
152 #[doc = "start the operation Writing 1 to this bit starts the operation which is selected by MODE\\[5:0\\], using the operands and data already written to the PKA RAM. This bit is always read as 0. When an illegal operation is selected while START bit is set no operation is started, and OPERRF bit is set in PKA_SR. START is ignored if PKA is busy."]
153 #[inline(always)]
154 pub fn set_start(&mut self, val: bool) {
155 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
156 }
157 #[doc = "PKA operation code When an operation not listed here is written by the application with EN bit set, OPERRF bit is set in PKA_SR register, and the write to MODE bitfield is ignored. When PKA is configured in limited mode (LMF = 1 in PKA_SR), writing a MODE different from 0x26 with EN bit to 1 triggers OPERRF bit to be set and write to MODE bit is ignored."]
158 #[inline(always)]
159 pub const fn mode(&self) -> u8 {
160 let val = (self.0 >> 8usize) & 0x3f;
161 val as u8
162 }
163 #[doc = "PKA operation code When an operation not listed here is written by the application with EN bit set, OPERRF bit is set in PKA_SR register, and the write to MODE bitfield is ignored. When PKA is configured in limited mode (LMF = 1 in PKA_SR), writing a MODE different from 0x26 with EN bit to 1 triggers OPERRF bit to be set and write to MODE bit is ignored."]
164 #[inline(always)]
165 pub fn set_mode(&mut self, val: u8) {
166 self.0 = (self.0 & !(0x3f << 8usize)) | (((val as u32) & 0x3f) << 8usize);
167 }
168 #[doc = "End of operation interrupt enable."]
169 #[inline(always)]
170 pub const fn procendie(&self) -> bool {
171 let val = (self.0 >> 17usize) & 0x01;
172 val != 0
173 }
174 #[doc = "End of operation interrupt enable."]
175 #[inline(always)]
176 pub fn set_procendie(&mut self, val: bool) {
177 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
178 }
179 #[doc = "RAM error interrupt enable."]
180 #[inline(always)]
181 pub const fn ramerrie(&self) -> bool {
182 let val = (self.0 >> 19usize) & 0x01;
183 val != 0
184 }
185 #[doc = "RAM error interrupt enable."]
186 #[inline(always)]
187 pub fn set_ramerrie(&mut self, val: bool) {
188 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
189 }
190 #[doc = "Address error interrupt enable."]
191 #[inline(always)]
192 pub const fn addrerrie(&self) -> bool {
193 let val = (self.0 >> 20usize) & 0x01;
194 val != 0
195 }
196 #[doc = "Address error interrupt enable."]
197 #[inline(always)]
198 pub fn set_addrerrie(&mut self, val: bool) {
199 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
200 }
201 #[doc = "Operation error interrupt enable."]
202 #[inline(always)]
203 pub const fn operrie(&self) -> bool {
204 let val = (self.0 >> 21usize) & 0x01;
205 val != 0
206 }
207 #[doc = "Operation error interrupt enable."]
208 #[inline(always)]
209 pub fn set_operrie(&mut self, val: bool) {
210 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
211 }
212 }
213 impl Default for Cr {
214 #[inline(always)]
215 fn default() -> Cr {
216 Cr(0)
217 }
218 }
219 impl core::fmt::Debug for Cr {
220 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
221 f.debug_struct("Cr")
222 .field("en", &self.en())
223 .field("start", &self.start())
224 .field("mode", &self.mode())
225 .field("procendie", &self.procendie())
226 .field("ramerrie", &self.ramerrie())
227 .field("addrerrie", &self.addrerrie())
228 .field("operrie", &self.operrie())
229 .finish()
230 }
231 }
232 #[cfg(feature = "defmt")]
233 impl defmt::Format for Cr {
234 fn format(&self, f: defmt::Formatter) {
235 #[derive(defmt :: Format)]
236 struct Cr {
237 en: bool,
238 start: bool,
239 mode: u8,
240 procendie: bool,
241 ramerrie: bool,
242 addrerrie: bool,
243 operrie: bool,
244 }
245 let proxy = Cr {
246 en: self.en(),
247 start: self.start(),
248 mode: self.mode(),
249 procendie: self.procendie(),
250 ramerrie: self.ramerrie(),
251 addrerrie: self.addrerrie(),
252 operrie: self.operrie(),
253 };
254 defmt::write!(f, "{}", proxy)
255 }
256 }
257 #[doc = "PKA status register."]
258 #[repr(transparent)]
259 #[derive(Copy, Clone, Eq, PartialEq)]
260 pub struct Sr(pub u32);
261 impl Sr {
262 #[doc = "PKA initialization OK This bit is asserted when PKA initialization is complete. When RNG is not able to output proper random numbers INITOK stays at 0."]
263 #[inline(always)]
264 pub const fn initok(&self) -> bool {
265 let val = (self.0 >> 0usize) & 0x01;
266 val != 0
267 }
268 #[doc = "PKA initialization OK This bit is asserted when PKA initialization is complete. When RNG is not able to output proper random numbers INITOK stays at 0."]
269 #[inline(always)]
270 pub fn set_initok(&mut self, val: bool) {
271 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
272 }
273 #[doc = "PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0)."]
274 #[inline(always)]
275 pub const fn busy(&self) -> bool {
276 let val = (self.0 >> 16usize) & 0x01;
277 val != 0
278 }
279 #[doc = "PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0)."]
280 #[inline(always)]
281 pub fn set_busy(&mut self, val: bool) {
282 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
283 }
284 #[doc = "PKA End of Operation flag."]
285 #[inline(always)]
286 pub const fn procendf(&self) -> bool {
287 let val = (self.0 >> 17usize) & 0x01;
288 val != 0
289 }
290 #[doc = "PKA End of Operation flag."]
291 #[inline(always)]
292 pub fn set_procendf(&mut self, val: bool) {
293 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
294 }
295 #[doc = "PKA RAM error flag This bit is cleared using RAMERRFC bit in PKA_CLRFR."]
296 #[inline(always)]
297 pub const fn ramerrf(&self) -> bool {
298 let val = (self.0 >> 19usize) & 0x01;
299 val != 0
300 }
301 #[doc = "PKA RAM error flag This bit is cleared using RAMERRFC bit in PKA_CLRFR."]
302 #[inline(always)]
303 pub fn set_ramerrf(&mut self, val: bool) {
304 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
305 }
306 #[doc = "Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR."]
307 #[inline(always)]
308 pub const fn addrerrf(&self) -> bool {
309 let val = (self.0 >> 20usize) & 0x01;
310 val != 0
311 }
312 #[doc = "Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR."]
313 #[inline(always)]
314 pub fn set_addrerrf(&mut self, val: bool) {
315 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
316 }
317 #[doc = "Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR."]
318 #[inline(always)]
319 pub const fn operrf(&self) -> bool {
320 let val = (self.0 >> 21usize) & 0x01;
321 val != 0
322 }
323 #[doc = "Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR."]
324 #[inline(always)]
325 pub fn set_operrf(&mut self, val: bool) {
326 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
327 }
328 }
329 impl Default for Sr {
330 #[inline(always)]
331 fn default() -> Sr {
332 Sr(0)
333 }
334 }
335 impl core::fmt::Debug for Sr {
336 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
337 f.debug_struct("Sr")
338 .field("initok", &self.initok())
339 .field("busy", &self.busy())
340 .field("procendf", &self.procendf())
341 .field("ramerrf", &self.ramerrf())
342 .field("addrerrf", &self.addrerrf())
343 .field("operrf", &self.operrf())
344 .finish()
345 }
346 }
347 #[cfg(feature = "defmt")]
348 impl defmt::Format for Sr {
349 fn format(&self, f: defmt::Formatter) {
350 #[derive(defmt :: Format)]
351 struct Sr {
352 initok: bool,
353 busy: bool,
354 procendf: bool,
355 ramerrf: bool,
356 addrerrf: bool,
357 operrf: bool,
358 }
359 let proxy = Sr {
360 initok: self.initok(),
361 busy: self.busy(),
362 procendf: self.procendf(),
363 ramerrf: self.ramerrf(),
364 addrerrf: self.addrerrf(),
365 operrf: self.operrf(),
366 };
367 defmt::write!(f, "{}", proxy)
368 }
369 }
370}
371