1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "Parallel synchronous slave interface."]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Pssi {
9 ptr: *mut u8,
10}
11unsafe impl Send for Pssi {}
12unsafe impl Sync for Pssi {}
13impl Pssi {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "PSSI control register."]
23 #[inline(always)]
24 pub const fn cr(self) -> crate::common::Reg<regs::Cr, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "PSSI status register."]
28 #[inline(always)]
29 pub const fn sr(self) -> crate::common::Reg<regs::Sr, crate::common::RW> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
31 }
32 #[doc = "PSSI raw interrupt status register."]
33 #[inline(always)]
34 pub const fn ris(self) -> crate::common::Reg<regs::Ris, crate::common::RW> {
35 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
36 }
37 #[doc = "PSSI interrupt enable register."]
38 #[inline(always)]
39 pub const fn ier(self) -> crate::common::Reg<regs::Ier, crate::common::RW> {
40 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
41 }
42 #[doc = "PSSI masked interrupt status register."]
43 #[inline(always)]
44 pub const fn mis(self) -> crate::common::Reg<regs::Mis, crate::common::RW> {
45 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
46 }
47 #[doc = "PSSI interrupt clear register."]
48 #[inline(always)]
49 pub const fn icr(self) -> crate::common::Reg<regs::Icr, crate::common::RW> {
50 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
51 }
52 #[doc = "PSSI data register."]
53 #[inline(always)]
54 pub const fn dr(self) -> crate::common::Reg<regs::Dr, crate::common::RW> {
55 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
56 }
57}
58pub mod regs {
59 #[doc = "PSSI control register."]
60 #[repr(transparent)]
61 #[derive(Copy, Clone, Eq, PartialEq)]
62 pub struct Cr(pub u32);
63 impl Cr {
64 #[doc = "Parallel data clock polarity This bit configures the capture edge of the parallel clock or the edge used for driving outputs, depending on OUTEN."]
65 #[inline(always)]
66 pub const fn ckpol(&self) -> super::vals::Ckpol {
67 let val = (self.0 >> 5usize) & 0x01;
68 super::vals::Ckpol::from_bits(val as u8)
69 }
70 #[doc = "Parallel data clock polarity This bit configures the capture edge of the parallel clock or the edge used for driving outputs, depending on OUTEN."]
71 #[inline(always)]
72 pub fn set_ckpol(&mut self, val: super::vals::Ckpol) {
73 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.to_bits() as u32) & 0x01) << 5usize);
74 }
75 #[doc = "Data enable (PSSI_DE) polarity This bit indicates the level on the PSSI_DE pin when the data are not valid on the parallel interface."]
76 #[inline(always)]
77 pub const fn depol(&self) -> super::vals::Depol {
78 let val = (self.0 >> 6usize) & 0x01;
79 super::vals::Depol::from_bits(val as u8)
80 }
81 #[doc = "Data enable (PSSI_DE) polarity This bit indicates the level on the PSSI_DE pin when the data are not valid on the parallel interface."]
82 #[inline(always)]
83 pub fn set_depol(&mut self, val: super::vals::Depol) {
84 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
85 }
86 #[doc = "Ready (PSSI_RDY) polarity This bit indicates the level on the PSSI_RDY pin when the data are not valid on the parallel interface."]
87 #[inline(always)]
88 pub const fn rdypol(&self) -> super::vals::Rdypol {
89 let val = (self.0 >> 8usize) & 0x01;
90 super::vals::Rdypol::from_bits(val as u8)
91 }
92 #[doc = "Ready (PSSI_RDY) polarity This bit indicates the level on the PSSI_RDY pin when the data are not valid on the parallel interface."]
93 #[inline(always)]
94 pub fn set_rdypol(&mut self, val: super::vals::Rdypol) {
95 self.0 = (self.0 & !(0x01 << 8usize)) | (((val.to_bits() as u32) & 0x01) << 8usize);
96 }
97 #[doc = "Extended data mode."]
98 #[inline(always)]
99 pub const fn edm(&self) -> super::vals::Edm {
100 let val = (self.0 >> 10usize) & 0x03;
101 super::vals::Edm::from_bits(val as u8)
102 }
103 #[doc = "Extended data mode."]
104 #[inline(always)]
105 pub fn set_edm(&mut self, val: super::vals::Edm) {
106 self.0 = (self.0 & !(0x03 << 10usize)) | (((val.to_bits() as u32) & 0x03) << 10usize);
107 }
108 #[doc = "PSSI enable The contents of the FIFO are flushed when ENABLE is cleared to 0. Note: When ENABLE=1, the content of PSSI_CR must not be changed, except for the ENABLE bit itself. All configuration bits can change as soon as ENABLE changes from 0 to 1. The DMA controller and all PSSI configuration registers must be programmed correctly before setting the ENABLE bit to 1. The ENABLE bit and the DCMI ENABLE bit (bit 15 of DCMI_CR) must not be set to 1 at the same time."]
109 #[inline(always)]
110 pub const fn enable(&self) -> bool {
111 let val = (self.0 >> 14usize) & 0x01;
112 val != 0
113 }
114 #[doc = "PSSI enable The contents of the FIFO are flushed when ENABLE is cleared to 0. Note: When ENABLE=1, the content of PSSI_CR must not be changed, except for the ENABLE bit itself. All configuration bits can change as soon as ENABLE changes from 0 to 1. The DMA controller and all PSSI configuration registers must be programmed correctly before setting the ENABLE bit to 1. The ENABLE bit and the DCMI ENABLE bit (bit 15 of DCMI_CR) must not be set to 1 at the same time."]
115 #[inline(always)]
116 pub fn set_enable(&mut self, val: bool) {
117 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
118 }
119 #[doc = "Data enable and ready configuration When the PSSI_RDY function is mapped to the PSSI_DE pin (settings 101 or 111), it is still the RDYPOL bit which determines its polarity. Similarly, when the PSSI_DE function is mapped to the PSSI_RDY pin (settings 110 or 111), it is still the DEPOL bit which determines its polarity."]
120 #[inline(always)]
121 pub const fn derdycfg(&self) -> super::vals::Derdycfg {
122 let val = (self.0 >> 18usize) & 0x07;
123 super::vals::Derdycfg::from_bits(val as u8)
124 }
125 #[doc = "Data enable and ready configuration When the PSSI_RDY function is mapped to the PSSI_DE pin (settings 101 or 111), it is still the RDYPOL bit which determines its polarity. Similarly, when the PSSI_DE function is mapped to the PSSI_RDY pin (settings 110 or 111), it is still the DEPOL bit which determines its polarity."]
126 #[inline(always)]
127 pub fn set_derdycfg(&mut self, val: super::vals::Derdycfg) {
128 self.0 = (self.0 & !(0x07 << 18usize)) | (((val.to_bits() as u32) & 0x07) << 18usize);
129 }
130 #[doc = "DMA enable bit."]
131 #[inline(always)]
132 pub const fn dmaen(&self) -> bool {
133 let val = (self.0 >> 30usize) & 0x01;
134 val != 0
135 }
136 #[doc = "DMA enable bit."]
137 #[inline(always)]
138 pub fn set_dmaen(&mut self, val: bool) {
139 self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
140 }
141 #[doc = "Data direction selection bit."]
142 #[inline(always)]
143 pub const fn outen(&self) -> super::vals::Outen {
144 let val = (self.0 >> 31usize) & 0x01;
145 super::vals::Outen::from_bits(val as u8)
146 }
147 #[doc = "Data direction selection bit."]
148 #[inline(always)]
149 pub fn set_outen(&mut self, val: super::vals::Outen) {
150 self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize);
151 }
152 }
153 impl Default for Cr {
154 #[inline(always)]
155 fn default() -> Cr {
156 Cr(0)
157 }
158 }
159 impl core::fmt::Debug for Cr {
160 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
161 f.debug_struct("Cr")
162 .field("ckpol", &self.ckpol())
163 .field("depol", &self.depol())
164 .field("rdypol", &self.rdypol())
165 .field("edm", &self.edm())
166 .field("enable", &self.enable())
167 .field("derdycfg", &self.derdycfg())
168 .field("dmaen", &self.dmaen())
169 .field("outen", &self.outen())
170 .finish()
171 }
172 }
173 #[cfg(feature = "defmt")]
174 impl defmt::Format for Cr {
175 fn format(&self, f: defmt::Formatter) {
176 #[derive(defmt :: Format)]
177 struct Cr {
178 ckpol: super::vals::Ckpol,
179 depol: super::vals::Depol,
180 rdypol: super::vals::Rdypol,
181 edm: super::vals::Edm,
182 enable: bool,
183 derdycfg: super::vals::Derdycfg,
184 dmaen: bool,
185 outen: super::vals::Outen,
186 }
187 let proxy = Cr {
188 ckpol: self.ckpol(),
189 depol: self.depol(),
190 rdypol: self.rdypol(),
191 edm: self.edm(),
192 enable: self.enable(),
193 derdycfg: self.derdycfg(),
194 dmaen: self.dmaen(),
195 outen: self.outen(),
196 };
197 defmt::write!(f, "{}", proxy)
198 }
199 }
200 #[doc = "PSSI data register."]
201 #[repr(transparent)]
202 #[derive(Copy, Clone, Eq, PartialEq)]
203 pub struct Dr(pub u32);
204 impl Dr {
205 #[doc = "Data byte 0."]
206 #[inline(always)]
207 pub const fn byte(&self, n: usize) -> u8 {
208 assert!(n < 4usize);
209 let offs = 0usize + n * 8usize;
210 let val = (self.0 >> offs) & 0xff;
211 val as u8
212 }
213 #[doc = "Data byte 0."]
214 #[inline(always)]
215 pub fn set_byte(&mut self, n: usize, val: u8) {
216 assert!(n < 4usize);
217 let offs = 0usize + n * 8usize;
218 self.0 = (self.0 & !(0xff << offs)) | (((val as u32) & 0xff) << offs);
219 }
220 }
221 impl Default for Dr {
222 #[inline(always)]
223 fn default() -> Dr {
224 Dr(0)
225 }
226 }
227 impl core::fmt::Debug for Dr {
228 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
229 f.debug_struct("Dr")
230 .field(
231 "byte",
232 &[
233 self.byte(0usize),
234 self.byte(1usize),
235 self.byte(2usize),
236 self.byte(3usize),
237 ],
238 )
239 .finish()
240 }
241 }
242 #[cfg(feature = "defmt")]
243 impl defmt::Format for Dr {
244 fn format(&self, f: defmt::Formatter) {
245 #[derive(defmt :: Format)]
246 struct Dr {
247 byte: [u8; 4usize],
248 }
249 let proxy = Dr {
250 byte: [
251 self.byte(0usize),
252 self.byte(1usize),
253 self.byte(2usize),
254 self.byte(3usize),
255 ],
256 };
257 defmt::write!(f, "{}", proxy)
258 }
259 }
260 #[doc = "PSSI interrupt clear register."]
261 #[repr(transparent)]
262 #[derive(Copy, Clone, Eq, PartialEq)]
263 pub struct Icr(pub u32);
264 impl Icr {
265 #[doc = "Data buffer overrun/underrun interrupt status clear Writing this bit to 1 clears the OVR_RIS bit in PSSI_RIS."]
266 #[inline(always)]
267 pub const fn ovr_isc(&self) -> bool {
268 let val = (self.0 >> 1usize) & 0x01;
269 val != 0
270 }
271 #[doc = "Data buffer overrun/underrun interrupt status clear Writing this bit to 1 clears the OVR_RIS bit in PSSI_RIS."]
272 #[inline(always)]
273 pub fn set_ovr_isc(&mut self, val: bool) {
274 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
275 }
276 }
277 impl Default for Icr {
278 #[inline(always)]
279 fn default() -> Icr {
280 Icr(0)
281 }
282 }
283 impl core::fmt::Debug for Icr {
284 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
285 f.debug_struct("Icr").field("ovr_isc", &self.ovr_isc()).finish()
286 }
287 }
288 #[cfg(feature = "defmt")]
289 impl defmt::Format for Icr {
290 fn format(&self, f: defmt::Formatter) {
291 #[derive(defmt :: Format)]
292 struct Icr {
293 ovr_isc: bool,
294 }
295 let proxy = Icr {
296 ovr_isc: self.ovr_isc(),
297 };
298 defmt::write!(f, "{}", proxy)
299 }
300 }
301 #[doc = "PSSI interrupt enable register."]
302 #[repr(transparent)]
303 #[derive(Copy, Clone, Eq, PartialEq)]
304 pub struct Ier(pub u32);
305 impl Ier {
306 #[doc = "Data buffer overrun/underrun interrupt enable."]
307 #[inline(always)]
308 pub const fn ovr_ie(&self) -> bool {
309 let val = (self.0 >> 1usize) & 0x01;
310 val != 0
311 }
312 #[doc = "Data buffer overrun/underrun interrupt enable."]
313 #[inline(always)]
314 pub fn set_ovr_ie(&mut self, val: bool) {
315 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
316 }
317 }
318 impl Default for Ier {
319 #[inline(always)]
320 fn default() -> Ier {
321 Ier(0)
322 }
323 }
324 impl core::fmt::Debug for Ier {
325 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
326 f.debug_struct("Ier").field("ovr_ie", &self.ovr_ie()).finish()
327 }
328 }
329 #[cfg(feature = "defmt")]
330 impl defmt::Format for Ier {
331 fn format(&self, f: defmt::Formatter) {
332 #[derive(defmt :: Format)]
333 struct Ier {
334 ovr_ie: bool,
335 }
336 let proxy = Ier { ovr_ie: self.ovr_ie() };
337 defmt::write!(f, "{}", proxy)
338 }
339 }
340 #[doc = "PSSI masked interrupt status register."]
341 #[repr(transparent)]
342 #[derive(Copy, Clone, Eq, PartialEq)]
343 pub struct Mis(pub u32);
344 impl Mis {
345 #[doc = "Data buffer overrun/underrun masked interrupt status This bit is set to 1 only when PSSI_IER/OVR_IE and PSSI_RIS/OVR_RIS are both set to 1."]
346 #[inline(always)]
347 pub const fn ovr_mis(&self) -> bool {
348 let val = (self.0 >> 1usize) & 0x01;
349 val != 0
350 }
351 #[doc = "Data buffer overrun/underrun masked interrupt status This bit is set to 1 only when PSSI_IER/OVR_IE and PSSI_RIS/OVR_RIS are both set to 1."]
352 #[inline(always)]
353 pub fn set_ovr_mis(&mut self, val: bool) {
354 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
355 }
356 }
357 impl Default for Mis {
358 #[inline(always)]
359 fn default() -> Mis {
360 Mis(0)
361 }
362 }
363 impl core::fmt::Debug for Mis {
364 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
365 f.debug_struct("Mis").field("ovr_mis", &self.ovr_mis()).finish()
366 }
367 }
368 #[cfg(feature = "defmt")]
369 impl defmt::Format for Mis {
370 fn format(&self, f: defmt::Formatter) {
371 #[derive(defmt :: Format)]
372 struct Mis {
373 ovr_mis: bool,
374 }
375 let proxy = Mis {
376 ovr_mis: self.ovr_mis(),
377 };
378 defmt::write!(f, "{}", proxy)
379 }
380 }
381 #[doc = "PSSI raw interrupt status register."]
382 #[repr(transparent)]
383 #[derive(Copy, Clone, Eq, PartialEq)]
384 pub struct Ris(pub u32);
385 impl Ris {
386 #[doc = "Data buffer overrun/underrun raw interrupt status This bit is cleared by writing a 1 to the OVR_ISC bit in PSSI_ICR."]
387 #[inline(always)]
388 pub const fn ovr_ris(&self) -> bool {
389 let val = (self.0 >> 1usize) & 0x01;
390 val != 0
391 }
392 #[doc = "Data buffer overrun/underrun raw interrupt status This bit is cleared by writing a 1 to the OVR_ISC bit in PSSI_ICR."]
393 #[inline(always)]
394 pub fn set_ovr_ris(&mut self, val: bool) {
395 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
396 }
397 }
398 impl Default for Ris {
399 #[inline(always)]
400 fn default() -> Ris {
401 Ris(0)
402 }
403 }
404 impl core::fmt::Debug for Ris {
405 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
406 f.debug_struct("Ris").field("ovr_ris", &self.ovr_ris()).finish()
407 }
408 }
409 #[cfg(feature = "defmt")]
410 impl defmt::Format for Ris {
411 fn format(&self, f: defmt::Formatter) {
412 #[derive(defmt :: Format)]
413 struct Ris {
414 ovr_ris: bool,
415 }
416 let proxy = Ris {
417 ovr_ris: self.ovr_ris(),
418 };
419 defmt::write!(f, "{}", proxy)
420 }
421 }
422 #[doc = "PSSI status register."]
423 #[repr(transparent)]
424 #[derive(Copy, Clone, Eq, PartialEq)]
425 pub struct Sr(pub u32);
426 impl Sr {
427 #[doc = "FIFO is ready to transfer four bytes."]
428 #[inline(always)]
429 pub const fn rtt4b(&self) -> bool {
430 let val = (self.0 >> 2usize) & 0x01;
431 val != 0
432 }
433 #[doc = "FIFO is ready to transfer four bytes."]
434 #[inline(always)]
435 pub fn set_rtt4b(&mut self, val: bool) {
436 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
437 }
438 #[doc = "FIFO is ready to transfer one byte."]
439 #[inline(always)]
440 pub const fn rtt1b(&self) -> bool {
441 let val = (self.0 >> 3usize) & 0x01;
442 val != 0
443 }
444 #[doc = "FIFO is ready to transfer one byte."]
445 #[inline(always)]
446 pub fn set_rtt1b(&mut self, val: bool) {
447 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
448 }
449 }
450 impl Default for Sr {
451 #[inline(always)]
452 fn default() -> Sr {
453 Sr(0)
454 }
455 }
456 impl core::fmt::Debug for Sr {
457 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
458 f.debug_struct("Sr")
459 .field("rtt4b", &self.rtt4b())
460 .field("rtt1b", &self.rtt1b())
461 .finish()
462 }
463 }
464 #[cfg(feature = "defmt")]
465 impl defmt::Format for Sr {
466 fn format(&self, f: defmt::Formatter) {
467 #[derive(defmt :: Format)]
468 struct Sr {
469 rtt4b: bool,
470 rtt1b: bool,
471 }
472 let proxy = Sr {
473 rtt4b: self.rtt4b(),
474 rtt1b: self.rtt1b(),
475 };
476 defmt::write!(f, "{}", proxy)
477 }
478 }
479}
480pub mod vals {
481 #[repr(u8)]
482 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
483 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
484 pub enum Ckpol {
485 #[doc = "Falling edge active for inputs or rising edge active for outputs."]
486 FALLING_EDGE = 0x0,
487 #[doc = "Rising edge active for inputs or falling edge active for outputs."]
488 RISING_EDGE = 0x01,
489 }
490 impl Ckpol {
491 #[inline(always)]
492 pub const fn from_bits(val: u8) -> Ckpol {
493 unsafe { core::mem::transmute(val & 0x01) }
494 }
495 #[inline(always)]
496 pub const fn to_bits(self) -> u8 {
497 unsafe { core::mem::transmute(self) }
498 }
499 }
500 impl From<u8> for Ckpol {
501 #[inline(always)]
502 fn from(val: u8) -> Ckpol {
503 Ckpol::from_bits(val)
504 }
505 }
506 impl From<Ckpol> for u8 {
507 #[inline(always)]
508 fn from(val: Ckpol) -> u8 {
509 Ckpol::to_bits(val)
510 }
511 }
512 #[repr(u8)]
513 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
514 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
515 pub enum Depol {
516 #[doc = "PSSI_DE active low (0 indicates that data is valid)."]
517 ACTIVE_LOW = 0x0,
518 #[doc = "PSSI_DE active high (1 indicates that data is valid)."]
519 ACTIVE_HIGH = 0x01,
520 }
521 impl Depol {
522 #[inline(always)]
523 pub const fn from_bits(val: u8) -> Depol {
524 unsafe { core::mem::transmute(val & 0x01) }
525 }
526 #[inline(always)]
527 pub const fn to_bits(self) -> u8 {
528 unsafe { core::mem::transmute(self) }
529 }
530 }
531 impl From<u8> for Depol {
532 #[inline(always)]
533 fn from(val: u8) -> Depol {
534 Depol::from_bits(val)
535 }
536 }
537 impl From<Depol> for u8 {
538 #[inline(always)]
539 fn from(val: Depol) -> u8 {
540 Depol::to_bits(val)
541 }
542 }
543 #[repr(u8)]
544 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
545 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
546 pub enum Derdycfg {
547 #[doc = "PSSI_DE and PSSI_RDY both disabled."]
548 DISABLED = 0x0,
549 #[doc = "Only PSSI_RDY enabled."]
550 RDY = 0x01,
551 #[doc = "Only PSSI_DE enabled."]
552 DE = 0x02,
553 #[doc = "Both PSSI_RDY and PSSI_DE alternate functions enabled."]
554 RDY_DE_ALT = 0x03,
555 #[doc = "Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_RDY pin."]
556 RDY_DE = 0x04,
557 #[doc = "Only PSSI_RDY function enabled, but mapped to PSSI_DE pin."]
558 RDY_REMAPPED = 0x05,
559 #[doc = "Only PSSI_DE function enabled, but mapped to PSSI_RDY pin."]
560 DE_REMAPPED = 0x06,
561 #[doc = "Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_DE pin."]
562 RDY_DE_BIDI = 0x07,
563 }
564 impl Derdycfg {
565 #[inline(always)]
566 pub const fn from_bits(val: u8) -> Derdycfg {
567 unsafe { core::mem::transmute(val & 0x07) }
568 }
569 #[inline(always)]
570 pub const fn to_bits(self) -> u8 {
571 unsafe { core::mem::transmute(self) }
572 }
573 }
574 impl From<u8> for Derdycfg {
575 #[inline(always)]
576 fn from(val: u8) -> Derdycfg {
577 Derdycfg::from_bits(val)
578 }
579 }
580 impl From<Derdycfg> for u8 {
581 #[inline(always)]
582 fn from(val: Derdycfg) -> u8 {
583 Derdycfg::to_bits(val)
584 }
585 }
586 #[repr(u8)]
587 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
588 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
589 pub enum Edm {
590 #[doc = "Interface captures 8-bit data on every parallel data clock."]
591 BIT_WIDTH8 = 0x0,
592 _RESERVED_1 = 0x01,
593 _RESERVED_2 = 0x02,
594 #[doc = "The interface captures 16-bit data on every parallel data clock."]
595 BIT_WIDTH16 = 0x03,
596 }
597 impl Edm {
598 #[inline(always)]
599 pub const fn from_bits(val: u8) -> Edm {
600 unsafe { core::mem::transmute(val & 0x03) }
601 }
602 #[inline(always)]
603 pub const fn to_bits(self) -> u8 {
604 unsafe { core::mem::transmute(self) }
605 }
606 }
607 impl From<u8> for Edm {
608 #[inline(always)]
609 fn from(val: u8) -> Edm {
610 Edm::from_bits(val)
611 }
612 }
613 impl From<Edm> for u8 {
614 #[inline(always)]
615 fn from(val: Edm) -> u8 {
616 Edm::to_bits(val)
617 }
618 }
619 #[repr(u8)]
620 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
621 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
622 pub enum Outen {
623 #[doc = "Data is input synchronously with PSSI_PDCK."]
624 RECEIVE_MODE = 0x0,
625 #[doc = "Data is output synchronously with PSSI_PDCK."]
626 TRANSMIT_MODE = 0x01,
627 }
628 impl Outen {
629 #[inline(always)]
630 pub const fn from_bits(val: u8) -> Outen {
631 unsafe { core::mem::transmute(val & 0x01) }
632 }
633 #[inline(always)]
634 pub const fn to_bits(self) -> u8 {
635 unsafe { core::mem::transmute(self) }
636 }
637 }
638 impl From<u8> for Outen {
639 #[inline(always)]
640 fn from(val: u8) -> Outen {
641 Outen::from_bits(val)
642 }
643 }
644 impl From<Outen> for u8 {
645 #[inline(always)]
646 fn from(val: Outen) -> u8 {
647 Outen::to_bits(val)
648 }
649 }
650 #[repr(u8)]
651 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
652 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
653 pub enum Rdypol {
654 #[doc = "PSSI_RDY active low (0 indicates that the receiver is ready to receive)."]
655 ACTIVE_LOW = 0x0,
656 #[doc = "PSSI_RDY active high (1 indicates that the receiver is ready to receive)."]
657 ACTIVE_HIGH = 0x01,
658 }
659 impl Rdypol {
660 #[inline(always)]
661 pub const fn from_bits(val: u8) -> Rdypol {
662 unsafe { core::mem::transmute(val & 0x01) }
663 }
664 #[inline(always)]
665 pub const fn to_bits(self) -> u8 {
666 unsafe { core::mem::transmute(self) }
667 }
668 }
669 impl From<u8> for Rdypol {
670 #[inline(always)]
671 fn from(val: u8) -> Rdypol {
672 Rdypol::from_bits(val)
673 }
674 }
675 impl From<Rdypol> for u8 {
676 #[inline(always)]
677 fn from(val: Rdypol) -> u8 {
678 Rdypol::to_bits(val)
679 }
680 }
681}
682