1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "Reset and clock control"]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Rcc {
9 ptr: *mut u8,
10}
11unsafe impl Send for Rcc {}
12unsafe impl Sync for Rcc {}
13impl Rcc {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "RCC clock control register"]
23 #[inline(always)]
24 pub const fn cr(self) -> crate::common::Reg<regs::Cr, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "RCC internal clock sources calibration register 1"]
28 #[inline(always)]
29 pub const fn icscr1(self) -> crate::common::Reg<regs::Icscr1, crate::common::RW> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
31 }
32 #[doc = "RCC internal clock sources calibration register 2"]
33 #[inline(always)]
34 pub const fn icscr2(self) -> crate::common::Reg<regs::Icscr2, crate::common::RW> {
35 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
36 }
37 #[doc = "RCC internal clock sources calibration register 3"]
38 #[inline(always)]
39 pub const fn icscr3(self) -> crate::common::Reg<regs::Icscr3, crate::common::RW> {
40 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
41 }
42 #[doc = "RCC clock recovery RC register"]
43 #[inline(always)]
44 pub const fn crrcr(self) -> crate::common::Reg<regs::Crrcr, crate::common::RW> {
45 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
46 }
47 #[doc = "RCC clock configuration register 1"]
48 #[inline(always)]
49 pub const fn cfgr1(self) -> crate::common::Reg<regs::Cfgr1, crate::common::RW> {
50 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) }
51 }
52 #[doc = "RCC clock configuration register 2"]
53 #[inline(always)]
54 pub const fn cfgr2(self) -> crate::common::Reg<regs::Cfgr2, crate::common::RW> {
55 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
56 }
57 #[doc = "RCC clock configuration register 3"]
58 #[inline(always)]
59 pub const fn cfgr3(self) -> crate::common::Reg<regs::Cfgr3, crate::common::RW> {
60 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
61 }
62 #[doc = "RCC PLL1 configuration register"]
63 #[inline(always)]
64 pub const fn pll1cfgr(self) -> crate::common::Reg<regs::Pll1cfgr, crate::common::RW> {
65 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
66 }
67 #[doc = "RCC PLL2 configuration register"]
68 #[inline(always)]
69 pub const fn pll2cfgr(self) -> crate::common::Reg<regs::Pll23cfgr, crate::common::RW> {
70 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
71 }
72 #[doc = "RCC PLL3 configuration register"]
73 #[inline(always)]
74 pub const fn pll3cfgr(self) -> crate::common::Reg<regs::Pll23cfgr, crate::common::RW> {
75 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) }
76 }
77 #[doc = "RCC PLL1 dividers register"]
78 #[inline(always)]
79 pub const fn pll1divr(self) -> crate::common::Reg<regs::Plldivr, crate::common::RW> {
80 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) }
81 }
82 #[doc = "RCC PLL1 fractional divider register"]
83 #[inline(always)]
84 pub const fn pll1fracr(self) -> crate::common::Reg<regs::Pllfracr, crate::common::RW> {
85 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) }
86 }
87 #[doc = "RCC PLL2 dividers configuration register"]
88 #[inline(always)]
89 pub const fn pll2divr(self) -> crate::common::Reg<regs::Plldivr, crate::common::RW> {
90 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) }
91 }
92 #[doc = "RCC PLL2 fractional divider register"]
93 #[inline(always)]
94 pub const fn pll2fracr(self) -> crate::common::Reg<regs::Pllfracr, crate::common::RW> {
95 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) }
96 }
97 #[doc = "RCC PLL3 dividers configuration register"]
98 #[inline(always)]
99 pub const fn pll3divr(self) -> crate::common::Reg<regs::Plldivr, crate::common::RW> {
100 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) }
101 }
102 #[doc = "RCC PLL3 fractional divider register"]
103 #[inline(always)]
104 pub const fn pll3fracr(self) -> crate::common::Reg<regs::Pllfracr, crate::common::RW> {
105 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) }
106 }
107 #[doc = "RCC clock interrupt enable register"]
108 #[inline(always)]
109 pub const fn cier(self) -> crate::common::Reg<regs::Cier, crate::common::RW> {
110 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x50usize) as _) }
111 }
112 #[doc = "RCC clock interrupt flag register"]
113 #[inline(always)]
114 pub const fn cifr(self) -> crate::common::Reg<regs::Cifr, crate::common::RW> {
115 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x54usize) as _) }
116 }
117 #[doc = "RCC clock interrupt clear register"]
118 #[inline(always)]
119 pub const fn cicr(self) -> crate::common::Reg<regs::Cicr, crate::common::RW> {
120 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x58usize) as _) }
121 }
122 #[doc = "RCC AHB1 peripheral reset register"]
123 #[inline(always)]
124 pub const fn ahb1rstr(self) -> crate::common::Reg<regs::Ahb1rstr, crate::common::RW> {
125 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize) as _) }
126 }
127 #[doc = "RCC AHB2 peripheral reset register 1"]
128 #[inline(always)]
129 pub const fn ahb2rstr1(self) -> crate::common::Reg<regs::Ahb2rstr1, crate::common::RW> {
130 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x64usize) as _) }
131 }
132 #[doc = "RCC AHB2 peripheral reset register 2"]
133 #[inline(always)]
134 pub const fn ahb2rstr2(self) -> crate::common::Reg<regs::Ahb2rstr2, crate::common::RW> {
135 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x68usize) as _) }
136 }
137 #[doc = "RCC AHB3 peripheral reset register"]
138 #[inline(always)]
139 pub const fn ahb3rstr(self) -> crate::common::Reg<regs::Ahb3rstr, crate::common::RW> {
140 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x6cusize) as _) }
141 }
142 #[doc = "RCC APB1 peripheral reset register 1"]
143 #[inline(always)]
144 pub const fn apb1rstr1(self) -> crate::common::Reg<regs::Apb1rstr1, crate::common::RW> {
145 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x74usize) as _) }
146 }
147 #[doc = "RCC APB1 peripheral reset register 2"]
148 #[inline(always)]
149 pub const fn apb1rstr2(self) -> crate::common::Reg<regs::Apb1rstr2, crate::common::RW> {
150 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x78usize) as _) }
151 }
152 #[doc = "RCC APB2 peripheral reset register"]
153 #[inline(always)]
154 pub const fn apb2rstr(self) -> crate::common::Reg<regs::Apb2rstr, crate::common::RW> {
155 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x7cusize) as _) }
156 }
157 #[doc = "RCC APB3 peripheral reset register"]
158 #[inline(always)]
159 pub const fn apb3rstr(self) -> crate::common::Reg<regs::Apb3rstr, crate::common::RW> {
160 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize) as _) }
161 }
162 #[doc = "RCC AHB1 peripheral clock enable register"]
163 #[inline(always)]
164 pub const fn ahb1enr(self) -> crate::common::Reg<regs::Ahb1enr, crate::common::RW> {
165 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x88usize) as _) }
166 }
167 #[doc = "RCC AHB2 peripheral clock enable register 1"]
168 #[inline(always)]
169 pub const fn ahb2enr1(self) -> crate::common::Reg<regs::Ahb2enr1, crate::common::RW> {
170 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x8cusize) as _) }
171 }
172 #[doc = "RCC AHB2 peripheral clock enable register 2"]
173 #[inline(always)]
174 pub const fn ahb2enr2(self) -> crate::common::Reg<regs::Ahb2enr2, crate::common::RW> {
175 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x90usize) as _) }
176 }
177 #[doc = "RCC AHB3 peripheral clock enable register"]
178 #[inline(always)]
179 pub const fn ahb3enr(self) -> crate::common::Reg<regs::Ahb3enr, crate::common::RW> {
180 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x94usize) as _) }
181 }
182 #[doc = "RCC APB1 peripheral clock enable register 1"]
183 #[inline(always)]
184 pub const fn apb1enr1(self) -> crate::common::Reg<regs::Apb1enr1, crate::common::RW> {
185 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x9cusize) as _) }
186 }
187 #[doc = "RCC APB1 peripheral clock enable register 2"]
188 #[inline(always)]
189 pub const fn apb1enr2(self) -> crate::common::Reg<regs::Apb1enr2, crate::common::RW> {
190 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa0usize) as _) }
191 }
192 #[doc = "RCC APB2 peripheral clock enable register"]
193 #[inline(always)]
194 pub const fn apb2enr(self) -> crate::common::Reg<regs::Apb2enr, crate::common::RW> {
195 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa4usize) as _) }
196 }
197 #[doc = "RCC APB3 peripheral clock enable register"]
198 #[inline(always)]
199 pub const fn apb3enr(self) -> crate::common::Reg<regs::Apb3enr, crate::common::RW> {
200 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xa8usize) as _) }
201 }
202 #[doc = "RCC AHB1 peripheral clocks enable in Sleep and Stop modes register"]
203 #[inline(always)]
204 pub const fn ahb1smenr(self) -> crate::common::Reg<regs::Ahb1smenr, crate::common::RW> {
205 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb0usize) as _) }
206 }
207 #[doc = "RCC AHB2 peripheral clocks enable in Sleep and Stop modes register 1"]
208 #[inline(always)]
209 pub const fn ahb2smenr1(self) -> crate::common::Reg<regs::Ahb2smenr1, crate::common::RW> {
210 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb4usize) as _) }
211 }
212 #[doc = "RCC AHB2 peripheral clocks enable in Sleep and Stop modes register 2"]
213 #[inline(always)]
214 pub const fn ahb2smenr2(self) -> crate::common::Reg<regs::Ahb2smenr2, crate::common::RW> {
215 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xb8usize) as _) }
216 }
217 #[doc = "RCC AHB3 peripheral clocks enable in Sleep and Stop modes register"]
218 #[inline(always)]
219 pub const fn ahb3smenr(self) -> crate::common::Reg<regs::Ahb3smenr, crate::common::RW> {
220 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xbcusize) as _) }
221 }
222 #[doc = "RCC APB1 peripheral clocks enable in Sleep and Stop modes register 1"]
223 #[inline(always)]
224 pub const fn apb1smenr1(self) -> crate::common::Reg<regs::Apb1smenr1, crate::common::RW> {
225 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc4usize) as _) }
226 }
227 #[doc = "RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2"]
228 #[inline(always)]
229 pub const fn apb1smenr2(self) -> crate::common::Reg<regs::Apb1smenr2, crate::common::RW> {
230 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xc8usize) as _) }
231 }
232 #[doc = "RCC APB2 peripheral clocks enable in Sleep and Stop modes register"]
233 #[inline(always)]
234 pub const fn apb2smenr(self) -> crate::common::Reg<regs::Apb2smenr, crate::common::RW> {
235 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xccusize) as _) }
236 }
237 #[doc = "RCC APB3 peripheral clock enable in Sleep and Stop modes register"]
238 #[inline(always)]
239 pub const fn apb3smenr(self) -> crate::common::Reg<regs::Apb3smenr, crate::common::RW> {
240 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xd0usize) as _) }
241 }
242 #[doc = "RCC SmartRun domain peripheral autonomous mode register"]
243 #[inline(always)]
244 pub const fn srdamr(self) -> crate::common::Reg<regs::Srdamr, crate::common::RW> {
245 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xd8usize) as _) }
246 }
247 #[doc = "RCC peripherals independent clock configuration register 1"]
248 #[inline(always)]
249 pub const fn ccipr1(self) -> crate::common::Reg<regs::Ccipr1, crate::common::RW> {
250 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xe0usize) as _) }
251 }
252 #[doc = "RCC peripherals independent clock configuration register 2"]
253 #[inline(always)]
254 pub const fn ccipr2(self) -> crate::common::Reg<regs::Ccipr2, crate::common::RW> {
255 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xe4usize) as _) }
256 }
257 #[doc = "RCC peripherals independent clock configuration register 3"]
258 #[inline(always)]
259 pub const fn ccipr3(self) -> crate::common::Reg<regs::Ccipr3, crate::common::RW> {
260 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xe8usize) as _) }
261 }
262 #[doc = "RCC Backup domain control register"]
263 #[inline(always)]
264 pub const fn bdcr(self) -> crate::common::Reg<regs::Bdcr, crate::common::RW> {
265 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xf0usize) as _) }
266 }
267 #[doc = "RCC control/status register"]
268 #[inline(always)]
269 pub const fn csr(self) -> crate::common::Reg<regs::Csr, crate::common::RW> {
270 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xf4usize) as _) }
271 }
272 #[doc = "RCC secure configuration register"]
273 #[inline(always)]
274 pub const fn seccfgr(self) -> crate::common::Reg<regs::Seccfgr, crate::common::RW> {
275 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0110usize) as _) }
276 }
277 #[doc = "RCC privilege configuration register"]
278 #[inline(always)]
279 pub const fn privcfgr(self) -> crate::common::Reg<regs::Privcfgr, crate::common::RW> {
280 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0114usize) as _) }
281 }
282}
283pub mod regs {
284 #[doc = "RCC AHB1 peripheral clock enable register"]
285 #[repr(transparent)]
286 #[derive(Copy, Clone, Eq, PartialEq)]
287 pub struct Ahb1enr(pub u32);
288 impl Ahb1enr {
289 #[doc = "GPDMA1 clock enable Set and cleared by software."]
290 #[inline(always)]
291 pub const fn gpdma1en(&self) -> bool {
292 let val = (self.0 >> 0usize) & 0x01;
293 val != 0
294 }
295 #[doc = "GPDMA1 clock enable Set and cleared by software."]
296 #[inline(always)]
297 pub fn set_gpdma1en(&mut self, val: bool) {
298 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
299 }
300 #[doc = "CORDIC clock enable Set and cleared by software."]
301 #[inline(always)]
302 pub const fn cordicen(&self) -> bool {
303 let val = (self.0 >> 1usize) & 0x01;
304 val != 0
305 }
306 #[doc = "CORDIC clock enable Set and cleared by software."]
307 #[inline(always)]
308 pub fn set_cordicen(&mut self, val: bool) {
309 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
310 }
311 #[doc = "FMAC clock enable Set and reset by software."]
312 #[inline(always)]
313 pub const fn fmacen(&self) -> bool {
314 let val = (self.0 >> 2usize) & 0x01;
315 val != 0
316 }
317 #[doc = "FMAC clock enable Set and reset by software."]
318 #[inline(always)]
319 pub fn set_fmacen(&mut self, val: bool) {
320 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
321 }
322 #[doc = "MDF1 clock enable Set and reset by software."]
323 #[inline(always)]
324 pub const fn mdf1en(&self) -> bool {
325 let val = (self.0 >> 3usize) & 0x01;
326 val != 0
327 }
328 #[doc = "MDF1 clock enable Set and reset by software."]
329 #[inline(always)]
330 pub fn set_mdf1en(&mut self, val: bool) {
331 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
332 }
333 #[doc = "FLASH clock enable Set and cleared by software. This bit can be disabled only when the Flash memory is in power down mode."]
334 #[inline(always)]
335 pub const fn flashen(&self) -> bool {
336 let val = (self.0 >> 8usize) & 0x01;
337 val != 0
338 }
339 #[doc = "FLASH clock enable Set and cleared by software. This bit can be disabled only when the Flash memory is in power down mode."]
340 #[inline(always)]
341 pub fn set_flashen(&mut self, val: bool) {
342 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
343 }
344 #[doc = "CRC clock enable Set and cleared by software."]
345 #[inline(always)]
346 pub const fn crcen(&self) -> bool {
347 let val = (self.0 >> 12usize) & 0x01;
348 val != 0
349 }
350 #[doc = "CRC clock enable Set and cleared by software."]
351 #[inline(always)]
352 pub fn set_crcen(&mut self, val: bool) {
353 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
354 }
355 #[doc = "JPEG clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
356 #[inline(always)]
357 pub const fn jpegen(&self) -> bool {
358 let val = (self.0 >> 15usize) & 0x01;
359 val != 0
360 }
361 #[doc = "JPEG clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
362 #[inline(always)]
363 pub fn set_jpegen(&mut self, val: bool) {
364 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
365 }
366 #[doc = "Touch sensing controller clock enable Set and cleared by software."]
367 #[inline(always)]
368 pub const fn tscen(&self) -> bool {
369 let val = (self.0 >> 16usize) & 0x01;
370 val != 0
371 }
372 #[doc = "Touch sensing controller clock enable Set and cleared by software."]
373 #[inline(always)]
374 pub fn set_tscen(&mut self, val: bool) {
375 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
376 }
377 #[doc = "RAMCFG clock enable Set and cleared by software."]
378 #[inline(always)]
379 pub const fn ramcfgen(&self) -> bool {
380 let val = (self.0 >> 17usize) & 0x01;
381 val != 0
382 }
383 #[doc = "RAMCFG clock enable Set and cleared by software."]
384 #[inline(always)]
385 pub fn set_ramcfgen(&mut self, val: bool) {
386 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
387 }
388 #[doc = "DMA2D clock enable Set and cleared by software."]
389 #[inline(always)]
390 pub const fn dma2den(&self) -> bool {
391 let val = (self.0 >> 18usize) & 0x01;
392 val != 0
393 }
394 #[doc = "DMA2D clock enable Set and cleared by software."]
395 #[inline(always)]
396 pub fn set_dma2den(&mut self, val: bool) {
397 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
398 }
399 #[doc = "GFXMMU clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
400 #[inline(always)]
401 pub const fn gfxmmuen(&self) -> bool {
402 let val = (self.0 >> 19usize) & 0x01;
403 val != 0
404 }
405 #[doc = "GFXMMU clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
406 #[inline(always)]
407 pub fn set_gfxmmuen(&mut self, val: bool) {
408 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
409 }
410 #[doc = "GPU2D clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
411 #[inline(always)]
412 pub const fn gpu2den(&self) -> bool {
413 let val = (self.0 >> 20usize) & 0x01;
414 val != 0
415 }
416 #[doc = "GPU2D clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
417 #[inline(always)]
418 pub fn set_gpu2den(&mut self, val: bool) {
419 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
420 }
421 #[doc = "DCACHE2 clock enable This bit is set and reset by software. Note: DCACHE2 clock must be enabled to access memories, even if the DCACHE2 is bypassed. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
422 #[inline(always)]
423 pub const fn dcache2en(&self) -> bool {
424 let val = (self.0 >> 21usize) & 0x01;
425 val != 0
426 }
427 #[doc = "DCACHE2 clock enable This bit is set and reset by software. Note: DCACHE2 clock must be enabled to access memories, even if the DCACHE2 is bypassed. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
428 #[inline(always)]
429 pub fn set_dcache2en(&mut self, val: bool) {
430 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
431 }
432 #[doc = "GTZC1 clock enable Set and reset by software."]
433 #[inline(always)]
434 pub const fn gtzc1en(&self) -> bool {
435 let val = (self.0 >> 24usize) & 0x01;
436 val != 0
437 }
438 #[doc = "GTZC1 clock enable Set and reset by software."]
439 #[inline(always)]
440 pub fn set_gtzc1en(&mut self, val: bool) {
441 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
442 }
443 #[doc = "BKPSRAM clock enable Set and reset by software."]
444 #[inline(always)]
445 pub const fn bkpsramen(&self) -> bool {
446 let val = (self.0 >> 28usize) & 0x01;
447 val != 0
448 }
449 #[doc = "BKPSRAM clock enable Set and reset by software."]
450 #[inline(always)]
451 pub fn set_bkpsramen(&mut self, val: bool) {
452 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
453 }
454 #[doc = "DCACHE1 clock enable Set and reset by software. Note: DCACHE1 clock must be enabled when external memories are accessed through OCTOSPI1, OCTOSPI2 or FSMC, even if the DCACHE1 is bypassed."]
455 #[inline(always)]
456 pub const fn dcache1en(&self) -> bool {
457 let val = (self.0 >> 30usize) & 0x01;
458 val != 0
459 }
460 #[doc = "DCACHE1 clock enable Set and reset by software. Note: DCACHE1 clock must be enabled when external memories are accessed through OCTOSPI1, OCTOSPI2 or FSMC, even if the DCACHE1 is bypassed."]
461 #[inline(always)]
462 pub fn set_dcache1en(&mut self, val: bool) {
463 self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
464 }
465 #[doc = "SRAM1 clock enable Set and reset by software."]
466 #[inline(always)]
467 pub const fn sram1en(&self) -> bool {
468 let val = (self.0 >> 31usize) & 0x01;
469 val != 0
470 }
471 #[doc = "SRAM1 clock enable Set and reset by software."]
472 #[inline(always)]
473 pub fn set_sram1en(&mut self, val: bool) {
474 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
475 }
476 }
477 impl Default for Ahb1enr {
478 #[inline(always)]
479 fn default() -> Ahb1enr {
480 Ahb1enr(0)
481 }
482 }
483 impl core::fmt::Debug for Ahb1enr {
484 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
485 f.debug_struct("Ahb1enr")
486 .field("gpdma1en", &self.gpdma1en())
487 .field("cordicen", &self.cordicen())
488 .field("fmacen", &self.fmacen())
489 .field("mdf1en", &self.mdf1en())
490 .field("flashen", &self.flashen())
491 .field("crcen", &self.crcen())
492 .field("jpegen", &self.jpegen())
493 .field("tscen", &self.tscen())
494 .field("ramcfgen", &self.ramcfgen())
495 .field("dma2den", &self.dma2den())
496 .field("gfxmmuen", &self.gfxmmuen())
497 .field("gpu2den", &self.gpu2den())
498 .field("dcache2en", &self.dcache2en())
499 .field("gtzc1en", &self.gtzc1en())
500 .field("bkpsramen", &self.bkpsramen())
501 .field("dcache1en", &self.dcache1en())
502 .field("sram1en", &self.sram1en())
503 .finish()
504 }
505 }
506 #[cfg(feature = "defmt")]
507 impl defmt::Format for Ahb1enr {
508 fn format(&self, f: defmt::Formatter) {
509 #[derive(defmt :: Format)]
510 struct Ahb1enr {
511 gpdma1en: bool,
512 cordicen: bool,
513 fmacen: bool,
514 mdf1en: bool,
515 flashen: bool,
516 crcen: bool,
517 jpegen: bool,
518 tscen: bool,
519 ramcfgen: bool,
520 dma2den: bool,
521 gfxmmuen: bool,
522 gpu2den: bool,
523 dcache2en: bool,
524 gtzc1en: bool,
525 bkpsramen: bool,
526 dcache1en: bool,
527 sram1en: bool,
528 }
529 let proxy = Ahb1enr {
530 gpdma1en: self.gpdma1en(),
531 cordicen: self.cordicen(),
532 fmacen: self.fmacen(),
533 mdf1en: self.mdf1en(),
534 flashen: self.flashen(),
535 crcen: self.crcen(),
536 jpegen: self.jpegen(),
537 tscen: self.tscen(),
538 ramcfgen: self.ramcfgen(),
539 dma2den: self.dma2den(),
540 gfxmmuen: self.gfxmmuen(),
541 gpu2den: self.gpu2den(),
542 dcache2en: self.dcache2en(),
543 gtzc1en: self.gtzc1en(),
544 bkpsramen: self.bkpsramen(),
545 dcache1en: self.dcache1en(),
546 sram1en: self.sram1en(),
547 };
548 defmt::write!(f, "{}", proxy)
549 }
550 }
551 #[doc = "RCC AHB1 peripheral reset register"]
552 #[repr(transparent)]
553 #[derive(Copy, Clone, Eq, PartialEq)]
554 pub struct Ahb1rstr(pub u32);
555 impl Ahb1rstr {
556 #[doc = "GPDMA1 reset Set and cleared by software."]
557 #[inline(always)]
558 pub const fn gpdma1rst(&self) -> bool {
559 let val = (self.0 >> 0usize) & 0x01;
560 val != 0
561 }
562 #[doc = "GPDMA1 reset Set and cleared by software."]
563 #[inline(always)]
564 pub fn set_gpdma1rst(&mut self, val: bool) {
565 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
566 }
567 #[doc = "CORDIC reset Set and cleared by software."]
568 #[inline(always)]
569 pub const fn cordicrst(&self) -> bool {
570 let val = (self.0 >> 1usize) & 0x01;
571 val != 0
572 }
573 #[doc = "CORDIC reset Set and cleared by software."]
574 #[inline(always)]
575 pub fn set_cordicrst(&mut self, val: bool) {
576 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
577 }
578 #[doc = "FMAC reset Set and cleared by software."]
579 #[inline(always)]
580 pub const fn fmacrst(&self) -> bool {
581 let val = (self.0 >> 2usize) & 0x01;
582 val != 0
583 }
584 #[doc = "FMAC reset Set and cleared by software."]
585 #[inline(always)]
586 pub fn set_fmacrst(&mut self, val: bool) {
587 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
588 }
589 #[doc = "MDF1 reset Set and cleared by software."]
590 #[inline(always)]
591 pub const fn mdf1rst(&self) -> bool {
592 let val = (self.0 >> 3usize) & 0x01;
593 val != 0
594 }
595 #[doc = "MDF1 reset Set and cleared by software."]
596 #[inline(always)]
597 pub fn set_mdf1rst(&mut self, val: bool) {
598 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
599 }
600 #[doc = "CRC reset Set and cleared by software."]
601 #[inline(always)]
602 pub const fn crcrst(&self) -> bool {
603 let val = (self.0 >> 12usize) & 0x01;
604 val != 0
605 }
606 #[doc = "CRC reset Set and cleared by software."]
607 #[inline(always)]
608 pub fn set_crcrst(&mut self, val: bool) {
609 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
610 }
611 #[doc = "JPEG reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
612 #[inline(always)]
613 pub const fn jpegrst(&self) -> bool {
614 let val = (self.0 >> 15usize) & 0x01;
615 val != 0
616 }
617 #[doc = "JPEG reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
618 #[inline(always)]
619 pub fn set_jpegrst(&mut self, val: bool) {
620 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
621 }
622 #[doc = "TSC reset Set and cleared by software."]
623 #[inline(always)]
624 pub const fn tscrst(&self) -> bool {
625 let val = (self.0 >> 16usize) & 0x01;
626 val != 0
627 }
628 #[doc = "TSC reset Set and cleared by software."]
629 #[inline(always)]
630 pub fn set_tscrst(&mut self, val: bool) {
631 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
632 }
633 #[doc = "RAMCFG reset Set and cleared by software."]
634 #[inline(always)]
635 pub const fn ramcfgrst(&self) -> bool {
636 let val = (self.0 >> 17usize) & 0x01;
637 val != 0
638 }
639 #[doc = "RAMCFG reset Set and cleared by software."]
640 #[inline(always)]
641 pub fn set_ramcfgrst(&mut self, val: bool) {
642 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
643 }
644 #[doc = "DMA2D reset Set and cleared by software."]
645 #[inline(always)]
646 pub const fn dma2drst(&self) -> bool {
647 let val = (self.0 >> 18usize) & 0x01;
648 val != 0
649 }
650 #[doc = "DMA2D reset Set and cleared by software."]
651 #[inline(always)]
652 pub fn set_dma2drst(&mut self, val: bool) {
653 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
654 }
655 #[doc = "GFXMMU reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
656 #[inline(always)]
657 pub const fn gfxmmurst(&self) -> bool {
658 let val = (self.0 >> 19usize) & 0x01;
659 val != 0
660 }
661 #[doc = "GFXMMU reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
662 #[inline(always)]
663 pub fn set_gfxmmurst(&mut self, val: bool) {
664 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
665 }
666 #[doc = "GPU2D reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
667 #[inline(always)]
668 pub const fn gpu2drst(&self) -> bool {
669 let val = (self.0 >> 20usize) & 0x01;
670 val != 0
671 }
672 #[doc = "GPU2D reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
673 #[inline(always)]
674 pub fn set_gpu2drst(&mut self, val: bool) {
675 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
676 }
677 }
678 impl Default for Ahb1rstr {
679 #[inline(always)]
680 fn default() -> Ahb1rstr {
681 Ahb1rstr(0)
682 }
683 }
684 impl core::fmt::Debug for Ahb1rstr {
685 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
686 f.debug_struct("Ahb1rstr")
687 .field("gpdma1rst", &self.gpdma1rst())
688 .field("cordicrst", &self.cordicrst())
689 .field("fmacrst", &self.fmacrst())
690 .field("mdf1rst", &self.mdf1rst())
691 .field("crcrst", &self.crcrst())
692 .field("jpegrst", &self.jpegrst())
693 .field("tscrst", &self.tscrst())
694 .field("ramcfgrst", &self.ramcfgrst())
695 .field("dma2drst", &self.dma2drst())
696 .field("gfxmmurst", &self.gfxmmurst())
697 .field("gpu2drst", &self.gpu2drst())
698 .finish()
699 }
700 }
701 #[cfg(feature = "defmt")]
702 impl defmt::Format for Ahb1rstr {
703 fn format(&self, f: defmt::Formatter) {
704 #[derive(defmt :: Format)]
705 struct Ahb1rstr {
706 gpdma1rst: bool,
707 cordicrst: bool,
708 fmacrst: bool,
709 mdf1rst: bool,
710 crcrst: bool,
711 jpegrst: bool,
712 tscrst: bool,
713 ramcfgrst: bool,
714 dma2drst: bool,
715 gfxmmurst: bool,
716 gpu2drst: bool,
717 }
718 let proxy = Ahb1rstr {
719 gpdma1rst: self.gpdma1rst(),
720 cordicrst: self.cordicrst(),
721 fmacrst: self.fmacrst(),
722 mdf1rst: self.mdf1rst(),
723 crcrst: self.crcrst(),
724 jpegrst: self.jpegrst(),
725 tscrst: self.tscrst(),
726 ramcfgrst: self.ramcfgrst(),
727 dma2drst: self.dma2drst(),
728 gfxmmurst: self.gfxmmurst(),
729 gpu2drst: self.gpu2drst(),
730 };
731 defmt::write!(f, "{}", proxy)
732 }
733 }
734 #[doc = "RCC AHB1 peripheral clocks enable in Sleep and Stop modes register"]
735 #[repr(transparent)]
736 #[derive(Copy, Clone, Eq, PartialEq)]
737 pub struct Ahb1smenr(pub u32);
738 impl Ahb1smenr {
739 #[doc = "GPDMA1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
740 #[inline(always)]
741 pub const fn gpdma1smen(&self) -> bool {
742 let val = (self.0 >> 0usize) & 0x01;
743 val != 0
744 }
745 #[doc = "GPDMA1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
746 #[inline(always)]
747 pub fn set_gpdma1smen(&mut self, val: bool) {
748 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
749 }
750 #[doc = "CORDIC clocks enable during Sleep and Stop modes Set and cleared by software during Sleep mode."]
751 #[inline(always)]
752 pub const fn cordicsmen(&self) -> bool {
753 let val = (self.0 >> 1usize) & 0x01;
754 val != 0
755 }
756 #[doc = "CORDIC clocks enable during Sleep and Stop modes Set and cleared by software during Sleep mode."]
757 #[inline(always)]
758 pub fn set_cordicsmen(&mut self, val: bool) {
759 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
760 }
761 #[doc = "FMAC clocks enable during Sleep and Stop modes. Set and cleared by software."]
762 #[inline(always)]
763 pub const fn fmacsmen(&self) -> bool {
764 let val = (self.0 >> 2usize) & 0x01;
765 val != 0
766 }
767 #[doc = "FMAC clocks enable during Sleep and Stop modes. Set and cleared by software."]
768 #[inline(always)]
769 pub fn set_fmacsmen(&mut self, val: bool) {
770 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
771 }
772 #[doc = "MDF1 clocks enable during Sleep and Stop modes. Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
773 #[inline(always)]
774 pub const fn mdf1smen(&self) -> bool {
775 let val = (self.0 >> 3usize) & 0x01;
776 val != 0
777 }
778 #[doc = "MDF1 clocks enable during Sleep and Stop modes. Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
779 #[inline(always)]
780 pub fn set_mdf1smen(&mut self, val: bool) {
781 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
782 }
783 #[doc = "FLASH clocks enable during Sleep and Stop modes Set and cleared by software."]
784 #[inline(always)]
785 pub const fn flashsmen(&self) -> bool {
786 let val = (self.0 >> 8usize) & 0x01;
787 val != 0
788 }
789 #[doc = "FLASH clocks enable during Sleep and Stop modes Set and cleared by software."]
790 #[inline(always)]
791 pub fn set_flashsmen(&mut self, val: bool) {
792 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
793 }
794 #[doc = "CRC clocks enable during Sleep and Stop modes Set and cleared by software."]
795 #[inline(always)]
796 pub const fn crcsmen(&self) -> bool {
797 let val = (self.0 >> 12usize) & 0x01;
798 val != 0
799 }
800 #[doc = "CRC clocks enable during Sleep and Stop modes Set and cleared by software."]
801 #[inline(always)]
802 pub fn set_crcsmen(&mut self, val: bool) {
803 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
804 }
805 #[doc = "JPEG clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
806 #[inline(always)]
807 pub const fn jpegsmen(&self) -> bool {
808 let val = (self.0 >> 15usize) & 0x01;
809 val != 0
810 }
811 #[doc = "JPEG clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
812 #[inline(always)]
813 pub fn set_jpegsmen(&mut self, val: bool) {
814 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
815 }
816 #[doc = "TSC clocks enable during Sleep and Stop modes Set and cleared by software."]
817 #[inline(always)]
818 pub const fn tscsmen(&self) -> bool {
819 let val = (self.0 >> 16usize) & 0x01;
820 val != 0
821 }
822 #[doc = "TSC clocks enable during Sleep and Stop modes Set and cleared by software."]
823 #[inline(always)]
824 pub fn set_tscsmen(&mut self, val: bool) {
825 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
826 }
827 #[doc = "RAMCFG clocks enable during Sleep and Stop modes Set and cleared by software."]
828 #[inline(always)]
829 pub const fn ramcfgsmen(&self) -> bool {
830 let val = (self.0 >> 17usize) & 0x01;
831 val != 0
832 }
833 #[doc = "RAMCFG clocks enable during Sleep and Stop modes Set and cleared by software."]
834 #[inline(always)]
835 pub fn set_ramcfgsmen(&mut self, val: bool) {
836 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
837 }
838 #[doc = "DMA2D clocks enable during Sleep and Stop modes Set and cleared by software."]
839 #[inline(always)]
840 pub const fn dma2dsmen(&self) -> bool {
841 let val = (self.0 >> 18usize) & 0x01;
842 val != 0
843 }
844 #[doc = "DMA2D clocks enable during Sleep and Stop modes Set and cleared by software."]
845 #[inline(always)]
846 pub fn set_dma2dsmen(&mut self, val: bool) {
847 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
848 }
849 #[doc = "GFXMMU clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
850 #[inline(always)]
851 pub const fn gfxmmusmen(&self) -> bool {
852 let val = (self.0 >> 19usize) & 0x01;
853 val != 0
854 }
855 #[doc = "GFXMMU clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
856 #[inline(always)]
857 pub fn set_gfxmmusmen(&mut self, val: bool) {
858 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
859 }
860 #[doc = "GPU2D clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
861 #[inline(always)]
862 pub const fn gpu2dsmen(&self) -> bool {
863 let val = (self.0 >> 20usize) & 0x01;
864 val != 0
865 }
866 #[doc = "GPU2D clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
867 #[inline(always)]
868 pub fn set_gpu2dsmen(&mut self, val: bool) {
869 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
870 }
871 #[doc = "DCACHE2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
872 #[inline(always)]
873 pub const fn dcache2smen(&self) -> bool {
874 let val = (self.0 >> 21usize) & 0x01;
875 val != 0
876 }
877 #[doc = "DCACHE2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
878 #[inline(always)]
879 pub fn set_dcache2smen(&mut self, val: bool) {
880 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
881 }
882 #[doc = "GTZC1 clocks enable during Sleep and Stop modes Set and cleared by software."]
883 #[inline(always)]
884 pub const fn gtzc1smen(&self) -> bool {
885 let val = (self.0 >> 24usize) & 0x01;
886 val != 0
887 }
888 #[doc = "GTZC1 clocks enable during Sleep and Stop modes Set and cleared by software."]
889 #[inline(always)]
890 pub fn set_gtzc1smen(&mut self, val: bool) {
891 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
892 }
893 #[doc = "BKPSRAM clocks enable during Sleep and Stop modes Set and cleared by software"]
894 #[inline(always)]
895 pub const fn bkpsramsmen(&self) -> bool {
896 let val = (self.0 >> 28usize) & 0x01;
897 val != 0
898 }
899 #[doc = "BKPSRAM clocks enable during Sleep and Stop modes Set and cleared by software"]
900 #[inline(always)]
901 pub fn set_bkpsramsmen(&mut self, val: bool) {
902 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
903 }
904 #[doc = "ICACHE clocks enable during Sleep and Stop modes Set and cleared by software."]
905 #[inline(always)]
906 pub const fn icachesmen(&self) -> bool {
907 let val = (self.0 >> 29usize) & 0x01;
908 val != 0
909 }
910 #[doc = "ICACHE clocks enable during Sleep and Stop modes Set and cleared by software."]
911 #[inline(always)]
912 pub fn set_icachesmen(&mut self, val: bool) {
913 self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
914 }
915 #[doc = "DCACHE1 clocks enable during Sleep and Stop modes Set and cleared by software."]
916 #[inline(always)]
917 pub const fn dcache1smen(&self) -> bool {
918 let val = (self.0 >> 30usize) & 0x01;
919 val != 0
920 }
921 #[doc = "DCACHE1 clocks enable during Sleep and Stop modes Set and cleared by software."]
922 #[inline(always)]
923 pub fn set_dcache1smen(&mut self, val: bool) {
924 self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
925 }
926 #[doc = "SRAM1 clocks enable during Sleep and Stop modes Set and cleared by software."]
927 #[inline(always)]
928 pub const fn sram1smen(&self) -> bool {
929 let val = (self.0 >> 31usize) & 0x01;
930 val != 0
931 }
932 #[doc = "SRAM1 clocks enable during Sleep and Stop modes Set and cleared by software."]
933 #[inline(always)]
934 pub fn set_sram1smen(&mut self, val: bool) {
935 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
936 }
937 }
938 impl Default for Ahb1smenr {
939 #[inline(always)]
940 fn default() -> Ahb1smenr {
941 Ahb1smenr(0)
942 }
943 }
944 impl core::fmt::Debug for Ahb1smenr {
945 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
946 f.debug_struct("Ahb1smenr")
947 .field("gpdma1smen", &self.gpdma1smen())
948 .field("cordicsmen", &self.cordicsmen())
949 .field("fmacsmen", &self.fmacsmen())
950 .field("mdf1smen", &self.mdf1smen())
951 .field("flashsmen", &self.flashsmen())
952 .field("crcsmen", &self.crcsmen())
953 .field("jpegsmen", &self.jpegsmen())
954 .field("tscsmen", &self.tscsmen())
955 .field("ramcfgsmen", &self.ramcfgsmen())
956 .field("dma2dsmen", &self.dma2dsmen())
957 .field("gfxmmusmen", &self.gfxmmusmen())
958 .field("gpu2dsmen", &self.gpu2dsmen())
959 .field("dcache2smen", &self.dcache2smen())
960 .field("gtzc1smen", &self.gtzc1smen())
961 .field("bkpsramsmen", &self.bkpsramsmen())
962 .field("icachesmen", &self.icachesmen())
963 .field("dcache1smen", &self.dcache1smen())
964 .field("sram1smen", &self.sram1smen())
965 .finish()
966 }
967 }
968 #[cfg(feature = "defmt")]
969 impl defmt::Format for Ahb1smenr {
970 fn format(&self, f: defmt::Formatter) {
971 #[derive(defmt :: Format)]
972 struct Ahb1smenr {
973 gpdma1smen: bool,
974 cordicsmen: bool,
975 fmacsmen: bool,
976 mdf1smen: bool,
977 flashsmen: bool,
978 crcsmen: bool,
979 jpegsmen: bool,
980 tscsmen: bool,
981 ramcfgsmen: bool,
982 dma2dsmen: bool,
983 gfxmmusmen: bool,
984 gpu2dsmen: bool,
985 dcache2smen: bool,
986 gtzc1smen: bool,
987 bkpsramsmen: bool,
988 icachesmen: bool,
989 dcache1smen: bool,
990 sram1smen: bool,
991 }
992 let proxy = Ahb1smenr {
993 gpdma1smen: self.gpdma1smen(),
994 cordicsmen: self.cordicsmen(),
995 fmacsmen: self.fmacsmen(),
996 mdf1smen: self.mdf1smen(),
997 flashsmen: self.flashsmen(),
998 crcsmen: self.crcsmen(),
999 jpegsmen: self.jpegsmen(),
1000 tscsmen: self.tscsmen(),
1001 ramcfgsmen: self.ramcfgsmen(),
1002 dma2dsmen: self.dma2dsmen(),
1003 gfxmmusmen: self.gfxmmusmen(),
1004 gpu2dsmen: self.gpu2dsmen(),
1005 dcache2smen: self.dcache2smen(),
1006 gtzc1smen: self.gtzc1smen(),
1007 bkpsramsmen: self.bkpsramsmen(),
1008 icachesmen: self.icachesmen(),
1009 dcache1smen: self.dcache1smen(),
1010 sram1smen: self.sram1smen(),
1011 };
1012 defmt::write!(f, "{}", proxy)
1013 }
1014 }
1015 #[doc = "RCC AHB2 peripheral clock enable register 1"]
1016 #[repr(transparent)]
1017 #[derive(Copy, Clone, Eq, PartialEq)]
1018 pub struct Ahb2enr1(pub u32);
1019 impl Ahb2enr1 {
1020 #[doc = "IO port A clock enable Set and cleared by software."]
1021 #[inline(always)]
1022 pub const fn gpioaen(&self) -> bool {
1023 let val = (self.0 >> 0usize) & 0x01;
1024 val != 0
1025 }
1026 #[doc = "IO port A clock enable Set and cleared by software."]
1027 #[inline(always)]
1028 pub fn set_gpioaen(&mut self, val: bool) {
1029 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1030 }
1031 #[doc = "IO port B clock enable Set and cleared by software."]
1032 #[inline(always)]
1033 pub const fn gpioben(&self) -> bool {
1034 let val = (self.0 >> 1usize) & 0x01;
1035 val != 0
1036 }
1037 #[doc = "IO port B clock enable Set and cleared by software."]
1038 #[inline(always)]
1039 pub fn set_gpioben(&mut self, val: bool) {
1040 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1041 }
1042 #[doc = "IO port C clock enable Set and cleared by software."]
1043 #[inline(always)]
1044 pub const fn gpiocen(&self) -> bool {
1045 let val = (self.0 >> 2usize) & 0x01;
1046 val != 0
1047 }
1048 #[doc = "IO port C clock enable Set and cleared by software."]
1049 #[inline(always)]
1050 pub fn set_gpiocen(&mut self, val: bool) {
1051 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1052 }
1053 #[doc = "IO port D clock enable Set and cleared by software."]
1054 #[inline(always)]
1055 pub const fn gpioden(&self) -> bool {
1056 let val = (self.0 >> 3usize) & 0x01;
1057 val != 0
1058 }
1059 #[doc = "IO port D clock enable Set and cleared by software."]
1060 #[inline(always)]
1061 pub fn set_gpioden(&mut self, val: bool) {
1062 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1063 }
1064 #[doc = "IO port E clock enable Set and cleared by software."]
1065 #[inline(always)]
1066 pub const fn gpioeen(&self) -> bool {
1067 let val = (self.0 >> 4usize) & 0x01;
1068 val != 0
1069 }
1070 #[doc = "IO port E clock enable Set and cleared by software."]
1071 #[inline(always)]
1072 pub fn set_gpioeen(&mut self, val: bool) {
1073 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1074 }
1075 #[doc = "IO port F clock enable Set and cleared by software."]
1076 #[inline(always)]
1077 pub const fn gpiofen(&self) -> bool {
1078 let val = (self.0 >> 5usize) & 0x01;
1079 val != 0
1080 }
1081 #[doc = "IO port F clock enable Set and cleared by software."]
1082 #[inline(always)]
1083 pub fn set_gpiofen(&mut self, val: bool) {
1084 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
1085 }
1086 #[doc = "IO port G clock enable Set and cleared by software."]
1087 #[inline(always)]
1088 pub const fn gpiogen(&self) -> bool {
1089 let val = (self.0 >> 6usize) & 0x01;
1090 val != 0
1091 }
1092 #[doc = "IO port G clock enable Set and cleared by software."]
1093 #[inline(always)]
1094 pub fn set_gpiogen(&mut self, val: bool) {
1095 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
1096 }
1097 #[doc = "IO port H clock enable Set and cleared by software."]
1098 #[inline(always)]
1099 pub const fn gpiohen(&self) -> bool {
1100 let val = (self.0 >> 7usize) & 0x01;
1101 val != 0
1102 }
1103 #[doc = "IO port H clock enable Set and cleared by software."]
1104 #[inline(always)]
1105 pub fn set_gpiohen(&mut self, val: bool) {
1106 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
1107 }
1108 #[doc = "IO port I clock enable Set and cleared by software."]
1109 #[inline(always)]
1110 pub const fn gpioien(&self) -> bool {
1111 let val = (self.0 >> 8usize) & 0x01;
1112 val != 0
1113 }
1114 #[doc = "IO port I clock enable Set and cleared by software."]
1115 #[inline(always)]
1116 pub fn set_gpioien(&mut self, val: bool) {
1117 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
1118 }
1119 #[doc = "I/O port J clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
1120 #[inline(always)]
1121 pub const fn gpiojen(&self) -> bool {
1122 let val = (self.0 >> 9usize) & 0x01;
1123 val != 0
1124 }
1125 #[doc = "I/O port J clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
1126 #[inline(always)]
1127 pub fn set_gpiojen(&mut self, val: bool) {
1128 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
1129 }
1130 #[doc = "ADC1 and ADC2 clock enable This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx."]
1131 #[inline(always)]
1132 pub const fn adc12en(&self) -> bool {
1133 let val = (self.0 >> 10usize) & 0x01;
1134 val != 0
1135 }
1136 #[doc = "ADC1 and ADC2 clock enable This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx."]
1137 #[inline(always)]
1138 pub fn set_adc12en(&mut self, val: bool) {
1139 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
1140 }
1141 #[doc = "DCMI and PSSI clock enable Set and cleared by software."]
1142 #[inline(always)]
1143 pub const fn dcmien(&self) -> bool {
1144 let val = (self.0 >> 12usize) & 0x01;
1145 val != 0
1146 }
1147 #[doc = "DCMI and PSSI clock enable Set and cleared by software."]
1148 #[inline(always)]
1149 pub fn set_dcmien(&mut self, val: bool) {
1150 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
1151 }
1152 #[doc = "OTG_FS clock enable Set and cleared by software."]
1153 #[inline(always)]
1154 pub const fn usb_otg_fsen(&self) -> bool {
1155 let val = (self.0 >> 14usize) & 0x01;
1156 val != 0
1157 }
1158 #[doc = "OTG_FS clock enable Set and cleared by software."]
1159 #[inline(always)]
1160 pub fn set_usb_otg_fsen(&mut self, val: bool) {
1161 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
1162 }
1163 #[doc = "OTG_HS clock enable Set and cleared by software."]
1164 #[inline(always)]
1165 pub const fn usb_otg_hsen(&self) -> bool {
1166 let val = (self.0 >> 14usize) & 0x01;
1167 val != 0
1168 }
1169 #[doc = "OTG_HS clock enable Set and cleared by software."]
1170 #[inline(always)]
1171 pub fn set_usb_otg_hsen(&mut self, val: bool) {
1172 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
1173 }
1174 #[doc = "OTG_HS PHY clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
1175 #[inline(always)]
1176 pub const fn usb_otg_hs_phyen(&self) -> bool {
1177 let val = (self.0 >> 15usize) & 0x01;
1178 val != 0
1179 }
1180 #[doc = "OTG_HS PHY clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
1181 #[inline(always)]
1182 pub fn set_usb_otg_hs_phyen(&mut self, val: bool) {
1183 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
1184 }
1185 #[doc = "AES clock enable Set and cleared by software."]
1186 #[inline(always)]
1187 pub const fn aesen(&self) -> bool {
1188 let val = (self.0 >> 16usize) & 0x01;
1189 val != 0
1190 }
1191 #[doc = "AES clock enable Set and cleared by software."]
1192 #[inline(always)]
1193 pub fn set_aesen(&mut self, val: bool) {
1194 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
1195 }
1196 #[doc = "HASH clock enable Set and cleared by software"]
1197 #[inline(always)]
1198 pub const fn hashen(&self) -> bool {
1199 let val = (self.0 >> 17usize) & 0x01;
1200 val != 0
1201 }
1202 #[doc = "HASH clock enable Set and cleared by software"]
1203 #[inline(always)]
1204 pub fn set_hashen(&mut self, val: bool) {
1205 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
1206 }
1207 #[doc = "RNG clock enable Set and cleared by software."]
1208 #[inline(always)]
1209 pub const fn rngen(&self) -> bool {
1210 let val = (self.0 >> 18usize) & 0x01;
1211 val != 0
1212 }
1213 #[doc = "RNG clock enable Set and cleared by software."]
1214 #[inline(always)]
1215 pub fn set_rngen(&mut self, val: bool) {
1216 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
1217 }
1218 #[doc = "PKA clock enable Set and cleared by software."]
1219 #[inline(always)]
1220 pub const fn pkaen(&self) -> bool {
1221 let val = (self.0 >> 19usize) & 0x01;
1222 val != 0
1223 }
1224 #[doc = "PKA clock enable Set and cleared by software."]
1225 #[inline(always)]
1226 pub fn set_pkaen(&mut self, val: bool) {
1227 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
1228 }
1229 #[doc = "SAES clock enable Set and cleared by software."]
1230 #[inline(always)]
1231 pub const fn saesen(&self) -> bool {
1232 let val = (self.0 >> 20usize) & 0x01;
1233 val != 0
1234 }
1235 #[doc = "SAES clock enable Set and cleared by software."]
1236 #[inline(always)]
1237 pub fn set_saesen(&mut self, val: bool) {
1238 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
1239 }
1240 #[doc = "OCTOSPIM clock enable Set and cleared by software."]
1241 #[inline(always)]
1242 pub const fn octospimen(&self) -> bool {
1243 let val = (self.0 >> 21usize) & 0x01;
1244 val != 0
1245 }
1246 #[doc = "OCTOSPIM clock enable Set and cleared by software."]
1247 #[inline(always)]
1248 pub fn set_octospimen(&mut self, val: bool) {
1249 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
1250 }
1251 #[doc = "OTFDEC1 clock enable Set and cleared by software."]
1252 #[inline(always)]
1253 pub const fn otfdec1en(&self) -> bool {
1254 let val = (self.0 >> 23usize) & 0x01;
1255 val != 0
1256 }
1257 #[doc = "OTFDEC1 clock enable Set and cleared by software."]
1258 #[inline(always)]
1259 pub fn set_otfdec1en(&mut self, val: bool) {
1260 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
1261 }
1262 #[doc = "OTFDEC2 clock enable Set and cleared by software."]
1263 #[inline(always)]
1264 pub const fn otfdec2en(&self) -> bool {
1265 let val = (self.0 >> 24usize) & 0x01;
1266 val != 0
1267 }
1268 #[doc = "OTFDEC2 clock enable Set and cleared by software."]
1269 #[inline(always)]
1270 pub fn set_otfdec2en(&mut self, val: bool) {
1271 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
1272 }
1273 #[doc = "SDMMC1 clock enable Set and cleared by software."]
1274 #[inline(always)]
1275 pub const fn sdmmc1en(&self) -> bool {
1276 let val = (self.0 >> 27usize) & 0x01;
1277 val != 0
1278 }
1279 #[doc = "SDMMC1 clock enable Set and cleared by software."]
1280 #[inline(always)]
1281 pub fn set_sdmmc1en(&mut self, val: bool) {
1282 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
1283 }
1284 #[doc = "SDMMC2 clock enable Set and cleared by software."]
1285 #[inline(always)]
1286 pub const fn sdmmc2en(&self) -> bool {
1287 let val = (self.0 >> 28usize) & 0x01;
1288 val != 0
1289 }
1290 #[doc = "SDMMC2 clock enable Set and cleared by software."]
1291 #[inline(always)]
1292 pub fn set_sdmmc2en(&mut self, val: bool) {
1293 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
1294 }
1295 #[doc = "SRAM2 clock enable Set and reset by software."]
1296 #[inline(always)]
1297 pub const fn sram2en(&self) -> bool {
1298 let val = (self.0 >> 30usize) & 0x01;
1299 val != 0
1300 }
1301 #[doc = "SRAM2 clock enable Set and reset by software."]
1302 #[inline(always)]
1303 pub fn set_sram2en(&mut self, val: bool) {
1304 self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
1305 }
1306 #[doc = "SRAM3 clock enable Set and reset by software."]
1307 #[inline(always)]
1308 pub const fn sram3en(&self) -> bool {
1309 let val = (self.0 >> 31usize) & 0x01;
1310 val != 0
1311 }
1312 #[doc = "SRAM3 clock enable Set and reset by software."]
1313 #[inline(always)]
1314 pub fn set_sram3en(&mut self, val: bool) {
1315 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
1316 }
1317 }
1318 impl Default for Ahb2enr1 {
1319 #[inline(always)]
1320 fn default() -> Ahb2enr1 {
1321 Ahb2enr1(0)
1322 }
1323 }
1324 impl core::fmt::Debug for Ahb2enr1 {
1325 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1326 f.debug_struct("Ahb2enr1")
1327 .field("gpioaen", &self.gpioaen())
1328 .field("gpioben", &self.gpioben())
1329 .field("gpiocen", &self.gpiocen())
1330 .field("gpioden", &self.gpioden())
1331 .field("gpioeen", &self.gpioeen())
1332 .field("gpiofen", &self.gpiofen())
1333 .field("gpiogen", &self.gpiogen())
1334 .field("gpiohen", &self.gpiohen())
1335 .field("gpioien", &self.gpioien())
1336 .field("gpiojen", &self.gpiojen())
1337 .field("adc12en", &self.adc12en())
1338 .field("dcmien", &self.dcmien())
1339 .field("usb_otg_fsen", &self.usb_otg_fsen())
1340 .field("usb_otg_hsen", &self.usb_otg_hsen())
1341 .field("usb_otg_hs_phyen", &self.usb_otg_hs_phyen())
1342 .field("aesen", &self.aesen())
1343 .field("hashen", &self.hashen())
1344 .field("rngen", &self.rngen())
1345 .field("pkaen", &self.pkaen())
1346 .field("saesen", &self.saesen())
1347 .field("octospimen", &self.octospimen())
1348 .field("otfdec1en", &self.otfdec1en())
1349 .field("otfdec2en", &self.otfdec2en())
1350 .field("sdmmc1en", &self.sdmmc1en())
1351 .field("sdmmc2en", &self.sdmmc2en())
1352 .field("sram2en", &self.sram2en())
1353 .field("sram3en", &self.sram3en())
1354 .finish()
1355 }
1356 }
1357 #[cfg(feature = "defmt")]
1358 impl defmt::Format for Ahb2enr1 {
1359 fn format(&self, f: defmt::Formatter) {
1360 #[derive(defmt :: Format)]
1361 struct Ahb2enr1 {
1362 gpioaen: bool,
1363 gpioben: bool,
1364 gpiocen: bool,
1365 gpioden: bool,
1366 gpioeen: bool,
1367 gpiofen: bool,
1368 gpiogen: bool,
1369 gpiohen: bool,
1370 gpioien: bool,
1371 gpiojen: bool,
1372 adc12en: bool,
1373 dcmien: bool,
1374 usb_otg_fsen: bool,
1375 usb_otg_hsen: bool,
1376 usb_otg_hs_phyen: bool,
1377 aesen: bool,
1378 hashen: bool,
1379 rngen: bool,
1380 pkaen: bool,
1381 saesen: bool,
1382 octospimen: bool,
1383 otfdec1en: bool,
1384 otfdec2en: bool,
1385 sdmmc1en: bool,
1386 sdmmc2en: bool,
1387 sram2en: bool,
1388 sram3en: bool,
1389 }
1390 let proxy = Ahb2enr1 {
1391 gpioaen: self.gpioaen(),
1392 gpioben: self.gpioben(),
1393 gpiocen: self.gpiocen(),
1394 gpioden: self.gpioden(),
1395 gpioeen: self.gpioeen(),
1396 gpiofen: self.gpiofen(),
1397 gpiogen: self.gpiogen(),
1398 gpiohen: self.gpiohen(),
1399 gpioien: self.gpioien(),
1400 gpiojen: self.gpiojen(),
1401 adc12en: self.adc12en(),
1402 dcmien: self.dcmien(),
1403 usb_otg_fsen: self.usb_otg_fsen(),
1404 usb_otg_hsen: self.usb_otg_hsen(),
1405 usb_otg_hs_phyen: self.usb_otg_hs_phyen(),
1406 aesen: self.aesen(),
1407 hashen: self.hashen(),
1408 rngen: self.rngen(),
1409 pkaen: self.pkaen(),
1410 saesen: self.saesen(),
1411 octospimen: self.octospimen(),
1412 otfdec1en: self.otfdec1en(),
1413 otfdec2en: self.otfdec2en(),
1414 sdmmc1en: self.sdmmc1en(),
1415 sdmmc2en: self.sdmmc2en(),
1416 sram2en: self.sram2en(),
1417 sram3en: self.sram3en(),
1418 };
1419 defmt::write!(f, "{}", proxy)
1420 }
1421 }
1422 #[doc = "RCC AHB2 peripheral clock enable register 2"]
1423 #[repr(transparent)]
1424 #[derive(Copy, Clone, Eq, PartialEq)]
1425 pub struct Ahb2enr2(pub u32);
1426 impl Ahb2enr2 {
1427 #[doc = "FSMC clock enable Set and cleared by software."]
1428 #[inline(always)]
1429 pub const fn fsmcen(&self) -> bool {
1430 let val = (self.0 >> 0usize) & 0x01;
1431 val != 0
1432 }
1433 #[doc = "FSMC clock enable Set and cleared by software."]
1434 #[inline(always)]
1435 pub fn set_fsmcen(&mut self, val: bool) {
1436 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1437 }
1438 #[doc = "OCTOSPI1 clock enable Set and cleared by software."]
1439 #[inline(always)]
1440 pub const fn octospi1en(&self) -> bool {
1441 let val = (self.0 >> 4usize) & 0x01;
1442 val != 0
1443 }
1444 #[doc = "OCTOSPI1 clock enable Set and cleared by software."]
1445 #[inline(always)]
1446 pub fn set_octospi1en(&mut self, val: bool) {
1447 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1448 }
1449 #[doc = "OCTOSPI2 clock enable Set and cleared by software."]
1450 #[inline(always)]
1451 pub const fn octospi2en(&self) -> bool {
1452 let val = (self.0 >> 8usize) & 0x01;
1453 val != 0
1454 }
1455 #[doc = "OCTOSPI2 clock enable Set and cleared by software."]
1456 #[inline(always)]
1457 pub fn set_octospi2en(&mut self, val: bool) {
1458 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
1459 }
1460 #[doc = "HSPI1 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
1461 #[inline(always)]
1462 pub const fn hspi1en(&self) -> bool {
1463 let val = (self.0 >> 12usize) & 0x01;
1464 val != 0
1465 }
1466 #[doc = "HSPI1 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
1467 #[inline(always)]
1468 pub fn set_hspi1en(&mut self, val: bool) {
1469 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
1470 }
1471 #[doc = "SRAM6 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
1472 #[inline(always)]
1473 pub const fn sram6en(&self) -> bool {
1474 let val = (self.0 >> 30usize) & 0x01;
1475 val != 0
1476 }
1477 #[doc = "SRAM6 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
1478 #[inline(always)]
1479 pub fn set_sram6en(&mut self, val: bool) {
1480 self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
1481 }
1482 #[doc = "SRAM5 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
1483 #[inline(always)]
1484 pub const fn sram5en(&self) -> bool {
1485 let val = (self.0 >> 31usize) & 0x01;
1486 val != 0
1487 }
1488 #[doc = "SRAM5 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
1489 #[inline(always)]
1490 pub fn set_sram5en(&mut self, val: bool) {
1491 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
1492 }
1493 }
1494 impl Default for Ahb2enr2 {
1495 #[inline(always)]
1496 fn default() -> Ahb2enr2 {
1497 Ahb2enr2(0)
1498 }
1499 }
1500 impl core::fmt::Debug for Ahb2enr2 {
1501 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1502 f.debug_struct("Ahb2enr2")
1503 .field("fsmcen", &self.fsmcen())
1504 .field("octospi1en", &self.octospi1en())
1505 .field("octospi2en", &self.octospi2en())
1506 .field("hspi1en", &self.hspi1en())
1507 .field("sram6en", &self.sram6en())
1508 .field("sram5en", &self.sram5en())
1509 .finish()
1510 }
1511 }
1512 #[cfg(feature = "defmt")]
1513 impl defmt::Format for Ahb2enr2 {
1514 fn format(&self, f: defmt::Formatter) {
1515 #[derive(defmt :: Format)]
1516 struct Ahb2enr2 {
1517 fsmcen: bool,
1518 octospi1en: bool,
1519 octospi2en: bool,
1520 hspi1en: bool,
1521 sram6en: bool,
1522 sram5en: bool,
1523 }
1524 let proxy = Ahb2enr2 {
1525 fsmcen: self.fsmcen(),
1526 octospi1en: self.octospi1en(),
1527 octospi2en: self.octospi2en(),
1528 hspi1en: self.hspi1en(),
1529 sram6en: self.sram6en(),
1530 sram5en: self.sram5en(),
1531 };
1532 defmt::write!(f, "{}", proxy)
1533 }
1534 }
1535 #[doc = "RCC AHB2 peripheral reset register 1"]
1536 #[repr(transparent)]
1537 #[derive(Copy, Clone, Eq, PartialEq)]
1538 pub struct Ahb2rstr1(pub u32);
1539 impl Ahb2rstr1 {
1540 #[doc = "IO port A reset Set and cleared by software."]
1541 #[inline(always)]
1542 pub const fn gpioarst(&self) -> bool {
1543 let val = (self.0 >> 0usize) & 0x01;
1544 val != 0
1545 }
1546 #[doc = "IO port A reset Set and cleared by software."]
1547 #[inline(always)]
1548 pub fn set_gpioarst(&mut self, val: bool) {
1549 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1550 }
1551 #[doc = "IO port B reset Set and cleared by software."]
1552 #[inline(always)]
1553 pub const fn gpiobrst(&self) -> bool {
1554 let val = (self.0 >> 1usize) & 0x01;
1555 val != 0
1556 }
1557 #[doc = "IO port B reset Set and cleared by software."]
1558 #[inline(always)]
1559 pub fn set_gpiobrst(&mut self, val: bool) {
1560 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1561 }
1562 #[doc = "IO port C reset Set and cleared by software."]
1563 #[inline(always)]
1564 pub const fn gpiocrst(&self) -> bool {
1565 let val = (self.0 >> 2usize) & 0x01;
1566 val != 0
1567 }
1568 #[doc = "IO port C reset Set and cleared by software."]
1569 #[inline(always)]
1570 pub fn set_gpiocrst(&mut self, val: bool) {
1571 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1572 }
1573 #[doc = "IO port D reset Set and cleared by software."]
1574 #[inline(always)]
1575 pub const fn gpiodrst(&self) -> bool {
1576 let val = (self.0 >> 3usize) & 0x01;
1577 val != 0
1578 }
1579 #[doc = "IO port D reset Set and cleared by software."]
1580 #[inline(always)]
1581 pub fn set_gpiodrst(&mut self, val: bool) {
1582 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1583 }
1584 #[doc = "IO port E reset Set and cleared by software."]
1585 #[inline(always)]
1586 pub const fn gpioerst(&self) -> bool {
1587 let val = (self.0 >> 4usize) & 0x01;
1588 val != 0
1589 }
1590 #[doc = "IO port E reset Set and cleared by software."]
1591 #[inline(always)]
1592 pub fn set_gpioerst(&mut self, val: bool) {
1593 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1594 }
1595 #[doc = "IO port F reset Set and cleared by software."]
1596 #[inline(always)]
1597 pub const fn gpiofrst(&self) -> bool {
1598 let val = (self.0 >> 5usize) & 0x01;
1599 val != 0
1600 }
1601 #[doc = "IO port F reset Set and cleared by software."]
1602 #[inline(always)]
1603 pub fn set_gpiofrst(&mut self, val: bool) {
1604 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
1605 }
1606 #[doc = "IO port G reset Set and cleared by software."]
1607 #[inline(always)]
1608 pub const fn gpiogrst(&self) -> bool {
1609 let val = (self.0 >> 6usize) & 0x01;
1610 val != 0
1611 }
1612 #[doc = "IO port G reset Set and cleared by software."]
1613 #[inline(always)]
1614 pub fn set_gpiogrst(&mut self, val: bool) {
1615 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
1616 }
1617 #[doc = "IO port H reset Set and cleared by software."]
1618 #[inline(always)]
1619 pub const fn gpiohrst(&self) -> bool {
1620 let val = (self.0 >> 7usize) & 0x01;
1621 val != 0
1622 }
1623 #[doc = "IO port H reset Set and cleared by software."]
1624 #[inline(always)]
1625 pub fn set_gpiohrst(&mut self, val: bool) {
1626 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
1627 }
1628 #[doc = "IO port I reset Set and cleared by software."]
1629 #[inline(always)]
1630 pub const fn gpioirst(&self) -> bool {
1631 let val = (self.0 >> 8usize) & 0x01;
1632 val != 0
1633 }
1634 #[doc = "IO port I reset Set and cleared by software."]
1635 #[inline(always)]
1636 pub fn set_gpioirst(&mut self, val: bool) {
1637 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
1638 }
1639 #[doc = "I/O port J reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
1640 #[inline(always)]
1641 pub const fn gpiojrst(&self) -> bool {
1642 let val = (self.0 >> 9usize) & 0x01;
1643 val != 0
1644 }
1645 #[doc = "I/O port J reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
1646 #[inline(always)]
1647 pub fn set_gpiojrst(&mut self, val: bool) {
1648 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
1649 }
1650 #[doc = "ADC1 and ADC2 reset This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx."]
1651 #[inline(always)]
1652 pub const fn adc12rst(&self) -> bool {
1653 let val = (self.0 >> 10usize) & 0x01;
1654 val != 0
1655 }
1656 #[doc = "ADC1 and ADC2 reset This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx."]
1657 #[inline(always)]
1658 pub fn set_adc12rst(&mut self, val: bool) {
1659 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
1660 }
1661 #[doc = "DCMI and PSSI reset Set and cleared by software."]
1662 #[inline(always)]
1663 pub const fn dcmirst(&self) -> bool {
1664 let val = (self.0 >> 12usize) & 0x01;
1665 val != 0
1666 }
1667 #[doc = "DCMI and PSSI reset Set and cleared by software."]
1668 #[inline(always)]
1669 pub fn set_dcmirst(&mut self, val: bool) {
1670 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
1671 }
1672 #[doc = "OTG_FS reset Set and cleared by software."]
1673 #[inline(always)]
1674 pub const fn usb_otg_fsrst(&self) -> bool {
1675 let val = (self.0 >> 14usize) & 0x01;
1676 val != 0
1677 }
1678 #[doc = "OTG_FS reset Set and cleared by software."]
1679 #[inline(always)]
1680 pub fn set_usb_otg_fsrst(&mut self, val: bool) {
1681 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
1682 }
1683 #[doc = "OTG_HS reset Set and cleared by software."]
1684 #[inline(always)]
1685 pub const fn usb_otg_hsrst(&self) -> bool {
1686 let val = (self.0 >> 14usize) & 0x01;
1687 val != 0
1688 }
1689 #[doc = "OTG_HS reset Set and cleared by software."]
1690 #[inline(always)]
1691 pub fn set_usb_otg_hsrst(&mut self, val: bool) {
1692 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
1693 }
1694 #[doc = "AES hardware accelerator reset Set and cleared by software."]
1695 #[inline(always)]
1696 pub const fn aesrst(&self) -> bool {
1697 let val = (self.0 >> 16usize) & 0x01;
1698 val != 0
1699 }
1700 #[doc = "AES hardware accelerator reset Set and cleared by software."]
1701 #[inline(always)]
1702 pub fn set_aesrst(&mut self, val: bool) {
1703 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
1704 }
1705 #[doc = "Hash reset Set and cleared by software."]
1706 #[inline(always)]
1707 pub const fn hashrst(&self) -> bool {
1708 let val = (self.0 >> 17usize) & 0x01;
1709 val != 0
1710 }
1711 #[doc = "Hash reset Set and cleared by software."]
1712 #[inline(always)]
1713 pub fn set_hashrst(&mut self, val: bool) {
1714 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
1715 }
1716 #[doc = "Random number generator reset Set and cleared by software."]
1717 #[inline(always)]
1718 pub const fn rngrst(&self) -> bool {
1719 let val = (self.0 >> 18usize) & 0x01;
1720 val != 0
1721 }
1722 #[doc = "Random number generator reset Set and cleared by software."]
1723 #[inline(always)]
1724 pub fn set_rngrst(&mut self, val: bool) {
1725 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
1726 }
1727 #[doc = "PKA reset Set and cleared by software."]
1728 #[inline(always)]
1729 pub const fn pkarst(&self) -> bool {
1730 let val = (self.0 >> 19usize) & 0x01;
1731 val != 0
1732 }
1733 #[doc = "PKA reset Set and cleared by software."]
1734 #[inline(always)]
1735 pub fn set_pkarst(&mut self, val: bool) {
1736 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
1737 }
1738 #[doc = "SAES hardware accelerator reset Set and cleared by software."]
1739 #[inline(always)]
1740 pub const fn saesrst(&self) -> bool {
1741 let val = (self.0 >> 20usize) & 0x01;
1742 val != 0
1743 }
1744 #[doc = "SAES hardware accelerator reset Set and cleared by software."]
1745 #[inline(always)]
1746 pub fn set_saesrst(&mut self, val: bool) {
1747 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
1748 }
1749 #[doc = "OCTOSPIM reset Set and cleared by software."]
1750 #[inline(always)]
1751 pub const fn octospimrst(&self) -> bool {
1752 let val = (self.0 >> 21usize) & 0x01;
1753 val != 0
1754 }
1755 #[doc = "OCTOSPIM reset Set and cleared by software."]
1756 #[inline(always)]
1757 pub fn set_octospimrst(&mut self, val: bool) {
1758 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
1759 }
1760 #[doc = "OTFDEC1 reset Set and cleared by software."]
1761 #[inline(always)]
1762 pub const fn otfdec1rst(&self) -> bool {
1763 let val = (self.0 >> 23usize) & 0x01;
1764 val != 0
1765 }
1766 #[doc = "OTFDEC1 reset Set and cleared by software."]
1767 #[inline(always)]
1768 pub fn set_otfdec1rst(&mut self, val: bool) {
1769 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
1770 }
1771 #[doc = "OTFDEC2 reset Set and cleared by software."]
1772 #[inline(always)]
1773 pub const fn otfdec2rst(&self) -> bool {
1774 let val = (self.0 >> 24usize) & 0x01;
1775 val != 0
1776 }
1777 #[doc = "OTFDEC2 reset Set and cleared by software."]
1778 #[inline(always)]
1779 pub fn set_otfdec2rst(&mut self, val: bool) {
1780 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
1781 }
1782 #[doc = "SDMMC1 reset Set and cleared by software."]
1783 #[inline(always)]
1784 pub const fn sdmmc1rst(&self) -> bool {
1785 let val = (self.0 >> 27usize) & 0x01;
1786 val != 0
1787 }
1788 #[doc = "SDMMC1 reset Set and cleared by software."]
1789 #[inline(always)]
1790 pub fn set_sdmmc1rst(&mut self, val: bool) {
1791 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
1792 }
1793 #[doc = "SDMMC2 reset Set and cleared by software."]
1794 #[inline(always)]
1795 pub const fn sdmmc2rst(&self) -> bool {
1796 let val = (self.0 >> 28usize) & 0x01;
1797 val != 0
1798 }
1799 #[doc = "SDMMC2 reset Set and cleared by software."]
1800 #[inline(always)]
1801 pub fn set_sdmmc2rst(&mut self, val: bool) {
1802 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
1803 }
1804 }
1805 impl Default for Ahb2rstr1 {
1806 #[inline(always)]
1807 fn default() -> Ahb2rstr1 {
1808 Ahb2rstr1(0)
1809 }
1810 }
1811 impl core::fmt::Debug for Ahb2rstr1 {
1812 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1813 f.debug_struct("Ahb2rstr1")
1814 .field("gpioarst", &self.gpioarst())
1815 .field("gpiobrst", &self.gpiobrst())
1816 .field("gpiocrst", &self.gpiocrst())
1817 .field("gpiodrst", &self.gpiodrst())
1818 .field("gpioerst", &self.gpioerst())
1819 .field("gpiofrst", &self.gpiofrst())
1820 .field("gpiogrst", &self.gpiogrst())
1821 .field("gpiohrst", &self.gpiohrst())
1822 .field("gpioirst", &self.gpioirst())
1823 .field("gpiojrst", &self.gpiojrst())
1824 .field("adc12rst", &self.adc12rst())
1825 .field("dcmirst", &self.dcmirst())
1826 .field("usb_otg_fsrst", &self.usb_otg_fsrst())
1827 .field("usb_otg_hsrst", &self.usb_otg_hsrst())
1828 .field("aesrst", &self.aesrst())
1829 .field("hashrst", &self.hashrst())
1830 .field("rngrst", &self.rngrst())
1831 .field("pkarst", &self.pkarst())
1832 .field("saesrst", &self.saesrst())
1833 .field("octospimrst", &self.octospimrst())
1834 .field("otfdec1rst", &self.otfdec1rst())
1835 .field("otfdec2rst", &self.otfdec2rst())
1836 .field("sdmmc1rst", &self.sdmmc1rst())
1837 .field("sdmmc2rst", &self.sdmmc2rst())
1838 .finish()
1839 }
1840 }
1841 #[cfg(feature = "defmt")]
1842 impl defmt::Format for Ahb2rstr1 {
1843 fn format(&self, f: defmt::Formatter) {
1844 #[derive(defmt :: Format)]
1845 struct Ahb2rstr1 {
1846 gpioarst: bool,
1847 gpiobrst: bool,
1848 gpiocrst: bool,
1849 gpiodrst: bool,
1850 gpioerst: bool,
1851 gpiofrst: bool,
1852 gpiogrst: bool,
1853 gpiohrst: bool,
1854 gpioirst: bool,
1855 gpiojrst: bool,
1856 adc12rst: bool,
1857 dcmirst: bool,
1858 usb_otg_fsrst: bool,
1859 usb_otg_hsrst: bool,
1860 aesrst: bool,
1861 hashrst: bool,
1862 rngrst: bool,
1863 pkarst: bool,
1864 saesrst: bool,
1865 octospimrst: bool,
1866 otfdec1rst: bool,
1867 otfdec2rst: bool,
1868 sdmmc1rst: bool,
1869 sdmmc2rst: bool,
1870 }
1871 let proxy = Ahb2rstr1 {
1872 gpioarst: self.gpioarst(),
1873 gpiobrst: self.gpiobrst(),
1874 gpiocrst: self.gpiocrst(),
1875 gpiodrst: self.gpiodrst(),
1876 gpioerst: self.gpioerst(),
1877 gpiofrst: self.gpiofrst(),
1878 gpiogrst: self.gpiogrst(),
1879 gpiohrst: self.gpiohrst(),
1880 gpioirst: self.gpioirst(),
1881 gpiojrst: self.gpiojrst(),
1882 adc12rst: self.adc12rst(),
1883 dcmirst: self.dcmirst(),
1884 usb_otg_fsrst: self.usb_otg_fsrst(),
1885 usb_otg_hsrst: self.usb_otg_hsrst(),
1886 aesrst: self.aesrst(),
1887 hashrst: self.hashrst(),
1888 rngrst: self.rngrst(),
1889 pkarst: self.pkarst(),
1890 saesrst: self.saesrst(),
1891 octospimrst: self.octospimrst(),
1892 otfdec1rst: self.otfdec1rst(),
1893 otfdec2rst: self.otfdec2rst(),
1894 sdmmc1rst: self.sdmmc1rst(),
1895 sdmmc2rst: self.sdmmc2rst(),
1896 };
1897 defmt::write!(f, "{}", proxy)
1898 }
1899 }
1900 #[doc = "RCC AHB2 peripheral reset register 2"]
1901 #[repr(transparent)]
1902 #[derive(Copy, Clone, Eq, PartialEq)]
1903 pub struct Ahb2rstr2(pub u32);
1904 impl Ahb2rstr2 {
1905 #[doc = "Flexible memory controller reset Set and cleared by software."]
1906 #[inline(always)]
1907 pub const fn fsmcrst(&self) -> bool {
1908 let val = (self.0 >> 0usize) & 0x01;
1909 val != 0
1910 }
1911 #[doc = "Flexible memory controller reset Set and cleared by software."]
1912 #[inline(always)]
1913 pub fn set_fsmcrst(&mut self, val: bool) {
1914 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1915 }
1916 #[doc = "OCTOSPI1 reset Set and cleared by software."]
1917 #[inline(always)]
1918 pub const fn octospi1rst(&self) -> bool {
1919 let val = (self.0 >> 4usize) & 0x01;
1920 val != 0
1921 }
1922 #[doc = "OCTOSPI1 reset Set and cleared by software."]
1923 #[inline(always)]
1924 pub fn set_octospi1rst(&mut self, val: bool) {
1925 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1926 }
1927 #[doc = "OCTOSPI2 reset Set and cleared by software."]
1928 #[inline(always)]
1929 pub const fn octospi2rst(&self) -> bool {
1930 let val = (self.0 >> 8usize) & 0x01;
1931 val != 0
1932 }
1933 #[doc = "OCTOSPI2 reset Set and cleared by software."]
1934 #[inline(always)]
1935 pub fn set_octospi2rst(&mut self, val: bool) {
1936 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
1937 }
1938 #[doc = "HSPI1 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
1939 #[inline(always)]
1940 pub const fn hspi1rst(&self) -> bool {
1941 let val = (self.0 >> 12usize) & 0x01;
1942 val != 0
1943 }
1944 #[doc = "HSPI1 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
1945 #[inline(always)]
1946 pub fn set_hspi1rst(&mut self, val: bool) {
1947 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
1948 }
1949 }
1950 impl Default for Ahb2rstr2 {
1951 #[inline(always)]
1952 fn default() -> Ahb2rstr2 {
1953 Ahb2rstr2(0)
1954 }
1955 }
1956 impl core::fmt::Debug for Ahb2rstr2 {
1957 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1958 f.debug_struct("Ahb2rstr2")
1959 .field("fsmcrst", &self.fsmcrst())
1960 .field("octospi1rst", &self.octospi1rst())
1961 .field("octospi2rst", &self.octospi2rst())
1962 .field("hspi1rst", &self.hspi1rst())
1963 .finish()
1964 }
1965 }
1966 #[cfg(feature = "defmt")]
1967 impl defmt::Format for Ahb2rstr2 {
1968 fn format(&self, f: defmt::Formatter) {
1969 #[derive(defmt :: Format)]
1970 struct Ahb2rstr2 {
1971 fsmcrst: bool,
1972 octospi1rst: bool,
1973 octospi2rst: bool,
1974 hspi1rst: bool,
1975 }
1976 let proxy = Ahb2rstr2 {
1977 fsmcrst: self.fsmcrst(),
1978 octospi1rst: self.octospi1rst(),
1979 octospi2rst: self.octospi2rst(),
1980 hspi1rst: self.hspi1rst(),
1981 };
1982 defmt::write!(f, "{}", proxy)
1983 }
1984 }
1985 #[doc = "RCC AHB2 peripheral clocks enable in Sleep and Stop modes register 1"]
1986 #[repr(transparent)]
1987 #[derive(Copy, Clone, Eq, PartialEq)]
1988 pub struct Ahb2smenr1(pub u32);
1989 impl Ahb2smenr1 {
1990 #[doc = "IO port A clocks enable during Sleep and Stop modes Set and cleared by software."]
1991 #[inline(always)]
1992 pub const fn gpioasmen(&self) -> bool {
1993 let val = (self.0 >> 0usize) & 0x01;
1994 val != 0
1995 }
1996 #[doc = "IO port A clocks enable during Sleep and Stop modes Set and cleared by software."]
1997 #[inline(always)]
1998 pub fn set_gpioasmen(&mut self, val: bool) {
1999 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2000 }
2001 #[doc = "IO port B clocks enable during Sleep and Stop modes Set and cleared by software."]
2002 #[inline(always)]
2003 pub const fn gpiobsmen(&self) -> bool {
2004 let val = (self.0 >> 1usize) & 0x01;
2005 val != 0
2006 }
2007 #[doc = "IO port B clocks enable during Sleep and Stop modes Set and cleared by software."]
2008 #[inline(always)]
2009 pub fn set_gpiobsmen(&mut self, val: bool) {
2010 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
2011 }
2012 #[doc = "IO port C clocks enable during Sleep and Stop modes Set and cleared by software."]
2013 #[inline(always)]
2014 pub const fn gpiocsmen(&self) -> bool {
2015 let val = (self.0 >> 2usize) & 0x01;
2016 val != 0
2017 }
2018 #[doc = "IO port C clocks enable during Sleep and Stop modes Set and cleared by software."]
2019 #[inline(always)]
2020 pub fn set_gpiocsmen(&mut self, val: bool) {
2021 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
2022 }
2023 #[doc = "IO port D clocks enable during Sleep and Stop modes Set and cleared by software."]
2024 #[inline(always)]
2025 pub const fn gpiodsmen(&self) -> bool {
2026 let val = (self.0 >> 3usize) & 0x01;
2027 val != 0
2028 }
2029 #[doc = "IO port D clocks enable during Sleep and Stop modes Set and cleared by software."]
2030 #[inline(always)]
2031 pub fn set_gpiodsmen(&mut self, val: bool) {
2032 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
2033 }
2034 #[doc = "IO port E clocks enable during Sleep and Stop modes Set and cleared by software."]
2035 #[inline(always)]
2036 pub const fn gpioesmen(&self) -> bool {
2037 let val = (self.0 >> 4usize) & 0x01;
2038 val != 0
2039 }
2040 #[doc = "IO port E clocks enable during Sleep and Stop modes Set and cleared by software."]
2041 #[inline(always)]
2042 pub fn set_gpioesmen(&mut self, val: bool) {
2043 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
2044 }
2045 #[doc = "IO port F clocks enable during Sleep and Stop modes Set and cleared by software."]
2046 #[inline(always)]
2047 pub const fn gpiofsmen(&self) -> bool {
2048 let val = (self.0 >> 5usize) & 0x01;
2049 val != 0
2050 }
2051 #[doc = "IO port F clocks enable during Sleep and Stop modes Set and cleared by software."]
2052 #[inline(always)]
2053 pub fn set_gpiofsmen(&mut self, val: bool) {
2054 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
2055 }
2056 #[doc = "IO port G clocks enable during Sleep and Stop modes Set and cleared by software."]
2057 #[inline(always)]
2058 pub const fn gpiogsmen(&self) -> bool {
2059 let val = (self.0 >> 6usize) & 0x01;
2060 val != 0
2061 }
2062 #[doc = "IO port G clocks enable during Sleep and Stop modes Set and cleared by software."]
2063 #[inline(always)]
2064 pub fn set_gpiogsmen(&mut self, val: bool) {
2065 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
2066 }
2067 #[doc = "IO port H clocks enable during Sleep and Stop modes Set and cleared by software."]
2068 #[inline(always)]
2069 pub const fn gpiohsmen(&self) -> bool {
2070 let val = (self.0 >> 7usize) & 0x01;
2071 val != 0
2072 }
2073 #[doc = "IO port H clocks enable during Sleep and Stop modes Set and cleared by software."]
2074 #[inline(always)]
2075 pub fn set_gpiohsmen(&mut self, val: bool) {
2076 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
2077 }
2078 #[doc = "IO port I clocks enable during Sleep and Stop modes Set and cleared by software."]
2079 #[inline(always)]
2080 pub const fn gpioismen(&self) -> bool {
2081 let val = (self.0 >> 8usize) & 0x01;
2082 val != 0
2083 }
2084 #[doc = "IO port I clocks enable during Sleep and Stop modes Set and cleared by software."]
2085 #[inline(always)]
2086 pub fn set_gpioismen(&mut self, val: bool) {
2087 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
2088 }
2089 #[doc = "I/O port J clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
2090 #[inline(always)]
2091 pub const fn gpiojsmen(&self) -> bool {
2092 let val = (self.0 >> 9usize) & 0x01;
2093 val != 0
2094 }
2095 #[doc = "I/O port J clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
2096 #[inline(always)]
2097 pub fn set_gpiojsmen(&mut self, val: bool) {
2098 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
2099 }
2100 #[doc = "ADC1 and ADC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585 and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx."]
2101 #[inline(always)]
2102 pub const fn adc12smen(&self) -> bool {
2103 let val = (self.0 >> 10usize) & 0x01;
2104 val != 0
2105 }
2106 #[doc = "ADC1 and ADC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585 and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx."]
2107 #[inline(always)]
2108 pub fn set_adc12smen(&mut self, val: bool) {
2109 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
2110 }
2111 #[doc = "DCMI and PSSI clocks enable during Sleep and Stop modes Set and cleared by software."]
2112 #[inline(always)]
2113 pub const fn dcmismen(&self) -> bool {
2114 let val = (self.0 >> 12usize) & 0x01;
2115 val != 0
2116 }
2117 #[doc = "DCMI and PSSI clocks enable during Sleep and Stop modes Set and cleared by software."]
2118 #[inline(always)]
2119 pub fn set_dcmismen(&mut self, val: bool) {
2120 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
2121 }
2122 #[doc = "OTG_FS clocks enable during Sleep and Stop modes Set and cleared by software."]
2123 #[inline(always)]
2124 pub const fn usb_otg_fssmen(&self) -> bool {
2125 let val = (self.0 >> 14usize) & 0x01;
2126 val != 0
2127 }
2128 #[doc = "OTG_FS clocks enable during Sleep and Stop modes Set and cleared by software."]
2129 #[inline(always)]
2130 pub fn set_usb_otg_fssmen(&mut self, val: bool) {
2131 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
2132 }
2133 #[doc = "OTG_HS clocks enable during Sleep and Stop modes Set and cleared by software."]
2134 #[inline(always)]
2135 pub const fn usb_otg_hssmen(&self) -> bool {
2136 let val = (self.0 >> 14usize) & 0x01;
2137 val != 0
2138 }
2139 #[doc = "OTG_HS clocks enable during Sleep and Stop modes Set and cleared by software."]
2140 #[inline(always)]
2141 pub fn set_usb_otg_hssmen(&mut self, val: bool) {
2142 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
2143 }
2144 #[doc = "OTG_HS PHY clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
2145 #[inline(always)]
2146 pub const fn usb_otg_hs_physmen(&self) -> bool {
2147 let val = (self.0 >> 15usize) & 0x01;
2148 val != 0
2149 }
2150 #[doc = "OTG_HS PHY clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
2151 #[inline(always)]
2152 pub fn set_usb_otg_hs_physmen(&mut self, val: bool) {
2153 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
2154 }
2155 #[doc = "AES clock enable during Sleep and Stop modes Set and cleared by software"]
2156 #[inline(always)]
2157 pub const fn aessmen(&self) -> bool {
2158 let val = (self.0 >> 16usize) & 0x01;
2159 val != 0
2160 }
2161 #[doc = "AES clock enable during Sleep and Stop modes Set and cleared by software"]
2162 #[inline(always)]
2163 pub fn set_aessmen(&mut self, val: bool) {
2164 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
2165 }
2166 #[doc = "HASH clock enable during Sleep and Stop modes Set and cleared by software"]
2167 #[inline(always)]
2168 pub const fn hashsmen(&self) -> bool {
2169 let val = (self.0 >> 17usize) & 0x01;
2170 val != 0
2171 }
2172 #[doc = "HASH clock enable during Sleep and Stop modes Set and cleared by software"]
2173 #[inline(always)]
2174 pub fn set_hashsmen(&mut self, val: bool) {
2175 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
2176 }
2177 #[doc = "Random number generator (RNG) clocks enable during Sleep and Stop modes Set and cleared by software."]
2178 #[inline(always)]
2179 pub const fn rngsmen(&self) -> bool {
2180 let val = (self.0 >> 18usize) & 0x01;
2181 val != 0
2182 }
2183 #[doc = "Random number generator (RNG) clocks enable during Sleep and Stop modes Set and cleared by software."]
2184 #[inline(always)]
2185 pub fn set_rngsmen(&mut self, val: bool) {
2186 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
2187 }
2188 #[doc = "PKA clocks enable during Sleep and Stop modes Set and cleared by software."]
2189 #[inline(always)]
2190 pub const fn pkasmen(&self) -> bool {
2191 let val = (self.0 >> 19usize) & 0x01;
2192 val != 0
2193 }
2194 #[doc = "PKA clocks enable during Sleep and Stop modes Set and cleared by software."]
2195 #[inline(always)]
2196 pub fn set_pkasmen(&mut self, val: bool) {
2197 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
2198 }
2199 #[doc = "SAES accelerator clocks enable during Sleep and Stop modes Set and cleared by software."]
2200 #[inline(always)]
2201 pub const fn saessmen(&self) -> bool {
2202 let val = (self.0 >> 20usize) & 0x01;
2203 val != 0
2204 }
2205 #[doc = "SAES accelerator clocks enable during Sleep and Stop modes Set and cleared by software."]
2206 #[inline(always)]
2207 pub fn set_saessmen(&mut self, val: bool) {
2208 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
2209 }
2210 #[doc = "OCTOSPIM clocks enable during Sleep and Stop modes Set and cleared by software."]
2211 #[inline(always)]
2212 pub const fn octospimsmen(&self) -> bool {
2213 let val = (self.0 >> 21usize) & 0x01;
2214 val != 0
2215 }
2216 #[doc = "OCTOSPIM clocks enable during Sleep and Stop modes Set and cleared by software."]
2217 #[inline(always)]
2218 pub fn set_octospimsmen(&mut self, val: bool) {
2219 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
2220 }
2221 #[doc = "OTFDEC1 clocks enable during Sleep and Stop modes Set and cleared by software."]
2222 #[inline(always)]
2223 pub const fn otfdec1smen(&self) -> bool {
2224 let val = (self.0 >> 23usize) & 0x01;
2225 val != 0
2226 }
2227 #[doc = "OTFDEC1 clocks enable during Sleep and Stop modes Set and cleared by software."]
2228 #[inline(always)]
2229 pub fn set_otfdec1smen(&mut self, val: bool) {
2230 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
2231 }
2232 #[doc = "OTFDEC2 clocks enable during Sleep and Stop modes Set and cleared by software."]
2233 #[inline(always)]
2234 pub const fn otfdec2smen(&self) -> bool {
2235 let val = (self.0 >> 24usize) & 0x01;
2236 val != 0
2237 }
2238 #[doc = "OTFDEC2 clocks enable during Sleep and Stop modes Set and cleared by software."]
2239 #[inline(always)]
2240 pub fn set_otfdec2smen(&mut self, val: bool) {
2241 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
2242 }
2243 #[doc = "SDMMC1 clocks enable during Sleep and Stop modes Set and cleared by software."]
2244 #[inline(always)]
2245 pub const fn sdmmc1smen(&self) -> bool {
2246 let val = (self.0 >> 27usize) & 0x01;
2247 val != 0
2248 }
2249 #[doc = "SDMMC1 clocks enable during Sleep and Stop modes Set and cleared by software."]
2250 #[inline(always)]
2251 pub fn set_sdmmc1smen(&mut self, val: bool) {
2252 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
2253 }
2254 #[doc = "SDMMC2 clocks enable during Sleep and Stop modes Set and cleared by software."]
2255 #[inline(always)]
2256 pub const fn sdmmc2smen(&self) -> bool {
2257 let val = (self.0 >> 28usize) & 0x01;
2258 val != 0
2259 }
2260 #[doc = "SDMMC2 clocks enable during Sleep and Stop modes Set and cleared by software."]
2261 #[inline(always)]
2262 pub fn set_sdmmc2smen(&mut self, val: bool) {
2263 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
2264 }
2265 #[doc = "SRAM2 clocks enable during Sleep and Stop modes Set and cleared by software."]
2266 #[inline(always)]
2267 pub const fn sram2smen(&self) -> bool {
2268 let val = (self.0 >> 30usize) & 0x01;
2269 val != 0
2270 }
2271 #[doc = "SRAM2 clocks enable during Sleep and Stop modes Set and cleared by software."]
2272 #[inline(always)]
2273 pub fn set_sram2smen(&mut self, val: bool) {
2274 self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
2275 }
2276 #[doc = "SRAM3 clocks enable during Sleep and Stop modes Set and cleared by software."]
2277 #[inline(always)]
2278 pub const fn sram3smen(&self) -> bool {
2279 let val = (self.0 >> 31usize) & 0x01;
2280 val != 0
2281 }
2282 #[doc = "SRAM3 clocks enable during Sleep and Stop modes Set and cleared by software."]
2283 #[inline(always)]
2284 pub fn set_sram3smen(&mut self, val: bool) {
2285 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
2286 }
2287 }
2288 impl Default for Ahb2smenr1 {
2289 #[inline(always)]
2290 fn default() -> Ahb2smenr1 {
2291 Ahb2smenr1(0)
2292 }
2293 }
2294 impl core::fmt::Debug for Ahb2smenr1 {
2295 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2296 f.debug_struct("Ahb2smenr1")
2297 .field("gpioasmen", &self.gpioasmen())
2298 .field("gpiobsmen", &self.gpiobsmen())
2299 .field("gpiocsmen", &self.gpiocsmen())
2300 .field("gpiodsmen", &self.gpiodsmen())
2301 .field("gpioesmen", &self.gpioesmen())
2302 .field("gpiofsmen", &self.gpiofsmen())
2303 .field("gpiogsmen", &self.gpiogsmen())
2304 .field("gpiohsmen", &self.gpiohsmen())
2305 .field("gpioismen", &self.gpioismen())
2306 .field("gpiojsmen", &self.gpiojsmen())
2307 .field("adc12smen", &self.adc12smen())
2308 .field("dcmismen", &self.dcmismen())
2309 .field("usb_otg_fssmen", &self.usb_otg_fssmen())
2310 .field("usb_otg_hssmen", &self.usb_otg_hssmen())
2311 .field("usb_otg_hs_physmen", &self.usb_otg_hs_physmen())
2312 .field("aessmen", &self.aessmen())
2313 .field("hashsmen", &self.hashsmen())
2314 .field("rngsmen", &self.rngsmen())
2315 .field("pkasmen", &self.pkasmen())
2316 .field("saessmen", &self.saessmen())
2317 .field("octospimsmen", &self.octospimsmen())
2318 .field("otfdec1smen", &self.otfdec1smen())
2319 .field("otfdec2smen", &self.otfdec2smen())
2320 .field("sdmmc1smen", &self.sdmmc1smen())
2321 .field("sdmmc2smen", &self.sdmmc2smen())
2322 .field("sram2smen", &self.sram2smen())
2323 .field("sram3smen", &self.sram3smen())
2324 .finish()
2325 }
2326 }
2327 #[cfg(feature = "defmt")]
2328 impl defmt::Format for Ahb2smenr1 {
2329 fn format(&self, f: defmt::Formatter) {
2330 #[derive(defmt :: Format)]
2331 struct Ahb2smenr1 {
2332 gpioasmen: bool,
2333 gpiobsmen: bool,
2334 gpiocsmen: bool,
2335 gpiodsmen: bool,
2336 gpioesmen: bool,
2337 gpiofsmen: bool,
2338 gpiogsmen: bool,
2339 gpiohsmen: bool,
2340 gpioismen: bool,
2341 gpiojsmen: bool,
2342 adc12smen: bool,
2343 dcmismen: bool,
2344 usb_otg_fssmen: bool,
2345 usb_otg_hssmen: bool,
2346 usb_otg_hs_physmen: bool,
2347 aessmen: bool,
2348 hashsmen: bool,
2349 rngsmen: bool,
2350 pkasmen: bool,
2351 saessmen: bool,
2352 octospimsmen: bool,
2353 otfdec1smen: bool,
2354 otfdec2smen: bool,
2355 sdmmc1smen: bool,
2356 sdmmc2smen: bool,
2357 sram2smen: bool,
2358 sram3smen: bool,
2359 }
2360 let proxy = Ahb2smenr1 {
2361 gpioasmen: self.gpioasmen(),
2362 gpiobsmen: self.gpiobsmen(),
2363 gpiocsmen: self.gpiocsmen(),
2364 gpiodsmen: self.gpiodsmen(),
2365 gpioesmen: self.gpioesmen(),
2366 gpiofsmen: self.gpiofsmen(),
2367 gpiogsmen: self.gpiogsmen(),
2368 gpiohsmen: self.gpiohsmen(),
2369 gpioismen: self.gpioismen(),
2370 gpiojsmen: self.gpiojsmen(),
2371 adc12smen: self.adc12smen(),
2372 dcmismen: self.dcmismen(),
2373 usb_otg_fssmen: self.usb_otg_fssmen(),
2374 usb_otg_hssmen: self.usb_otg_hssmen(),
2375 usb_otg_hs_physmen: self.usb_otg_hs_physmen(),
2376 aessmen: self.aessmen(),
2377 hashsmen: self.hashsmen(),
2378 rngsmen: self.rngsmen(),
2379 pkasmen: self.pkasmen(),
2380 saessmen: self.saessmen(),
2381 octospimsmen: self.octospimsmen(),
2382 otfdec1smen: self.otfdec1smen(),
2383 otfdec2smen: self.otfdec2smen(),
2384 sdmmc1smen: self.sdmmc1smen(),
2385 sdmmc2smen: self.sdmmc2smen(),
2386 sram2smen: self.sram2smen(),
2387 sram3smen: self.sram3smen(),
2388 };
2389 defmt::write!(f, "{}", proxy)
2390 }
2391 }
2392 #[doc = "RCC AHB2 peripheral clocks enable in Sleep and Stop modes register 2"]
2393 #[repr(transparent)]
2394 #[derive(Copy, Clone, Eq, PartialEq)]
2395 pub struct Ahb2smenr2(pub u32);
2396 impl Ahb2smenr2 {
2397 #[doc = "FSMC clocks enable during Sleep and Stop modes Set and cleared by software."]
2398 #[inline(always)]
2399 pub const fn fsmcsmen(&self) -> bool {
2400 let val = (self.0 >> 0usize) & 0x01;
2401 val != 0
2402 }
2403 #[doc = "FSMC clocks enable during Sleep and Stop modes Set and cleared by software."]
2404 #[inline(always)]
2405 pub fn set_fsmcsmen(&mut self, val: bool) {
2406 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2407 }
2408 #[doc = "OCTOSPI1 clocks enable during Sleep and Stop modes Set and cleared by software."]
2409 #[inline(always)]
2410 pub const fn octospi1smen(&self) -> bool {
2411 let val = (self.0 >> 4usize) & 0x01;
2412 val != 0
2413 }
2414 #[doc = "OCTOSPI1 clocks enable during Sleep and Stop modes Set and cleared by software."]
2415 #[inline(always)]
2416 pub fn set_octospi1smen(&mut self, val: bool) {
2417 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
2418 }
2419 #[doc = "OCTOSPI2 clocks enable during Sleep and Stop modes Set and cleared by software."]
2420 #[inline(always)]
2421 pub const fn octospi2smen(&self) -> bool {
2422 let val = (self.0 >> 8usize) & 0x01;
2423 val != 0
2424 }
2425 #[doc = "OCTOSPI2 clocks enable during Sleep and Stop modes Set and cleared by software."]
2426 #[inline(always)]
2427 pub fn set_octospi2smen(&mut self, val: bool) {
2428 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
2429 }
2430 #[doc = "HSPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
2431 #[inline(always)]
2432 pub const fn hspi1smen(&self) -> bool {
2433 let val = (self.0 >> 12usize) & 0x01;
2434 val != 0
2435 }
2436 #[doc = "HSPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
2437 #[inline(always)]
2438 pub fn set_hspi1smen(&mut self, val: bool) {
2439 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
2440 }
2441 #[doc = "SRAM6 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
2442 #[inline(always)]
2443 pub const fn sram6smen(&self) -> bool {
2444 let val = (self.0 >> 30usize) & 0x01;
2445 val != 0
2446 }
2447 #[doc = "SRAM6 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
2448 #[inline(always)]
2449 pub fn set_sram6smen(&mut self, val: bool) {
2450 self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
2451 }
2452 #[doc = "SRAM5 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
2453 #[inline(always)]
2454 pub const fn sram5smen(&self) -> bool {
2455 let val = (self.0 >> 31usize) & 0x01;
2456 val != 0
2457 }
2458 #[doc = "SRAM5 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
2459 #[inline(always)]
2460 pub fn set_sram5smen(&mut self, val: bool) {
2461 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
2462 }
2463 }
2464 impl Default for Ahb2smenr2 {
2465 #[inline(always)]
2466 fn default() -> Ahb2smenr2 {
2467 Ahb2smenr2(0)
2468 }
2469 }
2470 impl core::fmt::Debug for Ahb2smenr2 {
2471 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2472 f.debug_struct("Ahb2smenr2")
2473 .field("fsmcsmen", &self.fsmcsmen())
2474 .field("octospi1smen", &self.octospi1smen())
2475 .field("octospi2smen", &self.octospi2smen())
2476 .field("hspi1smen", &self.hspi1smen())
2477 .field("sram6smen", &self.sram6smen())
2478 .field("sram5smen", &self.sram5smen())
2479 .finish()
2480 }
2481 }
2482 #[cfg(feature = "defmt")]
2483 impl defmt::Format for Ahb2smenr2 {
2484 fn format(&self, f: defmt::Formatter) {
2485 #[derive(defmt :: Format)]
2486 struct Ahb2smenr2 {
2487 fsmcsmen: bool,
2488 octospi1smen: bool,
2489 octospi2smen: bool,
2490 hspi1smen: bool,
2491 sram6smen: bool,
2492 sram5smen: bool,
2493 }
2494 let proxy = Ahb2smenr2 {
2495 fsmcsmen: self.fsmcsmen(),
2496 octospi1smen: self.octospi1smen(),
2497 octospi2smen: self.octospi2smen(),
2498 hspi1smen: self.hspi1smen(),
2499 sram6smen: self.sram6smen(),
2500 sram5smen: self.sram5smen(),
2501 };
2502 defmt::write!(f, "{}", proxy)
2503 }
2504 }
2505 #[doc = "RCC AHB3 peripheral clock enable register"]
2506 #[repr(transparent)]
2507 #[derive(Copy, Clone, Eq, PartialEq)]
2508 pub struct Ahb3enr(pub u32);
2509 impl Ahb3enr {
2510 #[doc = "LPGPIO1 enable Set and cleared by software."]
2511 #[inline(always)]
2512 pub const fn lpgpio1en(&self) -> bool {
2513 let val = (self.0 >> 0usize) & 0x01;
2514 val != 0
2515 }
2516 #[doc = "LPGPIO1 enable Set and cleared by software."]
2517 #[inline(always)]
2518 pub fn set_lpgpio1en(&mut self, val: bool) {
2519 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2520 }
2521 #[doc = "PWR clock enable Set and cleared by software."]
2522 #[inline(always)]
2523 pub const fn pwren(&self) -> bool {
2524 let val = (self.0 >> 2usize) & 0x01;
2525 val != 0
2526 }
2527 #[doc = "PWR clock enable Set and cleared by software."]
2528 #[inline(always)]
2529 pub fn set_pwren(&mut self, val: bool) {
2530 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
2531 }
2532 #[doc = "ADC4 clock enable Set and cleared by software."]
2533 #[inline(always)]
2534 pub const fn adc4en(&self) -> bool {
2535 let val = (self.0 >> 5usize) & 0x01;
2536 val != 0
2537 }
2538 #[doc = "ADC4 clock enable Set and cleared by software."]
2539 #[inline(always)]
2540 pub fn set_adc4en(&mut self, val: bool) {
2541 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
2542 }
2543 #[doc = "DAC1 clock enable Set and cleared by software."]
2544 #[inline(always)]
2545 pub const fn dac1en(&self) -> bool {
2546 let val = (self.0 >> 6usize) & 0x01;
2547 val != 0
2548 }
2549 #[doc = "DAC1 clock enable Set and cleared by software."]
2550 #[inline(always)]
2551 pub fn set_dac1en(&mut self, val: bool) {
2552 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
2553 }
2554 #[doc = "LPDMA1 clock enable Set and cleared by software."]
2555 #[inline(always)]
2556 pub const fn lpdma1en(&self) -> bool {
2557 let val = (self.0 >> 9usize) & 0x01;
2558 val != 0
2559 }
2560 #[doc = "LPDMA1 clock enable Set and cleared by software."]
2561 #[inline(always)]
2562 pub fn set_lpdma1en(&mut self, val: bool) {
2563 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
2564 }
2565 #[doc = "ADF1 clock enable Set and cleared by software."]
2566 #[inline(always)]
2567 pub const fn adf1en(&self) -> bool {
2568 let val = (self.0 >> 10usize) & 0x01;
2569 val != 0
2570 }
2571 #[doc = "ADF1 clock enable Set and cleared by software."]
2572 #[inline(always)]
2573 pub fn set_adf1en(&mut self, val: bool) {
2574 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
2575 }
2576 #[doc = "GTZC2 clock enable Set and cleared by software."]
2577 #[inline(always)]
2578 pub const fn gtzc2en(&self) -> bool {
2579 let val = (self.0 >> 12usize) & 0x01;
2580 val != 0
2581 }
2582 #[doc = "GTZC2 clock enable Set and cleared by software."]
2583 #[inline(always)]
2584 pub fn set_gtzc2en(&mut self, val: bool) {
2585 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
2586 }
2587 #[doc = "SRAM4 clock enable Set and reset by software."]
2588 #[inline(always)]
2589 pub const fn sram4en(&self) -> bool {
2590 let val = (self.0 >> 31usize) & 0x01;
2591 val != 0
2592 }
2593 #[doc = "SRAM4 clock enable Set and reset by software."]
2594 #[inline(always)]
2595 pub fn set_sram4en(&mut self, val: bool) {
2596 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
2597 }
2598 }
2599 impl Default for Ahb3enr {
2600 #[inline(always)]
2601 fn default() -> Ahb3enr {
2602 Ahb3enr(0)
2603 }
2604 }
2605 impl core::fmt::Debug for Ahb3enr {
2606 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2607 f.debug_struct("Ahb3enr")
2608 .field("lpgpio1en", &self.lpgpio1en())
2609 .field("pwren", &self.pwren())
2610 .field("adc4en", &self.adc4en())
2611 .field("dac1en", &self.dac1en())
2612 .field("lpdma1en", &self.lpdma1en())
2613 .field("adf1en", &self.adf1en())
2614 .field("gtzc2en", &self.gtzc2en())
2615 .field("sram4en", &self.sram4en())
2616 .finish()
2617 }
2618 }
2619 #[cfg(feature = "defmt")]
2620 impl defmt::Format for Ahb3enr {
2621 fn format(&self, f: defmt::Formatter) {
2622 #[derive(defmt :: Format)]
2623 struct Ahb3enr {
2624 lpgpio1en: bool,
2625 pwren: bool,
2626 adc4en: bool,
2627 dac1en: bool,
2628 lpdma1en: bool,
2629 adf1en: bool,
2630 gtzc2en: bool,
2631 sram4en: bool,
2632 }
2633 let proxy = Ahb3enr {
2634 lpgpio1en: self.lpgpio1en(),
2635 pwren: self.pwren(),
2636 adc4en: self.adc4en(),
2637 dac1en: self.dac1en(),
2638 lpdma1en: self.lpdma1en(),
2639 adf1en: self.adf1en(),
2640 gtzc2en: self.gtzc2en(),
2641 sram4en: self.sram4en(),
2642 };
2643 defmt::write!(f, "{}", proxy)
2644 }
2645 }
2646 #[doc = "RCC AHB3 peripheral reset register"]
2647 #[repr(transparent)]
2648 #[derive(Copy, Clone, Eq, PartialEq)]
2649 pub struct Ahb3rstr(pub u32);
2650 impl Ahb3rstr {
2651 #[doc = "LPGPIO1 reset Set and cleared by software."]
2652 #[inline(always)]
2653 pub const fn lpgpio1rst(&self) -> bool {
2654 let val = (self.0 >> 0usize) & 0x01;
2655 val != 0
2656 }
2657 #[doc = "LPGPIO1 reset Set and cleared by software."]
2658 #[inline(always)]
2659 pub fn set_lpgpio1rst(&mut self, val: bool) {
2660 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2661 }
2662 #[doc = "ADC4 reset Set and cleared by software."]
2663 #[inline(always)]
2664 pub const fn adc4rst(&self) -> bool {
2665 let val = (self.0 >> 5usize) & 0x01;
2666 val != 0
2667 }
2668 #[doc = "ADC4 reset Set and cleared by software."]
2669 #[inline(always)]
2670 pub fn set_adc4rst(&mut self, val: bool) {
2671 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
2672 }
2673 #[doc = "DAC1 reset Set and cleared by software."]
2674 #[inline(always)]
2675 pub const fn dac1rst(&self) -> bool {
2676 let val = (self.0 >> 6usize) & 0x01;
2677 val != 0
2678 }
2679 #[doc = "DAC1 reset Set and cleared by software."]
2680 #[inline(always)]
2681 pub fn set_dac1rst(&mut self, val: bool) {
2682 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
2683 }
2684 #[doc = "LPDMA1 reset Set and cleared by software."]
2685 #[inline(always)]
2686 pub const fn lpdma1rst(&self) -> bool {
2687 let val = (self.0 >> 9usize) & 0x01;
2688 val != 0
2689 }
2690 #[doc = "LPDMA1 reset Set and cleared by software."]
2691 #[inline(always)]
2692 pub fn set_lpdma1rst(&mut self, val: bool) {
2693 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
2694 }
2695 #[doc = "ADF1 reset Set and cleared by software."]
2696 #[inline(always)]
2697 pub const fn adf1rst(&self) -> bool {
2698 let val = (self.0 >> 10usize) & 0x01;
2699 val != 0
2700 }
2701 #[doc = "ADF1 reset Set and cleared by software."]
2702 #[inline(always)]
2703 pub fn set_adf1rst(&mut self, val: bool) {
2704 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
2705 }
2706 }
2707 impl Default for Ahb3rstr {
2708 #[inline(always)]
2709 fn default() -> Ahb3rstr {
2710 Ahb3rstr(0)
2711 }
2712 }
2713 impl core::fmt::Debug for Ahb3rstr {
2714 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2715 f.debug_struct("Ahb3rstr")
2716 .field("lpgpio1rst", &self.lpgpio1rst())
2717 .field("adc4rst", &self.adc4rst())
2718 .field("dac1rst", &self.dac1rst())
2719 .field("lpdma1rst", &self.lpdma1rst())
2720 .field("adf1rst", &self.adf1rst())
2721 .finish()
2722 }
2723 }
2724 #[cfg(feature = "defmt")]
2725 impl defmt::Format for Ahb3rstr {
2726 fn format(&self, f: defmt::Formatter) {
2727 #[derive(defmt :: Format)]
2728 struct Ahb3rstr {
2729 lpgpio1rst: bool,
2730 adc4rst: bool,
2731 dac1rst: bool,
2732 lpdma1rst: bool,
2733 adf1rst: bool,
2734 }
2735 let proxy = Ahb3rstr {
2736 lpgpio1rst: self.lpgpio1rst(),
2737 adc4rst: self.adc4rst(),
2738 dac1rst: self.dac1rst(),
2739 lpdma1rst: self.lpdma1rst(),
2740 adf1rst: self.adf1rst(),
2741 };
2742 defmt::write!(f, "{}", proxy)
2743 }
2744 }
2745 #[doc = "RCC AHB3 peripheral clocks enable in Sleep and Stop modes register"]
2746 #[repr(transparent)]
2747 #[derive(Copy, Clone, Eq, PartialEq)]
2748 pub struct Ahb3smenr(pub u32);
2749 impl Ahb3smenr {
2750 #[doc = "LPGPIO1 enable during Sleep and Stop modes Set and cleared by software."]
2751 #[inline(always)]
2752 pub const fn lpgpio1smen(&self) -> bool {
2753 let val = (self.0 >> 0usize) & 0x01;
2754 val != 0
2755 }
2756 #[doc = "LPGPIO1 enable during Sleep and Stop modes Set and cleared by software."]
2757 #[inline(always)]
2758 pub fn set_lpgpio1smen(&mut self, val: bool) {
2759 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2760 }
2761 #[doc = "PWR clock enable during Sleep and Stop modes Set and cleared by software."]
2762 #[inline(always)]
2763 pub const fn pwrsmen(&self) -> bool {
2764 let val = (self.0 >> 2usize) & 0x01;
2765 val != 0
2766 }
2767 #[doc = "PWR clock enable during Sleep and Stop modes Set and cleared by software."]
2768 #[inline(always)]
2769 pub fn set_pwrsmen(&mut self, val: bool) {
2770 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
2771 }
2772 #[doc = "ADC4 clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
2773 #[inline(always)]
2774 pub const fn adc4smen(&self) -> bool {
2775 let val = (self.0 >> 5usize) & 0x01;
2776 val != 0
2777 }
2778 #[doc = "ADC4 clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
2779 #[inline(always)]
2780 pub fn set_adc4smen(&mut self, val: bool) {
2781 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
2782 }
2783 #[doc = "DAC1 clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
2784 #[inline(always)]
2785 pub const fn dac1smen(&self) -> bool {
2786 let val = (self.0 >> 6usize) & 0x01;
2787 val != 0
2788 }
2789 #[doc = "DAC1 clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
2790 #[inline(always)]
2791 pub fn set_dac1smen(&mut self, val: bool) {
2792 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
2793 }
2794 #[doc = "LPDMA1 clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
2795 #[inline(always)]
2796 pub const fn lpdma1smen(&self) -> bool {
2797 let val = (self.0 >> 9usize) & 0x01;
2798 val != 0
2799 }
2800 #[doc = "LPDMA1 clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
2801 #[inline(always)]
2802 pub fn set_lpdma1smen(&mut self, val: bool) {
2803 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
2804 }
2805 #[doc = "ADF1 clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
2806 #[inline(always)]
2807 pub const fn adf1smen(&self) -> bool {
2808 let val = (self.0 >> 10usize) & 0x01;
2809 val != 0
2810 }
2811 #[doc = "ADF1 clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
2812 #[inline(always)]
2813 pub fn set_adf1smen(&mut self, val: bool) {
2814 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
2815 }
2816 #[doc = "GTZC2 clock enable during Sleep and Stop modes Set and cleared by software."]
2817 #[inline(always)]
2818 pub const fn gtzc2smen(&self) -> bool {
2819 let val = (self.0 >> 12usize) & 0x01;
2820 val != 0
2821 }
2822 #[doc = "GTZC2 clock enable during Sleep and Stop modes Set and cleared by software."]
2823 #[inline(always)]
2824 pub fn set_gtzc2smen(&mut self, val: bool) {
2825 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
2826 }
2827 #[doc = "SRAM4 clocks enable during Sleep and Stop modes Set and cleared by software."]
2828 #[inline(always)]
2829 pub const fn sram4smen(&self) -> bool {
2830 let val = (self.0 >> 31usize) & 0x01;
2831 val != 0
2832 }
2833 #[doc = "SRAM4 clocks enable during Sleep and Stop modes Set and cleared by software."]
2834 #[inline(always)]
2835 pub fn set_sram4smen(&mut self, val: bool) {
2836 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
2837 }
2838 }
2839 impl Default for Ahb3smenr {
2840 #[inline(always)]
2841 fn default() -> Ahb3smenr {
2842 Ahb3smenr(0)
2843 }
2844 }
2845 impl core::fmt::Debug for Ahb3smenr {
2846 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2847 f.debug_struct("Ahb3smenr")
2848 .field("lpgpio1smen", &self.lpgpio1smen())
2849 .field("pwrsmen", &self.pwrsmen())
2850 .field("adc4smen", &self.adc4smen())
2851 .field("dac1smen", &self.dac1smen())
2852 .field("lpdma1smen", &self.lpdma1smen())
2853 .field("adf1smen", &self.adf1smen())
2854 .field("gtzc2smen", &self.gtzc2smen())
2855 .field("sram4smen", &self.sram4smen())
2856 .finish()
2857 }
2858 }
2859 #[cfg(feature = "defmt")]
2860 impl defmt::Format for Ahb3smenr {
2861 fn format(&self, f: defmt::Formatter) {
2862 #[derive(defmt :: Format)]
2863 struct Ahb3smenr {
2864 lpgpio1smen: bool,
2865 pwrsmen: bool,
2866 adc4smen: bool,
2867 dac1smen: bool,
2868 lpdma1smen: bool,
2869 adf1smen: bool,
2870 gtzc2smen: bool,
2871 sram4smen: bool,
2872 }
2873 let proxy = Ahb3smenr {
2874 lpgpio1smen: self.lpgpio1smen(),
2875 pwrsmen: self.pwrsmen(),
2876 adc4smen: self.adc4smen(),
2877 dac1smen: self.dac1smen(),
2878 lpdma1smen: self.lpdma1smen(),
2879 adf1smen: self.adf1smen(),
2880 gtzc2smen: self.gtzc2smen(),
2881 sram4smen: self.sram4smen(),
2882 };
2883 defmt::write!(f, "{}", proxy)
2884 }
2885 }
2886 #[doc = "RCC APB1 peripheral clock enable register 1"]
2887 #[repr(transparent)]
2888 #[derive(Copy, Clone, Eq, PartialEq)]
2889 pub struct Apb1enr1(pub u32);
2890 impl Apb1enr1 {
2891 #[doc = "TIM2 clock enable Set and cleared by software."]
2892 #[inline(always)]
2893 pub const fn tim2en(&self) -> bool {
2894 let val = (self.0 >> 0usize) & 0x01;
2895 val != 0
2896 }
2897 #[doc = "TIM2 clock enable Set and cleared by software."]
2898 #[inline(always)]
2899 pub fn set_tim2en(&mut self, val: bool) {
2900 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2901 }
2902 #[doc = "TIM3 clock enable Set and cleared by software."]
2903 #[inline(always)]
2904 pub const fn tim3en(&self) -> bool {
2905 let val = (self.0 >> 1usize) & 0x01;
2906 val != 0
2907 }
2908 #[doc = "TIM3 clock enable Set and cleared by software."]
2909 #[inline(always)]
2910 pub fn set_tim3en(&mut self, val: bool) {
2911 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
2912 }
2913 #[doc = "TIM4 clock enable Set and cleared by software."]
2914 #[inline(always)]
2915 pub const fn tim4en(&self) -> bool {
2916 let val = (self.0 >> 2usize) & 0x01;
2917 val != 0
2918 }
2919 #[doc = "TIM4 clock enable Set and cleared by software."]
2920 #[inline(always)]
2921 pub fn set_tim4en(&mut self, val: bool) {
2922 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
2923 }
2924 #[doc = "TIM5 clock enable Set and cleared by software."]
2925 #[inline(always)]
2926 pub const fn tim5en(&self) -> bool {
2927 let val = (self.0 >> 3usize) & 0x01;
2928 val != 0
2929 }
2930 #[doc = "TIM5 clock enable Set and cleared by software."]
2931 #[inline(always)]
2932 pub fn set_tim5en(&mut self, val: bool) {
2933 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
2934 }
2935 #[doc = "TIM6 clock enable Set and cleared by software."]
2936 #[inline(always)]
2937 pub const fn tim6en(&self) -> bool {
2938 let val = (self.0 >> 4usize) & 0x01;
2939 val != 0
2940 }
2941 #[doc = "TIM6 clock enable Set and cleared by software."]
2942 #[inline(always)]
2943 pub fn set_tim6en(&mut self, val: bool) {
2944 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
2945 }
2946 #[doc = "TIM7 clock enable Set and cleared by software."]
2947 #[inline(always)]
2948 pub const fn tim7en(&self) -> bool {
2949 let val = (self.0 >> 5usize) & 0x01;
2950 val != 0
2951 }
2952 #[doc = "TIM7 clock enable Set and cleared by software."]
2953 #[inline(always)]
2954 pub fn set_tim7en(&mut self, val: bool) {
2955 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
2956 }
2957 #[doc = "WWDG clock enable Set by software to enable the window watchdog clock. Reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset."]
2958 #[inline(always)]
2959 pub const fn wwdgen(&self) -> bool {
2960 let val = (self.0 >> 11usize) & 0x01;
2961 val != 0
2962 }
2963 #[doc = "WWDG clock enable Set by software to enable the window watchdog clock. Reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset."]
2964 #[inline(always)]
2965 pub fn set_wwdgen(&mut self, val: bool) {
2966 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
2967 }
2968 #[doc = "SPI2 clock enable Set and cleared by software."]
2969 #[inline(always)]
2970 pub const fn spi2en(&self) -> bool {
2971 let val = (self.0 >> 14usize) & 0x01;
2972 val != 0
2973 }
2974 #[doc = "SPI2 clock enable Set and cleared by software."]
2975 #[inline(always)]
2976 pub fn set_spi2en(&mut self, val: bool) {
2977 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
2978 }
2979 #[doc = "USART2 clock enable Set and cleared by software."]
2980 #[inline(always)]
2981 pub const fn usart2en(&self) -> bool {
2982 let val = (self.0 >> 17usize) & 0x01;
2983 val != 0
2984 }
2985 #[doc = "USART2 clock enable Set and cleared by software."]
2986 #[inline(always)]
2987 pub fn set_usart2en(&mut self, val: bool) {
2988 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
2989 }
2990 #[doc = "USART3 clock enable Set and cleared by software."]
2991 #[inline(always)]
2992 pub const fn usart3en(&self) -> bool {
2993 let val = (self.0 >> 18usize) & 0x01;
2994 val != 0
2995 }
2996 #[doc = "USART3 clock enable Set and cleared by software."]
2997 #[inline(always)]
2998 pub fn set_usart3en(&mut self, val: bool) {
2999 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
3000 }
3001 #[doc = "UART4 clock enable Set and cleared by software."]
3002 #[inline(always)]
3003 pub const fn uart4en(&self) -> bool {
3004 let val = (self.0 >> 19usize) & 0x01;
3005 val != 0
3006 }
3007 #[doc = "UART4 clock enable Set and cleared by software."]
3008 #[inline(always)]
3009 pub fn set_uart4en(&mut self, val: bool) {
3010 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
3011 }
3012 #[doc = "UART5 clock enable Set and cleared by software."]
3013 #[inline(always)]
3014 pub const fn uart5en(&self) -> bool {
3015 let val = (self.0 >> 20usize) & 0x01;
3016 val != 0
3017 }
3018 #[doc = "UART5 clock enable Set and cleared by software."]
3019 #[inline(always)]
3020 pub fn set_uart5en(&mut self, val: bool) {
3021 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
3022 }
3023 #[doc = "I2C1 clock enable Set and cleared by software."]
3024 #[inline(always)]
3025 pub const fn i2c1en(&self) -> bool {
3026 let val = (self.0 >> 21usize) & 0x01;
3027 val != 0
3028 }
3029 #[doc = "I2C1 clock enable Set and cleared by software."]
3030 #[inline(always)]
3031 pub fn set_i2c1en(&mut self, val: bool) {
3032 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
3033 }
3034 #[doc = "I2C2 clock enable Set and cleared by software."]
3035 #[inline(always)]
3036 pub const fn i2c2en(&self) -> bool {
3037 let val = (self.0 >> 22usize) & 0x01;
3038 val != 0
3039 }
3040 #[doc = "I2C2 clock enable Set and cleared by software."]
3041 #[inline(always)]
3042 pub fn set_i2c2en(&mut self, val: bool) {
3043 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
3044 }
3045 #[doc = "CRS clock enable Set and cleared by software."]
3046 #[inline(always)]
3047 pub const fn crsen(&self) -> bool {
3048 let val = (self.0 >> 24usize) & 0x01;
3049 val != 0
3050 }
3051 #[doc = "CRS clock enable Set and cleared by software."]
3052 #[inline(always)]
3053 pub fn set_crsen(&mut self, val: bool) {
3054 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
3055 }
3056 #[doc = "USART6 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
3057 #[inline(always)]
3058 pub const fn usart6en(&self) -> bool {
3059 let val = (self.0 >> 25usize) & 0x01;
3060 val != 0
3061 }
3062 #[doc = "USART6 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
3063 #[inline(always)]
3064 pub fn set_usart6en(&mut self, val: bool) {
3065 self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
3066 }
3067 }
3068 impl Default for Apb1enr1 {
3069 #[inline(always)]
3070 fn default() -> Apb1enr1 {
3071 Apb1enr1(0)
3072 }
3073 }
3074 impl core::fmt::Debug for Apb1enr1 {
3075 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3076 f.debug_struct("Apb1enr1")
3077 .field("tim2en", &self.tim2en())
3078 .field("tim3en", &self.tim3en())
3079 .field("tim4en", &self.tim4en())
3080 .field("tim5en", &self.tim5en())
3081 .field("tim6en", &self.tim6en())
3082 .field("tim7en", &self.tim7en())
3083 .field("wwdgen", &self.wwdgen())
3084 .field("spi2en", &self.spi2en())
3085 .field("usart2en", &self.usart2en())
3086 .field("usart3en", &self.usart3en())
3087 .field("uart4en", &self.uart4en())
3088 .field("uart5en", &self.uart5en())
3089 .field("i2c1en", &self.i2c1en())
3090 .field("i2c2en", &self.i2c2en())
3091 .field("crsen", &self.crsen())
3092 .field("usart6en", &self.usart6en())
3093 .finish()
3094 }
3095 }
3096 #[cfg(feature = "defmt")]
3097 impl defmt::Format for Apb1enr1 {
3098 fn format(&self, f: defmt::Formatter) {
3099 #[derive(defmt :: Format)]
3100 struct Apb1enr1 {
3101 tim2en: bool,
3102 tim3en: bool,
3103 tim4en: bool,
3104 tim5en: bool,
3105 tim6en: bool,
3106 tim7en: bool,
3107 wwdgen: bool,
3108 spi2en: bool,
3109 usart2en: bool,
3110 usart3en: bool,
3111 uart4en: bool,
3112 uart5en: bool,
3113 i2c1en: bool,
3114 i2c2en: bool,
3115 crsen: bool,
3116 usart6en: bool,
3117 }
3118 let proxy = Apb1enr1 {
3119 tim2en: self.tim2en(),
3120 tim3en: self.tim3en(),
3121 tim4en: self.tim4en(),
3122 tim5en: self.tim5en(),
3123 tim6en: self.tim6en(),
3124 tim7en: self.tim7en(),
3125 wwdgen: self.wwdgen(),
3126 spi2en: self.spi2en(),
3127 usart2en: self.usart2en(),
3128 usart3en: self.usart3en(),
3129 uart4en: self.uart4en(),
3130 uart5en: self.uart5en(),
3131 i2c1en: self.i2c1en(),
3132 i2c2en: self.i2c2en(),
3133 crsen: self.crsen(),
3134 usart6en: self.usart6en(),
3135 };
3136 defmt::write!(f, "{}", proxy)
3137 }
3138 }
3139 #[doc = "RCC APB1 peripheral clock enable register 2"]
3140 #[repr(transparent)]
3141 #[derive(Copy, Clone, Eq, PartialEq)]
3142 pub struct Apb1enr2(pub u32);
3143 impl Apb1enr2 {
3144 #[doc = "I2C4 clock enable Set and cleared by software"]
3145 #[inline(always)]
3146 pub const fn i2c4en(&self) -> bool {
3147 let val = (self.0 >> 1usize) & 0x01;
3148 val != 0
3149 }
3150 #[doc = "I2C4 clock enable Set and cleared by software"]
3151 #[inline(always)]
3152 pub fn set_i2c4en(&mut self, val: bool) {
3153 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
3154 }
3155 #[doc = "LPTIM2 clock enable Set and cleared by software."]
3156 #[inline(always)]
3157 pub const fn lptim2en(&self) -> bool {
3158 let val = (self.0 >> 5usize) & 0x01;
3159 val != 0
3160 }
3161 #[doc = "LPTIM2 clock enable Set and cleared by software."]
3162 #[inline(always)]
3163 pub fn set_lptim2en(&mut self, val: bool) {
3164 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
3165 }
3166 #[doc = "I2C5 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
3167 #[inline(always)]
3168 pub const fn i2c5en(&self) -> bool {
3169 let val = (self.0 >> 6usize) & 0x01;
3170 val != 0
3171 }
3172 #[doc = "I2C5 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
3173 #[inline(always)]
3174 pub fn set_i2c5en(&mut self, val: bool) {
3175 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
3176 }
3177 #[doc = "I2C6 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
3178 #[inline(always)]
3179 pub const fn i2c6en(&self) -> bool {
3180 let val = (self.0 >> 7usize) & 0x01;
3181 val != 0
3182 }
3183 #[doc = "I2C6 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
3184 #[inline(always)]
3185 pub fn set_i2c6en(&mut self, val: bool) {
3186 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
3187 }
3188 #[doc = "FDCAN1 clock enable Set and cleared by software."]
3189 #[inline(always)]
3190 pub const fn fdcan1en(&self) -> bool {
3191 let val = (self.0 >> 9usize) & 0x01;
3192 val != 0
3193 }
3194 #[doc = "FDCAN1 clock enable Set and cleared by software."]
3195 #[inline(always)]
3196 pub fn set_fdcan1en(&mut self, val: bool) {
3197 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
3198 }
3199 #[doc = "UCPD1 clock enable Set and cleared by software."]
3200 #[inline(always)]
3201 pub const fn ucpd1en(&self) -> bool {
3202 let val = (self.0 >> 23usize) & 0x01;
3203 val != 0
3204 }
3205 #[doc = "UCPD1 clock enable Set and cleared by software."]
3206 #[inline(always)]
3207 pub fn set_ucpd1en(&mut self, val: bool) {
3208 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
3209 }
3210 }
3211 impl Default for Apb1enr2 {
3212 #[inline(always)]
3213 fn default() -> Apb1enr2 {
3214 Apb1enr2(0)
3215 }
3216 }
3217 impl core::fmt::Debug for Apb1enr2 {
3218 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3219 f.debug_struct("Apb1enr2")
3220 .field("i2c4en", &self.i2c4en())
3221 .field("lptim2en", &self.lptim2en())
3222 .field("i2c5en", &self.i2c5en())
3223 .field("i2c6en", &self.i2c6en())
3224 .field("fdcan1en", &self.fdcan1en())
3225 .field("ucpd1en", &self.ucpd1en())
3226 .finish()
3227 }
3228 }
3229 #[cfg(feature = "defmt")]
3230 impl defmt::Format for Apb1enr2 {
3231 fn format(&self, f: defmt::Formatter) {
3232 #[derive(defmt :: Format)]
3233 struct Apb1enr2 {
3234 i2c4en: bool,
3235 lptim2en: bool,
3236 i2c5en: bool,
3237 i2c6en: bool,
3238 fdcan1en: bool,
3239 ucpd1en: bool,
3240 }
3241 let proxy = Apb1enr2 {
3242 i2c4en: self.i2c4en(),
3243 lptim2en: self.lptim2en(),
3244 i2c5en: self.i2c5en(),
3245 i2c6en: self.i2c6en(),
3246 fdcan1en: self.fdcan1en(),
3247 ucpd1en: self.ucpd1en(),
3248 };
3249 defmt::write!(f, "{}", proxy)
3250 }
3251 }
3252 #[doc = "RCC APB1 peripheral reset register 1"]
3253 #[repr(transparent)]
3254 #[derive(Copy, Clone, Eq, PartialEq)]
3255 pub struct Apb1rstr1(pub u32);
3256 impl Apb1rstr1 {
3257 #[doc = "TIM2 reset Set and cleared by software."]
3258 #[inline(always)]
3259 pub const fn tim2rst(&self) -> bool {
3260 let val = (self.0 >> 0usize) & 0x01;
3261 val != 0
3262 }
3263 #[doc = "TIM2 reset Set and cleared by software."]
3264 #[inline(always)]
3265 pub fn set_tim2rst(&mut self, val: bool) {
3266 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
3267 }
3268 #[doc = "TIM3 reset Set and cleared by software."]
3269 #[inline(always)]
3270 pub const fn tim3rst(&self) -> bool {
3271 let val = (self.0 >> 1usize) & 0x01;
3272 val != 0
3273 }
3274 #[doc = "TIM3 reset Set and cleared by software."]
3275 #[inline(always)]
3276 pub fn set_tim3rst(&mut self, val: bool) {
3277 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
3278 }
3279 #[doc = "TIM4 reset Set and cleared by software."]
3280 #[inline(always)]
3281 pub const fn tim4rst(&self) -> bool {
3282 let val = (self.0 >> 2usize) & 0x01;
3283 val != 0
3284 }
3285 #[doc = "TIM4 reset Set and cleared by software."]
3286 #[inline(always)]
3287 pub fn set_tim4rst(&mut self, val: bool) {
3288 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
3289 }
3290 #[doc = "TIM5 reset Set and cleared by software."]
3291 #[inline(always)]
3292 pub const fn tim5rst(&self) -> bool {
3293 let val = (self.0 >> 3usize) & 0x01;
3294 val != 0
3295 }
3296 #[doc = "TIM5 reset Set and cleared by software."]
3297 #[inline(always)]
3298 pub fn set_tim5rst(&mut self, val: bool) {
3299 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
3300 }
3301 #[doc = "TIM6 reset Set and cleared by software."]
3302 #[inline(always)]
3303 pub const fn tim6rst(&self) -> bool {
3304 let val = (self.0 >> 4usize) & 0x01;
3305 val != 0
3306 }
3307 #[doc = "TIM6 reset Set and cleared by software."]
3308 #[inline(always)]
3309 pub fn set_tim6rst(&mut self, val: bool) {
3310 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
3311 }
3312 #[doc = "TIM7 reset Set and cleared by software."]
3313 #[inline(always)]
3314 pub const fn tim7rst(&self) -> bool {
3315 let val = (self.0 >> 5usize) & 0x01;
3316 val != 0
3317 }
3318 #[doc = "TIM7 reset Set and cleared by software."]
3319 #[inline(always)]
3320 pub fn set_tim7rst(&mut self, val: bool) {
3321 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
3322 }
3323 #[doc = "SPI2 reset Set and cleared by software."]
3324 #[inline(always)]
3325 pub const fn spi2rst(&self) -> bool {
3326 let val = (self.0 >> 14usize) & 0x01;
3327 val != 0
3328 }
3329 #[doc = "SPI2 reset Set and cleared by software."]
3330 #[inline(always)]
3331 pub fn set_spi2rst(&mut self, val: bool) {
3332 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
3333 }
3334 #[doc = "USART2 reset Set and cleared by software."]
3335 #[inline(always)]
3336 pub const fn usart2rst(&self) -> bool {
3337 let val = (self.0 >> 17usize) & 0x01;
3338 val != 0
3339 }
3340 #[doc = "USART2 reset Set and cleared by software."]
3341 #[inline(always)]
3342 pub fn set_usart2rst(&mut self, val: bool) {
3343 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
3344 }
3345 #[doc = "USART3 reset Set and cleared by software."]
3346 #[inline(always)]
3347 pub const fn usart3rst(&self) -> bool {
3348 let val = (self.0 >> 18usize) & 0x01;
3349 val != 0
3350 }
3351 #[doc = "USART3 reset Set and cleared by software."]
3352 #[inline(always)]
3353 pub fn set_usart3rst(&mut self, val: bool) {
3354 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
3355 }
3356 #[doc = "UART4 reset Set and cleared by software."]
3357 #[inline(always)]
3358 pub const fn uart4rst(&self) -> bool {
3359 let val = (self.0 >> 19usize) & 0x01;
3360 val != 0
3361 }
3362 #[doc = "UART4 reset Set and cleared by software."]
3363 #[inline(always)]
3364 pub fn set_uart4rst(&mut self, val: bool) {
3365 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
3366 }
3367 #[doc = "UART5 reset Set and cleared by software."]
3368 #[inline(always)]
3369 pub const fn uart5rst(&self) -> bool {
3370 let val = (self.0 >> 20usize) & 0x01;
3371 val != 0
3372 }
3373 #[doc = "UART5 reset Set and cleared by software."]
3374 #[inline(always)]
3375 pub fn set_uart5rst(&mut self, val: bool) {
3376 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
3377 }
3378 #[doc = "I2C1 reset Set and cleared by software."]
3379 #[inline(always)]
3380 pub const fn i2c1rst(&self) -> bool {
3381 let val = (self.0 >> 21usize) & 0x01;
3382 val != 0
3383 }
3384 #[doc = "I2C1 reset Set and cleared by software."]
3385 #[inline(always)]
3386 pub fn set_i2c1rst(&mut self, val: bool) {
3387 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
3388 }
3389 #[doc = "I2C2 reset Set and cleared by software."]
3390 #[inline(always)]
3391 pub const fn i2c2rst(&self) -> bool {
3392 let val = (self.0 >> 22usize) & 0x01;
3393 val != 0
3394 }
3395 #[doc = "I2C2 reset Set and cleared by software."]
3396 #[inline(always)]
3397 pub fn set_i2c2rst(&mut self, val: bool) {
3398 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
3399 }
3400 #[doc = "CRS reset Set and cleared by software."]
3401 #[inline(always)]
3402 pub const fn crsrst(&self) -> bool {
3403 let val = (self.0 >> 24usize) & 0x01;
3404 val != 0
3405 }
3406 #[doc = "CRS reset Set and cleared by software."]
3407 #[inline(always)]
3408 pub fn set_crsrst(&mut self, val: bool) {
3409 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
3410 }
3411 #[doc = "USART6 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
3412 #[inline(always)]
3413 pub const fn usart6rst(&self) -> bool {
3414 let val = (self.0 >> 25usize) & 0x01;
3415 val != 0
3416 }
3417 #[doc = "USART6 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
3418 #[inline(always)]
3419 pub fn set_usart6rst(&mut self, val: bool) {
3420 self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
3421 }
3422 }
3423 impl Default for Apb1rstr1 {
3424 #[inline(always)]
3425 fn default() -> Apb1rstr1 {
3426 Apb1rstr1(0)
3427 }
3428 }
3429 impl core::fmt::Debug for Apb1rstr1 {
3430 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3431 f.debug_struct("Apb1rstr1")
3432 .field("tim2rst", &self.tim2rst())
3433 .field("tim3rst", &self.tim3rst())
3434 .field("tim4rst", &self.tim4rst())
3435 .field("tim5rst", &self.tim5rst())
3436 .field("tim6rst", &self.tim6rst())
3437 .field("tim7rst", &self.tim7rst())
3438 .field("spi2rst", &self.spi2rst())
3439 .field("usart2rst", &self.usart2rst())
3440 .field("usart3rst", &self.usart3rst())
3441 .field("uart4rst", &self.uart4rst())
3442 .field("uart5rst", &self.uart5rst())
3443 .field("i2c1rst", &self.i2c1rst())
3444 .field("i2c2rst", &self.i2c2rst())
3445 .field("crsrst", &self.crsrst())
3446 .field("usart6rst", &self.usart6rst())
3447 .finish()
3448 }
3449 }
3450 #[cfg(feature = "defmt")]
3451 impl defmt::Format for Apb1rstr1 {
3452 fn format(&self, f: defmt::Formatter) {
3453 #[derive(defmt :: Format)]
3454 struct Apb1rstr1 {
3455 tim2rst: bool,
3456 tim3rst: bool,
3457 tim4rst: bool,
3458 tim5rst: bool,
3459 tim6rst: bool,
3460 tim7rst: bool,
3461 spi2rst: bool,
3462 usart2rst: bool,
3463 usart3rst: bool,
3464 uart4rst: bool,
3465 uart5rst: bool,
3466 i2c1rst: bool,
3467 i2c2rst: bool,
3468 crsrst: bool,
3469 usart6rst: bool,
3470 }
3471 let proxy = Apb1rstr1 {
3472 tim2rst: self.tim2rst(),
3473 tim3rst: self.tim3rst(),
3474 tim4rst: self.tim4rst(),
3475 tim5rst: self.tim5rst(),
3476 tim6rst: self.tim6rst(),
3477 tim7rst: self.tim7rst(),
3478 spi2rst: self.spi2rst(),
3479 usart2rst: self.usart2rst(),
3480 usart3rst: self.usart3rst(),
3481 uart4rst: self.uart4rst(),
3482 uart5rst: self.uart5rst(),
3483 i2c1rst: self.i2c1rst(),
3484 i2c2rst: self.i2c2rst(),
3485 crsrst: self.crsrst(),
3486 usart6rst: self.usart6rst(),
3487 };
3488 defmt::write!(f, "{}", proxy)
3489 }
3490 }
3491 #[doc = "RCC APB1 peripheral reset register 2"]
3492 #[repr(transparent)]
3493 #[derive(Copy, Clone, Eq, PartialEq)]
3494 pub struct Apb1rstr2(pub u32);
3495 impl Apb1rstr2 {
3496 #[doc = "I2C4 reset Set and cleared by software"]
3497 #[inline(always)]
3498 pub const fn i2c4rst(&self) -> bool {
3499 let val = (self.0 >> 1usize) & 0x01;
3500 val != 0
3501 }
3502 #[doc = "I2C4 reset Set and cleared by software"]
3503 #[inline(always)]
3504 pub fn set_i2c4rst(&mut self, val: bool) {
3505 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
3506 }
3507 #[doc = "LPTIM2 reset Set and cleared by software."]
3508 #[inline(always)]
3509 pub const fn lptim2rst(&self) -> bool {
3510 let val = (self.0 >> 5usize) & 0x01;
3511 val != 0
3512 }
3513 #[doc = "LPTIM2 reset Set and cleared by software."]
3514 #[inline(always)]
3515 pub fn set_lptim2rst(&mut self, val: bool) {
3516 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
3517 }
3518 #[doc = "I2C5 reset This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
3519 #[inline(always)]
3520 pub const fn i2c5rst(&self) -> bool {
3521 let val = (self.0 >> 6usize) & 0x01;
3522 val != 0
3523 }
3524 #[doc = "I2C5 reset This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
3525 #[inline(always)]
3526 pub fn set_i2c5rst(&mut self, val: bool) {
3527 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
3528 }
3529 #[doc = "I2C6 reset This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
3530 #[inline(always)]
3531 pub const fn i2c6rst(&self) -> bool {
3532 let val = (self.0 >> 7usize) & 0x01;
3533 val != 0
3534 }
3535 #[doc = "I2C6 reset This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
3536 #[inline(always)]
3537 pub fn set_i2c6rst(&mut self, val: bool) {
3538 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
3539 }
3540 #[doc = "FDCAN1 reset Set and cleared by software."]
3541 #[inline(always)]
3542 pub const fn fdcan1rst(&self) -> bool {
3543 let val = (self.0 >> 9usize) & 0x01;
3544 val != 0
3545 }
3546 #[doc = "FDCAN1 reset Set and cleared by software."]
3547 #[inline(always)]
3548 pub fn set_fdcan1rst(&mut self, val: bool) {
3549 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
3550 }
3551 #[doc = "UCPD1 reset Set and cleared by software."]
3552 #[inline(always)]
3553 pub const fn ucpd1rst(&self) -> bool {
3554 let val = (self.0 >> 23usize) & 0x01;
3555 val != 0
3556 }
3557 #[doc = "UCPD1 reset Set and cleared by software."]
3558 #[inline(always)]
3559 pub fn set_ucpd1rst(&mut self, val: bool) {
3560 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
3561 }
3562 }
3563 impl Default for Apb1rstr2 {
3564 #[inline(always)]
3565 fn default() -> Apb1rstr2 {
3566 Apb1rstr2(0)
3567 }
3568 }
3569 impl core::fmt::Debug for Apb1rstr2 {
3570 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3571 f.debug_struct("Apb1rstr2")
3572 .field("i2c4rst", &self.i2c4rst())
3573 .field("lptim2rst", &self.lptim2rst())
3574 .field("i2c5rst", &self.i2c5rst())
3575 .field("i2c6rst", &self.i2c6rst())
3576 .field("fdcan1rst", &self.fdcan1rst())
3577 .field("ucpd1rst", &self.ucpd1rst())
3578 .finish()
3579 }
3580 }
3581 #[cfg(feature = "defmt")]
3582 impl defmt::Format for Apb1rstr2 {
3583 fn format(&self, f: defmt::Formatter) {
3584 #[derive(defmt :: Format)]
3585 struct Apb1rstr2 {
3586 i2c4rst: bool,
3587 lptim2rst: bool,
3588 i2c5rst: bool,
3589 i2c6rst: bool,
3590 fdcan1rst: bool,
3591 ucpd1rst: bool,
3592 }
3593 let proxy = Apb1rstr2 {
3594 i2c4rst: self.i2c4rst(),
3595 lptim2rst: self.lptim2rst(),
3596 i2c5rst: self.i2c5rst(),
3597 i2c6rst: self.i2c6rst(),
3598 fdcan1rst: self.fdcan1rst(),
3599 ucpd1rst: self.ucpd1rst(),
3600 };
3601 defmt::write!(f, "{}", proxy)
3602 }
3603 }
3604 #[doc = "RCC APB1 peripheral clocks enable in Sleep and Stop modes register 1"]
3605 #[repr(transparent)]
3606 #[derive(Copy, Clone, Eq, PartialEq)]
3607 pub struct Apb1smenr1(pub u32);
3608 impl Apb1smenr1 {
3609 #[doc = "TIM2 clocks enable during Sleep and Stop modes Set and cleared by software."]
3610 #[inline(always)]
3611 pub const fn tim2smen(&self) -> bool {
3612 let val = (self.0 >> 0usize) & 0x01;
3613 val != 0
3614 }
3615 #[doc = "TIM2 clocks enable during Sleep and Stop modes Set and cleared by software."]
3616 #[inline(always)]
3617 pub fn set_tim2smen(&mut self, val: bool) {
3618 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
3619 }
3620 #[doc = "TIM3 clocks enable during Sleep and Stop modes Set and cleared by software."]
3621 #[inline(always)]
3622 pub const fn tim3smen(&self) -> bool {
3623 let val = (self.0 >> 1usize) & 0x01;
3624 val != 0
3625 }
3626 #[doc = "TIM3 clocks enable during Sleep and Stop modes Set and cleared by software."]
3627 #[inline(always)]
3628 pub fn set_tim3smen(&mut self, val: bool) {
3629 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
3630 }
3631 #[doc = "TIM4 clocks enable during Sleep and Stop modes Set and cleared by software."]
3632 #[inline(always)]
3633 pub const fn tim4smen(&self) -> bool {
3634 let val = (self.0 >> 2usize) & 0x01;
3635 val != 0
3636 }
3637 #[doc = "TIM4 clocks enable during Sleep and Stop modes Set and cleared by software."]
3638 #[inline(always)]
3639 pub fn set_tim4smen(&mut self, val: bool) {
3640 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
3641 }
3642 #[doc = "TIM5 clocks enable during Sleep and Stop modes Set and cleared by software."]
3643 #[inline(always)]
3644 pub const fn tim5smen(&self) -> bool {
3645 let val = (self.0 >> 3usize) & 0x01;
3646 val != 0
3647 }
3648 #[doc = "TIM5 clocks enable during Sleep and Stop modes Set and cleared by software."]
3649 #[inline(always)]
3650 pub fn set_tim5smen(&mut self, val: bool) {
3651 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
3652 }
3653 #[doc = "TIM6 clocks enable during Sleep and Stop modes Set and cleared by software."]
3654 #[inline(always)]
3655 pub const fn tim6smen(&self) -> bool {
3656 let val = (self.0 >> 4usize) & 0x01;
3657 val != 0
3658 }
3659 #[doc = "TIM6 clocks enable during Sleep and Stop modes Set and cleared by software."]
3660 #[inline(always)]
3661 pub fn set_tim6smen(&mut self, val: bool) {
3662 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
3663 }
3664 #[doc = "TIM7 clocks enable during Sleep and Stop modes Set and cleared by software."]
3665 #[inline(always)]
3666 pub const fn tim7smen(&self) -> bool {
3667 let val = (self.0 >> 5usize) & 0x01;
3668 val != 0
3669 }
3670 #[doc = "TIM7 clocks enable during Sleep and Stop modes Set and cleared by software."]
3671 #[inline(always)]
3672 pub fn set_tim7smen(&mut self, val: bool) {
3673 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
3674 }
3675 #[doc = "Window watchdog clocks enable during Sleep and Stop modes Set and cleared by software. This bit is forced to 1 by hardware when the hardware WWDG option is activated."]
3676 #[inline(always)]
3677 pub const fn wwdgsmen(&self) -> bool {
3678 let val = (self.0 >> 11usize) & 0x01;
3679 val != 0
3680 }
3681 #[doc = "Window watchdog clocks enable during Sleep and Stop modes Set and cleared by software. This bit is forced to 1 by hardware when the hardware WWDG option is activated."]
3682 #[inline(always)]
3683 pub fn set_wwdgsmen(&mut self, val: bool) {
3684 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
3685 }
3686 #[doc = "SPI2 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
3687 #[inline(always)]
3688 pub const fn spi2smen(&self) -> bool {
3689 let val = (self.0 >> 14usize) & 0x01;
3690 val != 0
3691 }
3692 #[doc = "SPI2 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
3693 #[inline(always)]
3694 pub fn set_spi2smen(&mut self, val: bool) {
3695 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
3696 }
3697 #[doc = "USART2 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
3698 #[inline(always)]
3699 pub const fn usart2smen(&self) -> bool {
3700 let val = (self.0 >> 17usize) & 0x01;
3701 val != 0
3702 }
3703 #[doc = "USART2 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
3704 #[inline(always)]
3705 pub fn set_usart2smen(&mut self, val: bool) {
3706 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
3707 }
3708 #[doc = "USART3 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
3709 #[inline(always)]
3710 pub const fn usart3smen(&self) -> bool {
3711 let val = (self.0 >> 18usize) & 0x01;
3712 val != 0
3713 }
3714 #[doc = "USART3 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
3715 #[inline(always)]
3716 pub fn set_usart3smen(&mut self, val: bool) {
3717 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
3718 }
3719 #[doc = "UART4 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
3720 #[inline(always)]
3721 pub const fn uart4smen(&self) -> bool {
3722 let val = (self.0 >> 19usize) & 0x01;
3723 val != 0
3724 }
3725 #[doc = "UART4 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
3726 #[inline(always)]
3727 pub fn set_uart4smen(&mut self, val: bool) {
3728 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
3729 }
3730 #[doc = "UART5 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
3731 #[inline(always)]
3732 pub const fn uart5smen(&self) -> bool {
3733 let val = (self.0 >> 20usize) & 0x01;
3734 val != 0
3735 }
3736 #[doc = "UART5 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
3737 #[inline(always)]
3738 pub fn set_uart5smen(&mut self, val: bool) {
3739 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
3740 }
3741 #[doc = "I2C1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
3742 #[inline(always)]
3743 pub const fn i2c1smen(&self) -> bool {
3744 let val = (self.0 >> 21usize) & 0x01;
3745 val != 0
3746 }
3747 #[doc = "I2C1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
3748 #[inline(always)]
3749 pub fn set_i2c1smen(&mut self, val: bool) {
3750 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
3751 }
3752 #[doc = "I2C2 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
3753 #[inline(always)]
3754 pub const fn i2c2smen(&self) -> bool {
3755 let val = (self.0 >> 22usize) & 0x01;
3756 val != 0
3757 }
3758 #[doc = "I2C2 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
3759 #[inline(always)]
3760 pub fn set_i2c2smen(&mut self, val: bool) {
3761 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
3762 }
3763 #[doc = "CRS clock enable during Sleep and Stop modes Set and cleared by software."]
3764 #[inline(always)]
3765 pub const fn crssmen(&self) -> bool {
3766 let val = (self.0 >> 24usize) & 0x01;
3767 val != 0
3768 }
3769 #[doc = "CRS clock enable during Sleep and Stop modes Set and cleared by software."]
3770 #[inline(always)]
3771 pub fn set_crssmen(&mut self, val: bool) {
3772 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
3773 }
3774 #[doc = "USART6 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
3775 #[inline(always)]
3776 pub const fn usart6smen(&self) -> bool {
3777 let val = (self.0 >> 25usize) & 0x01;
3778 val != 0
3779 }
3780 #[doc = "USART6 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
3781 #[inline(always)]
3782 pub fn set_usart6smen(&mut self, val: bool) {
3783 self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
3784 }
3785 }
3786 impl Default for Apb1smenr1 {
3787 #[inline(always)]
3788 fn default() -> Apb1smenr1 {
3789 Apb1smenr1(0)
3790 }
3791 }
3792 impl core::fmt::Debug for Apb1smenr1 {
3793 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3794 f.debug_struct("Apb1smenr1")
3795 .field("tim2smen", &self.tim2smen())
3796 .field("tim3smen", &self.tim3smen())
3797 .field("tim4smen", &self.tim4smen())
3798 .field("tim5smen", &self.tim5smen())
3799 .field("tim6smen", &self.tim6smen())
3800 .field("tim7smen", &self.tim7smen())
3801 .field("wwdgsmen", &self.wwdgsmen())
3802 .field("spi2smen", &self.spi2smen())
3803 .field("usart2smen", &self.usart2smen())
3804 .field("usart3smen", &self.usart3smen())
3805 .field("uart4smen", &self.uart4smen())
3806 .field("uart5smen", &self.uart5smen())
3807 .field("i2c1smen", &self.i2c1smen())
3808 .field("i2c2smen", &self.i2c2smen())
3809 .field("crssmen", &self.crssmen())
3810 .field("usart6smen", &self.usart6smen())
3811 .finish()
3812 }
3813 }
3814 #[cfg(feature = "defmt")]
3815 impl defmt::Format for Apb1smenr1 {
3816 fn format(&self, f: defmt::Formatter) {
3817 #[derive(defmt :: Format)]
3818 struct Apb1smenr1 {
3819 tim2smen: bool,
3820 tim3smen: bool,
3821 tim4smen: bool,
3822 tim5smen: bool,
3823 tim6smen: bool,
3824 tim7smen: bool,
3825 wwdgsmen: bool,
3826 spi2smen: bool,
3827 usart2smen: bool,
3828 usart3smen: bool,
3829 uart4smen: bool,
3830 uart5smen: bool,
3831 i2c1smen: bool,
3832 i2c2smen: bool,
3833 crssmen: bool,
3834 usart6smen: bool,
3835 }
3836 let proxy = Apb1smenr1 {
3837 tim2smen: self.tim2smen(),
3838 tim3smen: self.tim3smen(),
3839 tim4smen: self.tim4smen(),
3840 tim5smen: self.tim5smen(),
3841 tim6smen: self.tim6smen(),
3842 tim7smen: self.tim7smen(),
3843 wwdgsmen: self.wwdgsmen(),
3844 spi2smen: self.spi2smen(),
3845 usart2smen: self.usart2smen(),
3846 usart3smen: self.usart3smen(),
3847 uart4smen: self.uart4smen(),
3848 uart5smen: self.uart5smen(),
3849 i2c1smen: self.i2c1smen(),
3850 i2c2smen: self.i2c2smen(),
3851 crssmen: self.crssmen(),
3852 usart6smen: self.usart6smen(),
3853 };
3854 defmt::write!(f, "{}", proxy)
3855 }
3856 }
3857 #[doc = "RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2"]
3858 #[repr(transparent)]
3859 #[derive(Copy, Clone, Eq, PartialEq)]
3860 pub struct Apb1smenr2(pub u32);
3861 impl Apb1smenr2 {
3862 #[doc = "I2C4 clocks enable during Sleep and Stop modes Set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
3863 #[inline(always)]
3864 pub const fn i2c4smen(&self) -> bool {
3865 let val = (self.0 >> 1usize) & 0x01;
3866 val != 0
3867 }
3868 #[doc = "I2C4 clocks enable during Sleep and Stop modes Set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
3869 #[inline(always)]
3870 pub fn set_i2c4smen(&mut self, val: bool) {
3871 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
3872 }
3873 #[doc = "LPTIM2 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
3874 #[inline(always)]
3875 pub const fn lptim2smen(&self) -> bool {
3876 let val = (self.0 >> 5usize) & 0x01;
3877 val != 0
3878 }
3879 #[doc = "LPTIM2 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
3880 #[inline(always)]
3881 pub fn set_lptim2smen(&mut self, val: bool) {
3882 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
3883 }
3884 #[doc = "I2C5 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
3885 #[inline(always)]
3886 pub const fn i2c5smen(&self) -> bool {
3887 let val = (self.0 >> 6usize) & 0x01;
3888 val != 0
3889 }
3890 #[doc = "I2C5 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
3891 #[inline(always)]
3892 pub fn set_i2c5smen(&mut self, val: bool) {
3893 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
3894 }
3895 #[doc = "I2C6 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
3896 #[inline(always)]
3897 pub const fn i2c6smen(&self) -> bool {
3898 let val = (self.0 >> 7usize) & 0x01;
3899 val != 0
3900 }
3901 #[doc = "I2C6 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
3902 #[inline(always)]
3903 pub fn set_i2c6smen(&mut self, val: bool) {
3904 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
3905 }
3906 #[doc = "FDCAN1 clocks enable during Sleep and Stop modes Set and cleared by software."]
3907 #[inline(always)]
3908 pub const fn fdcan1smen(&self) -> bool {
3909 let val = (self.0 >> 9usize) & 0x01;
3910 val != 0
3911 }
3912 #[doc = "FDCAN1 clocks enable during Sleep and Stop modes Set and cleared by software."]
3913 #[inline(always)]
3914 pub fn set_fdcan1smen(&mut self, val: bool) {
3915 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
3916 }
3917 #[doc = "UCPD1 clocks enable during Sleep and Stop modes Set and cleared by software."]
3918 #[inline(always)]
3919 pub const fn ucpd1smen(&self) -> bool {
3920 let val = (self.0 >> 23usize) & 0x01;
3921 val != 0
3922 }
3923 #[doc = "UCPD1 clocks enable during Sleep and Stop modes Set and cleared by software."]
3924 #[inline(always)]
3925 pub fn set_ucpd1smen(&mut self, val: bool) {
3926 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
3927 }
3928 }
3929 impl Default for Apb1smenr2 {
3930 #[inline(always)]
3931 fn default() -> Apb1smenr2 {
3932 Apb1smenr2(0)
3933 }
3934 }
3935 impl core::fmt::Debug for Apb1smenr2 {
3936 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3937 f.debug_struct("Apb1smenr2")
3938 .field("i2c4smen", &self.i2c4smen())
3939 .field("lptim2smen", &self.lptim2smen())
3940 .field("i2c5smen", &self.i2c5smen())
3941 .field("i2c6smen", &self.i2c6smen())
3942 .field("fdcan1smen", &self.fdcan1smen())
3943 .field("ucpd1smen", &self.ucpd1smen())
3944 .finish()
3945 }
3946 }
3947 #[cfg(feature = "defmt")]
3948 impl defmt::Format for Apb1smenr2 {
3949 fn format(&self, f: defmt::Formatter) {
3950 #[derive(defmt :: Format)]
3951 struct Apb1smenr2 {
3952 i2c4smen: bool,
3953 lptim2smen: bool,
3954 i2c5smen: bool,
3955 i2c6smen: bool,
3956 fdcan1smen: bool,
3957 ucpd1smen: bool,
3958 }
3959 let proxy = Apb1smenr2 {
3960 i2c4smen: self.i2c4smen(),
3961 lptim2smen: self.lptim2smen(),
3962 i2c5smen: self.i2c5smen(),
3963 i2c6smen: self.i2c6smen(),
3964 fdcan1smen: self.fdcan1smen(),
3965 ucpd1smen: self.ucpd1smen(),
3966 };
3967 defmt::write!(f, "{}", proxy)
3968 }
3969 }
3970 #[doc = "RCC APB2 peripheral clock enable register"]
3971 #[repr(transparent)]
3972 #[derive(Copy, Clone, Eq, PartialEq)]
3973 pub struct Apb2enr(pub u32);
3974 impl Apb2enr {
3975 #[doc = "TIM1 clock enable Set and cleared by software."]
3976 #[inline(always)]
3977 pub const fn tim1en(&self) -> bool {
3978 let val = (self.0 >> 11usize) & 0x01;
3979 val != 0
3980 }
3981 #[doc = "TIM1 clock enable Set and cleared by software."]
3982 #[inline(always)]
3983 pub fn set_tim1en(&mut self, val: bool) {
3984 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
3985 }
3986 #[doc = "SPI1 clock enable Set and cleared by software."]
3987 #[inline(always)]
3988 pub const fn spi1en(&self) -> bool {
3989 let val = (self.0 >> 12usize) & 0x01;
3990 val != 0
3991 }
3992 #[doc = "SPI1 clock enable Set and cleared by software."]
3993 #[inline(always)]
3994 pub fn set_spi1en(&mut self, val: bool) {
3995 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
3996 }
3997 #[doc = "TIM8 clock enable Set and cleared by software."]
3998 #[inline(always)]
3999 pub const fn tim8en(&self) -> bool {
4000 let val = (self.0 >> 13usize) & 0x01;
4001 val != 0
4002 }
4003 #[doc = "TIM8 clock enable Set and cleared by software."]
4004 #[inline(always)]
4005 pub fn set_tim8en(&mut self, val: bool) {
4006 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
4007 }
4008 #[doc = "USART1clock enable Set and cleared by software."]
4009 #[inline(always)]
4010 pub const fn usart1en(&self) -> bool {
4011 let val = (self.0 >> 14usize) & 0x01;
4012 val != 0
4013 }
4014 #[doc = "USART1clock enable Set and cleared by software."]
4015 #[inline(always)]
4016 pub fn set_usart1en(&mut self, val: bool) {
4017 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
4018 }
4019 #[doc = "TIM15 clock enable Set and cleared by software."]
4020 #[inline(always)]
4021 pub const fn tim15en(&self) -> bool {
4022 let val = (self.0 >> 16usize) & 0x01;
4023 val != 0
4024 }
4025 #[doc = "TIM15 clock enable Set and cleared by software."]
4026 #[inline(always)]
4027 pub fn set_tim15en(&mut self, val: bool) {
4028 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
4029 }
4030 #[doc = "TIM16 clock enable Set and cleared by software."]
4031 #[inline(always)]
4032 pub const fn tim16en(&self) -> bool {
4033 let val = (self.0 >> 17usize) & 0x01;
4034 val != 0
4035 }
4036 #[doc = "TIM16 clock enable Set and cleared by software."]
4037 #[inline(always)]
4038 pub fn set_tim16en(&mut self, val: bool) {
4039 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
4040 }
4041 #[doc = "TIM17 clock enable Set and cleared by software."]
4042 #[inline(always)]
4043 pub const fn tim17en(&self) -> bool {
4044 let val = (self.0 >> 18usize) & 0x01;
4045 val != 0
4046 }
4047 #[doc = "TIM17 clock enable Set and cleared by software."]
4048 #[inline(always)]
4049 pub fn set_tim17en(&mut self, val: bool) {
4050 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
4051 }
4052 #[doc = "SAI1 clock enable Set and cleared by software."]
4053 #[inline(always)]
4054 pub const fn sai1en(&self) -> bool {
4055 let val = (self.0 >> 21usize) & 0x01;
4056 val != 0
4057 }
4058 #[doc = "SAI1 clock enable Set and cleared by software."]
4059 #[inline(always)]
4060 pub fn set_sai1en(&mut self, val: bool) {
4061 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
4062 }
4063 #[doc = "SAI2 clock enable Set and cleared by software."]
4064 #[inline(always)]
4065 pub const fn sai2en(&self) -> bool {
4066 let val = (self.0 >> 22usize) & 0x01;
4067 val != 0
4068 }
4069 #[doc = "SAI2 clock enable Set and cleared by software."]
4070 #[inline(always)]
4071 pub fn set_sai2en(&mut self, val: bool) {
4072 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
4073 }
4074 #[doc = "USB clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
4075 #[inline(always)]
4076 pub const fn usben(&self) -> bool {
4077 let val = (self.0 >> 24usize) & 0x01;
4078 val != 0
4079 }
4080 #[doc = "USB clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
4081 #[inline(always)]
4082 pub fn set_usben(&mut self, val: bool) {
4083 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
4084 }
4085 #[doc = "GFXTIM clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
4086 #[inline(always)]
4087 pub const fn gfxtimen(&self) -> bool {
4088 let val = (self.0 >> 25usize) & 0x01;
4089 val != 0
4090 }
4091 #[doc = "GFXTIM clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
4092 #[inline(always)]
4093 pub fn set_gfxtimen(&mut self, val: bool) {
4094 self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
4095 }
4096 #[doc = "LTDC clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
4097 #[inline(always)]
4098 pub const fn ltdcen(&self) -> bool {
4099 let val = (self.0 >> 26usize) & 0x01;
4100 val != 0
4101 }
4102 #[doc = "LTDC clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
4103 #[inline(always)]
4104 pub fn set_ltdcen(&mut self, val: bool) {
4105 self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
4106 }
4107 #[doc = "DSI clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
4108 #[inline(always)]
4109 pub const fn dsien(&self) -> bool {
4110 let val = (self.0 >> 27usize) & 0x01;
4111 val != 0
4112 }
4113 #[doc = "DSI clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
4114 #[inline(always)]
4115 pub fn set_dsien(&mut self, val: bool) {
4116 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
4117 }
4118 }
4119 impl Default for Apb2enr {
4120 #[inline(always)]
4121 fn default() -> Apb2enr {
4122 Apb2enr(0)
4123 }
4124 }
4125 impl core::fmt::Debug for Apb2enr {
4126 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4127 f.debug_struct("Apb2enr")
4128 .field("tim1en", &self.tim1en())
4129 .field("spi1en", &self.spi1en())
4130 .field("tim8en", &self.tim8en())
4131 .field("usart1en", &self.usart1en())
4132 .field("tim15en", &self.tim15en())
4133 .field("tim16en", &self.tim16en())
4134 .field("tim17en", &self.tim17en())
4135 .field("sai1en", &self.sai1en())
4136 .field("sai2en", &self.sai2en())
4137 .field("usben", &self.usben())
4138 .field("gfxtimen", &self.gfxtimen())
4139 .field("ltdcen", &self.ltdcen())
4140 .field("dsien", &self.dsien())
4141 .finish()
4142 }
4143 }
4144 #[cfg(feature = "defmt")]
4145 impl defmt::Format for Apb2enr {
4146 fn format(&self, f: defmt::Formatter) {
4147 #[derive(defmt :: Format)]
4148 struct Apb2enr {
4149 tim1en: bool,
4150 spi1en: bool,
4151 tim8en: bool,
4152 usart1en: bool,
4153 tim15en: bool,
4154 tim16en: bool,
4155 tim17en: bool,
4156 sai1en: bool,
4157 sai2en: bool,
4158 usben: bool,
4159 gfxtimen: bool,
4160 ltdcen: bool,
4161 dsien: bool,
4162 }
4163 let proxy = Apb2enr {
4164 tim1en: self.tim1en(),
4165 spi1en: self.spi1en(),
4166 tim8en: self.tim8en(),
4167 usart1en: self.usart1en(),
4168 tim15en: self.tim15en(),
4169 tim16en: self.tim16en(),
4170 tim17en: self.tim17en(),
4171 sai1en: self.sai1en(),
4172 sai2en: self.sai2en(),
4173 usben: self.usben(),
4174 gfxtimen: self.gfxtimen(),
4175 ltdcen: self.ltdcen(),
4176 dsien: self.dsien(),
4177 };
4178 defmt::write!(f, "{}", proxy)
4179 }
4180 }
4181 #[doc = "RCC APB2 peripheral reset register"]
4182 #[repr(transparent)]
4183 #[derive(Copy, Clone, Eq, PartialEq)]
4184 pub struct Apb2rstr(pub u32);
4185 impl Apb2rstr {
4186 #[doc = "TIM1 reset Set and cleared by software."]
4187 #[inline(always)]
4188 pub const fn tim1rst(&self) -> bool {
4189 let val = (self.0 >> 11usize) & 0x01;
4190 val != 0
4191 }
4192 #[doc = "TIM1 reset Set and cleared by software."]
4193 #[inline(always)]
4194 pub fn set_tim1rst(&mut self, val: bool) {
4195 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
4196 }
4197 #[doc = "SPI1 reset Set and cleared by software."]
4198 #[inline(always)]
4199 pub const fn spi1rst(&self) -> bool {
4200 let val = (self.0 >> 12usize) & 0x01;
4201 val != 0
4202 }
4203 #[doc = "SPI1 reset Set and cleared by software."]
4204 #[inline(always)]
4205 pub fn set_spi1rst(&mut self, val: bool) {
4206 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
4207 }
4208 #[doc = "TIM8 reset Set and cleared by software."]
4209 #[inline(always)]
4210 pub const fn tim8rst(&self) -> bool {
4211 let val = (self.0 >> 13usize) & 0x01;
4212 val != 0
4213 }
4214 #[doc = "TIM8 reset Set and cleared by software."]
4215 #[inline(always)]
4216 pub fn set_tim8rst(&mut self, val: bool) {
4217 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
4218 }
4219 #[doc = "USART1 reset Set and cleared by software."]
4220 #[inline(always)]
4221 pub const fn usart1rst(&self) -> bool {
4222 let val = (self.0 >> 14usize) & 0x01;
4223 val != 0
4224 }
4225 #[doc = "USART1 reset Set and cleared by software."]
4226 #[inline(always)]
4227 pub fn set_usart1rst(&mut self, val: bool) {
4228 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
4229 }
4230 #[doc = "TIM15 reset Set and cleared by software."]
4231 #[inline(always)]
4232 pub const fn tim15rst(&self) -> bool {
4233 let val = (self.0 >> 16usize) & 0x01;
4234 val != 0
4235 }
4236 #[doc = "TIM15 reset Set and cleared by software."]
4237 #[inline(always)]
4238 pub fn set_tim15rst(&mut self, val: bool) {
4239 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
4240 }
4241 #[doc = "TIM16 reset Set and cleared by software."]
4242 #[inline(always)]
4243 pub const fn tim16rst(&self) -> bool {
4244 let val = (self.0 >> 17usize) & 0x01;
4245 val != 0
4246 }
4247 #[doc = "TIM16 reset Set and cleared by software."]
4248 #[inline(always)]
4249 pub fn set_tim16rst(&mut self, val: bool) {
4250 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
4251 }
4252 #[doc = "TIM17 reset Set and cleared by software."]
4253 #[inline(always)]
4254 pub const fn tim17rst(&self) -> bool {
4255 let val = (self.0 >> 18usize) & 0x01;
4256 val != 0
4257 }
4258 #[doc = "TIM17 reset Set and cleared by software."]
4259 #[inline(always)]
4260 pub fn set_tim17rst(&mut self, val: bool) {
4261 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
4262 }
4263 #[doc = "SAI1 reset Set and cleared by software."]
4264 #[inline(always)]
4265 pub const fn sai1rst(&self) -> bool {
4266 let val = (self.0 >> 21usize) & 0x01;
4267 val != 0
4268 }
4269 #[doc = "SAI1 reset Set and cleared by software."]
4270 #[inline(always)]
4271 pub fn set_sai1rst(&mut self, val: bool) {
4272 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
4273 }
4274 #[doc = "SAI2 reset Set and cleared by software."]
4275 #[inline(always)]
4276 pub const fn sai2rst(&self) -> bool {
4277 let val = (self.0 >> 22usize) & 0x01;
4278 val != 0
4279 }
4280 #[doc = "SAI2 reset Set and cleared by software."]
4281 #[inline(always)]
4282 pub fn set_sai2rst(&mut self, val: bool) {
4283 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
4284 }
4285 #[doc = "USB reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
4286 #[inline(always)]
4287 pub const fn usbrst(&self) -> bool {
4288 let val = (self.0 >> 24usize) & 0x01;
4289 val != 0
4290 }
4291 #[doc = "USB reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
4292 #[inline(always)]
4293 pub fn set_usbrst(&mut self, val: bool) {
4294 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
4295 }
4296 #[doc = "GFXTIM reset This bit is set and cleared by software. Note: .This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
4297 #[inline(always)]
4298 pub const fn gfxtimrst(&self) -> bool {
4299 let val = (self.0 >> 25usize) & 0x01;
4300 val != 0
4301 }
4302 #[doc = "GFXTIM reset This bit is set and cleared by software. Note: .This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
4303 #[inline(always)]
4304 pub fn set_gfxtimrst(&mut self, val: bool) {
4305 self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
4306 }
4307 #[doc = "LTDC reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
4308 #[inline(always)]
4309 pub const fn ltdcrst(&self) -> bool {
4310 let val = (self.0 >> 26usize) & 0x01;
4311 val != 0
4312 }
4313 #[doc = "LTDC reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
4314 #[inline(always)]
4315 pub fn set_ltdcrst(&mut self, val: bool) {
4316 self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
4317 }
4318 #[doc = "DSI reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
4319 #[inline(always)]
4320 pub const fn dsirst(&self) -> bool {
4321 let val = (self.0 >> 27usize) & 0x01;
4322 val != 0
4323 }
4324 #[doc = "DSI reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
4325 #[inline(always)]
4326 pub fn set_dsirst(&mut self, val: bool) {
4327 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
4328 }
4329 }
4330 impl Default for Apb2rstr {
4331 #[inline(always)]
4332 fn default() -> Apb2rstr {
4333 Apb2rstr(0)
4334 }
4335 }
4336 impl core::fmt::Debug for Apb2rstr {
4337 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4338 f.debug_struct("Apb2rstr")
4339 .field("tim1rst", &self.tim1rst())
4340 .field("spi1rst", &self.spi1rst())
4341 .field("tim8rst", &self.tim8rst())
4342 .field("usart1rst", &self.usart1rst())
4343 .field("tim15rst", &self.tim15rst())
4344 .field("tim16rst", &self.tim16rst())
4345 .field("tim17rst", &self.tim17rst())
4346 .field("sai1rst", &self.sai1rst())
4347 .field("sai2rst", &self.sai2rst())
4348 .field("usbrst", &self.usbrst())
4349 .field("gfxtimrst", &self.gfxtimrst())
4350 .field("ltdcrst", &self.ltdcrst())
4351 .field("dsirst", &self.dsirst())
4352 .finish()
4353 }
4354 }
4355 #[cfg(feature = "defmt")]
4356 impl defmt::Format for Apb2rstr {
4357 fn format(&self, f: defmt::Formatter) {
4358 #[derive(defmt :: Format)]
4359 struct Apb2rstr {
4360 tim1rst: bool,
4361 spi1rst: bool,
4362 tim8rst: bool,
4363 usart1rst: bool,
4364 tim15rst: bool,
4365 tim16rst: bool,
4366 tim17rst: bool,
4367 sai1rst: bool,
4368 sai2rst: bool,
4369 usbrst: bool,
4370 gfxtimrst: bool,
4371 ltdcrst: bool,
4372 dsirst: bool,
4373 }
4374 let proxy = Apb2rstr {
4375 tim1rst: self.tim1rst(),
4376 spi1rst: self.spi1rst(),
4377 tim8rst: self.tim8rst(),
4378 usart1rst: self.usart1rst(),
4379 tim15rst: self.tim15rst(),
4380 tim16rst: self.tim16rst(),
4381 tim17rst: self.tim17rst(),
4382 sai1rst: self.sai1rst(),
4383 sai2rst: self.sai2rst(),
4384 usbrst: self.usbrst(),
4385 gfxtimrst: self.gfxtimrst(),
4386 ltdcrst: self.ltdcrst(),
4387 dsirst: self.dsirst(),
4388 };
4389 defmt::write!(f, "{}", proxy)
4390 }
4391 }
4392 #[doc = "RCC APB2 peripheral clocks enable in Sleep and Stop modes register"]
4393 #[repr(transparent)]
4394 #[derive(Copy, Clone, Eq, PartialEq)]
4395 pub struct Apb2smenr(pub u32);
4396 impl Apb2smenr {
4397 #[doc = "TIM1 clocks enable during Sleep and Stop modes Set and cleared by software."]
4398 #[inline(always)]
4399 pub const fn tim1smen(&self) -> bool {
4400 let val = (self.0 >> 11usize) & 0x01;
4401 val != 0
4402 }
4403 #[doc = "TIM1 clocks enable during Sleep and Stop modes Set and cleared by software."]
4404 #[inline(always)]
4405 pub fn set_tim1smen(&mut self, val: bool) {
4406 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
4407 }
4408 #[doc = "SPI1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
4409 #[inline(always)]
4410 pub const fn spi1smen(&self) -> bool {
4411 let val = (self.0 >> 12usize) & 0x01;
4412 val != 0
4413 }
4414 #[doc = "SPI1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
4415 #[inline(always)]
4416 pub fn set_spi1smen(&mut self, val: bool) {
4417 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
4418 }
4419 #[doc = "TIM8 clocks enable during Sleep and Stop modes Set and cleared by software."]
4420 #[inline(always)]
4421 pub const fn tim8smen(&self) -> bool {
4422 let val = (self.0 >> 13usize) & 0x01;
4423 val != 0
4424 }
4425 #[doc = "TIM8 clocks enable during Sleep and Stop modes Set and cleared by software."]
4426 #[inline(always)]
4427 pub fn set_tim8smen(&mut self, val: bool) {
4428 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
4429 }
4430 #[doc = "USART1clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
4431 #[inline(always)]
4432 pub const fn usart1smen(&self) -> bool {
4433 let val = (self.0 >> 14usize) & 0x01;
4434 val != 0
4435 }
4436 #[doc = "USART1clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
4437 #[inline(always)]
4438 pub fn set_usart1smen(&mut self, val: bool) {
4439 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
4440 }
4441 #[doc = "TIM15 clocks enable during Sleep and Stop modes Set and cleared by software."]
4442 #[inline(always)]
4443 pub const fn tim15smen(&self) -> bool {
4444 let val = (self.0 >> 16usize) & 0x01;
4445 val != 0
4446 }
4447 #[doc = "TIM15 clocks enable during Sleep and Stop modes Set and cleared by software."]
4448 #[inline(always)]
4449 pub fn set_tim15smen(&mut self, val: bool) {
4450 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
4451 }
4452 #[doc = "TIM16 clocks enable during Sleep and Stop modes Set and cleared by software."]
4453 #[inline(always)]
4454 pub const fn tim16smen(&self) -> bool {
4455 let val = (self.0 >> 17usize) & 0x01;
4456 val != 0
4457 }
4458 #[doc = "TIM16 clocks enable during Sleep and Stop modes Set and cleared by software."]
4459 #[inline(always)]
4460 pub fn set_tim16smen(&mut self, val: bool) {
4461 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
4462 }
4463 #[doc = "TIM17 clocks enable during Sleep and Stop modes Set and cleared by software."]
4464 #[inline(always)]
4465 pub const fn tim17smen(&self) -> bool {
4466 let val = (self.0 >> 18usize) & 0x01;
4467 val != 0
4468 }
4469 #[doc = "TIM17 clocks enable during Sleep and Stop modes Set and cleared by software."]
4470 #[inline(always)]
4471 pub fn set_tim17smen(&mut self, val: bool) {
4472 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
4473 }
4474 #[doc = "SAI1 clocks enable during Sleep and Stop modes Set and cleared by software."]
4475 #[inline(always)]
4476 pub const fn sai1smen(&self) -> bool {
4477 let val = (self.0 >> 21usize) & 0x01;
4478 val != 0
4479 }
4480 #[doc = "SAI1 clocks enable during Sleep and Stop modes Set and cleared by software."]
4481 #[inline(always)]
4482 pub fn set_sai1smen(&mut self, val: bool) {
4483 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
4484 }
4485 #[doc = "SAI2 clocks enable during Sleep and Stop modes Set and cleared by software."]
4486 #[inline(always)]
4487 pub const fn sai2smen(&self) -> bool {
4488 let val = (self.0 >> 22usize) & 0x01;
4489 val != 0
4490 }
4491 #[doc = "SAI2 clocks enable during Sleep and Stop modes Set and cleared by software."]
4492 #[inline(always)]
4493 pub fn set_sai2smen(&mut self, val: bool) {
4494 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
4495 }
4496 #[doc = "USB clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
4497 #[inline(always)]
4498 pub const fn usbsmen(&self) -> bool {
4499 let val = (self.0 >> 24usize) & 0x01;
4500 val != 0
4501 }
4502 #[doc = "USB clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
4503 #[inline(always)]
4504 pub fn set_usbsmen(&mut self, val: bool) {
4505 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
4506 }
4507 #[doc = "GFXTIM clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
4508 #[inline(always)]
4509 pub const fn gfxtimsmen(&self) -> bool {
4510 let val = (self.0 >> 25usize) & 0x01;
4511 val != 0
4512 }
4513 #[doc = "GFXTIM clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
4514 #[inline(always)]
4515 pub fn set_gfxtimsmen(&mut self, val: bool) {
4516 self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
4517 }
4518 #[doc = "LTDC clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
4519 #[inline(always)]
4520 pub const fn ltdcsmen(&self) -> bool {
4521 let val = (self.0 >> 26usize) & 0x01;
4522 val != 0
4523 }
4524 #[doc = "LTDC clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
4525 #[inline(always)]
4526 pub fn set_ltdcsmen(&mut self, val: bool) {
4527 self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
4528 }
4529 #[doc = "DSI clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
4530 #[inline(always)]
4531 pub const fn dsismen(&self) -> bool {
4532 let val = (self.0 >> 27usize) & 0x01;
4533 val != 0
4534 }
4535 #[doc = "DSI clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
4536 #[inline(always)]
4537 pub fn set_dsismen(&mut self, val: bool) {
4538 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
4539 }
4540 }
4541 impl Default for Apb2smenr {
4542 #[inline(always)]
4543 fn default() -> Apb2smenr {
4544 Apb2smenr(0)
4545 }
4546 }
4547 impl core::fmt::Debug for Apb2smenr {
4548 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4549 f.debug_struct("Apb2smenr")
4550 .field("tim1smen", &self.tim1smen())
4551 .field("spi1smen", &self.spi1smen())
4552 .field("tim8smen", &self.tim8smen())
4553 .field("usart1smen", &self.usart1smen())
4554 .field("tim15smen", &self.tim15smen())
4555 .field("tim16smen", &self.tim16smen())
4556 .field("tim17smen", &self.tim17smen())
4557 .field("sai1smen", &self.sai1smen())
4558 .field("sai2smen", &self.sai2smen())
4559 .field("usbsmen", &self.usbsmen())
4560 .field("gfxtimsmen", &self.gfxtimsmen())
4561 .field("ltdcsmen", &self.ltdcsmen())
4562 .field("dsismen", &self.dsismen())
4563 .finish()
4564 }
4565 }
4566 #[cfg(feature = "defmt")]
4567 impl defmt::Format for Apb2smenr {
4568 fn format(&self, f: defmt::Formatter) {
4569 #[derive(defmt :: Format)]
4570 struct Apb2smenr {
4571 tim1smen: bool,
4572 spi1smen: bool,
4573 tim8smen: bool,
4574 usart1smen: bool,
4575 tim15smen: bool,
4576 tim16smen: bool,
4577 tim17smen: bool,
4578 sai1smen: bool,
4579 sai2smen: bool,
4580 usbsmen: bool,
4581 gfxtimsmen: bool,
4582 ltdcsmen: bool,
4583 dsismen: bool,
4584 }
4585 let proxy = Apb2smenr {
4586 tim1smen: self.tim1smen(),
4587 spi1smen: self.spi1smen(),
4588 tim8smen: self.tim8smen(),
4589 usart1smen: self.usart1smen(),
4590 tim15smen: self.tim15smen(),
4591 tim16smen: self.tim16smen(),
4592 tim17smen: self.tim17smen(),
4593 sai1smen: self.sai1smen(),
4594 sai2smen: self.sai2smen(),
4595 usbsmen: self.usbsmen(),
4596 gfxtimsmen: self.gfxtimsmen(),
4597 ltdcsmen: self.ltdcsmen(),
4598 dsismen: self.dsismen(),
4599 };
4600 defmt::write!(f, "{}", proxy)
4601 }
4602 }
4603 #[doc = "RCC APB3 peripheral clock enable register"]
4604 #[repr(transparent)]
4605 #[derive(Copy, Clone, Eq, PartialEq)]
4606 pub struct Apb3enr(pub u32);
4607 impl Apb3enr {
4608 #[doc = "SYSCFG clock enable Set and cleared by software."]
4609 #[inline(always)]
4610 pub const fn syscfgen(&self) -> bool {
4611 let val = (self.0 >> 1usize) & 0x01;
4612 val != 0
4613 }
4614 #[doc = "SYSCFG clock enable Set and cleared by software."]
4615 #[inline(always)]
4616 pub fn set_syscfgen(&mut self, val: bool) {
4617 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
4618 }
4619 #[doc = "SPI3 clock enable Set and cleared by software."]
4620 #[inline(always)]
4621 pub const fn spi3en(&self) -> bool {
4622 let val = (self.0 >> 5usize) & 0x01;
4623 val != 0
4624 }
4625 #[doc = "SPI3 clock enable Set and cleared by software."]
4626 #[inline(always)]
4627 pub fn set_spi3en(&mut self, val: bool) {
4628 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
4629 }
4630 #[doc = "LPUART1 clock enable Set and cleared by software."]
4631 #[inline(always)]
4632 pub const fn lpuart1en(&self) -> bool {
4633 let val = (self.0 >> 6usize) & 0x01;
4634 val != 0
4635 }
4636 #[doc = "LPUART1 clock enable Set and cleared by software."]
4637 #[inline(always)]
4638 pub fn set_lpuart1en(&mut self, val: bool) {
4639 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
4640 }
4641 #[doc = "I2C3 clock enable Set and cleared by software."]
4642 #[inline(always)]
4643 pub const fn i2c3en(&self) -> bool {
4644 let val = (self.0 >> 7usize) & 0x01;
4645 val != 0
4646 }
4647 #[doc = "I2C3 clock enable Set and cleared by software."]
4648 #[inline(always)]
4649 pub fn set_i2c3en(&mut self, val: bool) {
4650 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
4651 }
4652 #[doc = "LPTIM1 clock enable Set and cleared by software."]
4653 #[inline(always)]
4654 pub const fn lptim1en(&self) -> bool {
4655 let val = (self.0 >> 11usize) & 0x01;
4656 val != 0
4657 }
4658 #[doc = "LPTIM1 clock enable Set and cleared by software."]
4659 #[inline(always)]
4660 pub fn set_lptim1en(&mut self, val: bool) {
4661 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
4662 }
4663 #[doc = "LPTIM3 clock enable Set and cleared by software."]
4664 #[inline(always)]
4665 pub const fn lptim3en(&self) -> bool {
4666 let val = (self.0 >> 12usize) & 0x01;
4667 val != 0
4668 }
4669 #[doc = "LPTIM3 clock enable Set and cleared by software."]
4670 #[inline(always)]
4671 pub fn set_lptim3en(&mut self, val: bool) {
4672 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
4673 }
4674 #[doc = "LPTIM4 clock enable Set and cleared by software."]
4675 #[inline(always)]
4676 pub const fn lptim4en(&self) -> bool {
4677 let val = (self.0 >> 13usize) & 0x01;
4678 val != 0
4679 }
4680 #[doc = "LPTIM4 clock enable Set and cleared by software."]
4681 #[inline(always)]
4682 pub fn set_lptim4en(&mut self, val: bool) {
4683 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
4684 }
4685 #[doc = "OPAMP clock enable Set and cleared by software."]
4686 #[inline(always)]
4687 pub const fn opampen(&self) -> bool {
4688 let val = (self.0 >> 14usize) & 0x01;
4689 val != 0
4690 }
4691 #[doc = "OPAMP clock enable Set and cleared by software."]
4692 #[inline(always)]
4693 pub fn set_opampen(&mut self, val: bool) {
4694 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
4695 }
4696 #[doc = "COMP clock enable Set and cleared by software."]
4697 #[inline(always)]
4698 pub const fn compen(&self) -> bool {
4699 let val = (self.0 >> 15usize) & 0x01;
4700 val != 0
4701 }
4702 #[doc = "COMP clock enable Set and cleared by software."]
4703 #[inline(always)]
4704 pub fn set_compen(&mut self, val: bool) {
4705 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
4706 }
4707 #[doc = "VREFBUF clock enable Set and cleared by software."]
4708 #[inline(always)]
4709 pub const fn vrefen(&self) -> bool {
4710 let val = (self.0 >> 20usize) & 0x01;
4711 val != 0
4712 }
4713 #[doc = "VREFBUF clock enable Set and cleared by software."]
4714 #[inline(always)]
4715 pub fn set_vrefen(&mut self, val: bool) {
4716 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
4717 }
4718 #[doc = "RTC and TAMP APB clock enable Set and cleared by software."]
4719 #[inline(always)]
4720 pub const fn rtcapben(&self) -> bool {
4721 let val = (self.0 >> 21usize) & 0x01;
4722 val != 0
4723 }
4724 #[doc = "RTC and TAMP APB clock enable Set and cleared by software."]
4725 #[inline(always)]
4726 pub fn set_rtcapben(&mut self, val: bool) {
4727 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
4728 }
4729 }
4730 impl Default for Apb3enr {
4731 #[inline(always)]
4732 fn default() -> Apb3enr {
4733 Apb3enr(0)
4734 }
4735 }
4736 impl core::fmt::Debug for Apb3enr {
4737 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4738 f.debug_struct("Apb3enr")
4739 .field("syscfgen", &self.syscfgen())
4740 .field("spi3en", &self.spi3en())
4741 .field("lpuart1en", &self.lpuart1en())
4742 .field("i2c3en", &self.i2c3en())
4743 .field("lptim1en", &self.lptim1en())
4744 .field("lptim3en", &self.lptim3en())
4745 .field("lptim4en", &self.lptim4en())
4746 .field("opampen", &self.opampen())
4747 .field("compen", &self.compen())
4748 .field("vrefen", &self.vrefen())
4749 .field("rtcapben", &self.rtcapben())
4750 .finish()
4751 }
4752 }
4753 #[cfg(feature = "defmt")]
4754 impl defmt::Format for Apb3enr {
4755 fn format(&self, f: defmt::Formatter) {
4756 #[derive(defmt :: Format)]
4757 struct Apb3enr {
4758 syscfgen: bool,
4759 spi3en: bool,
4760 lpuart1en: bool,
4761 i2c3en: bool,
4762 lptim1en: bool,
4763 lptim3en: bool,
4764 lptim4en: bool,
4765 opampen: bool,
4766 compen: bool,
4767 vrefen: bool,
4768 rtcapben: bool,
4769 }
4770 let proxy = Apb3enr {
4771 syscfgen: self.syscfgen(),
4772 spi3en: self.spi3en(),
4773 lpuart1en: self.lpuart1en(),
4774 i2c3en: self.i2c3en(),
4775 lptim1en: self.lptim1en(),
4776 lptim3en: self.lptim3en(),
4777 lptim4en: self.lptim4en(),
4778 opampen: self.opampen(),
4779 compen: self.compen(),
4780 vrefen: self.vrefen(),
4781 rtcapben: self.rtcapben(),
4782 };
4783 defmt::write!(f, "{}", proxy)
4784 }
4785 }
4786 #[doc = "RCC APB3 peripheral reset register"]
4787 #[repr(transparent)]
4788 #[derive(Copy, Clone, Eq, PartialEq)]
4789 pub struct Apb3rstr(pub u32);
4790 impl Apb3rstr {
4791 #[doc = "SYSCFG reset Set and cleared by software."]
4792 #[inline(always)]
4793 pub const fn syscfgrst(&self) -> bool {
4794 let val = (self.0 >> 1usize) & 0x01;
4795 val != 0
4796 }
4797 #[doc = "SYSCFG reset Set and cleared by software."]
4798 #[inline(always)]
4799 pub fn set_syscfgrst(&mut self, val: bool) {
4800 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
4801 }
4802 #[doc = "SPI3 reset Set and cleared by software."]
4803 #[inline(always)]
4804 pub const fn spi3rst(&self) -> bool {
4805 let val = (self.0 >> 5usize) & 0x01;
4806 val != 0
4807 }
4808 #[doc = "SPI3 reset Set and cleared by software."]
4809 #[inline(always)]
4810 pub fn set_spi3rst(&mut self, val: bool) {
4811 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
4812 }
4813 #[doc = "LPUART1 reset Set and cleared by software."]
4814 #[inline(always)]
4815 pub const fn lpuart1rst(&self) -> bool {
4816 let val = (self.0 >> 6usize) & 0x01;
4817 val != 0
4818 }
4819 #[doc = "LPUART1 reset Set and cleared by software."]
4820 #[inline(always)]
4821 pub fn set_lpuart1rst(&mut self, val: bool) {
4822 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
4823 }
4824 #[doc = "I2C3 reset Set and cleared by software."]
4825 #[inline(always)]
4826 pub const fn i2c3rst(&self) -> bool {
4827 let val = (self.0 >> 7usize) & 0x01;
4828 val != 0
4829 }
4830 #[doc = "I2C3 reset Set and cleared by software."]
4831 #[inline(always)]
4832 pub fn set_i2c3rst(&mut self, val: bool) {
4833 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
4834 }
4835 #[doc = "LPTIM1 reset Set and cleared by software."]
4836 #[inline(always)]
4837 pub const fn lptim1rst(&self) -> bool {
4838 let val = (self.0 >> 11usize) & 0x01;
4839 val != 0
4840 }
4841 #[doc = "LPTIM1 reset Set and cleared by software."]
4842 #[inline(always)]
4843 pub fn set_lptim1rst(&mut self, val: bool) {
4844 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
4845 }
4846 #[doc = "LPTIM3 reset Set and cleared by software."]
4847 #[inline(always)]
4848 pub const fn lptim3rst(&self) -> bool {
4849 let val = (self.0 >> 12usize) & 0x01;
4850 val != 0
4851 }
4852 #[doc = "LPTIM3 reset Set and cleared by software."]
4853 #[inline(always)]
4854 pub fn set_lptim3rst(&mut self, val: bool) {
4855 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
4856 }
4857 #[doc = "LPTIM4 reset Set and cleared by software."]
4858 #[inline(always)]
4859 pub const fn lptim4rst(&self) -> bool {
4860 let val = (self.0 >> 13usize) & 0x01;
4861 val != 0
4862 }
4863 #[doc = "LPTIM4 reset Set and cleared by software."]
4864 #[inline(always)]
4865 pub fn set_lptim4rst(&mut self, val: bool) {
4866 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
4867 }
4868 #[doc = "OPAMP reset Set and cleared by software."]
4869 #[inline(always)]
4870 pub const fn opamprst(&self) -> bool {
4871 let val = (self.0 >> 14usize) & 0x01;
4872 val != 0
4873 }
4874 #[doc = "OPAMP reset Set and cleared by software."]
4875 #[inline(always)]
4876 pub fn set_opamprst(&mut self, val: bool) {
4877 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
4878 }
4879 #[doc = "COMP reset Set and cleared by software."]
4880 #[inline(always)]
4881 pub const fn comprst(&self) -> bool {
4882 let val = (self.0 >> 15usize) & 0x01;
4883 val != 0
4884 }
4885 #[doc = "COMP reset Set and cleared by software."]
4886 #[inline(always)]
4887 pub fn set_comprst(&mut self, val: bool) {
4888 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
4889 }
4890 #[doc = "VREFBUF reset Set and cleared by software."]
4891 #[inline(always)]
4892 pub const fn vrefrst(&self) -> bool {
4893 let val = (self.0 >> 20usize) & 0x01;
4894 val != 0
4895 }
4896 #[doc = "VREFBUF reset Set and cleared by software."]
4897 #[inline(always)]
4898 pub fn set_vrefrst(&mut self, val: bool) {
4899 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
4900 }
4901 }
4902 impl Default for Apb3rstr {
4903 #[inline(always)]
4904 fn default() -> Apb3rstr {
4905 Apb3rstr(0)
4906 }
4907 }
4908 impl core::fmt::Debug for Apb3rstr {
4909 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4910 f.debug_struct("Apb3rstr")
4911 .field("syscfgrst", &self.syscfgrst())
4912 .field("spi3rst", &self.spi3rst())
4913 .field("lpuart1rst", &self.lpuart1rst())
4914 .field("i2c3rst", &self.i2c3rst())
4915 .field("lptim1rst", &self.lptim1rst())
4916 .field("lptim3rst", &self.lptim3rst())
4917 .field("lptim4rst", &self.lptim4rst())
4918 .field("opamprst", &self.opamprst())
4919 .field("comprst", &self.comprst())
4920 .field("vrefrst", &self.vrefrst())
4921 .finish()
4922 }
4923 }
4924 #[cfg(feature = "defmt")]
4925 impl defmt::Format for Apb3rstr {
4926 fn format(&self, f: defmt::Formatter) {
4927 #[derive(defmt :: Format)]
4928 struct Apb3rstr {
4929 syscfgrst: bool,
4930 spi3rst: bool,
4931 lpuart1rst: bool,
4932 i2c3rst: bool,
4933 lptim1rst: bool,
4934 lptim3rst: bool,
4935 lptim4rst: bool,
4936 opamprst: bool,
4937 comprst: bool,
4938 vrefrst: bool,
4939 }
4940 let proxy = Apb3rstr {
4941 syscfgrst: self.syscfgrst(),
4942 spi3rst: self.spi3rst(),
4943 lpuart1rst: self.lpuart1rst(),
4944 i2c3rst: self.i2c3rst(),
4945 lptim1rst: self.lptim1rst(),
4946 lptim3rst: self.lptim3rst(),
4947 lptim4rst: self.lptim4rst(),
4948 opamprst: self.opamprst(),
4949 comprst: self.comprst(),
4950 vrefrst: self.vrefrst(),
4951 };
4952 defmt::write!(f, "{}", proxy)
4953 }
4954 }
4955 #[doc = "RCC APB3 peripheral clock enable in Sleep and Stop modes register"]
4956 #[repr(transparent)]
4957 #[derive(Copy, Clone, Eq, PartialEq)]
4958 pub struct Apb3smenr(pub u32);
4959 impl Apb3smenr {
4960 #[doc = "SYSCFG clocks enable during Sleep and Stop modes Set and cleared by software."]
4961 #[inline(always)]
4962 pub const fn syscfgsmen(&self) -> bool {
4963 let val = (self.0 >> 1usize) & 0x01;
4964 val != 0
4965 }
4966 #[doc = "SYSCFG clocks enable during Sleep and Stop modes Set and cleared by software."]
4967 #[inline(always)]
4968 pub fn set_syscfgsmen(&mut self, val: bool) {
4969 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
4970 }
4971 #[doc = "SPI3 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
4972 #[inline(always)]
4973 pub const fn spi3smen(&self) -> bool {
4974 let val = (self.0 >> 5usize) & 0x01;
4975 val != 0
4976 }
4977 #[doc = "SPI3 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
4978 #[inline(always)]
4979 pub fn set_spi3smen(&mut self, val: bool) {
4980 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
4981 }
4982 #[doc = "LPUART1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
4983 #[inline(always)]
4984 pub const fn lpuart1smen(&self) -> bool {
4985 let val = (self.0 >> 6usize) & 0x01;
4986 val != 0
4987 }
4988 #[doc = "LPUART1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
4989 #[inline(always)]
4990 pub fn set_lpuart1smen(&mut self, val: bool) {
4991 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
4992 }
4993 #[doc = "I2C3 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
4994 #[inline(always)]
4995 pub const fn i2c3smen(&self) -> bool {
4996 let val = (self.0 >> 7usize) & 0x01;
4997 val != 0
4998 }
4999 #[doc = "I2C3 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
5000 #[inline(always)]
5001 pub fn set_i2c3smen(&mut self, val: bool) {
5002 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
5003 }
5004 #[doc = "LPTIM1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
5005 #[inline(always)]
5006 pub const fn lptim1smen(&self) -> bool {
5007 let val = (self.0 >> 11usize) & 0x01;
5008 val != 0
5009 }
5010 #[doc = "LPTIM1 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
5011 #[inline(always)]
5012 pub fn set_lptim1smen(&mut self, val: bool) {
5013 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
5014 }
5015 #[doc = "LPTIM3 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
5016 #[inline(always)]
5017 pub const fn lptim3smen(&self) -> bool {
5018 let val = (self.0 >> 12usize) & 0x01;
5019 val != 0
5020 }
5021 #[doc = "LPTIM3 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
5022 #[inline(always)]
5023 pub fn set_lptim3smen(&mut self, val: bool) {
5024 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
5025 }
5026 #[doc = "LPTIM4 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
5027 #[inline(always)]
5028 pub const fn lptim4smen(&self) -> bool {
5029 let val = (self.0 >> 13usize) & 0x01;
5030 val != 0
5031 }
5032 #[doc = "LPTIM4 clocks enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
5033 #[inline(always)]
5034 pub fn set_lptim4smen(&mut self, val: bool) {
5035 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
5036 }
5037 #[doc = "OPAMP clocks enable during Sleep and Stop modes Set and cleared by software."]
5038 #[inline(always)]
5039 pub const fn opampsmen(&self) -> bool {
5040 let val = (self.0 >> 14usize) & 0x01;
5041 val != 0
5042 }
5043 #[doc = "OPAMP clocks enable during Sleep and Stop modes Set and cleared by software."]
5044 #[inline(always)]
5045 pub fn set_opampsmen(&mut self, val: bool) {
5046 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
5047 }
5048 #[doc = "COMP clocks enable during Sleep and Stop modes Set and cleared by software."]
5049 #[inline(always)]
5050 pub const fn compsmen(&self) -> bool {
5051 let val = (self.0 >> 15usize) & 0x01;
5052 val != 0
5053 }
5054 #[doc = "COMP clocks enable during Sleep and Stop modes Set and cleared by software."]
5055 #[inline(always)]
5056 pub fn set_compsmen(&mut self, val: bool) {
5057 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
5058 }
5059 #[doc = "VREFBUF clocks enable during Sleep and Stop modes Set and cleared by software."]
5060 #[inline(always)]
5061 pub const fn vrefsmen(&self) -> bool {
5062 let val = (self.0 >> 20usize) & 0x01;
5063 val != 0
5064 }
5065 #[doc = "VREFBUF clocks enable during Sleep and Stop modes Set and cleared by software."]
5066 #[inline(always)]
5067 pub fn set_vrefsmen(&mut self, val: bool) {
5068 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
5069 }
5070 #[doc = "RTC and TAMP APB clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
5071 #[inline(always)]
5072 pub const fn rtcapbsmen(&self) -> bool {
5073 let val = (self.0 >> 21usize) & 0x01;
5074 val != 0
5075 }
5076 #[doc = "RTC and TAMP APB clock enable during Sleep and Stop modes Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
5077 #[inline(always)]
5078 pub fn set_rtcapbsmen(&mut self, val: bool) {
5079 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
5080 }
5081 }
5082 impl Default for Apb3smenr {
5083 #[inline(always)]
5084 fn default() -> Apb3smenr {
5085 Apb3smenr(0)
5086 }
5087 }
5088 impl core::fmt::Debug for Apb3smenr {
5089 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5090 f.debug_struct("Apb3smenr")
5091 .field("syscfgsmen", &self.syscfgsmen())
5092 .field("spi3smen", &self.spi3smen())
5093 .field("lpuart1smen", &self.lpuart1smen())
5094 .field("i2c3smen", &self.i2c3smen())
5095 .field("lptim1smen", &self.lptim1smen())
5096 .field("lptim3smen", &self.lptim3smen())
5097 .field("lptim4smen", &self.lptim4smen())
5098 .field("opampsmen", &self.opampsmen())
5099 .field("compsmen", &self.compsmen())
5100 .field("vrefsmen", &self.vrefsmen())
5101 .field("rtcapbsmen", &self.rtcapbsmen())
5102 .finish()
5103 }
5104 }
5105 #[cfg(feature = "defmt")]
5106 impl defmt::Format for Apb3smenr {
5107 fn format(&self, f: defmt::Formatter) {
5108 #[derive(defmt :: Format)]
5109 struct Apb3smenr {
5110 syscfgsmen: bool,
5111 spi3smen: bool,
5112 lpuart1smen: bool,
5113 i2c3smen: bool,
5114 lptim1smen: bool,
5115 lptim3smen: bool,
5116 lptim4smen: bool,
5117 opampsmen: bool,
5118 compsmen: bool,
5119 vrefsmen: bool,
5120 rtcapbsmen: bool,
5121 }
5122 let proxy = Apb3smenr {
5123 syscfgsmen: self.syscfgsmen(),
5124 spi3smen: self.spi3smen(),
5125 lpuart1smen: self.lpuart1smen(),
5126 i2c3smen: self.i2c3smen(),
5127 lptim1smen: self.lptim1smen(),
5128 lptim3smen: self.lptim3smen(),
5129 lptim4smen: self.lptim4smen(),
5130 opampsmen: self.opampsmen(),
5131 compsmen: self.compsmen(),
5132 vrefsmen: self.vrefsmen(),
5133 rtcapbsmen: self.rtcapbsmen(),
5134 };
5135 defmt::write!(f, "{}", proxy)
5136 }
5137 }
5138 #[doc = "RCC Backup domain control register"]
5139 #[repr(transparent)]
5140 #[derive(Copy, Clone, Eq, PartialEq)]
5141 pub struct Bdcr(pub u32);
5142 impl Bdcr {
5143 #[doc = "LSE oscillator enable Set and cleared by software."]
5144 #[inline(always)]
5145 pub const fn lseon(&self) -> bool {
5146 let val = (self.0 >> 0usize) & 0x01;
5147 val != 0
5148 }
5149 #[doc = "LSE oscillator enable Set and cleared by software."]
5150 #[inline(always)]
5151 pub fn set_lseon(&mut self, val: bool) {
5152 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
5153 }
5154 #[doc = "LSE oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles."]
5155 #[inline(always)]
5156 pub const fn lserdy(&self) -> bool {
5157 let val = (self.0 >> 1usize) & 0x01;
5158 val != 0
5159 }
5160 #[doc = "LSE oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles."]
5161 #[inline(always)]
5162 pub fn set_lserdy(&mut self, val: bool) {
5163 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
5164 }
5165 #[doc = "LSE oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0)."]
5166 #[inline(always)]
5167 pub const fn lsebyp(&self) -> bool {
5168 let val = (self.0 >> 2usize) & 0x01;
5169 val != 0
5170 }
5171 #[doc = "LSE oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0)."]
5172 #[inline(always)]
5173 pub fn set_lsebyp(&mut self, val: bool) {
5174 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
5175 }
5176 #[doc = "LSE oscillator drive capability Set by software to modulate the drive capability of the LSE oscillator. This field can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0). Note: The oscillator is in 'Xtal mode when it is not in bypass mode."]
5177 #[inline(always)]
5178 pub const fn lsedrv(&self) -> super::vals::Lsedrv {
5179 let val = (self.0 >> 3usize) & 0x03;
5180 super::vals::Lsedrv::from_bits(val as u8)
5181 }
5182 #[doc = "LSE oscillator drive capability Set by software to modulate the drive capability of the LSE oscillator. This field can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0). Note: The oscillator is in 'Xtal mode when it is not in bypass mode."]
5183 #[inline(always)]
5184 pub fn set_lsedrv(&mut self, val: super::vals::Lsedrv) {
5185 self.0 = (self.0 & !(0x03 << 3usize)) | (((val.to_bits() as u32) & 0x03) << 3usize);
5186 }
5187 #[doc = "CSS on LSE enable Set by software to enable the CSS on LSE. LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case, the software must disable the LSECSSON bit."]
5188 #[inline(always)]
5189 pub const fn lsecsson(&self) -> bool {
5190 let val = (self.0 >> 5usize) & 0x01;
5191 val != 0
5192 }
5193 #[doc = "CSS on LSE enable Set by software to enable the CSS on LSE. LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case, the software must disable the LSECSSON bit."]
5194 #[inline(always)]
5195 pub fn set_lsecsson(&mut self, val: bool) {
5196 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
5197 }
5198 #[doc = "CSS on LSE failure Detection Set by hardware to indicate when a failure is detected by the CCS on the external 32 kHz oscillator (LSE)."]
5199 #[inline(always)]
5200 pub const fn lsecssd(&self) -> bool {
5201 let val = (self.0 >> 6usize) & 0x01;
5202 val != 0
5203 }
5204 #[doc = "CSS on LSE failure Detection Set by hardware to indicate when a failure is detected by the CCS on the external 32 kHz oscillator (LSE)."]
5205 #[inline(always)]
5206 pub fn set_lsecssd(&mut self, val: bool) {
5207 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
5208 }
5209 #[doc = "LSE system clock (LSESYS) enable Set by software to enable always the LSE system clock generated by RCC. This clock can be used by any peripheral when its source clock is the LSE or at system level in case of one of the LSCOSEL, MCO, MSI PLL mode or CSS on LSE is needed. The LSESYS clock can be generated even if LSESYSEN= 0 if the LSE clock is requested by the CSS on LSE, by a peripheral or any other source clock using LSE."]
5210 #[inline(always)]
5211 pub const fn lsesysen(&self) -> bool {
5212 let val = (self.0 >> 7usize) & 0x01;
5213 val != 0
5214 }
5215 #[doc = "LSE system clock (LSESYS) enable Set by software to enable always the LSE system clock generated by RCC. This clock can be used by any peripheral when its source clock is the LSE or at system level in case of one of the LSCOSEL, MCO, MSI PLL mode or CSS on LSE is needed. The LSESYS clock can be generated even if LSESYSEN= 0 if the LSE clock is requested by the CSS on LSE, by a peripheral or any other source clock using LSE."]
5216 #[inline(always)]
5217 pub fn set_lsesysen(&mut self, val: bool) {
5218 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
5219 }
5220 #[doc = "RTC and TAMP clock source selection Set by software to select the clock source for the RTC and TAMP . Once the RTC and TAMP clock source has been selected, it cannot be changed anymore unless the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them."]
5221 #[inline(always)]
5222 pub const fn rtcsel(&self) -> super::vals::Rtcsel {
5223 let val = (self.0 >> 8usize) & 0x03;
5224 super::vals::Rtcsel::from_bits(val as u8)
5225 }
5226 #[doc = "RTC and TAMP clock source selection Set by software to select the clock source for the RTC and TAMP . Once the RTC and TAMP clock source has been selected, it cannot be changed anymore unless the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them."]
5227 #[inline(always)]
5228 pub fn set_rtcsel(&mut self, val: super::vals::Rtcsel) {
5229 self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize);
5230 }
5231 #[doc = "LSE system clock (LSESYS) ready Set and cleared by hardware to indicate when the LSE system clock is stable.When the LSESYSEN bit is set, the LSESYSRDY flag is set after two LSE clock cycles. The LSE clock must be already enabled and stable (LSEON and LSERDY are set). When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles."]
5232 #[inline(always)]
5233 pub const fn lsesysrdy(&self) -> bool {
5234 let val = (self.0 >> 11usize) & 0x01;
5235 val != 0
5236 }
5237 #[doc = "LSE system clock (LSESYS) ready Set and cleared by hardware to indicate when the LSE system clock is stable.When the LSESYSEN bit is set, the LSESYSRDY flag is set after two LSE clock cycles. The LSE clock must be already enabled and stable (LSEON and LSERDY are set). When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles."]
5238 #[inline(always)]
5239 pub fn set_lsesysrdy(&mut self, val: bool) {
5240 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
5241 }
5242 #[doc = "LSE clock glitch filter enable Set and cleared by hardware to enable the LSE glitch filter. This bit can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0)"]
5243 #[inline(always)]
5244 pub const fn lsegfon(&self) -> bool {
5245 let val = (self.0 >> 12usize) & 0x01;
5246 val != 0
5247 }
5248 #[doc = "LSE clock glitch filter enable Set and cleared by hardware to enable the LSE glitch filter. This bit can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0)"]
5249 #[inline(always)]
5250 pub fn set_lsegfon(&mut self, val: bool) {
5251 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
5252 }
5253 #[doc = "RTC and TAMP clock enable Set and cleared by software."]
5254 #[inline(always)]
5255 pub const fn rtcen(&self) -> bool {
5256 let val = (self.0 >> 15usize) & 0x01;
5257 val != 0
5258 }
5259 #[doc = "RTC and TAMP clock enable Set and cleared by software."]
5260 #[inline(always)]
5261 pub fn set_rtcen(&mut self, val: bool) {
5262 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
5263 }
5264 #[doc = "Backup domain software reset Set and cleared by software."]
5265 #[inline(always)]
5266 pub const fn bdrst(&self) -> bool {
5267 let val = (self.0 >> 16usize) & 0x01;
5268 val != 0
5269 }
5270 #[doc = "Backup domain software reset Set and cleared by software."]
5271 #[inline(always)]
5272 pub fn set_bdrst(&mut self, val: bool) {
5273 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
5274 }
5275 #[doc = "Low-speed clock output (LSCO) enable Set and cleared by software."]
5276 #[inline(always)]
5277 pub const fn lscoen(&self) -> bool {
5278 let val = (self.0 >> 24usize) & 0x01;
5279 val != 0
5280 }
5281 #[doc = "Low-speed clock output (LSCO) enable Set and cleared by software."]
5282 #[inline(always)]
5283 pub fn set_lscoen(&mut self, val: bool) {
5284 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
5285 }
5286 #[doc = "Low-speed clock output selection Set and cleared by software."]
5287 #[inline(always)]
5288 pub const fn lscosel(&self) -> super::vals::Lscosel {
5289 let val = (self.0 >> 25usize) & 0x01;
5290 super::vals::Lscosel::from_bits(val as u8)
5291 }
5292 #[doc = "Low-speed clock output selection Set and cleared by software."]
5293 #[inline(always)]
5294 pub fn set_lscosel(&mut self, val: super::vals::Lscosel) {
5295 self.0 = (self.0 & !(0x01 << 25usize)) | (((val.to_bits() as u32) & 0x01) << 25usize);
5296 }
5297 #[doc = "LSI oscillator enable Set and cleared by software."]
5298 #[inline(always)]
5299 pub const fn lsion(&self) -> bool {
5300 let val = (self.0 >> 26usize) & 0x01;
5301 val != 0
5302 }
5303 #[doc = "LSI oscillator enable Set and cleared by software."]
5304 #[inline(always)]
5305 pub fn set_lsion(&mut self, val: bool) {
5306 self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
5307 }
5308 #[doc = "LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0."]
5309 #[inline(always)]
5310 pub const fn lsirdy(&self) -> bool {
5311 let val = (self.0 >> 27usize) & 0x01;
5312 val != 0
5313 }
5314 #[doc = "LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0."]
5315 #[inline(always)]
5316 pub fn set_lsirdy(&mut self, val: bool) {
5317 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
5318 }
5319 #[doc = "Low-speed clock divider configuration Set and cleared by software to enable the LSI division. This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). If the LSI was previously enabled, it is necessary to wait for at least 60 μs after clearing LSION bit (synchronization time for LSI to be really disabled), before writing LSIPREDIV. The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC."]
5320 #[inline(always)]
5321 pub const fn lsiprediv(&self) -> super::vals::Lsiprediv {
5322 let val = (self.0 >> 28usize) & 0x01;
5323 super::vals::Lsiprediv::from_bits(val as u8)
5324 }
5325 #[doc = "Low-speed clock divider configuration Set and cleared by software to enable the LSI division. This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). If the LSI was previously enabled, it is necessary to wait for at least 60 μs after clearing LSION bit (synchronization time for LSI to be really disabled), before writing LSIPREDIV. The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC."]
5326 #[inline(always)]
5327 pub fn set_lsiprediv(&mut self, val: super::vals::Lsiprediv) {
5328 self.0 = (self.0 & !(0x01 << 28usize)) | (((val.to_bits() as u32) & 0x01) << 28usize);
5329 }
5330 }
5331 impl Default for Bdcr {
5332 #[inline(always)]
5333 fn default() -> Bdcr {
5334 Bdcr(0)
5335 }
5336 }
5337 impl core::fmt::Debug for Bdcr {
5338 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5339 f.debug_struct("Bdcr")
5340 .field("lseon", &self.lseon())
5341 .field("lserdy", &self.lserdy())
5342 .field("lsebyp", &self.lsebyp())
5343 .field("lsedrv", &self.lsedrv())
5344 .field("lsecsson", &self.lsecsson())
5345 .field("lsecssd", &self.lsecssd())
5346 .field("lsesysen", &self.lsesysen())
5347 .field("rtcsel", &self.rtcsel())
5348 .field("lsesysrdy", &self.lsesysrdy())
5349 .field("lsegfon", &self.lsegfon())
5350 .field("rtcen", &self.rtcen())
5351 .field("bdrst", &self.bdrst())
5352 .field("lscoen", &self.lscoen())
5353 .field("lscosel", &self.lscosel())
5354 .field("lsion", &self.lsion())
5355 .field("lsirdy", &self.lsirdy())
5356 .field("lsiprediv", &self.lsiprediv())
5357 .finish()
5358 }
5359 }
5360 #[cfg(feature = "defmt")]
5361 impl defmt::Format for Bdcr {
5362 fn format(&self, f: defmt::Formatter) {
5363 #[derive(defmt :: Format)]
5364 struct Bdcr {
5365 lseon: bool,
5366 lserdy: bool,
5367 lsebyp: bool,
5368 lsedrv: super::vals::Lsedrv,
5369 lsecsson: bool,
5370 lsecssd: bool,
5371 lsesysen: bool,
5372 rtcsel: super::vals::Rtcsel,
5373 lsesysrdy: bool,
5374 lsegfon: bool,
5375 rtcen: bool,
5376 bdrst: bool,
5377 lscoen: bool,
5378 lscosel: super::vals::Lscosel,
5379 lsion: bool,
5380 lsirdy: bool,
5381 lsiprediv: super::vals::Lsiprediv,
5382 }
5383 let proxy = Bdcr {
5384 lseon: self.lseon(),
5385 lserdy: self.lserdy(),
5386 lsebyp: self.lsebyp(),
5387 lsedrv: self.lsedrv(),
5388 lsecsson: self.lsecsson(),
5389 lsecssd: self.lsecssd(),
5390 lsesysen: self.lsesysen(),
5391 rtcsel: self.rtcsel(),
5392 lsesysrdy: self.lsesysrdy(),
5393 lsegfon: self.lsegfon(),
5394 rtcen: self.rtcen(),
5395 bdrst: self.bdrst(),
5396 lscoen: self.lscoen(),
5397 lscosel: self.lscosel(),
5398 lsion: self.lsion(),
5399 lsirdy: self.lsirdy(),
5400 lsiprediv: self.lsiprediv(),
5401 };
5402 defmt::write!(f, "{}", proxy)
5403 }
5404 }
5405 #[doc = "RCC peripherals independent clock configuration register 1"]
5406 #[repr(transparent)]
5407 #[derive(Copy, Clone, Eq, PartialEq)]
5408 pub struct Ccipr1(pub u32);
5409 impl Ccipr1 {
5410 #[doc = "USART1 kernel clock source selection This bits are used to select the USART1 kernel clock source. Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE."]
5411 #[inline(always)]
5412 pub const fn usart1sel(&self) -> super::vals::Usart1sel {
5413 let val = (self.0 >> 0usize) & 0x03;
5414 super::vals::Usart1sel::from_bits(val as u8)
5415 }
5416 #[doc = "USART1 kernel clock source selection This bits are used to select the USART1 kernel clock source. Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE."]
5417 #[inline(always)]
5418 pub fn set_usart1sel(&mut self, val: super::vals::Usart1sel) {
5419 self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
5420 }
5421 #[doc = "USART2 kernel clock source selection This bits are used to select the USART2 kernel clock source. Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE."]
5422 #[inline(always)]
5423 pub const fn usart2sel(&self) -> super::vals::Usartsel {
5424 let val = (self.0 >> 2usize) & 0x03;
5425 super::vals::Usartsel::from_bits(val as u8)
5426 }
5427 #[doc = "USART2 kernel clock source selection This bits are used to select the USART2 kernel clock source. Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE."]
5428 #[inline(always)]
5429 pub fn set_usart2sel(&mut self, val: super::vals::Usartsel) {
5430 self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
5431 }
5432 #[doc = "USART3 kernel clock source selection This bits are used to select the USART3 kernel clock source. Note: The USART3 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE."]
5433 #[inline(always)]
5434 pub const fn usart3sel(&self) -> super::vals::Usartsel {
5435 let val = (self.0 >> 4usize) & 0x03;
5436 super::vals::Usartsel::from_bits(val as u8)
5437 }
5438 #[doc = "USART3 kernel clock source selection This bits are used to select the USART3 kernel clock source. Note: The USART3 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE."]
5439 #[inline(always)]
5440 pub fn set_usart3sel(&mut self, val: super::vals::Usartsel) {
5441 self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
5442 }
5443 #[doc = "UART4 kernel clock source selection This bits are used to select the UART4 kernel clock source. Note: The UART4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE."]
5444 #[inline(always)]
5445 pub const fn uart4sel(&self) -> super::vals::Usartsel {
5446 let val = (self.0 >> 6usize) & 0x03;
5447 super::vals::Usartsel::from_bits(val as u8)
5448 }
5449 #[doc = "UART4 kernel clock source selection This bits are used to select the UART4 kernel clock source. Note: The UART4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE."]
5450 #[inline(always)]
5451 pub fn set_uart4sel(&mut self, val: super::vals::Usartsel) {
5452 self.0 = (self.0 & !(0x03 << 6usize)) | (((val.to_bits() as u32) & 0x03) << 6usize);
5453 }
5454 #[doc = "UART5 kernel clock source selection These bits are used to select the UART5 kernel clock source. Note: The UART5 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE."]
5455 #[inline(always)]
5456 pub const fn uart5sel(&self) -> super::vals::Usartsel {
5457 let val = (self.0 >> 8usize) & 0x03;
5458 super::vals::Usartsel::from_bits(val as u8)
5459 }
5460 #[doc = "UART5 kernel clock source selection These bits are used to select the UART5 kernel clock source. Note: The UART5 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE."]
5461 #[inline(always)]
5462 pub fn set_uart5sel(&mut self, val: super::vals::Usartsel) {
5463 self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize);
5464 }
5465 #[doc = "I2C1 kernel clock source selection These bits are used to select the I2C1 kernel clock source. Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK."]
5466 #[inline(always)]
5467 pub const fn i2c1sel(&self) -> super::vals::I2csel {
5468 let val = (self.0 >> 10usize) & 0x03;
5469 super::vals::I2csel::from_bits(val as u8)
5470 }
5471 #[doc = "I2C1 kernel clock source selection These bits are used to select the I2C1 kernel clock source. Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK."]
5472 #[inline(always)]
5473 pub fn set_i2c1sel(&mut self, val: super::vals::I2csel) {
5474 self.0 = (self.0 & !(0x03 << 10usize)) | (((val.to_bits() as u32) & 0x03) << 10usize);
5475 }
5476 #[doc = "I2C2 kernel clock source selection These bits are used to select the I2C2 kernel clock source. Note: The I2C2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK."]
5477 #[inline(always)]
5478 pub const fn i2c2sel(&self) -> super::vals::I2csel {
5479 let val = (self.0 >> 12usize) & 0x03;
5480 super::vals::I2csel::from_bits(val as u8)
5481 }
5482 #[doc = "I2C2 kernel clock source selection These bits are used to select the I2C2 kernel clock source. Note: The I2C2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK."]
5483 #[inline(always)]
5484 pub fn set_i2c2sel(&mut self, val: super::vals::I2csel) {
5485 self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize);
5486 }
5487 #[doc = "I2C4 kernel clock source selection These bits are used to select the I2C4 kernel clock source. Note: The I2C4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK."]
5488 #[inline(always)]
5489 pub const fn i2c4sel(&self) -> super::vals::I2csel {
5490 let val = (self.0 >> 14usize) & 0x03;
5491 super::vals::I2csel::from_bits(val as u8)
5492 }
5493 #[doc = "I2C4 kernel clock source selection These bits are used to select the I2C4 kernel clock source. Note: The I2C4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK."]
5494 #[inline(always)]
5495 pub fn set_i2c4sel(&mut self, val: super::vals::I2csel) {
5496 self.0 = (self.0 & !(0x03 << 14usize)) | (((val.to_bits() as u32) & 0x03) << 14usize);
5497 }
5498 #[doc = "SPI2 kernel clock source selection These bits are used to select the SPI2 kernel clock source. Note: The SPI2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK."]
5499 #[inline(always)]
5500 pub const fn spi2sel(&self) -> super::vals::Spi2sel {
5501 let val = (self.0 >> 16usize) & 0x03;
5502 super::vals::Spi2sel::from_bits(val as u8)
5503 }
5504 #[doc = "SPI2 kernel clock source selection These bits are used to select the SPI2 kernel clock source. Note: The SPI2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK."]
5505 #[inline(always)]
5506 pub fn set_spi2sel(&mut self, val: super::vals::Spi2sel) {
5507 self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize);
5508 }
5509 #[doc = "Low-power timer 2 kernel clock source selection These bits are used to select the LPTIM2 kernel clock source. Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI if HSIKERON = 1."]
5510 #[inline(always)]
5511 pub const fn lptim2sel(&self) -> super::vals::Lptim2sel {
5512 let val = (self.0 >> 18usize) & 0x03;
5513 super::vals::Lptim2sel::from_bits(val as u8)
5514 }
5515 #[doc = "Low-power timer 2 kernel clock source selection These bits are used to select the LPTIM2 kernel clock source. Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI if HSIKERON = 1."]
5516 #[inline(always)]
5517 pub fn set_lptim2sel(&mut self, val: super::vals::Lptim2sel) {
5518 self.0 = (self.0 & !(0x03 << 18usize)) | (((val.to_bits() as u32) & 0x03) << 18usize);
5519 }
5520 #[doc = "SPI1 kernel clock source selection These bits are used to select the SPI1 kernel clock source. Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK."]
5521 #[inline(always)]
5522 pub const fn spi1sel(&self) -> super::vals::Spi1sel {
5523 let val = (self.0 >> 20usize) & 0x03;
5524 super::vals::Spi1sel::from_bits(val as u8)
5525 }
5526 #[doc = "SPI1 kernel clock source selection These bits are used to select the SPI1 kernel clock source. Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK."]
5527 #[inline(always)]
5528 pub fn set_spi1sel(&mut self, val: super::vals::Spi1sel) {
5529 self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize);
5530 }
5531 #[doc = "SysTick clock source selection These bits are used to select the SysTick clock source. Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one HCLK cycle is introduced, due to the LSE or LSI sampling with HCLK in the SysTick circuitry."]
5532 #[inline(always)]
5533 pub const fn systicksel(&self) -> super::vals::Systicksel {
5534 let val = (self.0 >> 22usize) & 0x03;
5535 super::vals::Systicksel::from_bits(val as u8)
5536 }
5537 #[doc = "SysTick clock source selection These bits are used to select the SysTick clock source. Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one HCLK cycle is introduced, due to the LSE or LSI sampling with HCLK in the SysTick circuitry."]
5538 #[inline(always)]
5539 pub fn set_systicksel(&mut self, val: super::vals::Systicksel) {
5540 self.0 = (self.0 & !(0x03 << 22usize)) | (((val.to_bits() as u32) & 0x03) << 22usize);
5541 }
5542 #[doc = "FDCAN1 kernel clock source selection These bits are used to select the FDCAN1 kernel clock source."]
5543 #[inline(always)]
5544 pub const fn fdcan1sel(&self) -> super::vals::Fdcansel {
5545 let val = (self.0 >> 24usize) & 0x03;
5546 super::vals::Fdcansel::from_bits(val as u8)
5547 }
5548 #[doc = "FDCAN1 kernel clock source selection These bits are used to select the FDCAN1 kernel clock source."]
5549 #[inline(always)]
5550 pub fn set_fdcan1sel(&mut self, val: super::vals::Fdcansel) {
5551 self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize);
5552 }
5553 #[doc = "intermediate clock source selection These bits are used to select the clock source used by OTG_FS and SDMMC."]
5554 #[inline(always)]
5555 pub const fn iclksel(&self) -> super::vals::Iclksel {
5556 let val = (self.0 >> 26usize) & 0x03;
5557 super::vals::Iclksel::from_bits(val as u8)
5558 }
5559 #[doc = "intermediate clock source selection These bits are used to select the clock source used by OTG_FS and SDMMC."]
5560 #[inline(always)]
5561 pub fn set_iclksel(&mut self, val: super::vals::Iclksel) {
5562 self.0 = (self.0 & !(0x03 << 26usize)) | (((val.to_bits() as u32) & 0x03) << 26usize);
5563 }
5564 #[doc = "Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture When the TIMICSEL2 bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected either to HSI/256, MSI/4 or MSI/1024. Depending on TIMICSEL\\[1:0\\]
5565value, MSI is either MSIK or MSIS. When TIMICSEL2 is cleared, the HSI, MSIK and MSIS clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture. 0xx: HSI, MSIK and MSIS dividers disabled Note: The clock division must be disabled (TIMICSEL configured to 0xx) before selecting or changing a clock sources division."]
5566 #[inline(always)]
5567 pub const fn timicsel(&self) -> super::vals::Timicsel {
5568 let val = (self.0 >> 29usize) & 0x07;
5569 super::vals::Timicsel::from_bits(val as u8)
5570 }
5571 #[doc = "Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture When the TIMICSEL2 bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected either to HSI/256, MSI/4 or MSI/1024. Depending on TIMICSEL\\[1:0\\]
5572value, MSI is either MSIK or MSIS. When TIMICSEL2 is cleared, the HSI, MSIK and MSIS clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture. 0xx: HSI, MSIK and MSIS dividers disabled Note: The clock division must be disabled (TIMICSEL configured to 0xx) before selecting or changing a clock sources division."]
5573 #[inline(always)]
5574 pub fn set_timicsel(&mut self, val: super::vals::Timicsel) {
5575 self.0 = (self.0 & !(0x07 << 29usize)) | (((val.to_bits() as u32) & 0x07) << 29usize);
5576 }
5577 }
5578 impl Default for Ccipr1 {
5579 #[inline(always)]
5580 fn default() -> Ccipr1 {
5581 Ccipr1(0)
5582 }
5583 }
5584 impl core::fmt::Debug for Ccipr1 {
5585 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5586 f.debug_struct("Ccipr1")
5587 .field("usart1sel", &self.usart1sel())
5588 .field("usart2sel", &self.usart2sel())
5589 .field("usart3sel", &self.usart3sel())
5590 .field("uart4sel", &self.uart4sel())
5591 .field("uart5sel", &self.uart5sel())
5592 .field("i2c1sel", &self.i2c1sel())
5593 .field("i2c2sel", &self.i2c2sel())
5594 .field("i2c4sel", &self.i2c4sel())
5595 .field("spi2sel", &self.spi2sel())
5596 .field("lptim2sel", &self.lptim2sel())
5597 .field("spi1sel", &self.spi1sel())
5598 .field("systicksel", &self.systicksel())
5599 .field("fdcan1sel", &self.fdcan1sel())
5600 .field("iclksel", &self.iclksel())
5601 .field("timicsel", &self.timicsel())
5602 .finish()
5603 }
5604 }
5605 #[cfg(feature = "defmt")]
5606 impl defmt::Format for Ccipr1 {
5607 fn format(&self, f: defmt::Formatter) {
5608 #[derive(defmt :: Format)]
5609 struct Ccipr1 {
5610 usart1sel: super::vals::Usart1sel,
5611 usart2sel: super::vals::Usartsel,
5612 usart3sel: super::vals::Usartsel,
5613 uart4sel: super::vals::Usartsel,
5614 uart5sel: super::vals::Usartsel,
5615 i2c1sel: super::vals::I2csel,
5616 i2c2sel: super::vals::I2csel,
5617 i2c4sel: super::vals::I2csel,
5618 spi2sel: super::vals::Spi2sel,
5619 lptim2sel: super::vals::Lptim2sel,
5620 spi1sel: super::vals::Spi1sel,
5621 systicksel: super::vals::Systicksel,
5622 fdcan1sel: super::vals::Fdcansel,
5623 iclksel: super::vals::Iclksel,
5624 timicsel: super::vals::Timicsel,
5625 }
5626 let proxy = Ccipr1 {
5627 usart1sel: self.usart1sel(),
5628 usart2sel: self.usart2sel(),
5629 usart3sel: self.usart3sel(),
5630 uart4sel: self.uart4sel(),
5631 uart5sel: self.uart5sel(),
5632 i2c1sel: self.i2c1sel(),
5633 i2c2sel: self.i2c2sel(),
5634 i2c4sel: self.i2c4sel(),
5635 spi2sel: self.spi2sel(),
5636 lptim2sel: self.lptim2sel(),
5637 spi1sel: self.spi1sel(),
5638 systicksel: self.systicksel(),
5639 fdcan1sel: self.fdcan1sel(),
5640 iclksel: self.iclksel(),
5641 timicsel: self.timicsel(),
5642 };
5643 defmt::write!(f, "{}", proxy)
5644 }
5645 }
5646 #[doc = "RCC peripherals independent clock configuration register 2"]
5647 #[repr(transparent)]
5648 #[derive(Copy, Clone, Eq, PartialEq)]
5649 pub struct Ccipr2(pub u32);
5650 impl Ccipr2 {
5651 #[doc = "MDF1 kernel clock source selection These bits are used to select the MDF1 kernel clock source. others: reserved"]
5652 #[inline(always)]
5653 pub const fn mdf1sel(&self) -> super::vals::Mdfsel {
5654 let val = (self.0 >> 0usize) & 0x07;
5655 super::vals::Mdfsel::from_bits(val as u8)
5656 }
5657 #[doc = "MDF1 kernel clock source selection These bits are used to select the MDF1 kernel clock source. others: reserved"]
5658 #[inline(always)]
5659 pub fn set_mdf1sel(&mut self, val: super::vals::Mdfsel) {
5660 self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize);
5661 }
5662 #[doc = "SAI1 kernel clock source selection These bits are used to select the SAI1 kernel clock source. others: reserved Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible."]
5663 #[inline(always)]
5664 pub const fn sai1sel(&self) -> super::vals::Saisel {
5665 let val = (self.0 >> 5usize) & 0x07;
5666 super::vals::Saisel::from_bits(val as u8)
5667 }
5668 #[doc = "SAI1 kernel clock source selection These bits are used to select the SAI1 kernel clock source. others: reserved Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible."]
5669 #[inline(always)]
5670 pub fn set_sai1sel(&mut self, val: super::vals::Saisel) {
5671 self.0 = (self.0 & !(0x07 << 5usize)) | (((val.to_bits() as u32) & 0x07) << 5usize);
5672 }
5673 #[doc = "SAI2 kernel clock source selection These bits are used to select the SAI2 kernel clock source. others: reserved Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible."]
5674 #[inline(always)]
5675 pub const fn sai2sel(&self) -> super::vals::Saisel {
5676 let val = (self.0 >> 8usize) & 0x07;
5677 super::vals::Saisel::from_bits(val as u8)
5678 }
5679 #[doc = "SAI2 kernel clock source selection These bits are used to select the SAI2 kernel clock source. others: reserved Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible."]
5680 #[inline(always)]
5681 pub fn set_sai2sel(&mut self, val: super::vals::Saisel) {
5682 self.0 = (self.0 & !(0x07 << 8usize)) | (((val.to_bits() as u32) & 0x07) << 8usize);
5683 }
5684 #[doc = "SAES kernel clock source selection This bit is used to select the SAES kernel clock source."]
5685 #[inline(always)]
5686 pub const fn saessel(&self) -> super::vals::Saessel {
5687 let val = (self.0 >> 11usize) & 0x01;
5688 super::vals::Saessel::from_bits(val as u8)
5689 }
5690 #[doc = "SAES kernel clock source selection This bit is used to select the SAES kernel clock source."]
5691 #[inline(always)]
5692 pub fn set_saessel(&mut self, val: super::vals::Saessel) {
5693 self.0 = (self.0 & !(0x01 << 11usize)) | (((val.to_bits() as u32) & 0x01) << 11usize);
5694 }
5695 #[doc = "RNGSEL kernel clock source selection These bits are used to select the RNG kernel clock source."]
5696 #[inline(always)]
5697 pub const fn rngsel(&self) -> super::vals::Rngsel {
5698 let val = (self.0 >> 12usize) & 0x03;
5699 super::vals::Rngsel::from_bits(val as u8)
5700 }
5701 #[doc = "RNGSEL kernel clock source selection These bits are used to select the RNG kernel clock source."]
5702 #[inline(always)]
5703 pub fn set_rngsel(&mut self, val: super::vals::Rngsel) {
5704 self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize);
5705 }
5706 #[doc = "SDMMC1 and SDMMC2 kernel clock source selection This bit is used to select the SDMMC kernel clock source. It is recommended to change this bit only after reset and before enabling the SDMMC."]
5707 #[inline(always)]
5708 pub const fn sdmmcsel(&self) -> super::vals::Sdmmcsel {
5709 let val = (self.0 >> 14usize) & 0x01;
5710 super::vals::Sdmmcsel::from_bits(val as u8)
5711 }
5712 #[doc = "SDMMC1 and SDMMC2 kernel clock source selection This bit is used to select the SDMMC kernel clock source. It is recommended to change this bit only after reset and before enabling the SDMMC."]
5713 #[inline(always)]
5714 pub fn set_sdmmcsel(&mut self, val: super::vals::Sdmmcsel) {
5715 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.to_bits() as u32) & 0x01) << 14usize);
5716 }
5717 #[doc = "DSI kernel clock source selection This bit is used to select the DSI kernel clock source. This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. Note: If not present, consider this bit as reserved and keep it at reset value."]
5718 #[inline(always)]
5719 pub const fn dsisel(&self) -> super::vals::Dsisel {
5720 let val = (self.0 >> 15usize) & 0x01;
5721 super::vals::Dsisel::from_bits(val as u8)
5722 }
5723 #[doc = "DSI kernel clock source selection This bit is used to select the DSI kernel clock source. This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. Note: If not present, consider this bit as reserved and keep it at reset value."]
5724 #[inline(always)]
5725 pub fn set_dsisel(&mut self, val: super::vals::Dsisel) {
5726 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.to_bits() as u32) & 0x01) << 15usize);
5727 }
5728 #[doc = "USART6 kernel clock source selection These bits are used to select the USART6 kernel clock source. The USART6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI or LSE. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."]
5729 #[inline(always)]
5730 pub const fn usart6sel(&self) -> super::vals::Usartsel {
5731 let val = (self.0 >> 16usize) & 0x03;
5732 super::vals::Usartsel::from_bits(val as u8)
5733 }
5734 #[doc = "USART6 kernel clock source selection These bits are used to select the USART6 kernel clock source. The USART6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI or LSE. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."]
5735 #[inline(always)]
5736 pub fn set_usart6sel(&mut self, val: super::vals::Usartsel) {
5737 self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize);
5738 }
5739 #[doc = "LTDC kernel clock source selection This bit is used to select the LTDC kernel clock source. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
5740 #[inline(always)]
5741 pub const fn ltdcsel(&self) -> super::vals::Ltdcsel {
5742 let val = (self.0 >> 18usize) & 0x01;
5743 super::vals::Ltdcsel::from_bits(val as u8)
5744 }
5745 #[doc = "LTDC kernel clock source selection This bit is used to select the LTDC kernel clock source. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."]
5746 #[inline(always)]
5747 pub fn set_ltdcsel(&mut self, val: super::vals::Ltdcsel) {
5748 self.0 = (self.0 & !(0x01 << 18usize)) | (((val.to_bits() as u32) & 0x01) << 18usize);
5749 }
5750 #[doc = "OCTOSPI1 and OCTOSPI2 kernel clock source selection These bits are used to select the OCTOSPI1 and OCTOSPI2 kernel clock source."]
5751 #[inline(always)]
5752 pub const fn octospisel(&self) -> super::vals::Octospisel {
5753 let val = (self.0 >> 20usize) & 0x03;
5754 super::vals::Octospisel::from_bits(val as u8)
5755 }
5756 #[doc = "OCTOSPI1 and OCTOSPI2 kernel clock source selection These bits are used to select the OCTOSPI1 and OCTOSPI2 kernel clock source."]
5757 #[inline(always)]
5758 pub fn set_octospisel(&mut self, val: super::vals::Octospisel) {
5759 self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize);
5760 }
5761 #[doc = "HSPI1 kernel clock source selection These bits are used to select the HSPI1 kernel clock source. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."]
5762 #[inline(always)]
5763 pub const fn hspi1sel(&self) -> super::vals::Hspisel {
5764 let val = (self.0 >> 22usize) & 0x03;
5765 super::vals::Hspisel::from_bits(val as u8)
5766 }
5767 #[doc = "HSPI1 kernel clock source selection These bits are used to select the HSPI1 kernel clock source. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."]
5768 #[inline(always)]
5769 pub fn set_hspi1sel(&mut self, val: super::vals::Hspisel) {
5770 self.0 = (self.0 & !(0x03 << 22usize)) | (((val.to_bits() as u32) & 0x03) << 22usize);
5771 }
5772 #[doc = "I2C5 kernel clock source selection These bits are used to select the I2C5 kernel clock source. The I2C5 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI�or MSIK. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."]
5773 #[inline(always)]
5774 pub const fn i2c5sel(&self) -> super::vals::I2csel {
5775 let val = (self.0 >> 24usize) & 0x03;
5776 super::vals::I2csel::from_bits(val as u8)
5777 }
5778 #[doc = "I2C5 kernel clock source selection These bits are used to select the I2C5 kernel clock source. The I2C5 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI�or MSIK. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."]
5779 #[inline(always)]
5780 pub fn set_i2c5sel(&mut self, val: super::vals::I2csel) {
5781 self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize);
5782 }
5783 #[doc = "I2C6 kernel clock source selection These bits are used to select the I2C6 kernel clock source. The I2C6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI�or MSIK. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."]
5784 #[inline(always)]
5785 pub const fn i2c6sel(&self) -> super::vals::I2csel {
5786 let val = (self.0 >> 26usize) & 0x03;
5787 super::vals::I2csel::from_bits(val as u8)
5788 }
5789 #[doc = "I2C6 kernel clock source selection These bits are used to select the I2C6 kernel clock source. The I2C6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI�or MSIK. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."]
5790 #[inline(always)]
5791 pub fn set_i2c6sel(&mut self, val: super::vals::I2csel) {
5792 self.0 = (self.0 & !(0x03 << 26usize)) | (((val.to_bits() as u32) & 0x03) << 26usize);
5793 }
5794 #[doc = "OTG_HS PHY kernel clock source selection These bits are used to select the OTG_HS PHY kernel clock source. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."]
5795 #[inline(always)]
5796 pub const fn otghssel(&self) -> super::vals::Otghssel {
5797 let val = (self.0 >> 30usize) & 0x03;
5798 super::vals::Otghssel::from_bits(val as u8)
5799 }
5800 #[doc = "OTG_HS PHY kernel clock source selection These bits are used to select the OTG_HS PHY kernel clock source. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."]
5801 #[inline(always)]
5802 pub fn set_otghssel(&mut self, val: super::vals::Otghssel) {
5803 self.0 = (self.0 & !(0x03 << 30usize)) | (((val.to_bits() as u32) & 0x03) << 30usize);
5804 }
5805 }
5806 impl Default for Ccipr2 {
5807 #[inline(always)]
5808 fn default() -> Ccipr2 {
5809 Ccipr2(0)
5810 }
5811 }
5812 impl core::fmt::Debug for Ccipr2 {
5813 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5814 f.debug_struct("Ccipr2")
5815 .field("mdf1sel", &self.mdf1sel())
5816 .field("sai1sel", &self.sai1sel())
5817 .field("sai2sel", &self.sai2sel())
5818 .field("saessel", &self.saessel())
5819 .field("rngsel", &self.rngsel())
5820 .field("sdmmcsel", &self.sdmmcsel())
5821 .field("dsisel", &self.dsisel())
5822 .field("usart6sel", &self.usart6sel())
5823 .field("ltdcsel", &self.ltdcsel())
5824 .field("octospisel", &self.octospisel())
5825 .field("hspi1sel", &self.hspi1sel())
5826 .field("i2c5sel", &self.i2c5sel())
5827 .field("i2c6sel", &self.i2c6sel())
5828 .field("otghssel", &self.otghssel())
5829 .finish()
5830 }
5831 }
5832 #[cfg(feature = "defmt")]
5833 impl defmt::Format for Ccipr2 {
5834 fn format(&self, f: defmt::Formatter) {
5835 #[derive(defmt :: Format)]
5836 struct Ccipr2 {
5837 mdf1sel: super::vals::Mdfsel,
5838 sai1sel: super::vals::Saisel,
5839 sai2sel: super::vals::Saisel,
5840 saessel: super::vals::Saessel,
5841 rngsel: super::vals::Rngsel,
5842 sdmmcsel: super::vals::Sdmmcsel,
5843 dsisel: super::vals::Dsisel,
5844 usart6sel: super::vals::Usartsel,
5845 ltdcsel: super::vals::Ltdcsel,
5846 octospisel: super::vals::Octospisel,
5847 hspi1sel: super::vals::Hspisel,
5848 i2c5sel: super::vals::I2csel,
5849 i2c6sel: super::vals::I2csel,
5850 otghssel: super::vals::Otghssel,
5851 }
5852 let proxy = Ccipr2 {
5853 mdf1sel: self.mdf1sel(),
5854 sai1sel: self.sai1sel(),
5855 sai2sel: self.sai2sel(),
5856 saessel: self.saessel(),
5857 rngsel: self.rngsel(),
5858 sdmmcsel: self.sdmmcsel(),
5859 dsisel: self.dsisel(),
5860 usart6sel: self.usart6sel(),
5861 ltdcsel: self.ltdcsel(),
5862 octospisel: self.octospisel(),
5863 hspi1sel: self.hspi1sel(),
5864 i2c5sel: self.i2c5sel(),
5865 i2c6sel: self.i2c6sel(),
5866 otghssel: self.otghssel(),
5867 };
5868 defmt::write!(f, "{}", proxy)
5869 }
5870 }
5871 #[doc = "RCC peripherals independent clock configuration register 3"]
5872 #[repr(transparent)]
5873 #[derive(Copy, Clone, Eq, PartialEq)]
5874 pub struct Ccipr3(pub u32);
5875 impl Ccipr3 {
5876 #[doc = "LPUART1 kernel clock source selection These bits are used to select the LPUART1 kernel clock source. others: reserved Note: The LPUART1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI, LSE or MSIK."]
5877 #[inline(always)]
5878 pub const fn lpuart1sel(&self) -> super::vals::Lpusartsel {
5879 let val = (self.0 >> 0usize) & 0x07;
5880 super::vals::Lpusartsel::from_bits(val as u8)
5881 }
5882 #[doc = "LPUART1 kernel clock source selection These bits are used to select the LPUART1 kernel clock source. others: reserved Note: The LPUART1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI, LSE or MSIK."]
5883 #[inline(always)]
5884 pub fn set_lpuart1sel(&mut self, val: super::vals::Lpusartsel) {
5885 self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize);
5886 }
5887 #[doc = "SPI3 kernel clock source selection These bits are used to select the SPI3 kernel clock source. Note: The SPI3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK."]
5888 #[inline(always)]
5889 pub const fn spi3sel(&self) -> super::vals::Spi3sel {
5890 let val = (self.0 >> 3usize) & 0x03;
5891 super::vals::Spi3sel::from_bits(val as u8)
5892 }
5893 #[doc = "SPI3 kernel clock source selection These bits are used to select the SPI3 kernel clock source. Note: The SPI3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK."]
5894 #[inline(always)]
5895 pub fn set_spi3sel(&mut self, val: super::vals::Spi3sel) {
5896 self.0 = (self.0 & !(0x03 << 3usize)) | (((val.to_bits() as u32) & 0x03) << 3usize);
5897 }
5898 #[doc = "I2C3 kernel clock source selection These bits are used to select the I2C3 kernel clock source. Note: The I2C3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK."]
5899 #[inline(always)]
5900 pub const fn i2c3sel(&self) -> super::vals::I2c3sel {
5901 let val = (self.0 >> 6usize) & 0x03;
5902 super::vals::I2c3sel::from_bits(val as u8)
5903 }
5904 #[doc = "I2C3 kernel clock source selection These bits are used to select the I2C3 kernel clock source. Note: The I2C3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK."]
5905 #[inline(always)]
5906 pub fn set_i2c3sel(&mut self, val: super::vals::I2c3sel) {
5907 self.0 = (self.0 & !(0x03 << 6usize)) | (((val.to_bits() as u32) & 0x03) << 6usize);
5908 }
5909 #[doc = "LPTIM3 and LPTIM4 kernel clock source selection These bits are used to select the LPTIM3 and LPTIM4 kernel clock source. Note: The LPTIM3 and LPTIM4 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI with HSIKERON = 1 or MSIK with MSIKERON = 1."]
5910 #[inline(always)]
5911 pub const fn lptim34sel(&self) -> super::vals::Lptimsel {
5912 let val = (self.0 >> 8usize) & 0x03;
5913 super::vals::Lptimsel::from_bits(val as u8)
5914 }
5915 #[doc = "LPTIM3 and LPTIM4 kernel clock source selection These bits are used to select the LPTIM3 and LPTIM4 kernel clock source. Note: The LPTIM3 and LPTIM4 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI with HSIKERON = 1 or MSIK with MSIKERON = 1."]
5916 #[inline(always)]
5917 pub fn set_lptim34sel(&mut self, val: super::vals::Lptimsel) {
5918 self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize);
5919 }
5920 #[doc = "LPTIM1 kernel clock source selection These bits are used to select the LPTIM1 kernel clock source. Note: The LPTIM1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI with HSIKERON = 1 or MSIK with MSIKERON = 1."]
5921 #[inline(always)]
5922 pub const fn lptim1sel(&self) -> super::vals::Lptimsel {
5923 let val = (self.0 >> 10usize) & 0x03;
5924 super::vals::Lptimsel::from_bits(val as u8)
5925 }
5926 #[doc = "LPTIM1 kernel clock source selection These bits are used to select the LPTIM1 kernel clock source. Note: The LPTIM1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI with HSIKERON = 1 or MSIK with MSIKERON = 1."]
5927 #[inline(always)]
5928 pub fn set_lptim1sel(&mut self, val: super::vals::Lptimsel) {
5929 self.0 = (self.0 & !(0x03 << 10usize)) | (((val.to_bits() as u32) & 0x03) << 10usize);
5930 }
5931 #[doc = "ADC1, ADC4 and DAC1 kernel clock source selection These bits are used to select the ADC1, ADC4 and DAC1 kernel clock source. others: reserved Note: The ADC1, ADC4 and DAC1 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK (only ADC4 and DAC1 are functional in Stop 2 mode)."]
5932 #[inline(always)]
5933 pub const fn adcdacsel(&self) -> super::vals::Adcdacsel {
5934 let val = (self.0 >> 12usize) & 0x07;
5935 super::vals::Adcdacsel::from_bits(val as u8)
5936 }
5937 #[doc = "ADC1, ADC4 and DAC1 kernel clock source selection These bits are used to select the ADC1, ADC4 and DAC1 kernel clock source. others: reserved Note: The ADC1, ADC4 and DAC1 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK (only ADC4 and DAC1 are functional in Stop 2 mode)."]
5938 #[inline(always)]
5939 pub fn set_adcdacsel(&mut self, val: super::vals::Adcdacsel) {
5940 self.0 = (self.0 & !(0x07 << 12usize)) | (((val.to_bits() as u32) & 0x07) << 12usize);
5941 }
5942 #[doc = "DAC1 sample and hold clock source selection This bit is used to select the DAC1 sample and hold clock source."]
5943 #[inline(always)]
5944 pub const fn dac1sel(&self) -> super::vals::Dacsel {
5945 let val = (self.0 >> 15usize) & 0x01;
5946 super::vals::Dacsel::from_bits(val as u8)
5947 }
5948 #[doc = "DAC1 sample and hold clock source selection This bit is used to select the DAC1 sample and hold clock source."]
5949 #[inline(always)]
5950 pub fn set_dac1sel(&mut self, val: super::vals::Dacsel) {
5951 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.to_bits() as u32) & 0x01) << 15usize);
5952 }
5953 #[doc = "ADF1 kernel clock source selection These bits are used to select the ADF1 kernel clock source. others: reserved Note: The ADF1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is AUDIOCLK or MSIK."]
5954 #[inline(always)]
5955 pub const fn adf1sel(&self) -> super::vals::Adfsel {
5956 let val = (self.0 >> 16usize) & 0x07;
5957 super::vals::Adfsel::from_bits(val as u8)
5958 }
5959 #[doc = "ADF1 kernel clock source selection These bits are used to select the ADF1 kernel clock source. others: reserved Note: The ADF1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is AUDIOCLK or MSIK."]
5960 #[inline(always)]
5961 pub fn set_adf1sel(&mut self, val: super::vals::Adfsel) {
5962 self.0 = (self.0 & !(0x07 << 16usize)) | (((val.to_bits() as u32) & 0x07) << 16usize);
5963 }
5964 }
5965 impl Default for Ccipr3 {
5966 #[inline(always)]
5967 fn default() -> Ccipr3 {
5968 Ccipr3(0)
5969 }
5970 }
5971 impl core::fmt::Debug for Ccipr3 {
5972 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5973 f.debug_struct("Ccipr3")
5974 .field("lpuart1sel", &self.lpuart1sel())
5975 .field("spi3sel", &self.spi3sel())
5976 .field("i2c3sel", &self.i2c3sel())
5977 .field("lptim34sel", &self.lptim34sel())
5978 .field("lptim1sel", &self.lptim1sel())
5979 .field("adcdacsel", &self.adcdacsel())
5980 .field("dac1sel", &self.dac1sel())
5981 .field("adf1sel", &self.adf1sel())
5982 .finish()
5983 }
5984 }
5985 #[cfg(feature = "defmt")]
5986 impl defmt::Format for Ccipr3 {
5987 fn format(&self, f: defmt::Formatter) {
5988 #[derive(defmt :: Format)]
5989 struct Ccipr3 {
5990 lpuart1sel: super::vals::Lpusartsel,
5991 spi3sel: super::vals::Spi3sel,
5992 i2c3sel: super::vals::I2c3sel,
5993 lptim34sel: super::vals::Lptimsel,
5994 lptim1sel: super::vals::Lptimsel,
5995 adcdacsel: super::vals::Adcdacsel,
5996 dac1sel: super::vals::Dacsel,
5997 adf1sel: super::vals::Adfsel,
5998 }
5999 let proxy = Ccipr3 {
6000 lpuart1sel: self.lpuart1sel(),
6001 spi3sel: self.spi3sel(),
6002 i2c3sel: self.i2c3sel(),
6003 lptim34sel: self.lptim34sel(),
6004 lptim1sel: self.lptim1sel(),
6005 adcdacsel: self.adcdacsel(),
6006 dac1sel: self.dac1sel(),
6007 adf1sel: self.adf1sel(),
6008 };
6009 defmt::write!(f, "{}", proxy)
6010 }
6011 }
6012 #[doc = "RCC clock configuration register 1"]
6013 #[repr(transparent)]
6014 #[derive(Copy, Clone, Eq, PartialEq)]
6015 pub struct Cfgr1(pub u32);
6016 impl Cfgr1 {
6017 #[doc = "system clock switch Set and cleared by software to select system clock source (SYSCLK). Configured by hardware to force MSIS oscillator selection when exiting Standby or Shutdown mode. Configured by hardware to force MSIS or HSI oscillator selection when exiting Stop mode or in case of HSE oscillator failure, depending on STOPWUCK value."]
6018 #[inline(always)]
6019 pub const fn sw(&self) -> super::vals::Sw {
6020 let val = (self.0 >> 0usize) & 0x03;
6021 super::vals::Sw::from_bits(val as u8)
6022 }
6023 #[doc = "system clock switch Set and cleared by software to select system clock source (SYSCLK). Configured by hardware to force MSIS oscillator selection when exiting Standby or Shutdown mode. Configured by hardware to force MSIS or HSI oscillator selection when exiting Stop mode or in case of HSE oscillator failure, depending on STOPWUCK value."]
6024 #[inline(always)]
6025 pub fn set_sw(&mut self, val: super::vals::Sw) {
6026 self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
6027 }
6028 #[doc = "system clock switch status Set and cleared by hardware to indicate which clock source is used as system clock."]
6029 #[inline(always)]
6030 pub const fn sws(&self) -> super::vals::Sw {
6031 let val = (self.0 >> 2usize) & 0x03;
6032 super::vals::Sw::from_bits(val as u8)
6033 }
6034 #[doc = "system clock switch status Set and cleared by hardware to indicate which clock source is used as system clock."]
6035 #[inline(always)]
6036 pub fn set_sws(&mut self, val: super::vals::Sw) {
6037 self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
6038 }
6039 #[doc = "wakeup from Stop and CSS backup clock selection Set and cleared by software to select the system clock used when exiting Stop mode. The selected clock is also used as emergency clock for the clock security system on HSE. Warning: STOPWUCK must not be modified when the CSS is enabled by HSECSSON bit in RCC_CR and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW = 10)."]
6040 #[inline(always)]
6041 pub const fn stopwuck(&self) -> super::vals::Stopwuck {
6042 let val = (self.0 >> 4usize) & 0x01;
6043 super::vals::Stopwuck::from_bits(val as u8)
6044 }
6045 #[doc = "wakeup from Stop and CSS backup clock selection Set and cleared by software to select the system clock used when exiting Stop mode. The selected clock is also used as emergency clock for the clock security system on HSE. Warning: STOPWUCK must not be modified when the CSS is enabled by HSECSSON bit in RCC_CR and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW = 10)."]
6046 #[inline(always)]
6047 pub fn set_stopwuck(&mut self, val: super::vals::Stopwuck) {
6048 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize);
6049 }
6050 #[doc = "wakeup from Stop kernel clock automatic enable selection Set and cleared by software to enable automatically another oscillator when exiting Stop mode. This oscillator can be used as independent kernel clock by peripherals."]
6051 #[inline(always)]
6052 pub const fn stopkerwuck(&self) -> super::vals::Stopkerwuck {
6053 let val = (self.0 >> 5usize) & 0x01;
6054 super::vals::Stopkerwuck::from_bits(val as u8)
6055 }
6056 #[doc = "wakeup from Stop kernel clock automatic enable selection Set and cleared by software to enable automatically another oscillator when exiting Stop mode. This oscillator can be used as independent kernel clock by peripherals."]
6057 #[inline(always)]
6058 pub fn set_stopkerwuck(&mut self, val: super::vals::Stopkerwuck) {
6059 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.to_bits() as u32) & 0x01) << 5usize);
6060 }
6061 #[doc = "microcontroller clock output Set and cleared by software. Others: reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching."]
6062 #[inline(always)]
6063 pub const fn mcosel(&self) -> super::vals::Mcosel {
6064 let val = (self.0 >> 24usize) & 0x0f;
6065 super::vals::Mcosel::from_bits(val as u8)
6066 }
6067 #[doc = "microcontroller clock output Set and cleared by software. Others: reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching."]
6068 #[inline(always)]
6069 pub fn set_mcosel(&mut self, val: super::vals::Mcosel) {
6070 self.0 = (self.0 & !(0x0f << 24usize)) | (((val.to_bits() as u32) & 0x0f) << 24usize);
6071 }
6072 #[doc = "microcontroller clock output prescaler Set and cleared by software. It is highly recommended to change this prescaler before MCO output is enabled. Others: not allowed"]
6073 #[inline(always)]
6074 pub const fn mcopre(&self) -> super::vals::Mcopre {
6075 let val = (self.0 >> 28usize) & 0x07;
6076 super::vals::Mcopre::from_bits(val as u8)
6077 }
6078 #[doc = "microcontroller clock output prescaler Set and cleared by software. It is highly recommended to change this prescaler before MCO output is enabled. Others: not allowed"]
6079 #[inline(always)]
6080 pub fn set_mcopre(&mut self, val: super::vals::Mcopre) {
6081 self.0 = (self.0 & !(0x07 << 28usize)) | (((val.to_bits() as u32) & 0x07) << 28usize);
6082 }
6083 }
6084 impl Default for Cfgr1 {
6085 #[inline(always)]
6086 fn default() -> Cfgr1 {
6087 Cfgr1(0)
6088 }
6089 }
6090 impl core::fmt::Debug for Cfgr1 {
6091 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6092 f.debug_struct("Cfgr1")
6093 .field("sw", &self.sw())
6094 .field("sws", &self.sws())
6095 .field("stopwuck", &self.stopwuck())
6096 .field("stopkerwuck", &self.stopkerwuck())
6097 .field("mcosel", &self.mcosel())
6098 .field("mcopre", &self.mcopre())
6099 .finish()
6100 }
6101 }
6102 #[cfg(feature = "defmt")]
6103 impl defmt::Format for Cfgr1 {
6104 fn format(&self, f: defmt::Formatter) {
6105 #[derive(defmt :: Format)]
6106 struct Cfgr1 {
6107 sw: super::vals::Sw,
6108 sws: super::vals::Sw,
6109 stopwuck: super::vals::Stopwuck,
6110 stopkerwuck: super::vals::Stopkerwuck,
6111 mcosel: super::vals::Mcosel,
6112 mcopre: super::vals::Mcopre,
6113 }
6114 let proxy = Cfgr1 {
6115 sw: self.sw(),
6116 sws: self.sws(),
6117 stopwuck: self.stopwuck(),
6118 stopkerwuck: self.stopkerwuck(),
6119 mcosel: self.mcosel(),
6120 mcopre: self.mcopre(),
6121 };
6122 defmt::write!(f, "{}", proxy)
6123 }
6124 }
6125 #[doc = "RCC clock configuration register 2"]
6126 #[repr(transparent)]
6127 #[derive(Copy, Clone, Eq, PartialEq)]
6128 pub struct Cfgr2(pub u32);
6129 impl Cfgr2 {
6130 #[doc = "AHB prescaler Set and cleared by software to control the division factor of the AHB clock (HCLK). Depending on the device voltage range, the software must set these bits correctly to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to ). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account. 0xxx: SYSCLK not divided"]
6131 #[inline(always)]
6132 pub const fn hpre(&self) -> super::vals::Hpre {
6133 let val = (self.0 >> 0usize) & 0x0f;
6134 super::vals::Hpre::from_bits(val as u8)
6135 }
6136 #[doc = "AHB prescaler Set and cleared by software to control the division factor of the AHB clock (HCLK). Depending on the device voltage range, the software must set these bits correctly to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to ). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account. 0xxx: SYSCLK not divided"]
6137 #[inline(always)]
6138 pub fn set_hpre(&mut self, val: super::vals::Hpre) {
6139 self.0 = (self.0 & !(0x0f << 0usize)) | (((val.to_bits() as u32) & 0x0f) << 0usize);
6140 }
6141 #[doc = "APB1 prescaler Set and cleared by software to control the division factor of the APB1 clock (PCLK1). 0xx: HCLK not divided"]
6142 #[inline(always)]
6143 pub const fn ppre1(&self) -> super::vals::Ppre {
6144 let val = (self.0 >> 4usize) & 0x07;
6145 super::vals::Ppre::from_bits(val as u8)
6146 }
6147 #[doc = "APB1 prescaler Set and cleared by software to control the division factor of the APB1 clock (PCLK1). 0xx: HCLK not divided"]
6148 #[inline(always)]
6149 pub fn set_ppre1(&mut self, val: super::vals::Ppre) {
6150 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32) & 0x07) << 4usize);
6151 }
6152 #[doc = "APB2 prescaler Set and cleared by software to control the division factor of the APB2 clock (PCLK2). 0xx: HCLK not divided"]
6153 #[inline(always)]
6154 pub const fn ppre2(&self) -> super::vals::Ppre {
6155 let val = (self.0 >> 8usize) & 0x07;
6156 super::vals::Ppre::from_bits(val as u8)
6157 }
6158 #[doc = "APB2 prescaler Set and cleared by software to control the division factor of the APB2 clock (PCLK2). 0xx: HCLK not divided"]
6159 #[inline(always)]
6160 pub fn set_ppre2(&mut self, val: super::vals::Ppre) {
6161 self.0 = (self.0 & !(0x07 << 8usize)) | (((val.to_bits() as u32) & 0x07) << 8usize);
6162 }
6163 #[doc = "DSI PHY prescaler This bitfiled is set and cleared by software to control the division factor of DSI PHY bus clock (DCLK). 0xx: DCLK not divided Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."]
6164 #[inline(always)]
6165 pub const fn dpre(&self) -> super::vals::Dpre {
6166 let val = (self.0 >> 12usize) & 0x07;
6167 super::vals::Dpre::from_bits(val as u8)
6168 }
6169 #[doc = "DSI PHY prescaler This bitfiled is set and cleared by software to control the division factor of DSI PHY bus clock (DCLK). 0xx: DCLK not divided Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."]
6170 #[inline(always)]
6171 pub fn set_dpre(&mut self, val: super::vals::Dpre) {
6172 self.0 = (self.0 & !(0x07 << 12usize)) | (((val.to_bits() as u32) & 0x07) << 12usize);
6173 }
6174 #[doc = "AHB1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals (except those listed hereafter) are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks are off, except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1."]
6175 #[inline(always)]
6176 pub const fn ahb1dis(&self) -> bool {
6177 let val = (self.0 >> 16usize) & 0x01;
6178 val != 0
6179 }
6180 #[doc = "AHB1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals (except those listed hereafter) are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks are off, except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1."]
6181 #[inline(always)]
6182 pub fn set_ahb1dis(&mut self, val: bool) {
6183 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
6184 }
6185 #[doc = "AHB2_1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR1 (except SRAM2 and SRAM3) are used and when their clocks are disabled in RCC_AHB2ENR1. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR1 are off, except for SRAM2 and SRAM3."]
6186 #[inline(always)]
6187 pub const fn ahb2dis1(&self) -> bool {
6188 let val = (self.0 >> 17usize) & 0x01;
6189 val != 0
6190 }
6191 #[doc = "AHB2_1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR1 (except SRAM2 and SRAM3) are used and when their clocks are disabled in RCC_AHB2ENR1. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR1 are off, except for SRAM2 and SRAM3."]
6192 #[inline(always)]
6193 pub fn set_ahb2dis1(&mut self, val: bool) {
6194 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
6195 }
6196 #[doc = "AHB2_2 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR2 are used and when their clocks are disabled in RCC_AHB2ENR2. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2EBNR2 are off."]
6197 #[inline(always)]
6198 pub const fn ahb2dis2(&self) -> bool {
6199 let val = (self.0 >> 18usize) & 0x01;
6200 val != 0
6201 }
6202 #[doc = "AHB2_2 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR2 are used and when their clocks are disabled in RCC_AHB2ENR2. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2EBNR2 are off."]
6203 #[inline(always)]
6204 pub fn set_ahb2dis2(&mut self, val: bool) {
6205 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
6206 }
6207 #[doc = "APB1 clock disable This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG."]
6208 #[inline(always)]
6209 pub const fn apb1dis(&self) -> bool {
6210 let val = (self.0 >> 19usize) & 0x01;
6211 val != 0
6212 }
6213 #[doc = "APB1 clock disable This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG."]
6214 #[inline(always)]
6215 pub fn set_apb1dis(&mut self, val: bool) {
6216 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
6217 }
6218 #[doc = "APB2 clock disable This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all the APB2 peripherals clocks are off."]
6219 #[inline(always)]
6220 pub const fn apb2dis(&self) -> bool {
6221 let val = (self.0 >> 20usize) & 0x01;
6222 val != 0
6223 }
6224 #[doc = "APB2 clock disable This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all the APB2 peripherals clocks are off."]
6225 #[inline(always)]
6226 pub fn set_apb2dis(&mut self, val: bool) {
6227 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
6228 }
6229 }
6230 impl Default for Cfgr2 {
6231 #[inline(always)]
6232 fn default() -> Cfgr2 {
6233 Cfgr2(0)
6234 }
6235 }
6236 impl core::fmt::Debug for Cfgr2 {
6237 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6238 f.debug_struct("Cfgr2")
6239 .field("hpre", &self.hpre())
6240 .field("ppre1", &self.ppre1())
6241 .field("ppre2", &self.ppre2())
6242 .field("dpre", &self.dpre())
6243 .field("ahb1dis", &self.ahb1dis())
6244 .field("ahb2dis1", &self.ahb2dis1())
6245 .field("ahb2dis2", &self.ahb2dis2())
6246 .field("apb1dis", &self.apb1dis())
6247 .field("apb2dis", &self.apb2dis())
6248 .finish()
6249 }
6250 }
6251 #[cfg(feature = "defmt")]
6252 impl defmt::Format for Cfgr2 {
6253 fn format(&self, f: defmt::Formatter) {
6254 #[derive(defmt :: Format)]
6255 struct Cfgr2 {
6256 hpre: super::vals::Hpre,
6257 ppre1: super::vals::Ppre,
6258 ppre2: super::vals::Ppre,
6259 dpre: super::vals::Dpre,
6260 ahb1dis: bool,
6261 ahb2dis1: bool,
6262 ahb2dis2: bool,
6263 apb1dis: bool,
6264 apb2dis: bool,
6265 }
6266 let proxy = Cfgr2 {
6267 hpre: self.hpre(),
6268 ppre1: self.ppre1(),
6269 ppre2: self.ppre2(),
6270 dpre: self.dpre(),
6271 ahb1dis: self.ahb1dis(),
6272 ahb2dis1: self.ahb2dis1(),
6273 ahb2dis2: self.ahb2dis2(),
6274 apb1dis: self.apb1dis(),
6275 apb2dis: self.apb2dis(),
6276 };
6277 defmt::write!(f, "{}", proxy)
6278 }
6279 }
6280 #[doc = "RCC clock configuration register 3"]
6281 #[repr(transparent)]
6282 #[derive(Copy, Clone, Eq, PartialEq)]
6283 pub struct Cfgr3(pub u32);
6284 impl Cfgr3 {
6285 #[doc = "APB3 prescaler Set and cleared by software to control the division factor of the APB3 clock (PCLK3). 0xx: HCLK not divided"]
6286 #[inline(always)]
6287 pub const fn ppre3(&self) -> super::vals::Ppre {
6288 let val = (self.0 >> 4usize) & 0x07;
6289 super::vals::Ppre::from_bits(val as u8)
6290 }
6291 #[doc = "APB3 prescaler Set and cleared by software to control the division factor of the APB3 clock (PCLK3). 0xx: HCLK not divided"]
6292 #[inline(always)]
6293 pub fn set_ppre3(&mut self, val: super::vals::Ppre) {
6294 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32) & 0x07) << 4usize);
6295 }
6296 #[doc = "AHB3 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB3 peripherals (except SRAM4) are used and when their clocks are disabled in RCC_AHB3ENR. When this bit is set, all the AHB3 peripherals clocks are off, except for SRAM4."]
6297 #[inline(always)]
6298 pub const fn ahb3dis(&self) -> bool {
6299 let val = (self.0 >> 16usize) & 0x01;
6300 val != 0
6301 }
6302 #[doc = "AHB3 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB3 peripherals (except SRAM4) are used and when their clocks are disabled in RCC_AHB3ENR. When this bit is set, all the AHB3 peripherals clocks are off, except for SRAM4."]
6303 #[inline(always)]
6304 pub fn set_ahb3dis(&mut self, val: bool) {
6305 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
6306 }
6307 #[doc = "APB3 clock disable This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals from RCC_APB3ENR are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off."]
6308 #[inline(always)]
6309 pub const fn apb3dis(&self) -> bool {
6310 let val = (self.0 >> 17usize) & 0x01;
6311 val != 0
6312 }
6313 #[doc = "APB3 clock disable This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals from RCC_APB3ENR are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off."]
6314 #[inline(always)]
6315 pub fn set_apb3dis(&mut self, val: bool) {
6316 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
6317 }
6318 }
6319 impl Default for Cfgr3 {
6320 #[inline(always)]
6321 fn default() -> Cfgr3 {
6322 Cfgr3(0)
6323 }
6324 }
6325 impl core::fmt::Debug for Cfgr3 {
6326 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6327 f.debug_struct("Cfgr3")
6328 .field("ppre3", &self.ppre3())
6329 .field("ahb3dis", &self.ahb3dis())
6330 .field("apb3dis", &self.apb3dis())
6331 .finish()
6332 }
6333 }
6334 #[cfg(feature = "defmt")]
6335 impl defmt::Format for Cfgr3 {
6336 fn format(&self, f: defmt::Formatter) {
6337 #[derive(defmt :: Format)]
6338 struct Cfgr3 {
6339 ppre3: super::vals::Ppre,
6340 ahb3dis: bool,
6341 apb3dis: bool,
6342 }
6343 let proxy = Cfgr3 {
6344 ppre3: self.ppre3(),
6345 ahb3dis: self.ahb3dis(),
6346 apb3dis: self.apb3dis(),
6347 };
6348 defmt::write!(f, "{}", proxy)
6349 }
6350 }
6351 #[doc = "RCC clock interrupt clear register"]
6352 #[repr(transparent)]
6353 #[derive(Copy, Clone, Eq, PartialEq)]
6354 pub struct Cicr(pub u32);
6355 impl Cicr {
6356 #[doc = "LSI ready interrupt clear Writing this bit to 1 clears the LSIRDYF flag. Writing 0 has no effect."]
6357 #[inline(always)]
6358 pub const fn lsirdyc(&self) -> bool {
6359 let val = (self.0 >> 0usize) & 0x01;
6360 val != 0
6361 }
6362 #[doc = "LSI ready interrupt clear Writing this bit to 1 clears the LSIRDYF flag. Writing 0 has no effect."]
6363 #[inline(always)]
6364 pub fn set_lsirdyc(&mut self, val: bool) {
6365 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
6366 }
6367 #[doc = "LSE ready interrupt clear Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect."]
6368 #[inline(always)]
6369 pub const fn lserdyc(&self) -> bool {
6370 let val = (self.0 >> 1usize) & 0x01;
6371 val != 0
6372 }
6373 #[doc = "LSE ready interrupt clear Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect."]
6374 #[inline(always)]
6375 pub fn set_lserdyc(&mut self, val: bool) {
6376 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
6377 }
6378 #[doc = "MSIS ready interrupt clear Writing this bit to 1 clears the MSISRDYF flag. Writing 0 has no effect."]
6379 #[inline(always)]
6380 pub const fn msisrdyc(&self) -> bool {
6381 let val = (self.0 >> 2usize) & 0x01;
6382 val != 0
6383 }
6384 #[doc = "MSIS ready interrupt clear Writing this bit to 1 clears the MSISRDYF flag. Writing 0 has no effect."]
6385 #[inline(always)]
6386 pub fn set_msisrdyc(&mut self, val: bool) {
6387 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
6388 }
6389 #[doc = "HSI ready interrupt clear Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect."]
6390 #[inline(always)]
6391 pub const fn hsirdyc(&self) -> bool {
6392 let val = (self.0 >> 3usize) & 0x01;
6393 val != 0
6394 }
6395 #[doc = "HSI ready interrupt clear Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect."]
6396 #[inline(always)]
6397 pub fn set_hsirdyc(&mut self, val: bool) {
6398 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
6399 }
6400 #[doc = "HSE ready interrupt clear Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect."]
6401 #[inline(always)]
6402 pub const fn hserdyc(&self) -> bool {
6403 let val = (self.0 >> 4usize) & 0x01;
6404 val != 0
6405 }
6406 #[doc = "HSE ready interrupt clear Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect."]
6407 #[inline(always)]
6408 pub fn set_hserdyc(&mut self, val: bool) {
6409 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
6410 }
6411 #[doc = "HSI48 ready interrupt clear Writing this bit to 1 clears the HSI48RDYF flag. Writing 0 has no effect."]
6412 #[inline(always)]
6413 pub const fn hsi48rdyc(&self) -> bool {
6414 let val = (self.0 >> 5usize) & 0x01;
6415 val != 0
6416 }
6417 #[doc = "HSI48 ready interrupt clear Writing this bit to 1 clears the HSI48RDYF flag. Writing 0 has no effect."]
6418 #[inline(always)]
6419 pub fn set_hsi48rdyc(&mut self, val: bool) {
6420 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
6421 }
6422 #[doc = "PLL1 ready interrupt clear Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect."]
6423 #[inline(always)]
6424 pub const fn pllrdyc(&self, n: usize) -> bool {
6425 assert!(n < 3usize);
6426 let offs = 6usize + n * 1usize;
6427 let val = (self.0 >> offs) & 0x01;
6428 val != 0
6429 }
6430 #[doc = "PLL1 ready interrupt clear Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect."]
6431 #[inline(always)]
6432 pub fn set_pllrdyc(&mut self, n: usize, val: bool) {
6433 assert!(n < 3usize);
6434 let offs = 6usize + n * 1usize;
6435 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
6436 }
6437 #[doc = "Clock security system interrupt clear Writing this bit to 1 clears the CSSF flag. Writing 0 has no effect."]
6438 #[inline(always)]
6439 pub const fn cssc(&self) -> bool {
6440 let val = (self.0 >> 10usize) & 0x01;
6441 val != 0
6442 }
6443 #[doc = "Clock security system interrupt clear Writing this bit to 1 clears the CSSF flag. Writing 0 has no effect."]
6444 #[inline(always)]
6445 pub fn set_cssc(&mut self, val: bool) {
6446 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
6447 }
6448 #[doc = "MSIK oscillator ready interrupt clear Writing this bit to 1 clears the MSIKRDYF flag. Writing 0 has no effect."]
6449 #[inline(always)]
6450 pub const fn msikrdyc(&self) -> bool {
6451 let val = (self.0 >> 11usize) & 0x01;
6452 val != 0
6453 }
6454 #[doc = "MSIK oscillator ready interrupt clear Writing this bit to 1 clears the MSIKRDYF flag. Writing 0 has no effect."]
6455 #[inline(always)]
6456 pub fn set_msikrdyc(&mut self, val: bool) {
6457 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
6458 }
6459 #[doc = "SHSI oscillator ready interrupt clear Writing this bit to 1 clears the SHSIRDYF flag. Writing 0 has no effect."]
6460 #[inline(always)]
6461 pub const fn shsirdyc(&self) -> bool {
6462 let val = (self.0 >> 12usize) & 0x01;
6463 val != 0
6464 }
6465 #[doc = "SHSI oscillator ready interrupt clear Writing this bit to 1 clears the SHSIRDYF flag. Writing 0 has no effect."]
6466 #[inline(always)]
6467 pub fn set_shsirdyc(&mut self, val: bool) {
6468 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
6469 }
6470 }
6471 impl Default for Cicr {
6472 #[inline(always)]
6473 fn default() -> Cicr {
6474 Cicr(0)
6475 }
6476 }
6477 impl core::fmt::Debug for Cicr {
6478 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6479 f.debug_struct("Cicr")
6480 .field("lsirdyc", &self.lsirdyc())
6481 .field("lserdyc", &self.lserdyc())
6482 .field("msisrdyc", &self.msisrdyc())
6483 .field("hsirdyc", &self.hsirdyc())
6484 .field("hserdyc", &self.hserdyc())
6485 .field("hsi48rdyc", &self.hsi48rdyc())
6486 .field(
6487 "pllrdyc",
6488 &[self.pllrdyc(0usize), self.pllrdyc(1usize), self.pllrdyc(2usize)],
6489 )
6490 .field("cssc", &self.cssc())
6491 .field("msikrdyc", &self.msikrdyc())
6492 .field("shsirdyc", &self.shsirdyc())
6493 .finish()
6494 }
6495 }
6496 #[cfg(feature = "defmt")]
6497 impl defmt::Format for Cicr {
6498 fn format(&self, f: defmt::Formatter) {
6499 #[derive(defmt :: Format)]
6500 struct Cicr {
6501 lsirdyc: bool,
6502 lserdyc: bool,
6503 msisrdyc: bool,
6504 hsirdyc: bool,
6505 hserdyc: bool,
6506 hsi48rdyc: bool,
6507 pllrdyc: [bool; 3usize],
6508 cssc: bool,
6509 msikrdyc: bool,
6510 shsirdyc: bool,
6511 }
6512 let proxy = Cicr {
6513 lsirdyc: self.lsirdyc(),
6514 lserdyc: self.lserdyc(),
6515 msisrdyc: self.msisrdyc(),
6516 hsirdyc: self.hsirdyc(),
6517 hserdyc: self.hserdyc(),
6518 hsi48rdyc: self.hsi48rdyc(),
6519 pllrdyc: [self.pllrdyc(0usize), self.pllrdyc(1usize), self.pllrdyc(2usize)],
6520 cssc: self.cssc(),
6521 msikrdyc: self.msikrdyc(),
6522 shsirdyc: self.shsirdyc(),
6523 };
6524 defmt::write!(f, "{}", proxy)
6525 }
6526 }
6527 #[doc = "RCC clock interrupt enable register"]
6528 #[repr(transparent)]
6529 #[derive(Copy, Clone, Eq, PartialEq)]
6530 pub struct Cier(pub u32);
6531 impl Cier {
6532 #[doc = "LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization."]
6533 #[inline(always)]
6534 pub const fn lsirdyie(&self) -> bool {
6535 let val = (self.0 >> 0usize) & 0x01;
6536 val != 0
6537 }
6538 #[doc = "LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization."]
6539 #[inline(always)]
6540 pub fn set_lsirdyie(&mut self, val: bool) {
6541 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
6542 }
6543 #[doc = "LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization."]
6544 #[inline(always)]
6545 pub const fn lserdyie(&self) -> bool {
6546 let val = (self.0 >> 1usize) & 0x01;
6547 val != 0
6548 }
6549 #[doc = "LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization."]
6550 #[inline(always)]
6551 pub fn set_lserdyie(&mut self, val: bool) {
6552 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
6553 }
6554 #[doc = "MSIS ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the MSIS oscillator stabilization."]
6555 #[inline(always)]
6556 pub const fn msisrdyie(&self) -> bool {
6557 let val = (self.0 >> 2usize) & 0x01;
6558 val != 0
6559 }
6560 #[doc = "MSIS ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the MSIS oscillator stabilization."]
6561 #[inline(always)]
6562 pub fn set_msisrdyie(&mut self, val: bool) {
6563 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
6564 }
6565 #[doc = "HSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization."]
6566 #[inline(always)]
6567 pub const fn hsirdyie(&self) -> bool {
6568 let val = (self.0 >> 3usize) & 0x01;
6569 val != 0
6570 }
6571 #[doc = "HSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization."]
6572 #[inline(always)]
6573 pub fn set_hsirdyie(&mut self, val: bool) {
6574 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
6575 }
6576 #[doc = "HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization."]
6577 #[inline(always)]
6578 pub const fn hserdyie(&self) -> bool {
6579 let val = (self.0 >> 4usize) & 0x01;
6580 val != 0
6581 }
6582 #[doc = "HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization."]
6583 #[inline(always)]
6584 pub fn set_hserdyie(&mut self, val: bool) {
6585 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
6586 }
6587 #[doc = "HSI48 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI48 oscillator stabilization."]
6588 #[inline(always)]
6589 pub const fn hsi48rdyie(&self) -> bool {
6590 let val = (self.0 >> 5usize) & 0x01;
6591 val != 0
6592 }
6593 #[doc = "HSI48 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI48 oscillator stabilization."]
6594 #[inline(always)]
6595 pub fn set_hsi48rdyie(&mut self, val: bool) {
6596 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
6597 }
6598 #[doc = "PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL1 lock."]
6599 #[inline(always)]
6600 pub const fn pllrdyie(&self, n: usize) -> bool {
6601 assert!(n < 3usize);
6602 let offs = 6usize + n * 1usize;
6603 let val = (self.0 >> offs) & 0x01;
6604 val != 0
6605 }
6606 #[doc = "PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL1 lock."]
6607 #[inline(always)]
6608 pub fn set_pllrdyie(&mut self, n: usize, val: bool) {
6609 assert!(n < 3usize);
6610 let offs = 6usize + n * 1usize;
6611 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
6612 }
6613 #[doc = "MSIK ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the MSIK oscillator stabilization."]
6614 #[inline(always)]
6615 pub const fn msikrdyie(&self) -> bool {
6616 let val = (self.0 >> 11usize) & 0x01;
6617 val != 0
6618 }
6619 #[doc = "MSIK ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the MSIK oscillator stabilization."]
6620 #[inline(always)]
6621 pub fn set_msikrdyie(&mut self, val: bool) {
6622 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
6623 }
6624 #[doc = "SHSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the SHSI oscillator stabilization."]
6625 #[inline(always)]
6626 pub const fn shsirdyie(&self) -> bool {
6627 let val = (self.0 >> 12usize) & 0x01;
6628 val != 0
6629 }
6630 #[doc = "SHSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the SHSI oscillator stabilization."]
6631 #[inline(always)]
6632 pub fn set_shsirdyie(&mut self, val: bool) {
6633 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
6634 }
6635 }
6636 impl Default for Cier {
6637 #[inline(always)]
6638 fn default() -> Cier {
6639 Cier(0)
6640 }
6641 }
6642 impl core::fmt::Debug for Cier {
6643 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6644 f.debug_struct("Cier")
6645 .field("lsirdyie", &self.lsirdyie())
6646 .field("lserdyie", &self.lserdyie())
6647 .field("msisrdyie", &self.msisrdyie())
6648 .field("hsirdyie", &self.hsirdyie())
6649 .field("hserdyie", &self.hserdyie())
6650 .field("hsi48rdyie", &self.hsi48rdyie())
6651 .field(
6652 "pllrdyie",
6653 &[self.pllrdyie(0usize), self.pllrdyie(1usize), self.pllrdyie(2usize)],
6654 )
6655 .field("msikrdyie", &self.msikrdyie())
6656 .field("shsirdyie", &self.shsirdyie())
6657 .finish()
6658 }
6659 }
6660 #[cfg(feature = "defmt")]
6661 impl defmt::Format for Cier {
6662 fn format(&self, f: defmt::Formatter) {
6663 #[derive(defmt :: Format)]
6664 struct Cier {
6665 lsirdyie: bool,
6666 lserdyie: bool,
6667 msisrdyie: bool,
6668 hsirdyie: bool,
6669 hserdyie: bool,
6670 hsi48rdyie: bool,
6671 pllrdyie: [bool; 3usize],
6672 msikrdyie: bool,
6673 shsirdyie: bool,
6674 }
6675 let proxy = Cier {
6676 lsirdyie: self.lsirdyie(),
6677 lserdyie: self.lserdyie(),
6678 msisrdyie: self.msisrdyie(),
6679 hsirdyie: self.hsirdyie(),
6680 hserdyie: self.hserdyie(),
6681 hsi48rdyie: self.hsi48rdyie(),
6682 pllrdyie: [self.pllrdyie(0usize), self.pllrdyie(1usize), self.pllrdyie(2usize)],
6683 msikrdyie: self.msikrdyie(),
6684 shsirdyie: self.shsirdyie(),
6685 };
6686 defmt::write!(f, "{}", proxy)
6687 }
6688 }
6689 #[doc = "RCC clock interrupt flag register"]
6690 #[repr(transparent)]
6691 #[derive(Copy, Clone, Eq, PartialEq)]
6692 pub struct Cifr(pub u32);
6693 impl Cifr {
6694 #[doc = "LSI ready interrupt flag Set by hardware when the LSI clock becomes stable and LSIRDYIE is set. Cleared by software setting the LSIRDYC bit."]
6695 #[inline(always)]
6696 pub const fn lsirdyf(&self) -> bool {
6697 let val = (self.0 >> 0usize) & 0x01;
6698 val != 0
6699 }
6700 #[doc = "LSI ready interrupt flag Set by hardware when the LSI clock becomes stable and LSIRDYIE is set. Cleared by software setting the LSIRDYC bit."]
6701 #[inline(always)]
6702 pub fn set_lsirdyf(&mut self, val: bool) {
6703 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
6704 }
6705 #[doc = "LSE ready interrupt flag Set by hardware when the LSE clock becomes stable and LSERDYIE is set. Cleared by software setting the LSERDYC bit."]
6706 #[inline(always)]
6707 pub const fn lserdyf(&self) -> bool {
6708 let val = (self.0 >> 1usize) & 0x01;
6709 val != 0
6710 }
6711 #[doc = "LSE ready interrupt flag Set by hardware when the LSE clock becomes stable and LSERDYIE is set. Cleared by software setting the LSERDYC bit."]
6712 #[inline(always)]
6713 pub fn set_lserdyf(&mut self, val: bool) {
6714 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
6715 }
6716 #[doc = "MSIS ready interrupt flag Set by hardware when the MSIS clock becomes stable and MSISRDYIE is set. Cleared by software setting the MSISRDYC bit."]
6717 #[inline(always)]
6718 pub const fn msisrdyf(&self) -> bool {
6719 let val = (self.0 >> 2usize) & 0x01;
6720 val != 0
6721 }
6722 #[doc = "MSIS ready interrupt flag Set by hardware when the MSIS clock becomes stable and MSISRDYIE is set. Cleared by software setting the MSISRDYC bit."]
6723 #[inline(always)]
6724 pub fn set_msisrdyf(&mut self, val: bool) {
6725 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
6726 }
6727 #[doc = "HSI ready interrupt flag Set by hardware when the HSI clock becomes stable and HSIRDYIE is set in a response to setting the HSION (see RCC_CR). When HSION is not set but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSIRDYC bit."]
6728 #[inline(always)]
6729 pub const fn hsirdyf(&self) -> bool {
6730 let val = (self.0 >> 3usize) & 0x01;
6731 val != 0
6732 }
6733 #[doc = "HSI ready interrupt flag Set by hardware when the HSI clock becomes stable and HSIRDYIE is set in a response to setting the HSION (see RCC_CR). When HSION is not set but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSIRDYC bit."]
6734 #[inline(always)]
6735 pub fn set_hsirdyf(&mut self, val: bool) {
6736 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
6737 }
6738 #[doc = "HSE ready interrupt flag Set by hardware when the HSE clock becomes stable and HSERDYIE is set. Cleared by software setting the HSERDYC bit."]
6739 #[inline(always)]
6740 pub const fn hserdyf(&self) -> bool {
6741 let val = (self.0 >> 4usize) & 0x01;
6742 val != 0
6743 }
6744 #[doc = "HSE ready interrupt flag Set by hardware when the HSE clock becomes stable and HSERDYIE is set. Cleared by software setting the HSERDYC bit."]
6745 #[inline(always)]
6746 pub fn set_hserdyf(&mut self, val: bool) {
6747 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
6748 }
6749 #[doc = "HSI48 ready interrupt flag Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. Cleared by software setting the HSI48RDYC bit."]
6750 #[inline(always)]
6751 pub const fn hsi48rdyf(&self) -> bool {
6752 let val = (self.0 >> 5usize) & 0x01;
6753 val != 0
6754 }
6755 #[doc = "HSI48 ready interrupt flag Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. Cleared by software setting the HSI48RDYC bit."]
6756 #[inline(always)]
6757 pub fn set_hsi48rdyf(&mut self, val: bool) {
6758 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
6759 }
6760 #[doc = "PLL1 ready interrupt flag Set by hardware when the PLL1 locks and PLL1RDYIE is set. Cleared by software setting the PLL1RDYC bit."]
6761 #[inline(always)]
6762 pub const fn pllrdyf(&self, n: usize) -> bool {
6763 assert!(n < 3usize);
6764 let offs = 6usize + n * 1usize;
6765 let val = (self.0 >> offs) & 0x01;
6766 val != 0
6767 }
6768 #[doc = "PLL1 ready interrupt flag Set by hardware when the PLL1 locks and PLL1RDYIE is set. Cleared by software setting the PLL1RDYC bit."]
6769 #[inline(always)]
6770 pub fn set_pllrdyf(&mut self, n: usize, val: bool) {
6771 assert!(n < 3usize);
6772 let offs = 6usize + n * 1usize;
6773 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
6774 }
6775 #[doc = "Clock security system interrupt flag Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit."]
6776 #[inline(always)]
6777 pub const fn cssf(&self) -> bool {
6778 let val = (self.0 >> 10usize) & 0x01;
6779 val != 0
6780 }
6781 #[doc = "Clock security system interrupt flag Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit."]
6782 #[inline(always)]
6783 pub fn set_cssf(&mut self, val: bool) {
6784 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
6785 }
6786 #[doc = "MSIK ready interrupt flag Set by hardware when the MSIK clock becomes stable and MSIKRDYIE is set. Cleared by software setting the MSIKRDYC bit."]
6787 #[inline(always)]
6788 pub const fn msikrdyf(&self) -> bool {
6789 let val = (self.0 >> 11usize) & 0x01;
6790 val != 0
6791 }
6792 #[doc = "MSIK ready interrupt flag Set by hardware when the MSIK clock becomes stable and MSIKRDYIE is set. Cleared by software setting the MSIKRDYC bit."]
6793 #[inline(always)]
6794 pub fn set_msikrdyf(&mut self, val: bool) {
6795 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
6796 }
6797 #[doc = "SHSI ready interrupt flag Set by hardware when the SHSI clock becomes stable and SHSIRDYIE is set. Cleared by software setting the SHSIRDYC bit."]
6798 #[inline(always)]
6799 pub const fn shsirdyf(&self) -> bool {
6800 let val = (self.0 >> 12usize) & 0x01;
6801 val != 0
6802 }
6803 #[doc = "SHSI ready interrupt flag Set by hardware when the SHSI clock becomes stable and SHSIRDYIE is set. Cleared by software setting the SHSIRDYC bit."]
6804 #[inline(always)]
6805 pub fn set_shsirdyf(&mut self, val: bool) {
6806 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
6807 }
6808 }
6809 impl Default for Cifr {
6810 #[inline(always)]
6811 fn default() -> Cifr {
6812 Cifr(0)
6813 }
6814 }
6815 impl core::fmt::Debug for Cifr {
6816 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6817 f.debug_struct("Cifr")
6818 .field("lsirdyf", &self.lsirdyf())
6819 .field("lserdyf", &self.lserdyf())
6820 .field("msisrdyf", &self.msisrdyf())
6821 .field("hsirdyf", &self.hsirdyf())
6822 .field("hserdyf", &self.hserdyf())
6823 .field("hsi48rdyf", &self.hsi48rdyf())
6824 .field(
6825 "pllrdyf",
6826 &[self.pllrdyf(0usize), self.pllrdyf(1usize), self.pllrdyf(2usize)],
6827 )
6828 .field("cssf", &self.cssf())
6829 .field("msikrdyf", &self.msikrdyf())
6830 .field("shsirdyf", &self.shsirdyf())
6831 .finish()
6832 }
6833 }
6834 #[cfg(feature = "defmt")]
6835 impl defmt::Format for Cifr {
6836 fn format(&self, f: defmt::Formatter) {
6837 #[derive(defmt :: Format)]
6838 struct Cifr {
6839 lsirdyf: bool,
6840 lserdyf: bool,
6841 msisrdyf: bool,
6842 hsirdyf: bool,
6843 hserdyf: bool,
6844 hsi48rdyf: bool,
6845 pllrdyf: [bool; 3usize],
6846 cssf: bool,
6847 msikrdyf: bool,
6848 shsirdyf: bool,
6849 }
6850 let proxy = Cifr {
6851 lsirdyf: self.lsirdyf(),
6852 lserdyf: self.lserdyf(),
6853 msisrdyf: self.msisrdyf(),
6854 hsirdyf: self.hsirdyf(),
6855 hserdyf: self.hserdyf(),
6856 hsi48rdyf: self.hsi48rdyf(),
6857 pllrdyf: [self.pllrdyf(0usize), self.pllrdyf(1usize), self.pllrdyf(2usize)],
6858 cssf: self.cssf(),
6859 msikrdyf: self.msikrdyf(),
6860 shsirdyf: self.shsirdyf(),
6861 };
6862 defmt::write!(f, "{}", proxy)
6863 }
6864 }
6865 #[doc = "RCC clock control register"]
6866 #[repr(transparent)]
6867 #[derive(Copy, Clone, Eq, PartialEq)]
6868 pub struct Cr(pub u32);
6869 impl Cr {
6870 #[doc = "MSIS clock enable Set and cleared by software. Cleared by hardware to stop the MSIS oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the MSIS oscillator ON when exiting Standby or Shutdown mode. Set by hardware to force the MSIS oscillator ON when STOPWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator. Set by hardware when used directly or indirectly as system clock."]
6871 #[inline(always)]
6872 pub const fn msison(&self) -> bool {
6873 let val = (self.0 >> 0usize) & 0x01;
6874 val != 0
6875 }
6876 #[doc = "MSIS clock enable Set and cleared by software. Cleared by hardware to stop the MSIS oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the MSIS oscillator ON when exiting Standby or Shutdown mode. Set by hardware to force the MSIS oscillator ON when STOPWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator. Set by hardware when used directly or indirectly as system clock."]
6877 #[inline(always)]
6878 pub fn set_msison(&mut self, val: bool) {
6879 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
6880 }
6881 #[doc = "MSI enable for some peripheral kernels Set and cleared by software to force MSI ON even in Stop modes. Keeping the MSI ON in Stop mode allows the communication speed not to be reduced by the MSI startup time. This bit has no effect on MSISON and MSIKON values (see autonomous mode for more details). The MSIKERON must be configured at 0 before entering Stop 3 mode."]
6882 #[inline(always)]
6883 pub const fn msikeron(&self) -> bool {
6884 let val = (self.0 >> 1usize) & 0x01;
6885 val != 0
6886 }
6887 #[doc = "MSI enable for some peripheral kernels Set and cleared by software to force MSI ON even in Stop modes. Keeping the MSI ON in Stop mode allows the communication speed not to be reduced by the MSI startup time. This bit has no effect on MSISON and MSIKON values (see autonomous mode for more details). The MSIKERON must be configured at 0 before entering Stop 3 mode."]
6888 #[inline(always)]
6889 pub fn set_msikeron(&mut self, val: bool) {
6890 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
6891 }
6892 #[doc = "MSIS clock ready flag Set by hardware to indicate that the MSIS oscillator is stable. This bit is set only when MSIS is enabled by software by setting MSISON. Note: Once the MSISON bit is cleared, MSISRDY goes low after six MSIS clock cycles."]
6893 #[inline(always)]
6894 pub const fn msisrdy(&self) -> bool {
6895 let val = (self.0 >> 2usize) & 0x01;
6896 val != 0
6897 }
6898 #[doc = "MSIS clock ready flag Set by hardware to indicate that the MSIS oscillator is stable. This bit is set only when MSIS is enabled by software by setting MSISON. Note: Once the MSISON bit is cleared, MSISRDY goes low after six MSIS clock cycles."]
6899 #[inline(always)]
6900 pub fn set_msisrdy(&mut self, val: bool) {
6901 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
6902 }
6903 #[doc = "MSI clock PLL-mode enable Set and cleared by software to enable/disable the PLL part of the MSI clock source. MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware). A hardware protection prevents from enabling MSIPLLEN if LSE is not ready. This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the CSS on LSE detects a LSE failure (see RCC_CSR)."]
6904 #[inline(always)]
6905 pub const fn msipllen(&self) -> bool {
6906 let val = (self.0 >> 3usize) & 0x01;
6907 val != 0
6908 }
6909 #[doc = "MSI clock PLL-mode enable Set and cleared by software to enable/disable the PLL part of the MSI clock source. MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware). A hardware protection prevents from enabling MSIPLLEN if LSE is not ready. This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the CSS on LSE detects a LSE failure (see RCC_CSR)."]
6910 #[inline(always)]
6911 pub fn set_msipllen(&mut self, val: bool) {
6912 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
6913 }
6914 #[doc = "MSIK clock enable Set and cleared by software. Cleared by hardware to stop the MSIK when entering Stop, Standby or Shutdown mode. Set by hardware to force the MSIK oscillator ON when exiting Standby or Shutdown mode. Set by hardware to force the MSIK oscillator ON when STOPWUCK = 0 or STOPKERWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator."]
6915 #[inline(always)]
6916 pub const fn msikon(&self) -> bool {
6917 let val = (self.0 >> 4usize) & 0x01;
6918 val != 0
6919 }
6920 #[doc = "MSIK clock enable Set and cleared by software. Cleared by hardware to stop the MSIK when entering Stop, Standby or Shutdown mode. Set by hardware to force the MSIK oscillator ON when exiting Standby or Shutdown mode. Set by hardware to force the MSIK oscillator ON when STOPWUCK = 0 or STOPKERWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator."]
6921 #[inline(always)]
6922 pub fn set_msikon(&mut self, val: bool) {
6923 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
6924 }
6925 #[doc = "MSIK clock ready flag Set by hardware to indicate that the MSIK is stable. This bit is set only when MSI kernel oscillator is enabled by software by setting MSIKON. Note: Once the MSIKON bit is cleared, MSIKRDY goes low after six MSIK oscillator clock cycles."]
6926 #[inline(always)]
6927 pub const fn msikrdy(&self) -> bool {
6928 let val = (self.0 >> 5usize) & 0x01;
6929 val != 0
6930 }
6931 #[doc = "MSIK clock ready flag Set by hardware to indicate that the MSIK is stable. This bit is set only when MSI kernel oscillator is enabled by software by setting MSIKON. Note: Once the MSIKON bit is cleared, MSIKRDY goes low after six MSIK oscillator clock cycles."]
6932 #[inline(always)]
6933 pub fn set_msikrdy(&mut self, val: bool) {
6934 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
6935 }
6936 #[doc = "MSI clock with PLL mode selection Set and cleared by software to select which MSI output clock uses the PLL mode. This bit can be written only when the MSI PLL mode is disabled (MSIPLLEN = 0). Note: If the MSI kernel clock output uses the same oscillator source than the MSI system clock output, then the PLL mode is applied to the both clocks outputs."]
6937 #[inline(always)]
6938 pub const fn msipllsel(&self) -> super::vals::Msipllsel {
6939 let val = (self.0 >> 6usize) & 0x01;
6940 super::vals::Msipllsel::from_bits(val as u8)
6941 }
6942 #[doc = "MSI clock with PLL mode selection Set and cleared by software to select which MSI output clock uses the PLL mode. This bit can be written only when the MSI PLL mode is disabled (MSIPLLEN = 0). Note: If the MSI kernel clock output uses the same oscillator source than the MSI system clock output, then the PLL mode is applied to the both clocks outputs."]
6943 #[inline(always)]
6944 pub fn set_msipllsel(&mut self, val: super::vals::Msipllsel) {
6945 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
6946 }
6947 #[doc = "MSI PLL mode fast startup Set and reset by software to enable/disable the fast PLL mode start-up of the MSI clock source. This bit is used only if PLL mode is selected (MSIPLLEN = 1). The fast start-up feature is not active the first time the PLL mode is selected. The fast start-up is active when the MSI in PLL mode returns from switch off."]
6948 #[inline(always)]
6949 pub const fn msipllfast(&self) -> super::vals::Msipllfast {
6950 let val = (self.0 >> 7usize) & 0x01;
6951 super::vals::Msipllfast::from_bits(val as u8)
6952 }
6953 #[doc = "MSI PLL mode fast startup Set and reset by software to enable/disable the fast PLL mode start-up of the MSI clock source. This bit is used only if PLL mode is selected (MSIPLLEN = 1). The fast start-up feature is not active the first time the PLL mode is selected. The fast start-up is active when the MSI in PLL mode returns from switch off."]
6954 #[inline(always)]
6955 pub fn set_msipllfast(&mut self, val: super::vals::Msipllfast) {
6956 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize);
6957 }
6958 #[doc = "HSI clock enable Set and cleared by software. Cleared by hardware to stop the HSI oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the HSI oscillator ON when STOPWUCK = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator. This bit is set by hardware if the HSI is used directly or indirectly as system clock."]
6959 #[inline(always)]
6960 pub const fn hsion(&self) -> bool {
6961 let val = (self.0 >> 8usize) & 0x01;
6962 val != 0
6963 }
6964 #[doc = "HSI clock enable Set and cleared by software. Cleared by hardware to stop the HSI oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the HSI oscillator ON when STOPWUCK = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator. This bit is set by hardware if the HSI is used directly or indirectly as system clock."]
6965 #[inline(always)]
6966 pub fn set_hsion(&mut self, val: bool) {
6967 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
6968 }
6969 #[doc = "HSI enable for some peripheral kernels Set and cleared by software to force HSI ON even in Stop modes. Keeping the HSI ON in Stop mode allows the communication speed not to be reduced by the HSI startup time. This bit has no effect on HSION value. Refer to for more details. The HSIKERON must be configured at 0 before entering Stop 3 mode."]
6970 #[inline(always)]
6971 pub const fn hsikeron(&self) -> bool {
6972 let val = (self.0 >> 9usize) & 0x01;
6973 val != 0
6974 }
6975 #[doc = "HSI enable for some peripheral kernels Set and cleared by software to force HSI ON even in Stop modes. Keeping the HSI ON in Stop mode allows the communication speed not to be reduced by the HSI startup time. This bit has no effect on HSION value. Refer to for more details. The HSIKERON must be configured at 0 before entering Stop 3 mode."]
6976 #[inline(always)]
6977 pub fn set_hsikeron(&mut self, val: bool) {
6978 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
6979 }
6980 #[doc = "HSI clock ready flag Set by hardware to indicate that HSI oscillator is stable. This bit is set only when HSI is enabled by software by setting HSION. Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI clock cycles."]
6981 #[inline(always)]
6982 pub const fn hsirdy(&self) -> bool {
6983 let val = (self.0 >> 10usize) & 0x01;
6984 val != 0
6985 }
6986 #[doc = "HSI clock ready flag Set by hardware to indicate that HSI oscillator is stable. This bit is set only when HSI is enabled by software by setting HSION. Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI clock cycles."]
6987 #[inline(always)]
6988 pub fn set_hsirdy(&mut self, val: bool) {
6989 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
6990 }
6991 #[doc = "HSI48 clock enable Set and cleared by software. Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes."]
6992 #[inline(always)]
6993 pub const fn hsi48on(&self) -> bool {
6994 let val = (self.0 >> 12usize) & 0x01;
6995 val != 0
6996 }
6997 #[doc = "HSI48 clock enable Set and cleared by software. Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes."]
6998 #[inline(always)]
6999 pub fn set_hsi48on(&mut self, val: bool) {
7000 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
7001 }
7002 #[doc = "HSI48 clock ready flag Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON."]
7003 #[inline(always)]
7004 pub const fn hsi48rdy(&self) -> bool {
7005 let val = (self.0 >> 13usize) & 0x01;
7006 val != 0
7007 }
7008 #[doc = "HSI48 clock ready flag Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON."]
7009 #[inline(always)]
7010 pub fn set_hsi48rdy(&mut self, val: bool) {
7011 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
7012 }
7013 #[doc = "SHSI clock enable Set and cleared by software. Cleared by hardware to stop the SHSI when entering in Stop, Standby or Shutdown modes."]
7014 #[inline(always)]
7015 pub const fn shsion(&self) -> bool {
7016 let val = (self.0 >> 14usize) & 0x01;
7017 val != 0
7018 }
7019 #[doc = "SHSI clock enable Set and cleared by software. Cleared by hardware to stop the SHSI when entering in Stop, Standby or Shutdown modes."]
7020 #[inline(always)]
7021 pub fn set_shsion(&mut self, val: bool) {
7022 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
7023 }
7024 #[doc = "SHSI clock ready flag Set by hardware to indicate that the SHSI oscillator is stable. This bit is set only when SHSI is enabled by software by setting SHSION. Note: Once the SHSION bit is cleared, SHSIRDY goes low after six SHSI clock cycles."]
7025 #[inline(always)]
7026 pub const fn shsirdy(&self) -> bool {
7027 let val = (self.0 >> 15usize) & 0x01;
7028 val != 0
7029 }
7030 #[doc = "SHSI clock ready flag Set by hardware to indicate that the SHSI oscillator is stable. This bit is set only when SHSI is enabled by software by setting SHSION. Note: Once the SHSION bit is cleared, SHSIRDY goes low after six SHSI clock cycles."]
7031 #[inline(always)]
7032 pub fn set_shsirdy(&mut self, val: bool) {
7033 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
7034 }
7035 #[doc = "HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock."]
7036 #[inline(always)]
7037 pub const fn hseon(&self) -> bool {
7038 let val = (self.0 >> 16usize) & 0x01;
7039 val != 0
7040 }
7041 #[doc = "HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock."]
7042 #[inline(always)]
7043 pub fn set_hseon(&mut self, val: bool) {
7044 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
7045 }
7046 #[doc = "HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. Note: Once the HSEON bit is cleared, HSERDY goes low after six HSE clock cycles."]
7047 #[inline(always)]
7048 pub const fn hserdy(&self) -> bool {
7049 let val = (self.0 >> 17usize) & 0x01;
7050 val != 0
7051 }
7052 #[doc = "HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. Note: Once the HSEON bit is cleared, HSERDY goes low after six HSE clock cycles."]
7053 #[inline(always)]
7054 pub fn set_hserdy(&mut self, val: bool) {
7055 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
7056 }
7057 #[doc = "HSE crystal oscillator bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled."]
7058 #[inline(always)]
7059 pub const fn hsebyp(&self) -> bool {
7060 let val = (self.0 >> 18usize) & 0x01;
7061 val != 0
7062 }
7063 #[doc = "HSE crystal oscillator bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled."]
7064 #[inline(always)]
7065 pub fn set_hsebyp(&mut self, val: bool) {
7066 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
7067 }
7068 #[doc = "Clock security system enable Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset."]
7069 #[inline(always)]
7070 pub const fn csson(&self) -> bool {
7071 let val = (self.0 >> 19usize) & 0x01;
7072 val != 0
7073 }
7074 #[doc = "Clock security system enable Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset."]
7075 #[inline(always)]
7076 pub fn set_csson(&mut self, val: bool) {
7077 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
7078 }
7079 #[doc = "HSE external clock bypass mode Set and reset by software to select the external clock mode in bypass mode. External clock mode must be configured with HSEON bit to be used by the device. This bit can be written only if the HSE oscillator is disabled. This bit is active only if the HSE bypass mode is enabled."]
7080 #[inline(always)]
7081 pub const fn hseext(&self) -> super::vals::Hseext {
7082 let val = (self.0 >> 20usize) & 0x01;
7083 super::vals::Hseext::from_bits(val as u8)
7084 }
7085 #[doc = "HSE external clock bypass mode Set and reset by software to select the external clock mode in bypass mode. External clock mode must be configured with HSEON bit to be used by the device. This bit can be written only if the HSE oscillator is disabled. This bit is active only if the HSE bypass mode is enabled."]
7086 #[inline(always)]
7087 pub fn set_hseext(&mut self, val: super::vals::Hseext) {
7088 self.0 = (self.0 & !(0x01 << 20usize)) | (((val.to_bits() as u32) & 0x01) << 20usize);
7089 }
7090 #[doc = "PLL1 enable Set and cleared by software to enable the main PLL. Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL1 clock is used as the system clock."]
7091 #[inline(always)]
7092 pub const fn pllon(&self, n: usize) -> bool {
7093 assert!(n < 3usize);
7094 let offs = 24usize + n * 2usize;
7095 let val = (self.0 >> offs) & 0x01;
7096 val != 0
7097 }
7098 #[doc = "PLL1 enable Set and cleared by software to enable the main PLL. Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL1 clock is used as the system clock."]
7099 #[inline(always)]
7100 pub fn set_pllon(&mut self, n: usize, val: bool) {
7101 assert!(n < 3usize);
7102 let offs = 24usize + n * 2usize;
7103 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
7104 }
7105 #[doc = "PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked."]
7106 #[inline(always)]
7107 pub const fn pllrdy(&self, n: usize) -> bool {
7108 assert!(n < 3usize);
7109 let offs = 25usize + n * 2usize;
7110 let val = (self.0 >> offs) & 0x01;
7111 val != 0
7112 }
7113 #[doc = "PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked."]
7114 #[inline(always)]
7115 pub fn set_pllrdy(&mut self, n: usize, val: bool) {
7116 assert!(n < 3usize);
7117 let offs = 25usize + n * 2usize;
7118 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
7119 }
7120 }
7121 impl Default for Cr {
7122 #[inline(always)]
7123 fn default() -> Cr {
7124 Cr(0)
7125 }
7126 }
7127 impl core::fmt::Debug for Cr {
7128 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7129 f.debug_struct("Cr")
7130 .field("msison", &self.msison())
7131 .field("msikeron", &self.msikeron())
7132 .field("msisrdy", &self.msisrdy())
7133 .field("msipllen", &self.msipllen())
7134 .field("msikon", &self.msikon())
7135 .field("msikrdy", &self.msikrdy())
7136 .field("msipllsel", &self.msipllsel())
7137 .field("msipllfast", &self.msipllfast())
7138 .field("hsion", &self.hsion())
7139 .field("hsikeron", &self.hsikeron())
7140 .field("hsirdy", &self.hsirdy())
7141 .field("hsi48on", &self.hsi48on())
7142 .field("hsi48rdy", &self.hsi48rdy())
7143 .field("shsion", &self.shsion())
7144 .field("shsirdy", &self.shsirdy())
7145 .field("hseon", &self.hseon())
7146 .field("hserdy", &self.hserdy())
7147 .field("hsebyp", &self.hsebyp())
7148 .field("csson", &self.csson())
7149 .field("hseext", &self.hseext())
7150 .field("pllon", &[self.pllon(0usize), self.pllon(1usize), self.pllon(2usize)])
7151 .field(
7152 "pllrdy",
7153 &[self.pllrdy(0usize), self.pllrdy(1usize), self.pllrdy(2usize)],
7154 )
7155 .finish()
7156 }
7157 }
7158 #[cfg(feature = "defmt")]
7159 impl defmt::Format for Cr {
7160 fn format(&self, f: defmt::Formatter) {
7161 #[derive(defmt :: Format)]
7162 struct Cr {
7163 msison: bool,
7164 msikeron: bool,
7165 msisrdy: bool,
7166 msipllen: bool,
7167 msikon: bool,
7168 msikrdy: bool,
7169 msipllsel: super::vals::Msipllsel,
7170 msipllfast: super::vals::Msipllfast,
7171 hsion: bool,
7172 hsikeron: bool,
7173 hsirdy: bool,
7174 hsi48on: bool,
7175 hsi48rdy: bool,
7176 shsion: bool,
7177 shsirdy: bool,
7178 hseon: bool,
7179 hserdy: bool,
7180 hsebyp: bool,
7181 csson: bool,
7182 hseext: super::vals::Hseext,
7183 pllon: [bool; 3usize],
7184 pllrdy: [bool; 3usize],
7185 }
7186 let proxy = Cr {
7187 msison: self.msison(),
7188 msikeron: self.msikeron(),
7189 msisrdy: self.msisrdy(),
7190 msipllen: self.msipllen(),
7191 msikon: self.msikon(),
7192 msikrdy: self.msikrdy(),
7193 msipllsel: self.msipllsel(),
7194 msipllfast: self.msipllfast(),
7195 hsion: self.hsion(),
7196 hsikeron: self.hsikeron(),
7197 hsirdy: self.hsirdy(),
7198 hsi48on: self.hsi48on(),
7199 hsi48rdy: self.hsi48rdy(),
7200 shsion: self.shsion(),
7201 shsirdy: self.shsirdy(),
7202 hseon: self.hseon(),
7203 hserdy: self.hserdy(),
7204 hsebyp: self.hsebyp(),
7205 csson: self.csson(),
7206 hseext: self.hseext(),
7207 pllon: [self.pllon(0usize), self.pllon(1usize), self.pllon(2usize)],
7208 pllrdy: [self.pllrdy(0usize), self.pllrdy(1usize), self.pllrdy(2usize)],
7209 };
7210 defmt::write!(f, "{}", proxy)
7211 }
7212 }
7213 #[doc = "RCC clock recovery RC register"]
7214 #[repr(transparent)]
7215 #[derive(Copy, Clone, Eq, PartialEq)]
7216 pub struct Crrcr(pub u32);
7217 impl Crrcr {
7218 #[doc = "HSI48 clock calibration These bits are initialized at startup with the factory-programmed HSI48 calibration trim value."]
7219 #[inline(always)]
7220 pub const fn hsi48cal(&self) -> u16 {
7221 let val = (self.0 >> 0usize) & 0x01ff;
7222 val as u16
7223 }
7224 #[doc = "HSI48 clock calibration These bits are initialized at startup with the factory-programmed HSI48 calibration trim value."]
7225 #[inline(always)]
7226 pub fn set_hsi48cal(&mut self, val: u16) {
7227 self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
7228 }
7229 }
7230 impl Default for Crrcr {
7231 #[inline(always)]
7232 fn default() -> Crrcr {
7233 Crrcr(0)
7234 }
7235 }
7236 impl core::fmt::Debug for Crrcr {
7237 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7238 f.debug_struct("Crrcr").field("hsi48cal", &self.hsi48cal()).finish()
7239 }
7240 }
7241 #[cfg(feature = "defmt")]
7242 impl defmt::Format for Crrcr {
7243 fn format(&self, f: defmt::Formatter) {
7244 #[derive(defmt :: Format)]
7245 struct Crrcr {
7246 hsi48cal: u16,
7247 }
7248 let proxy = Crrcr {
7249 hsi48cal: self.hsi48cal(),
7250 };
7251 defmt::write!(f, "{}", proxy)
7252 }
7253 }
7254 #[doc = "RCC control/status register"]
7255 #[repr(transparent)]
7256 #[derive(Copy, Clone, Eq, PartialEq)]
7257 pub struct Csr(pub u32);
7258 impl Csr {
7259 #[doc = "MSIK range after Standby mode Set by software to chose the MSIK frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSIKSRANGE can be written only when MSIRGSEL = 1. others: reserved Note: Changing the MSIKSRANGE does not change the current MSIK frequency."]
7260 #[inline(always)]
7261 pub const fn msiksrange(&self) -> super::vals::Msixsrange {
7262 let val = (self.0 >> 8usize) & 0x0f;
7263 super::vals::Msixsrange::from_bits(val as u8)
7264 }
7265 #[doc = "MSIK range after Standby mode Set by software to chose the MSIK frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSIKSRANGE can be written only when MSIRGSEL = 1. others: reserved Note: Changing the MSIKSRANGE does not change the current MSIK frequency."]
7266 #[inline(always)]
7267 pub fn set_msiksrange(&mut self, val: super::vals::Msixsrange) {
7268 self.0 = (self.0 & !(0x0f << 8usize)) | (((val.to_bits() as u32) & 0x0f) << 8usize);
7269 }
7270 #[doc = "MSIS range after Standby mode Set by software to chose the MSIS frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSISSRANGE can be written only when MSIRGSEL = 1. others: reserved Note: Changing the MSISSRANGE does not change the current MSIS frequency."]
7271 #[inline(always)]
7272 pub const fn msissrange(&self) -> super::vals::Msixsrange {
7273 let val = (self.0 >> 12usize) & 0x0f;
7274 super::vals::Msixsrange::from_bits(val as u8)
7275 }
7276 #[doc = "MSIS range after Standby mode Set by software to chose the MSIS frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4 MHz. MSISSRANGE can be written only when MSIRGSEL = 1. others: reserved Note: Changing the MSISSRANGE does not change the current MSIS frequency."]
7277 #[inline(always)]
7278 pub fn set_msissrange(&mut self, val: super::vals::Msixsrange) {
7279 self.0 = (self.0 & !(0x0f << 12usize)) | (((val.to_bits() as u32) & 0x0f) << 12usize);
7280 }
7281 #[doc = "Remove reset flag Set by software to clear the reset flags."]
7282 #[inline(always)]
7283 pub const fn rmvf(&self) -> bool {
7284 let val = (self.0 >> 23usize) & 0x01;
7285 val != 0
7286 }
7287 #[doc = "Remove reset flag Set by software to clear the reset flags."]
7288 #[inline(always)]
7289 pub fn set_rmvf(&mut self, val: bool) {
7290 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
7291 }
7292 #[doc = "Option byte loader reset flag Set by hardware when a reset from the option byte loading occurs. Cleared by writing to the RMVF bit."]
7293 #[inline(always)]
7294 pub const fn oblrstf(&self) -> bool {
7295 let val = (self.0 >> 25usize) & 0x01;
7296 val != 0
7297 }
7298 #[doc = "Option byte loader reset flag Set by hardware when a reset from the option byte loading occurs. Cleared by writing to the RMVF bit."]
7299 #[inline(always)]
7300 pub fn set_oblrstf(&mut self, val: bool) {
7301 self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
7302 }
7303 #[doc = "NRST pin reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by writing to the RMVF bit."]
7304 #[inline(always)]
7305 pub const fn pinrstf(&self) -> bool {
7306 let val = (self.0 >> 26usize) & 0x01;
7307 val != 0
7308 }
7309 #[doc = "NRST pin reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by writing to the RMVF bit."]
7310 #[inline(always)]
7311 pub fn set_pinrstf(&mut self, val: bool) {
7312 self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
7313 }
7314 #[doc = "BOR flag Set by hardware when a BOR occurs. Cleared by writing to the RMVF bit."]
7315 #[inline(always)]
7316 pub const fn borrstf(&self) -> bool {
7317 let val = (self.0 >> 27usize) & 0x01;
7318 val != 0
7319 }
7320 #[doc = "BOR flag Set by hardware when a BOR occurs. Cleared by writing to the RMVF bit."]
7321 #[inline(always)]
7322 pub fn set_borrstf(&mut self, val: bool) {
7323 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
7324 }
7325 #[doc = "Software reset flag Set by hardware when a software reset occurs. Cleared by writing to the RMVF bit."]
7326 #[inline(always)]
7327 pub const fn sftrstf(&self) -> bool {
7328 let val = (self.0 >> 28usize) & 0x01;
7329 val != 0
7330 }
7331 #[doc = "Software reset flag Set by hardware when a software reset occurs. Cleared by writing to the RMVF bit."]
7332 #[inline(always)]
7333 pub fn set_sftrstf(&mut self, val: bool) {
7334 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
7335 }
7336 #[doc = "Independent watchdog reset flag Set by hardware when an independent watchdog reset domain occurs. Cleared by writing to the RMVF bit."]
7337 #[inline(always)]
7338 pub const fn iwdgrstf(&self) -> bool {
7339 let val = (self.0 >> 29usize) & 0x01;
7340 val != 0
7341 }
7342 #[doc = "Independent watchdog reset flag Set by hardware when an independent watchdog reset domain occurs. Cleared by writing to the RMVF bit."]
7343 #[inline(always)]
7344 pub fn set_iwdgrstf(&mut self, val: bool) {
7345 self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
7346 }
7347 #[doc = "Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by writing to the RMVF bit."]
7348 #[inline(always)]
7349 pub const fn wwdgrstf(&self) -> bool {
7350 let val = (self.0 >> 30usize) & 0x01;
7351 val != 0
7352 }
7353 #[doc = "Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by writing to the RMVF bit."]
7354 #[inline(always)]
7355 pub fn set_wwdgrstf(&mut self, val: bool) {
7356 self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
7357 }
7358 #[doc = "Low-power reset flag Set by hardware when a reset occurs due to Stop, Standby or Shutdown mode entry, whereas the corresponding nRST_STOP, nRST_STBY or nRST_SHDW option bit is cleared. Cleared by writing to the RMVF bit."]
7359 #[inline(always)]
7360 pub const fn lpwrrstf(&self) -> bool {
7361 let val = (self.0 >> 31usize) & 0x01;
7362 val != 0
7363 }
7364 #[doc = "Low-power reset flag Set by hardware when a reset occurs due to Stop, Standby or Shutdown mode entry, whereas the corresponding nRST_STOP, nRST_STBY or nRST_SHDW option bit is cleared. Cleared by writing to the RMVF bit."]
7365 #[inline(always)]
7366 pub fn set_lpwrrstf(&mut self, val: bool) {
7367 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
7368 }
7369 }
7370 impl Default for Csr {
7371 #[inline(always)]
7372 fn default() -> Csr {
7373 Csr(0)
7374 }
7375 }
7376 impl core::fmt::Debug for Csr {
7377 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7378 f.debug_struct("Csr")
7379 .field("msiksrange", &self.msiksrange())
7380 .field("msissrange", &self.msissrange())
7381 .field("rmvf", &self.rmvf())
7382 .field("oblrstf", &self.oblrstf())
7383 .field("pinrstf", &self.pinrstf())
7384 .field("borrstf", &self.borrstf())
7385 .field("sftrstf", &self.sftrstf())
7386 .field("iwdgrstf", &self.iwdgrstf())
7387 .field("wwdgrstf", &self.wwdgrstf())
7388 .field("lpwrrstf", &self.lpwrrstf())
7389 .finish()
7390 }
7391 }
7392 #[cfg(feature = "defmt")]
7393 impl defmt::Format for Csr {
7394 fn format(&self, f: defmt::Formatter) {
7395 #[derive(defmt :: Format)]
7396 struct Csr {
7397 msiksrange: super::vals::Msixsrange,
7398 msissrange: super::vals::Msixsrange,
7399 rmvf: bool,
7400 oblrstf: bool,
7401 pinrstf: bool,
7402 borrstf: bool,
7403 sftrstf: bool,
7404 iwdgrstf: bool,
7405 wwdgrstf: bool,
7406 lpwrrstf: bool,
7407 }
7408 let proxy = Csr {
7409 msiksrange: self.msiksrange(),
7410 msissrange: self.msissrange(),
7411 rmvf: self.rmvf(),
7412 oblrstf: self.oblrstf(),
7413 pinrstf: self.pinrstf(),
7414 borrstf: self.borrstf(),
7415 sftrstf: self.sftrstf(),
7416 iwdgrstf: self.iwdgrstf(),
7417 wwdgrstf: self.wwdgrstf(),
7418 lpwrrstf: self.lpwrrstf(),
7419 };
7420 defmt::write!(f, "{}", proxy)
7421 }
7422 }
7423 #[doc = "RCC internal clock sources calibration register 1"]
7424 #[repr(transparent)]
7425 #[derive(Copy, Clone, Eq, PartialEq)]
7426 pub struct Icscr1(pub u32);
7427 impl Icscr1 {
7428 #[doc = "MSIRC3 clock calibration for MSI ranges 12 to 15 These bits are initialized at startup with the factory-programmed MSIRC3 calibration trim value for ranges 12 to 15. When MSITRIM3 is written, MSICAL3 is updated with the sum of MSITRIM3\\[4:0\\]
7429and the factory calibration trim value MSIRC2\\[4:0\\]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level."]
7430 #[inline(always)]
7431 pub const fn msical3(&self) -> u8 {
7432 let val = (self.0 >> 0usize) & 0x1f;
7433 val as u8
7434 }
7435 #[doc = "MSIRC3 clock calibration for MSI ranges 12 to 15 These bits are initialized at startup with the factory-programmed MSIRC3 calibration trim value for ranges 12 to 15. When MSITRIM3 is written, MSICAL3 is updated with the sum of MSITRIM3\\[4:0\\]
7436and the factory calibration trim value MSIRC2\\[4:0\\]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level."]
7437 #[inline(always)]
7438 pub fn set_msical3(&mut self, val: u8) {
7439 self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
7440 }
7441 #[doc = "MSIRC2 clock calibration for MSI ranges 8 to 11 These bits are initialized at startup with the factory-programmed MSIRC2 calibration trim value for ranges 8 to 11. When MSITRIM2 is written, MSICAL2 is updated with the sum of MSITRIM2\\[4:0\\]
7442and the factory calibration trim value MSIRC2\\[4:0\\]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level."]
7443 #[inline(always)]
7444 pub const fn msical2(&self) -> u8 {
7445 let val = (self.0 >> 5usize) & 0x1f;
7446 val as u8
7447 }
7448 #[doc = "MSIRC2 clock calibration for MSI ranges 8 to 11 These bits are initialized at startup with the factory-programmed MSIRC2 calibration trim value for ranges 8 to 11. When MSITRIM2 is written, MSICAL2 is updated with the sum of MSITRIM2\\[4:0\\]
7449and the factory calibration trim value MSIRC2\\[4:0\\]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level."]
7450 #[inline(always)]
7451 pub fn set_msical2(&mut self, val: u8) {
7452 self.0 = (self.0 & !(0x1f << 5usize)) | (((val as u32) & 0x1f) << 5usize);
7453 }
7454 #[doc = "MSIRC1 clock calibration for MSI ranges 4 to 7 These bits are initialized at startup with the factory-programmed MSIRC1 calibration trim value for ranges 4 to 7. When MSITRIM1 is written, MSICAL1 is updated with the sum of MSITRIM1\\[4:0\\]
7455and the factory calibration trim value MSIRC1\\[4:0\\]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level."]
7456 #[inline(always)]
7457 pub const fn msical1(&self) -> u8 {
7458 let val = (self.0 >> 10usize) & 0x1f;
7459 val as u8
7460 }
7461 #[doc = "MSIRC1 clock calibration for MSI ranges 4 to 7 These bits are initialized at startup with the factory-programmed MSIRC1 calibration trim value for ranges 4 to 7. When MSITRIM1 is written, MSICAL1 is updated with the sum of MSITRIM1\\[4:0\\]
7462and the factory calibration trim value MSIRC1\\[4:0\\]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level."]
7463 #[inline(always)]
7464 pub fn set_msical1(&mut self, val: u8) {
7465 self.0 = (self.0 & !(0x1f << 10usize)) | (((val as u32) & 0x1f) << 10usize);
7466 }
7467 #[doc = "MSIRC0 clock calibration for MSI ranges 0 to 3 These bits are initialized at startup with the factory-programmed MSIRC0 calibration trim value for ranges 0 to 3. When MSITRIM0 is written, MSICAL0 is updated with the sum of MSITRIM0\\[4:0\\]
7468and the factory-programmed calibration trim value MSIRC0\\[4:0\\]."]
7469 #[inline(always)]
7470 pub const fn msical0(&self) -> u8 {
7471 let val = (self.0 >> 15usize) & 0x1f;
7472 val as u8
7473 }
7474 #[doc = "MSIRC0 clock calibration for MSI ranges 0 to 3 These bits are initialized at startup with the factory-programmed MSIRC0 calibration trim value for ranges 0 to 3. When MSITRIM0 is written, MSICAL0 is updated with the sum of MSITRIM0\\[4:0\\]
7475and the factory-programmed calibration trim value MSIRC0\\[4:0\\]."]
7476 #[inline(always)]
7477 pub fn set_msical0(&mut self, val: u8) {
7478 self.0 = (self.0 & !(0x1f << 15usize)) | (((val as u32) & 0x1f) << 15usize);
7479 }
7480 #[doc = "MSI bias mode selection Set by software to select the MSI bias mode. By default, the MSI bias is in continuous mode in order to maintain the output clocks accuracy. Setting this bit reduces the MSI consumption under range 4 but decrease its accuracy."]
7481 #[inline(always)]
7482 pub const fn msibias(&self) -> super::vals::Msibias {
7483 let val = (self.0 >> 22usize) & 0x01;
7484 super::vals::Msibias::from_bits(val as u8)
7485 }
7486 #[doc = "MSI bias mode selection Set by software to select the MSI bias mode. By default, the MSI bias is in continuous mode in order to maintain the output clocks accuracy. Setting this bit reduces the MSI consumption under range 4 but decrease its accuracy."]
7487 #[inline(always)]
7488 pub fn set_msibias(&mut self, val: super::vals::Msibias) {
7489 self.0 = (self.0 & !(0x01 << 22usize)) | (((val.to_bits() as u32) & 0x01) << 22usize);
7490 }
7491 #[doc = "MSI clock range selection Set by software to select the MSIS and MSIK clocks range with MSISRANGE\\[3:0\\]
7492and MSIKRANGE\\[3:0\\]. Write 0 has no effect. After exiting Standby or Shutdown mode, or after a reset, this bit is at 0 and the MSIS and MSIK ranges are provided by MSISSRANGE\\[3:0\\]
7493and MSIKSRANGE\\[3:0\\]
7494in RCC_CSR."]
7495 #[inline(always)]
7496 pub const fn msirgsel(&self) -> super::vals::Msirgsel {
7497 let val = (self.0 >> 23usize) & 0x01;
7498 super::vals::Msirgsel::from_bits(val as u8)
7499 }
7500 #[doc = "MSI clock range selection Set by software to select the MSIS and MSIK clocks range with MSISRANGE\\[3:0\\]
7501and MSIKRANGE\\[3:0\\]. Write 0 has no effect. After exiting Standby or Shutdown mode, or after a reset, this bit is at 0 and the MSIS and MSIK ranges are provided by MSISSRANGE\\[3:0\\]
7502and MSIKSRANGE\\[3:0\\]
7503in RCC_CSR."]
7504 #[inline(always)]
7505 pub fn set_msirgsel(&mut self, val: super::vals::Msirgsel) {
7506 self.0 = (self.0 & !(0x01 << 23usize)) | (((val.to_bits() as u32) & 0x01) << 23usize);
7507 }
7508 #[doc = "MSIK clock ranges These bits are configured by software to choose the frequency range of MSIK oscillator when MSIRGSEL is set. 16 frequency ranges are available: Note: MSIKRANGE can be modified when MSIK is OFF (MSISON = 0) or when MSIK is ready (MSIKRDY = 1). MSIKRANGE must NOT be modified when MSIK is ON and NOT ready (MSIKON = 1 and MSIKRDY = 0) MSIKRANGE is kept when the device wakes up from Stop mode, except when the MSIK range is above 24 MHz. In this case MSIKRANGE is changed by hardware into Range 2 (24 MHz)."]
7509 #[inline(always)]
7510 pub const fn msikrange(&self) -> super::vals::Msirange {
7511 let val = (self.0 >> 24usize) & 0x0f;
7512 super::vals::Msirange::from_bits(val as u8)
7513 }
7514 #[doc = "MSIK clock ranges These bits are configured by software to choose the frequency range of MSIK oscillator when MSIRGSEL is set. 16 frequency ranges are available: Note: MSIKRANGE can be modified when MSIK is OFF (MSISON = 0) or when MSIK is ready (MSIKRDY = 1). MSIKRANGE must NOT be modified when MSIK is ON and NOT ready (MSIKON = 1 and MSIKRDY = 0) MSIKRANGE is kept when the device wakes up from Stop mode, except when the MSIK range is above 24 MHz. In this case MSIKRANGE is changed by hardware into Range 2 (24 MHz)."]
7515 #[inline(always)]
7516 pub fn set_msikrange(&mut self, val: super::vals::Msirange) {
7517 self.0 = (self.0 & !(0x0f << 24usize)) | (((val.to_bits() as u32) & 0x0f) << 24usize);
7518 }
7519 #[doc = "MSIS clock ranges These bits are configured by software to choose the frequency range of MSIS oscillator when MSIRGSEL is set. 16 frequency ranges are available: Note: MSISRANGE can be modified when MSIS is OFF (MSISON = 0) or when MSIS is ready (MSISRDY = 1). MSISRANGE must NOT be modified when MSIS is ON and NOT ready (MSISON = 1 and MSISRDY = 0) MSISRANGE is kept when the device wakes up from Stop mode, except when the MSIS range is above 24 MHz. In this case MSISRANGE is changed by hardware into Range 2 (24 MHz)."]
7520 #[inline(always)]
7521 pub const fn msisrange(&self) -> super::vals::Msirange {
7522 let val = (self.0 >> 28usize) & 0x0f;
7523 super::vals::Msirange::from_bits(val as u8)
7524 }
7525 #[doc = "MSIS clock ranges These bits are configured by software to choose the frequency range of MSIS oscillator when MSIRGSEL is set. 16 frequency ranges are available: Note: MSISRANGE can be modified when MSIS is OFF (MSISON = 0) or when MSIS is ready (MSISRDY = 1). MSISRANGE must NOT be modified when MSIS is ON and NOT ready (MSISON = 1 and MSISRDY = 0) MSISRANGE is kept when the device wakes up from Stop mode, except when the MSIS range is above 24 MHz. In this case MSISRANGE is changed by hardware into Range 2 (24 MHz)."]
7526 #[inline(always)]
7527 pub fn set_msisrange(&mut self, val: super::vals::Msirange) {
7528 self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize);
7529 }
7530 }
7531 impl Default for Icscr1 {
7532 #[inline(always)]
7533 fn default() -> Icscr1 {
7534 Icscr1(0)
7535 }
7536 }
7537 impl core::fmt::Debug for Icscr1 {
7538 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7539 f.debug_struct("Icscr1")
7540 .field("msical3", &self.msical3())
7541 .field("msical2", &self.msical2())
7542 .field("msical1", &self.msical1())
7543 .field("msical0", &self.msical0())
7544 .field("msibias", &self.msibias())
7545 .field("msirgsel", &self.msirgsel())
7546 .field("msikrange", &self.msikrange())
7547 .field("msisrange", &self.msisrange())
7548 .finish()
7549 }
7550 }
7551 #[cfg(feature = "defmt")]
7552 impl defmt::Format for Icscr1 {
7553 fn format(&self, f: defmt::Formatter) {
7554 #[derive(defmt :: Format)]
7555 struct Icscr1 {
7556 msical3: u8,
7557 msical2: u8,
7558 msical1: u8,
7559 msical0: u8,
7560 msibias: super::vals::Msibias,
7561 msirgsel: super::vals::Msirgsel,
7562 msikrange: super::vals::Msirange,
7563 msisrange: super::vals::Msirange,
7564 }
7565 let proxy = Icscr1 {
7566 msical3: self.msical3(),
7567 msical2: self.msical2(),
7568 msical1: self.msical1(),
7569 msical0: self.msical0(),
7570 msibias: self.msibias(),
7571 msirgsel: self.msirgsel(),
7572 msikrange: self.msikrange(),
7573 msisrange: self.msisrange(),
7574 };
7575 defmt::write!(f, "{}", proxy)
7576 }
7577 }
7578 #[doc = "RCC internal clock sources calibration register 2"]
7579 #[repr(transparent)]
7580 #[derive(Copy, Clone, Eq, PartialEq)]
7581 pub struct Icscr2(pub u32);
7582 impl Icscr2 {
7583 #[doc = "MSI clock trimming for ranges 12 to 15 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC3\\[4:0\\]
7584bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI."]
7585 #[inline(always)]
7586 pub const fn msitrim3(&self) -> u8 {
7587 let val = (self.0 >> 0usize) & 0x1f;
7588 val as u8
7589 }
7590 #[doc = "MSI clock trimming for ranges 12 to 15 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC3\\[4:0\\]
7591bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI."]
7592 #[inline(always)]
7593 pub fn set_msitrim3(&mut self, val: u8) {
7594 self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
7595 }
7596 #[doc = "MSI clock trimming for ranges 8 to 11 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC2\\[4:0\\]
7597bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI."]
7598 #[inline(always)]
7599 pub const fn msitrim2(&self) -> u8 {
7600 let val = (self.0 >> 5usize) & 0x1f;
7601 val as u8
7602 }
7603 #[doc = "MSI clock trimming for ranges 8 to 11 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC2\\[4:0\\]
7604bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI."]
7605 #[inline(always)]
7606 pub fn set_msitrim2(&mut self, val: u8) {
7607 self.0 = (self.0 & !(0x1f << 5usize)) | (((val as u32) & 0x1f) << 5usize);
7608 }
7609 #[doc = "MSI clock trimming for ranges 4 to 7 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC1\\[4:0\\]
7610bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI."]
7611 #[inline(always)]
7612 pub const fn msitrim1(&self) -> u8 {
7613 let val = (self.0 >> 10usize) & 0x1f;
7614 val as u8
7615 }
7616 #[doc = "MSI clock trimming for ranges 4 to 7 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC1\\[4:0\\]
7617bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI."]
7618 #[inline(always)]
7619 pub fn set_msitrim1(&mut self, val: u8) {
7620 self.0 = (self.0 & !(0x1f << 10usize)) | (((val as u32) & 0x1f) << 10usize);
7621 }
7622 #[doc = "MSI clock trimming for ranges 0 to 3 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC0\\[4:0\\]
7623bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI."]
7624 #[inline(always)]
7625 pub const fn msitrim0(&self) -> u8 {
7626 let val = (self.0 >> 15usize) & 0x1f;
7627 val as u8
7628 }
7629 #[doc = "MSI clock trimming for ranges 0 to 3 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC0\\[4:0\\]
7630bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI."]
7631 #[inline(always)]
7632 pub fn set_msitrim0(&mut self, val: u8) {
7633 self.0 = (self.0 & !(0x1f << 15usize)) | (((val as u32) & 0x1f) << 15usize);
7634 }
7635 }
7636 impl Default for Icscr2 {
7637 #[inline(always)]
7638 fn default() -> Icscr2 {
7639 Icscr2(0)
7640 }
7641 }
7642 impl core::fmt::Debug for Icscr2 {
7643 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7644 f.debug_struct("Icscr2")
7645 .field("msitrim3", &self.msitrim3())
7646 .field("msitrim2", &self.msitrim2())
7647 .field("msitrim1", &self.msitrim1())
7648 .field("msitrim0", &self.msitrim0())
7649 .finish()
7650 }
7651 }
7652 #[cfg(feature = "defmt")]
7653 impl defmt::Format for Icscr2 {
7654 fn format(&self, f: defmt::Formatter) {
7655 #[derive(defmt :: Format)]
7656 struct Icscr2 {
7657 msitrim3: u8,
7658 msitrim2: u8,
7659 msitrim1: u8,
7660 msitrim0: u8,
7661 }
7662 let proxy = Icscr2 {
7663 msitrim3: self.msitrim3(),
7664 msitrim2: self.msitrim2(),
7665 msitrim1: self.msitrim1(),
7666 msitrim0: self.msitrim0(),
7667 };
7668 defmt::write!(f, "{}", proxy)
7669 }
7670 }
7671 #[doc = "RCC internal clock sources calibration register 3"]
7672 #[repr(transparent)]
7673 #[derive(Copy, Clone, Eq, PartialEq)]
7674 pub struct Icscr3(pub u32);
7675 impl Icscr3 {
7676 #[doc = "HSI clock calibration These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value."]
7677 #[inline(always)]
7678 pub const fn hsical(&self) -> u16 {
7679 let val = (self.0 >> 0usize) & 0x0fff;
7680 val as u16
7681 }
7682 #[doc = "HSI clock calibration These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value."]
7683 #[inline(always)]
7684 pub fn set_hsical(&mut self, val: u16) {
7685 self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
7686 }
7687 #[doc = "HSI clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL\\[11:0\\]
7688bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI."]
7689 #[inline(always)]
7690 pub const fn hsitrim(&self) -> u8 {
7691 let val = (self.0 >> 16usize) & 0x1f;
7692 val as u8
7693 }
7694 #[doc = "HSI clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL\\[11:0\\]
7695bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI."]
7696 #[inline(always)]
7697 pub fn set_hsitrim(&mut self, val: u8) {
7698 self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize);
7699 }
7700 }
7701 impl Default for Icscr3 {
7702 #[inline(always)]
7703 fn default() -> Icscr3 {
7704 Icscr3(0)
7705 }
7706 }
7707 impl core::fmt::Debug for Icscr3 {
7708 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7709 f.debug_struct("Icscr3")
7710 .field("hsical", &self.hsical())
7711 .field("hsitrim", &self.hsitrim())
7712 .finish()
7713 }
7714 }
7715 #[cfg(feature = "defmt")]
7716 impl defmt::Format for Icscr3 {
7717 fn format(&self, f: defmt::Formatter) {
7718 #[derive(defmt :: Format)]
7719 struct Icscr3 {
7720 hsical: u16,
7721 hsitrim: u8,
7722 }
7723 let proxy = Icscr3 {
7724 hsical: self.hsical(),
7725 hsitrim: self.hsitrim(),
7726 };
7727 defmt::write!(f, "{}", proxy)
7728 }
7729 }
7730 #[doc = "RCC PLL configuration register"]
7731 #[repr(transparent)]
7732 #[derive(Copy, Clone, Eq, PartialEq)]
7733 pub struct Pll1cfgr(pub u32);
7734 impl Pll1cfgr {
7735 #[doc = "PLL entry clock source Set and cleared by software to select PLL clock source. These bits can be written only when the PLL is disabled. In order to save power, when no PLL is used, the value of PLLSRC must be 0."]
7736 #[inline(always)]
7737 pub const fn pllsrc(&self) -> super::vals::Pllsrc {
7738 let val = (self.0 >> 0usize) & 0x03;
7739 super::vals::Pllsrc::from_bits(val as u8)
7740 }
7741 #[doc = "PLL entry clock source Set and cleared by software to select PLL clock source. These bits can be written only when the PLL is disabled. In order to save power, when no PLL is used, the value of PLLSRC must be 0."]
7742 #[inline(always)]
7743 pub fn set_pllsrc(&mut self, val: super::vals::Pllsrc) {
7744 self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
7745 }
7746 #[doc = "PLL input frequency range Set and reset by software to select the proper reference frequency range used for PLL. This bit must be written before enabling the PLL. 00-01-10: PLL input (ref1_ck) clock range frequency between 4 and 8 MHz"]
7747 #[inline(always)]
7748 pub const fn pllrge(&self) -> super::vals::Pllrge {
7749 let val = (self.0 >> 2usize) & 0x03;
7750 super::vals::Pllrge::from_bits(val as u8)
7751 }
7752 #[doc = "PLL input frequency range Set and reset by software to select the proper reference frequency range used for PLL. This bit must be written before enabling the PLL. 00-01-10: PLL input (ref1_ck) clock range frequency between 4 and 8 MHz"]
7753 #[inline(always)]
7754 pub fn set_pllrge(&mut self, val: super::vals::Pllrge) {
7755 self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
7756 }
7757 #[doc = "PLL fractional latch enable Set and reset by software to latch the content of PLLFRACN into the ΣΠmodulator. In order to latch the PLLFRACN value into the ΣΠmodulator, PLLFRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLLFRACN into the modulator (see for details)."]
7758 #[inline(always)]
7759 pub const fn pllfracen(&self) -> bool {
7760 let val = (self.0 >> 4usize) & 0x01;
7761 val != 0
7762 }
7763 #[doc = "PLL fractional latch enable Set and reset by software to latch the content of PLLFRACN into the ΣΠmodulator. In order to latch the PLLFRACN value into the ΣΠmodulator, PLLFRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLLFRACN into the modulator (see for details)."]
7764 #[inline(always)]
7765 pub fn set_pllfracen(&mut self, val: bool) {
7766 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
7767 }
7768 #[doc = "Prescaler for PLL Set and cleared by software to configure the prescaler of the PLL. The VCO1 input frequency is PLL input clock frequency/PLLM. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). ..."]
7769 #[inline(always)]
7770 pub const fn pllm(&self) -> super::vals::Pllm {
7771 let val = (self.0 >> 8usize) & 0x0f;
7772 super::vals::Pllm::from_bits(val as u8)
7773 }
7774 #[doc = "Prescaler for PLL Set and cleared by software to configure the prescaler of the PLL. The VCO1 input frequency is PLL input clock frequency/PLLM. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). ..."]
7775 #[inline(always)]
7776 pub fn set_pllm(&mut self, val: super::vals::Pllm) {
7777 self.0 = (self.0 & !(0x0f << 8usize)) | (((val.to_bits() as u32) & 0x0f) << 8usize);
7778 }
7779 #[doc = "Prescaler for EPOD booster input clock Set and cleared by software to configure the prescaler of the PLL, used for the EPOD booster. The EPOD booster input frequency is PLL input clock frequency/PLLMBOOST. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0) and EPOD Boost mode is disabled (see ). others: reserved"]
7780 #[inline(always)]
7781 pub const fn pllmboost(&self) -> super::vals::Pllmboost {
7782 let val = (self.0 >> 12usize) & 0x0f;
7783 super::vals::Pllmboost::from_bits(val as u8)
7784 }
7785 #[doc = "Prescaler for EPOD booster input clock Set and cleared by software to configure the prescaler of the PLL, used for the EPOD booster. The EPOD booster input frequency is PLL input clock frequency/PLLMBOOST. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0) and EPOD Boost mode is disabled (see ). others: reserved"]
7786 #[inline(always)]
7787 pub fn set_pllmboost(&mut self, val: super::vals::Pllmboost) {
7788 self.0 = (self.0 & !(0x0f << 12usize)) | (((val.to_bits() as u32) & 0x0f) << 12usize);
7789 }
7790 #[doc = "PLL DIVP divider output enable Set and reset by software to enable the PLL_p_ck output of the PLL. To save power, PLLPEN and PLLP bits must be set to 0 when the PLL_p_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)."]
7791 #[inline(always)]
7792 pub const fn pllpen(&self) -> bool {
7793 let val = (self.0 >> 16usize) & 0x01;
7794 val != 0
7795 }
7796 #[doc = "PLL DIVP divider output enable Set and reset by software to enable the PLL_p_ck output of the PLL. To save power, PLLPEN and PLLP bits must be set to 0 when the PLL_p_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)."]
7797 #[inline(always)]
7798 pub fn set_pllpen(&mut self, val: bool) {
7799 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
7800 }
7801 #[doc = "PLL DIVQ divider output enable Set and reset by software to enable the PLL_q_ck output of the PLL. To save power, PLLQEN and PLLQ bits must be set to 0 when the PLL_q_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)."]
7802 #[inline(always)]
7803 pub const fn pllqen(&self) -> bool {
7804 let val = (self.0 >> 17usize) & 0x01;
7805 val != 0
7806 }
7807 #[doc = "PLL DIVQ divider output enable Set and reset by software to enable the PLL_q_ck output of the PLL. To save power, PLLQEN and PLLQ bits must be set to 0 when the PLL_q_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)."]
7808 #[inline(always)]
7809 pub fn set_pllqen(&mut self, val: bool) {
7810 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
7811 }
7812 #[doc = "PLL DIVR divider output enable Set and reset by software to enable the PLL_r_ck output of the PLL. To save power, PLLRENPLL2REN and PLLR bits must be set to 0 when the PLL_r_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)."]
7813 #[inline(always)]
7814 pub const fn pllren(&self) -> bool {
7815 let val = (self.0 >> 18usize) & 0x01;
7816 val != 0
7817 }
7818 #[doc = "PLL DIVR divider output enable Set and reset by software to enable the PLL_r_ck output of the PLL. To save power, PLLRENPLL2REN and PLLR bits must be set to 0 when the PLL_r_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)."]
7819 #[inline(always)]
7820 pub fn set_pllren(&mut self, val: bool) {
7821 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
7822 }
7823 }
7824 impl Default for Pll1cfgr {
7825 #[inline(always)]
7826 fn default() -> Pll1cfgr {
7827 Pll1cfgr(0)
7828 }
7829 }
7830 impl core::fmt::Debug for Pll1cfgr {
7831 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7832 f.debug_struct("Pll1cfgr")
7833 .field("pllsrc", &self.pllsrc())
7834 .field("pllrge", &self.pllrge())
7835 .field("pllfracen", &self.pllfracen())
7836 .field("pllm", &self.pllm())
7837 .field("pllmboost", &self.pllmboost())
7838 .field("pllpen", &self.pllpen())
7839 .field("pllqen", &self.pllqen())
7840 .field("pllren", &self.pllren())
7841 .finish()
7842 }
7843 }
7844 #[cfg(feature = "defmt")]
7845 impl defmt::Format for Pll1cfgr {
7846 fn format(&self, f: defmt::Formatter) {
7847 #[derive(defmt :: Format)]
7848 struct Pll1cfgr {
7849 pllsrc: super::vals::Pllsrc,
7850 pllrge: super::vals::Pllrge,
7851 pllfracen: bool,
7852 pllm: super::vals::Pllm,
7853 pllmboost: super::vals::Pllmboost,
7854 pllpen: bool,
7855 pllqen: bool,
7856 pllren: bool,
7857 }
7858 let proxy = Pll1cfgr {
7859 pllsrc: self.pllsrc(),
7860 pllrge: self.pllrge(),
7861 pllfracen: self.pllfracen(),
7862 pllm: self.pllm(),
7863 pllmboost: self.pllmboost(),
7864 pllpen: self.pllpen(),
7865 pllqen: self.pllqen(),
7866 pllren: self.pllren(),
7867 };
7868 defmt::write!(f, "{}", proxy)
7869 }
7870 }
7871 #[doc = "RCC PLL configuration register"]
7872 #[repr(transparent)]
7873 #[derive(Copy, Clone, Eq, PartialEq)]
7874 pub struct Pll23cfgr(pub u32);
7875 impl Pll23cfgr {
7876 #[doc = "PLL entry clock source Set and cleared by software to select PLL clock source. These bits can be written only when the PLL is disabled. In order to save power, when no PLL is used, the value of PLLSRC must be 0."]
7877 #[inline(always)]
7878 pub const fn pllsrc(&self) -> super::vals::Pllsrc {
7879 let val = (self.0 >> 0usize) & 0x03;
7880 super::vals::Pllsrc::from_bits(val as u8)
7881 }
7882 #[doc = "PLL entry clock source Set and cleared by software to select PLL clock source. These bits can be written only when the PLL is disabled. In order to save power, when no PLL is used, the value of PLLSRC must be 0."]
7883 #[inline(always)]
7884 pub fn set_pllsrc(&mut self, val: super::vals::Pllsrc) {
7885 self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
7886 }
7887 #[doc = "PLL input frequency range Set and reset by software to select the proper reference frequency range used for PLL. This bit must be written before enabling the PLL. 00-01-10: PLL input (ref1_ck) clock range frequency between 4 and 8 MHz"]
7888 #[inline(always)]
7889 pub const fn pllrge(&self) -> super::vals::Pllrge {
7890 let val = (self.0 >> 2usize) & 0x03;
7891 super::vals::Pllrge::from_bits(val as u8)
7892 }
7893 #[doc = "PLL input frequency range Set and reset by software to select the proper reference frequency range used for PLL. This bit must be written before enabling the PLL. 00-01-10: PLL input (ref1_ck) clock range frequency between 4 and 8 MHz"]
7894 #[inline(always)]
7895 pub fn set_pllrge(&mut self, val: super::vals::Pllrge) {
7896 self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
7897 }
7898 #[doc = "PLL fractional latch enable Set and reset by software to latch the content of PLLFRACN into the ΣΠmodulator. In order to latch the PLLFRACN value into the ΣΠmodulator, PLLFRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLLFRACN into the modulator (see for details)."]
7899 #[inline(always)]
7900 pub const fn pllfracen(&self) -> bool {
7901 let val = (self.0 >> 4usize) & 0x01;
7902 val != 0
7903 }
7904 #[doc = "PLL fractional latch enable Set and reset by software to latch the content of PLLFRACN into the ΣΠmodulator. In order to latch the PLLFRACN value into the ΣΠmodulator, PLLFRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLLFRACN into the modulator (see for details)."]
7905 #[inline(always)]
7906 pub fn set_pllfracen(&mut self, val: bool) {
7907 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
7908 }
7909 #[doc = "Prescaler for PLL Set and cleared by software to configure the prescaler of the PLL. The VCO1 input frequency is PLL input clock frequency/PLLM. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). ..."]
7910 #[inline(always)]
7911 pub const fn pllm(&self) -> super::vals::Pllm {
7912 let val = (self.0 >> 8usize) & 0x0f;
7913 super::vals::Pllm::from_bits(val as u8)
7914 }
7915 #[doc = "Prescaler for PLL Set and cleared by software to configure the prescaler of the PLL. The VCO1 input frequency is PLL input clock frequency/PLLM. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). ..."]
7916 #[inline(always)]
7917 pub fn set_pllm(&mut self, val: super::vals::Pllm) {
7918 self.0 = (self.0 & !(0x0f << 8usize)) | (((val.to_bits() as u32) & 0x0f) << 8usize);
7919 }
7920 #[doc = "PLL DIVP divider output enable Set and reset by software to enable the PLL_p_ck output of the PLL. To save power, PLLPEN and PLLP bits must be set to 0 when the PLL_p_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)."]
7921 #[inline(always)]
7922 pub const fn pllpen(&self) -> bool {
7923 let val = (self.0 >> 16usize) & 0x01;
7924 val != 0
7925 }
7926 #[doc = "PLL DIVP divider output enable Set and reset by software to enable the PLL_p_ck output of the PLL. To save power, PLLPEN and PLLP bits must be set to 0 when the PLL_p_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)."]
7927 #[inline(always)]
7928 pub fn set_pllpen(&mut self, val: bool) {
7929 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
7930 }
7931 #[doc = "PLL DIVQ divider output enable Set and reset by software to enable the PLL_q_ck output of the PLL. To save power, PLLQEN and PLLQ bits must be set to 0 when the PLL_q_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)."]
7932 #[inline(always)]
7933 pub const fn pllqen(&self) -> bool {
7934 let val = (self.0 >> 17usize) & 0x01;
7935 val != 0
7936 }
7937 #[doc = "PLL DIVQ divider output enable Set and reset by software to enable the PLL_q_ck output of the PLL. To save power, PLLQEN and PLLQ bits must be set to 0 when the PLL_q_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)."]
7938 #[inline(always)]
7939 pub fn set_pllqen(&mut self, val: bool) {
7940 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
7941 }
7942 #[doc = "PLL DIVR divider output enable Set and reset by software to enable the PLL_r_ck output of the PLL. To save power, PLLRENPLL2REN and PLLR bits must be set to 0 when the PLL_r_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)."]
7943 #[inline(always)]
7944 pub const fn pllren(&self) -> bool {
7945 let val = (self.0 >> 18usize) & 0x01;
7946 val != 0
7947 }
7948 #[doc = "PLL DIVR divider output enable Set and reset by software to enable the PLL_r_ck output of the PLL. To save power, PLLRENPLL2REN and PLLR bits must be set to 0 when the PLL_r_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0)."]
7949 #[inline(always)]
7950 pub fn set_pllren(&mut self, val: bool) {
7951 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
7952 }
7953 }
7954 impl Default for Pll23cfgr {
7955 #[inline(always)]
7956 fn default() -> Pll23cfgr {
7957 Pll23cfgr(0)
7958 }
7959 }
7960 impl core::fmt::Debug for Pll23cfgr {
7961 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7962 f.debug_struct("Pll23cfgr")
7963 .field("pllsrc", &self.pllsrc())
7964 .field("pllrge", &self.pllrge())
7965 .field("pllfracen", &self.pllfracen())
7966 .field("pllm", &self.pllm())
7967 .field("pllpen", &self.pllpen())
7968 .field("pllqen", &self.pllqen())
7969 .field("pllren", &self.pllren())
7970 .finish()
7971 }
7972 }
7973 #[cfg(feature = "defmt")]
7974 impl defmt::Format for Pll23cfgr {
7975 fn format(&self, f: defmt::Formatter) {
7976 #[derive(defmt :: Format)]
7977 struct Pll23cfgr {
7978 pllsrc: super::vals::Pllsrc,
7979 pllrge: super::vals::Pllrge,
7980 pllfracen: bool,
7981 pllm: super::vals::Pllm,
7982 pllpen: bool,
7983 pllqen: bool,
7984 pllren: bool,
7985 }
7986 let proxy = Pll23cfgr {
7987 pllsrc: self.pllsrc(),
7988 pllrge: self.pllrge(),
7989 pllfracen: self.pllfracen(),
7990 pllm: self.pllm(),
7991 pllpen: self.pllpen(),
7992 pllqen: self.pllqen(),
7993 pllren: self.pllren(),
7994 };
7995 defmt::write!(f, "{}", proxy)
7996 }
7997 }
7998 #[doc = "RCC PLL1 dividers register"]
7999 #[repr(transparent)]
8000 #[derive(Copy, Clone, Eq, PartialEq)]
8001 pub struct Plldivr(pub u32);
8002 impl Plldivr {
8003 #[doc = "Multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0). ... ... Others: reserved VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded into PLL1FRACN, with: PLL1N between 4 and 512 input frequency Fref1_ck between 4 and 16 MHz"]
8004 #[inline(always)]
8005 pub const fn plln(&self) -> super::vals::Plln {
8006 let val = (self.0 >> 0usize) & 0x01ff;
8007 super::vals::Plln::from_bits(val as u16)
8008 }
8009 #[doc = "Multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0). ... ... Others: reserved VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded into PLL1FRACN, with: PLL1N between 4 and 512 input frequency Fref1_ck between 4 and 16 MHz"]
8010 #[inline(always)]
8011 pub fn set_plln(&mut self, val: super::vals::Plln) {
8012 self.0 = (self.0 & !(0x01ff << 0usize)) | (((val.to_bits() as u32) & 0x01ff) << 0usize);
8013 }
8014 #[doc = "PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Note that odd division factors are not allowed. ..."]
8015 #[inline(always)]
8016 pub const fn pllp(&self) -> super::vals::Plldiv {
8017 let val = (self.0 >> 9usize) & 0x7f;
8018 super::vals::Plldiv::from_bits(val as u8)
8019 }
8020 #[doc = "PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Note that odd division factors are not allowed. ..."]
8021 #[inline(always)]
8022 pub fn set_pllp(&mut self, val: super::vals::Plldiv) {
8023 self.0 = (self.0 & !(0x7f << 9usize)) | (((val.to_bits() as u32) & 0x7f) << 9usize);
8024 }
8025 #[doc = "PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ..."]
8026 #[inline(always)]
8027 pub const fn pllq(&self) -> super::vals::Plldiv {
8028 let val = (self.0 >> 16usize) & 0x7f;
8029 super::vals::Plldiv::from_bits(val as u8)
8030 }
8031 #[doc = "PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ..."]
8032 #[inline(always)]
8033 pub fn set_pllq(&mut self, val: super::vals::Plldiv) {
8034 self.0 = (self.0 & !(0x7f << 16usize)) | (((val.to_bits() as u32) & 0x7f) << 16usize);
8035 }
8036 #[doc = "PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ..."]
8037 #[inline(always)]
8038 pub const fn pllr(&self) -> super::vals::Plldiv {
8039 let val = (self.0 >> 24usize) & 0x7f;
8040 super::vals::Plldiv::from_bits(val as u8)
8041 }
8042 #[doc = "PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ..."]
8043 #[inline(always)]
8044 pub fn set_pllr(&mut self, val: super::vals::Plldiv) {
8045 self.0 = (self.0 & !(0x7f << 24usize)) | (((val.to_bits() as u32) & 0x7f) << 24usize);
8046 }
8047 }
8048 impl Default for Plldivr {
8049 #[inline(always)]
8050 fn default() -> Plldivr {
8051 Plldivr(0)
8052 }
8053 }
8054 impl core::fmt::Debug for Plldivr {
8055 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
8056 f.debug_struct("Plldivr")
8057 .field("plln", &self.plln())
8058 .field("pllp", &self.pllp())
8059 .field("pllq", &self.pllq())
8060 .field("pllr", &self.pllr())
8061 .finish()
8062 }
8063 }
8064 #[cfg(feature = "defmt")]
8065 impl defmt::Format for Plldivr {
8066 fn format(&self, f: defmt::Formatter) {
8067 #[derive(defmt :: Format)]
8068 struct Plldivr {
8069 plln: super::vals::Plln,
8070 pllp: super::vals::Plldiv,
8071 pllq: super::vals::Plldiv,
8072 pllr: super::vals::Plldiv,
8073 }
8074 let proxy = Plldivr {
8075 plln: self.plln(),
8076 pllp: self.pllp(),
8077 pllq: self.pllq(),
8078 pllr: self.pllr(),
8079 };
8080 defmt::write!(f, "{}", proxy)
8081 }
8082 }
8083 #[doc = "RCC PLL1 fractional divider register"]
8084 #[repr(transparent)]
8085 #[derive(Copy, Clone, Eq, PartialEq)]
8086 pub struct Pllfracr(pub u32);
8087 impl Pllfracr {
8088 #[doc = "Fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with: PLL1N must be between 4 and 512. PLL1FRACN can be between 0 and 213- 1. The input frequency Fref1_ck must be between 4 and 16 MHz. To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL1FRACEN to 0. Write the new fractional value into PLL1FRACN. Set the bit PLL1FRACEN to 1."]
8089 #[inline(always)]
8090 pub const fn pllfracn(&self) -> u16 {
8091 let val = (self.0 >> 3usize) & 0x1fff;
8092 val as u16
8093 }
8094 #[doc = "Fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with: PLL1N must be between 4 and 512. PLL1FRACN can be between 0 and 213- 1. The input frequency Fref1_ck must be between 4 and 16 MHz. To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL1FRACEN to 0. Write the new fractional value into PLL1FRACN. Set the bit PLL1FRACEN to 1."]
8095 #[inline(always)]
8096 pub fn set_pllfracn(&mut self, val: u16) {
8097 self.0 = (self.0 & !(0x1fff << 3usize)) | (((val as u32) & 0x1fff) << 3usize);
8098 }
8099 }
8100 impl Default for Pllfracr {
8101 #[inline(always)]
8102 fn default() -> Pllfracr {
8103 Pllfracr(0)
8104 }
8105 }
8106 impl core::fmt::Debug for Pllfracr {
8107 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
8108 f.debug_struct("Pllfracr").field("pllfracn", &self.pllfracn()).finish()
8109 }
8110 }
8111 #[cfg(feature = "defmt")]
8112 impl defmt::Format for Pllfracr {
8113 fn format(&self, f: defmt::Formatter) {
8114 #[derive(defmt :: Format)]
8115 struct Pllfracr {
8116 pllfracn: u16,
8117 }
8118 let proxy = Pllfracr {
8119 pllfracn: self.pllfracn(),
8120 };
8121 defmt::write!(f, "{}", proxy)
8122 }
8123 }
8124 #[doc = "RCC privilege configuration register"]
8125 #[repr(transparent)]
8126 #[derive(Copy, Clone, Eq, PartialEq)]
8127 pub struct Privcfgr(pub u32);
8128 impl Privcfgr {
8129 #[doc = "RCC secure functions privilege configuration Set and reset by software. This bit can be written only by a secure privileged access."]
8130 #[inline(always)]
8131 pub const fn spriv(&self) -> bool {
8132 let val = (self.0 >> 0usize) & 0x01;
8133 val != 0
8134 }
8135 #[doc = "RCC secure functions privilege configuration Set and reset by software. This bit can be written only by a secure privileged access."]
8136 #[inline(always)]
8137 pub fn set_spriv(&mut self, val: bool) {
8138 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
8139 }
8140 #[doc = "RCC non-secure functions privilege configuration Set and reset by software. This bit can be written only by privileged access, secure or non-secure."]
8141 #[inline(always)]
8142 pub const fn nspriv(&self) -> bool {
8143 let val = (self.0 >> 1usize) & 0x01;
8144 val != 0
8145 }
8146 #[doc = "RCC non-secure functions privilege configuration Set and reset by software. This bit can be written only by privileged access, secure or non-secure."]
8147 #[inline(always)]
8148 pub fn set_nspriv(&mut self, val: bool) {
8149 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
8150 }
8151 }
8152 impl Default for Privcfgr {
8153 #[inline(always)]
8154 fn default() -> Privcfgr {
8155 Privcfgr(0)
8156 }
8157 }
8158 impl core::fmt::Debug for Privcfgr {
8159 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
8160 f.debug_struct("Privcfgr")
8161 .field("spriv", &self.spriv())
8162 .field("nspriv", &self.nspriv())
8163 .finish()
8164 }
8165 }
8166 #[cfg(feature = "defmt")]
8167 impl defmt::Format for Privcfgr {
8168 fn format(&self, f: defmt::Formatter) {
8169 #[derive(defmt :: Format)]
8170 struct Privcfgr {
8171 spriv: bool,
8172 nspriv: bool,
8173 }
8174 let proxy = Privcfgr {
8175 spriv: self.spriv(),
8176 nspriv: self.nspriv(),
8177 };
8178 defmt::write!(f, "{}", proxy)
8179 }
8180 }
8181 #[doc = "RCC secure configuration register"]
8182 #[repr(transparent)]
8183 #[derive(Copy, Clone, Eq, PartialEq)]
8184 pub struct Seccfgr(pub u32);
8185 impl Seccfgr {
8186 #[doc = "HSI clock configuration and status bits security Set and reset by software."]
8187 #[inline(always)]
8188 pub const fn hsisec(&self) -> super::vals::Security {
8189 let val = (self.0 >> 0usize) & 0x01;
8190 super::vals::Security::from_bits(val as u8)
8191 }
8192 #[doc = "HSI clock configuration and status bits security Set and reset by software."]
8193 #[inline(always)]
8194 pub fn set_hsisec(&mut self, val: super::vals::Security) {
8195 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize);
8196 }
8197 #[doc = "HSE clock configuration bits, status bits and HSE_CSS security Set and reset by software."]
8198 #[inline(always)]
8199 pub const fn hsesec(&self) -> super::vals::Security {
8200 let val = (self.0 >> 1usize) & 0x01;
8201 super::vals::Security::from_bits(val as u8)
8202 }
8203 #[doc = "HSE clock configuration bits, status bits and HSE_CSS security Set and reset by software."]
8204 #[inline(always)]
8205 pub fn set_hsesec(&mut self, val: super::vals::Security) {
8206 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize);
8207 }
8208 #[doc = "MSI clock configuration and status bits security Set and reset by software."]
8209 #[inline(always)]
8210 pub const fn msisec(&self) -> super::vals::Security {
8211 let val = (self.0 >> 2usize) & 0x01;
8212 super::vals::Security::from_bits(val as u8)
8213 }
8214 #[doc = "MSI clock configuration and status bits security Set and reset by software."]
8215 #[inline(always)]
8216 pub fn set_msisec(&mut self, val: super::vals::Security) {
8217 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize);
8218 }
8219 #[doc = "LSI clock configuration and status bits security Set and reset by software."]
8220 #[inline(always)]
8221 pub const fn lsisec(&self) -> super::vals::Security {
8222 let val = (self.0 >> 3usize) & 0x01;
8223 super::vals::Security::from_bits(val as u8)
8224 }
8225 #[doc = "LSI clock configuration and status bits security Set and reset by software."]
8226 #[inline(always)]
8227 pub fn set_lsisec(&mut self, val: super::vals::Security) {
8228 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize);
8229 }
8230 #[doc = "LSE clock configuration and status bits security Set and reset by software."]
8231 #[inline(always)]
8232 pub const fn lsesec(&self) -> super::vals::Security {
8233 let val = (self.0 >> 4usize) & 0x01;
8234 super::vals::Security::from_bits(val as u8)
8235 }
8236 #[doc = "LSE clock configuration and status bits security Set and reset by software."]
8237 #[inline(always)]
8238 pub fn set_lsesec(&mut self, val: super::vals::Security) {
8239 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize);
8240 }
8241 #[doc = "SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security Set and reset by software."]
8242 #[inline(always)]
8243 pub const fn sysclksec(&self) -> super::vals::Security {
8244 let val = (self.0 >> 5usize) & 0x01;
8245 super::vals::Security::from_bits(val as u8)
8246 }
8247 #[doc = "SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security Set and reset by software."]
8248 #[inline(always)]
8249 pub fn set_sysclksec(&mut self, val: super::vals::Security) {
8250 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.to_bits() as u32) & 0x01) << 5usize);
8251 }
8252 #[doc = "AHBx/APBx prescaler configuration bits security Set and reset by software."]
8253 #[inline(always)]
8254 pub const fn prescsec(&self) -> super::vals::Security {
8255 let val = (self.0 >> 6usize) & 0x01;
8256 super::vals::Security::from_bits(val as u8)
8257 }
8258 #[doc = "AHBx/APBx prescaler configuration bits security Set and reset by software."]
8259 #[inline(always)]
8260 pub fn set_prescsec(&mut self, val: super::vals::Security) {
8261 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
8262 }
8263 #[doc = "PLL1 clock configuration and status bits security Set and reset by software."]
8264 #[inline(always)]
8265 pub const fn pllsec(&self, n: usize) -> super::vals::Security {
8266 assert!(n < 3usize);
8267 let offs = 7usize + n * 1usize;
8268 let val = (self.0 >> offs) & 0x01;
8269 super::vals::Security::from_bits(val as u8)
8270 }
8271 #[doc = "PLL1 clock configuration and status bits security Set and reset by software."]
8272 #[inline(always)]
8273 pub fn set_pllsec(&mut self, n: usize, val: super::vals::Security) {
8274 assert!(n < 3usize);
8275 let offs = 7usize + n * 1usize;
8276 self.0 = (self.0 & !(0x01 << offs)) | (((val.to_bits() as u32) & 0x01) << offs);
8277 }
8278 #[doc = "intermediate clock source selection security Set and reset by software."]
8279 #[inline(always)]
8280 pub const fn iclksec(&self) -> super::vals::Security {
8281 let val = (self.0 >> 10usize) & 0x01;
8282 super::vals::Security::from_bits(val as u8)
8283 }
8284 #[doc = "intermediate clock source selection security Set and reset by software."]
8285 #[inline(always)]
8286 pub fn set_iclksec(&mut self, val: super::vals::Security) {
8287 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.to_bits() as u32) & 0x01) << 10usize);
8288 }
8289 #[doc = "HSI48 clock configuration and status bits security Set and reset by software."]
8290 #[inline(always)]
8291 pub const fn hsi48sec(&self) -> super::vals::Security {
8292 let val = (self.0 >> 11usize) & 0x01;
8293 super::vals::Security::from_bits(val as u8)
8294 }
8295 #[doc = "HSI48 clock configuration and status bits security Set and reset by software."]
8296 #[inline(always)]
8297 pub fn set_hsi48sec(&mut self, val: super::vals::Security) {
8298 self.0 = (self.0 & !(0x01 << 11usize)) | (((val.to_bits() as u32) & 0x01) << 11usize);
8299 }
8300 #[doc = "Remove reset flag security Set and reset by software."]
8301 #[inline(always)]
8302 pub const fn rmvfsec(&self) -> super::vals::Security {
8303 let val = (self.0 >> 12usize) & 0x01;
8304 super::vals::Security::from_bits(val as u8)
8305 }
8306 #[doc = "Remove reset flag security Set and reset by software."]
8307 #[inline(always)]
8308 pub fn set_rmvfsec(&mut self, val: super::vals::Security) {
8309 self.0 = (self.0 & !(0x01 << 12usize)) | (((val.to_bits() as u32) & 0x01) << 12usize);
8310 }
8311 }
8312 impl Default for Seccfgr {
8313 #[inline(always)]
8314 fn default() -> Seccfgr {
8315 Seccfgr(0)
8316 }
8317 }
8318 impl core::fmt::Debug for Seccfgr {
8319 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
8320 f.debug_struct("Seccfgr")
8321 .field("hsisec", &self.hsisec())
8322 .field("hsesec", &self.hsesec())
8323 .field("msisec", &self.msisec())
8324 .field("lsisec", &self.lsisec())
8325 .field("lsesec", &self.lsesec())
8326 .field("sysclksec", &self.sysclksec())
8327 .field("prescsec", &self.prescsec())
8328 .field(
8329 "pllsec",
8330 &[self.pllsec(0usize), self.pllsec(1usize), self.pllsec(2usize)],
8331 )
8332 .field("iclksec", &self.iclksec())
8333 .field("hsi48sec", &self.hsi48sec())
8334 .field("rmvfsec", &self.rmvfsec())
8335 .finish()
8336 }
8337 }
8338 #[cfg(feature = "defmt")]
8339 impl defmt::Format for Seccfgr {
8340 fn format(&self, f: defmt::Formatter) {
8341 #[derive(defmt :: Format)]
8342 struct Seccfgr {
8343 hsisec: super::vals::Security,
8344 hsesec: super::vals::Security,
8345 msisec: super::vals::Security,
8346 lsisec: super::vals::Security,
8347 lsesec: super::vals::Security,
8348 sysclksec: super::vals::Security,
8349 prescsec: super::vals::Security,
8350 pllsec: [super::vals::Security; 3usize],
8351 iclksec: super::vals::Security,
8352 hsi48sec: super::vals::Security,
8353 rmvfsec: super::vals::Security,
8354 }
8355 let proxy = Seccfgr {
8356 hsisec: self.hsisec(),
8357 hsesec: self.hsesec(),
8358 msisec: self.msisec(),
8359 lsisec: self.lsisec(),
8360 lsesec: self.lsesec(),
8361 sysclksec: self.sysclksec(),
8362 prescsec: self.prescsec(),
8363 pllsec: [self.pllsec(0usize), self.pllsec(1usize), self.pllsec(2usize)],
8364 iclksec: self.iclksec(),
8365 hsi48sec: self.hsi48sec(),
8366 rmvfsec: self.rmvfsec(),
8367 };
8368 defmt::write!(f, "{}", proxy)
8369 }
8370 }
8371 #[doc = "RCC SmartRun domain peripheral autonomous mode register"]
8372 #[repr(transparent)]
8373 #[derive(Copy, Clone, Eq, PartialEq)]
8374 pub struct Srdamr(pub u32);
8375 impl Srdamr {
8376 #[doc = "SPI3 autonomous mode enable in Stop 0,1, 2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
8377 #[inline(always)]
8378 pub const fn spi3amen(&self) -> bool {
8379 let val = (self.0 >> 5usize) & 0x01;
8380 val != 0
8381 }
8382 #[doc = "SPI3 autonomous mode enable in Stop 0,1, 2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
8383 #[inline(always)]
8384 pub fn set_spi3amen(&mut self, val: bool) {
8385 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
8386 }
8387 #[doc = "LPUART1 autonomous mode enable in Stop 0,1, 2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
8388 #[inline(always)]
8389 pub const fn lpuart1amen(&self) -> bool {
8390 let val = (self.0 >> 6usize) & 0x01;
8391 val != 0
8392 }
8393 #[doc = "LPUART1 autonomous mode enable in Stop 0,1, 2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
8394 #[inline(always)]
8395 pub fn set_lpuart1amen(&mut self, val: bool) {
8396 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
8397 }
8398 #[doc = "I2C3 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
8399 #[inline(always)]
8400 pub const fn i2c3amen(&self) -> bool {
8401 let val = (self.0 >> 7usize) & 0x01;
8402 val != 0
8403 }
8404 #[doc = "I2C3 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
8405 #[inline(always)]
8406 pub fn set_i2c3amen(&mut self, val: bool) {
8407 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
8408 }
8409 #[doc = "LPTIM1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
8410 #[inline(always)]
8411 pub const fn lptim1amen(&self) -> bool {
8412 let val = (self.0 >> 11usize) & 0x01;
8413 val != 0
8414 }
8415 #[doc = "LPTIM1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
8416 #[inline(always)]
8417 pub fn set_lptim1amen(&mut self, val: bool) {
8418 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
8419 }
8420 #[doc = "LPTIM3 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
8421 #[inline(always)]
8422 pub const fn lptim3amen(&self) -> bool {
8423 let val = (self.0 >> 12usize) & 0x01;
8424 val != 0
8425 }
8426 #[doc = "LPTIM3 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
8427 #[inline(always)]
8428 pub fn set_lptim3amen(&mut self, val: bool) {
8429 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
8430 }
8431 #[doc = "LPTIM4 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
8432 #[inline(always)]
8433 pub const fn lptim4amen(&self) -> bool {
8434 let val = (self.0 >> 13usize) & 0x01;
8435 val != 0
8436 }
8437 #[doc = "LPTIM4 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
8438 #[inline(always)]
8439 pub fn set_lptim4amen(&mut self, val: bool) {
8440 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
8441 }
8442 #[doc = "OPAMP autonomous mode enable in Stop 0,1,2 mode Set and cleared by software."]
8443 #[inline(always)]
8444 pub const fn opampamen(&self) -> bool {
8445 let val = (self.0 >> 14usize) & 0x01;
8446 val != 0
8447 }
8448 #[doc = "OPAMP autonomous mode enable in Stop 0,1,2 mode Set and cleared by software."]
8449 #[inline(always)]
8450 pub fn set_opampamen(&mut self, val: bool) {
8451 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
8452 }
8453 #[doc = "COMP autonomous mode enable in Stop 0,1,2 mode Set and cleared by software."]
8454 #[inline(always)]
8455 pub const fn compamen(&self) -> bool {
8456 let val = (self.0 >> 15usize) & 0x01;
8457 val != 0
8458 }
8459 #[doc = "COMP autonomous mode enable in Stop 0,1,2 mode Set and cleared by software."]
8460 #[inline(always)]
8461 pub fn set_compamen(&mut self, val: bool) {
8462 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
8463 }
8464 #[doc = "VREFBUF autonomous mode enable in Stop 0,1,2 mode Set and cleared by software."]
8465 #[inline(always)]
8466 pub const fn vrefamen(&self) -> bool {
8467 let val = (self.0 >> 20usize) & 0x01;
8468 val != 0
8469 }
8470 #[doc = "VREFBUF autonomous mode enable in Stop 0,1,2 mode Set and cleared by software."]
8471 #[inline(always)]
8472 pub fn set_vrefamen(&mut self, val: bool) {
8473 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
8474 }
8475 #[doc = "RTC and TAMP autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
8476 #[inline(always)]
8477 pub const fn rtcapbamen(&self) -> bool {
8478 let val = (self.0 >> 21usize) & 0x01;
8479 val != 0
8480 }
8481 #[doc = "RTC and TAMP autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
8482 #[inline(always)]
8483 pub fn set_rtcapbamen(&mut self, val: bool) {
8484 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
8485 }
8486 #[doc = "ADC4 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
8487 #[inline(always)]
8488 pub const fn adc4amen(&self) -> bool {
8489 let val = (self.0 >> 25usize) & 0x01;
8490 val != 0
8491 }
8492 #[doc = "ADC4 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
8493 #[inline(always)]
8494 pub fn set_adc4amen(&mut self, val: bool) {
8495 self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
8496 }
8497 #[doc = "LPGPIO1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software."]
8498 #[inline(always)]
8499 pub const fn lpgpio1amen(&self) -> bool {
8500 let val = (self.0 >> 26usize) & 0x01;
8501 val != 0
8502 }
8503 #[doc = "LPGPIO1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software."]
8504 #[inline(always)]
8505 pub fn set_lpgpio1amen(&mut self, val: bool) {
8506 self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
8507 }
8508 #[doc = "DAC1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
8509 #[inline(always)]
8510 pub const fn dac1amen(&self) -> bool {
8511 let val = (self.0 >> 27usize) & 0x01;
8512 val != 0
8513 }
8514 #[doc = "DAC1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
8515 #[inline(always)]
8516 pub fn set_dac1amen(&mut self, val: bool) {
8517 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
8518 }
8519 #[doc = "LPDMA1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
8520 #[inline(always)]
8521 pub const fn lpdma1amen(&self) -> bool {
8522 let val = (self.0 >> 28usize) & 0x01;
8523 val != 0
8524 }
8525 #[doc = "LPDMA1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
8526 #[inline(always)]
8527 pub fn set_lpdma1amen(&mut self, val: bool) {
8528 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
8529 }
8530 #[doc = "ADF1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
8531 #[inline(always)]
8532 pub const fn adf1amen(&self) -> bool {
8533 let val = (self.0 >> 29usize) & 0x01;
8534 val != 0
8535 }
8536 #[doc = "ADF1 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes."]
8537 #[inline(always)]
8538 pub fn set_adf1amen(&mut self, val: bool) {
8539 self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
8540 }
8541 #[doc = "SRAM4 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software."]
8542 #[inline(always)]
8543 pub const fn sram4amen(&self) -> bool {
8544 let val = (self.0 >> 31usize) & 0x01;
8545 val != 0
8546 }
8547 #[doc = "SRAM4 autonomous mode enable in Stop 0,1,2 mode Set and cleared by software."]
8548 #[inline(always)]
8549 pub fn set_sram4amen(&mut self, val: bool) {
8550 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
8551 }
8552 }
8553 impl Default for Srdamr {
8554 #[inline(always)]
8555 fn default() -> Srdamr {
8556 Srdamr(0)
8557 }
8558 }
8559 impl core::fmt::Debug for Srdamr {
8560 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
8561 f.debug_struct("Srdamr")
8562 .field("spi3amen", &self.spi3amen())
8563 .field("lpuart1amen", &self.lpuart1amen())
8564 .field("i2c3amen", &self.i2c3amen())
8565 .field("lptim1amen", &self.lptim1amen())
8566 .field("lptim3amen", &self.lptim3amen())
8567 .field("lptim4amen", &self.lptim4amen())
8568 .field("opampamen", &self.opampamen())
8569 .field("compamen", &self.compamen())
8570 .field("vrefamen", &self.vrefamen())
8571 .field("rtcapbamen", &self.rtcapbamen())
8572 .field("adc4amen", &self.adc4amen())
8573 .field("lpgpio1amen", &self.lpgpio1amen())
8574 .field("dac1amen", &self.dac1amen())
8575 .field("lpdma1amen", &self.lpdma1amen())
8576 .field("adf1amen", &self.adf1amen())
8577 .field("sram4amen", &self.sram4amen())
8578 .finish()
8579 }
8580 }
8581 #[cfg(feature = "defmt")]
8582 impl defmt::Format for Srdamr {
8583 fn format(&self, f: defmt::Formatter) {
8584 #[derive(defmt :: Format)]
8585 struct Srdamr {
8586 spi3amen: bool,
8587 lpuart1amen: bool,
8588 i2c3amen: bool,
8589 lptim1amen: bool,
8590 lptim3amen: bool,
8591 lptim4amen: bool,
8592 opampamen: bool,
8593 compamen: bool,
8594 vrefamen: bool,
8595 rtcapbamen: bool,
8596 adc4amen: bool,
8597 lpgpio1amen: bool,
8598 dac1amen: bool,
8599 lpdma1amen: bool,
8600 adf1amen: bool,
8601 sram4amen: bool,
8602 }
8603 let proxy = Srdamr {
8604 spi3amen: self.spi3amen(),
8605 lpuart1amen: self.lpuart1amen(),
8606 i2c3amen: self.i2c3amen(),
8607 lptim1amen: self.lptim1amen(),
8608 lptim3amen: self.lptim3amen(),
8609 lptim4amen: self.lptim4amen(),
8610 opampamen: self.opampamen(),
8611 compamen: self.compamen(),
8612 vrefamen: self.vrefamen(),
8613 rtcapbamen: self.rtcapbamen(),
8614 adc4amen: self.adc4amen(),
8615 lpgpio1amen: self.lpgpio1amen(),
8616 dac1amen: self.dac1amen(),
8617 lpdma1amen: self.lpdma1amen(),
8618 adf1amen: self.adf1amen(),
8619 sram4amen: self.sram4amen(),
8620 };
8621 defmt::write!(f, "{}", proxy)
8622 }
8623 }
8624}
8625pub mod vals {
8626 #[repr(u8)]
8627 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8628 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8629 pub enum Adcdacsel {
8630 #[doc = "HCLK clock selected"]
8631 HCLK1 = 0x0,
8632 #[doc = "SYSCLK selected"]
8633 SYS = 0x01,
8634 #[doc = "PLL2 R (pll2_r_ck) selected"]
8635 PLL2_R = 0x02,
8636 #[doc = "HSE clock selected"]
8637 HSE = 0x03,
8638 #[doc = "HSI clock selected"]
8639 HSI = 0x04,
8640 #[doc = "MSIK clock selected"]
8641 MSIK = 0x05,
8642 _RESERVED_6 = 0x06,
8643 _RESERVED_7 = 0x07,
8644 }
8645 impl Adcdacsel {
8646 #[inline(always)]
8647 pub const fn from_bits(val: u8) -> Adcdacsel {
8648 unsafe { core::mem::transmute(val & 0x07) }
8649 }
8650 #[inline(always)]
8651 pub const fn to_bits(self) -> u8 {
8652 unsafe { core::mem::transmute(self) }
8653 }
8654 }
8655 impl From<u8> for Adcdacsel {
8656 #[inline(always)]
8657 fn from(val: u8) -> Adcdacsel {
8658 Adcdacsel::from_bits(val)
8659 }
8660 }
8661 impl From<Adcdacsel> for u8 {
8662 #[inline(always)]
8663 fn from(val: Adcdacsel) -> u8 {
8664 Adcdacsel::to_bits(val)
8665 }
8666 }
8667 #[repr(u8)]
8668 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8669 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8670 pub enum Adfsel {
8671 #[doc = "HCLK selected"]
8672 HCLK3 = 0x0,
8673 #[doc = "PLL1 P (pll1_p_ck) selected"]
8674 PLL1_P = 0x01,
8675 #[doc = "PLL3 Q (pll3_q_ck) selected"]
8676 PLL3_Q = 0x02,
8677 #[doc = "input pin AUDIOCLK selected"]
8678 AUDIOCLK = 0x03,
8679 #[doc = "MSIK clock selected"]
8680 MSIK = 0x04,
8681 _RESERVED_5 = 0x05,
8682 _RESERVED_6 = 0x06,
8683 _RESERVED_7 = 0x07,
8684 }
8685 impl Adfsel {
8686 #[inline(always)]
8687 pub const fn from_bits(val: u8) -> Adfsel {
8688 unsafe { core::mem::transmute(val & 0x07) }
8689 }
8690 #[inline(always)]
8691 pub const fn to_bits(self) -> u8 {
8692 unsafe { core::mem::transmute(self) }
8693 }
8694 }
8695 impl From<u8> for Adfsel {
8696 #[inline(always)]
8697 fn from(val: u8) -> Adfsel {
8698 Adfsel::from_bits(val)
8699 }
8700 }
8701 impl From<Adfsel> for u8 {
8702 #[inline(always)]
8703 fn from(val: Adfsel) -> u8 {
8704 Adfsel::to_bits(val)
8705 }
8706 }
8707 #[repr(u8)]
8708 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8709 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8710 pub enum Dacsel {
8711 #[doc = "LSE selected"]
8712 LSE = 0x0,
8713 #[doc = "LSI selected"]
8714 LSI = 0x01,
8715 }
8716 impl Dacsel {
8717 #[inline(always)]
8718 pub const fn from_bits(val: u8) -> Dacsel {
8719 unsafe { core::mem::transmute(val & 0x01) }
8720 }
8721 #[inline(always)]
8722 pub const fn to_bits(self) -> u8 {
8723 unsafe { core::mem::transmute(self) }
8724 }
8725 }
8726 impl From<u8> for Dacsel {
8727 #[inline(always)]
8728 fn from(val: u8) -> Dacsel {
8729 Dacsel::from_bits(val)
8730 }
8731 }
8732 impl From<Dacsel> for u8 {
8733 #[inline(always)]
8734 fn from(val: Dacsel) -> u8 {
8735 Dacsel::to_bits(val)
8736 }
8737 }
8738 #[repr(u8)]
8739 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8740 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8741 pub enum Dpre {
8742 #[doc = "DCLK not divided"]
8743 DIV1 = 0x0,
8744 _RESERVED_1 = 0x01,
8745 _RESERVED_2 = 0x02,
8746 _RESERVED_3 = 0x03,
8747 #[doc = "DCLK divided by 2"]
8748 DIV2 = 0x04,
8749 #[doc = "DCLK divided by 4"]
8750 DIV4 = 0x05,
8751 #[doc = "DCLK divided by 8"]
8752 DIV8 = 0x06,
8753 #[doc = "DCLK divided by 16"]
8754 DIV16 = 0x07,
8755 }
8756 impl Dpre {
8757 #[inline(always)]
8758 pub const fn from_bits(val: u8) -> Dpre {
8759 unsafe { core::mem::transmute(val & 0x07) }
8760 }
8761 #[inline(always)]
8762 pub const fn to_bits(self) -> u8 {
8763 unsafe { core::mem::transmute(self) }
8764 }
8765 }
8766 impl From<u8> for Dpre {
8767 #[inline(always)]
8768 fn from(val: u8) -> Dpre {
8769 Dpre::from_bits(val)
8770 }
8771 }
8772 impl From<Dpre> for u8 {
8773 #[inline(always)]
8774 fn from(val: Dpre) -> u8 {
8775 Dpre::to_bits(val)
8776 }
8777 }
8778 #[repr(u8)]
8779 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8780 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8781 pub enum Dsisel {
8782 #[doc = "PLL3 “P” (pll3_p_ck) selected"]
8783 PLL3_P = 0x0,
8784 #[doc = "DSI PHY PLL output selected (formerly called DCLK, renamed to DSI_PHY to match other chip families)"]
8785 DSI_PHY = 0x01,
8786 }
8787 impl Dsisel {
8788 #[inline(always)]
8789 pub const fn from_bits(val: u8) -> Dsisel {
8790 unsafe { core::mem::transmute(val & 0x01) }
8791 }
8792 #[inline(always)]
8793 pub const fn to_bits(self) -> u8 {
8794 unsafe { core::mem::transmute(self) }
8795 }
8796 }
8797 impl From<u8> for Dsisel {
8798 #[inline(always)]
8799 fn from(val: u8) -> Dsisel {
8800 Dsisel::from_bits(val)
8801 }
8802 }
8803 impl From<Dsisel> for u8 {
8804 #[inline(always)]
8805 fn from(val: Dsisel) -> u8 {
8806 Dsisel::to_bits(val)
8807 }
8808 }
8809 #[repr(u8)]
8810 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8811 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8812 pub enum Fdcansel {
8813 #[doc = "HSE clock selected"]
8814 HSE = 0x0,
8815 #[doc = "PLL1 Q (pll1_q_ck) selected"]
8816 PLL1_Q = 0x01,
8817 #[doc = "PLL2 P (pll2_p_ck) selected"]
8818 PLL2_P = 0x02,
8819 _RESERVED_3 = 0x03,
8820 }
8821 impl Fdcansel {
8822 #[inline(always)]
8823 pub const fn from_bits(val: u8) -> Fdcansel {
8824 unsafe { core::mem::transmute(val & 0x03) }
8825 }
8826 #[inline(always)]
8827 pub const fn to_bits(self) -> u8 {
8828 unsafe { core::mem::transmute(self) }
8829 }
8830 }
8831 impl From<u8> for Fdcansel {
8832 #[inline(always)]
8833 fn from(val: u8) -> Fdcansel {
8834 Fdcansel::from_bits(val)
8835 }
8836 }
8837 impl From<Fdcansel> for u8 {
8838 #[inline(always)]
8839 fn from(val: Fdcansel) -> u8 {
8840 Fdcansel::to_bits(val)
8841 }
8842 }
8843 #[repr(u8)]
8844 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8845 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8846 pub enum Hpre {
8847 #[doc = "SYSCLK not divided"]
8848 DIV1 = 0x0,
8849 _RESERVED_1 = 0x01,
8850 _RESERVED_2 = 0x02,
8851 _RESERVED_3 = 0x03,
8852 _RESERVED_4 = 0x04,
8853 _RESERVED_5 = 0x05,
8854 _RESERVED_6 = 0x06,
8855 _RESERVED_7 = 0x07,
8856 #[doc = "SYSCLK divided by 2"]
8857 DIV2 = 0x08,
8858 #[doc = "SYSCLK divided by 4"]
8859 DIV4 = 0x09,
8860 #[doc = "SYSCLK divided by 8"]
8861 DIV8 = 0x0a,
8862 #[doc = "SYSCLK divided by 16"]
8863 DIV16 = 0x0b,
8864 #[doc = "SYSCLK divided by 64"]
8865 DIV64 = 0x0c,
8866 #[doc = "SYSCLK divided by 128"]
8867 DIV128 = 0x0d,
8868 #[doc = "SYSCLK divided by 256"]
8869 DIV256 = 0x0e,
8870 #[doc = "SYSCLK divided by 512"]
8871 DIV512 = 0x0f,
8872 }
8873 impl Hpre {
8874 #[inline(always)]
8875 pub const fn from_bits(val: u8) -> Hpre {
8876 unsafe { core::mem::transmute(val & 0x0f) }
8877 }
8878 #[inline(always)]
8879 pub const fn to_bits(self) -> u8 {
8880 unsafe { core::mem::transmute(self) }
8881 }
8882 }
8883 impl From<u8> for Hpre {
8884 #[inline(always)]
8885 fn from(val: u8) -> Hpre {
8886 Hpre::from_bits(val)
8887 }
8888 }
8889 impl From<Hpre> for u8 {
8890 #[inline(always)]
8891 fn from(val: Hpre) -> u8 {
8892 Hpre::to_bits(val)
8893 }
8894 }
8895 #[repr(u8)]
8896 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8897 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8898 pub enum Hseext {
8899 #[doc = "external HSE clock analog mode"]
8900 ANALOG = 0x0,
8901 #[doc = "external HSE clock digital mode (through I/O Schmitt trigger)"]
8902 DIGITAL = 0x01,
8903 }
8904 impl Hseext {
8905 #[inline(always)]
8906 pub const fn from_bits(val: u8) -> Hseext {
8907 unsafe { core::mem::transmute(val & 0x01) }
8908 }
8909 #[inline(always)]
8910 pub const fn to_bits(self) -> u8 {
8911 unsafe { core::mem::transmute(self) }
8912 }
8913 }
8914 impl From<u8> for Hseext {
8915 #[inline(always)]
8916 fn from(val: u8) -> Hseext {
8917 Hseext::from_bits(val)
8918 }
8919 }
8920 impl From<Hseext> for u8 {
8921 #[inline(always)]
8922 fn from(val: Hseext) -> u8 {
8923 Hseext::to_bits(val)
8924 }
8925 }
8926 #[repr(u8)]
8927 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8928 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8929 pub enum Hspisel {
8930 #[doc = "SYSCLK selected"]
8931 SYS = 0x0,
8932 #[doc = "PLL1 “Q” (pll1_q_ck) selected, can be up to 200 MHz"]
8933 PLL1_Q = 0x01,
8934 #[doc = "PLL2 “Q” (pll2_q_ck) selected, can be up to 200 MHz"]
8935 PLL2_Q = 0x02,
8936 #[doc = "PLL3 “R” (pll3_r_ck) selected, can be up to 200 MHz"]
8937 PLL3_R = 0x03,
8938 }
8939 impl Hspisel {
8940 #[inline(always)]
8941 pub const fn from_bits(val: u8) -> Hspisel {
8942 unsafe { core::mem::transmute(val & 0x03) }
8943 }
8944 #[inline(always)]
8945 pub const fn to_bits(self) -> u8 {
8946 unsafe { core::mem::transmute(self) }
8947 }
8948 }
8949 impl From<u8> for Hspisel {
8950 #[inline(always)]
8951 fn from(val: u8) -> Hspisel {
8952 Hspisel::from_bits(val)
8953 }
8954 }
8955 impl From<Hspisel> for u8 {
8956 #[inline(always)]
8957 fn from(val: Hspisel) -> u8 {
8958 Hspisel::to_bits(val)
8959 }
8960 }
8961 #[repr(u8)]
8962 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8963 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8964 pub enum I2c3sel {
8965 #[doc = "PCLK3 selected"]
8966 PCLK3 = 0x0,
8967 #[doc = "SYSCLK selected"]
8968 SYS = 0x01,
8969 #[doc = "HSI selected"]
8970 HSI = 0x02,
8971 #[doc = "MSIK selected"]
8972 MSIK = 0x03,
8973 }
8974 impl I2c3sel {
8975 #[inline(always)]
8976 pub const fn from_bits(val: u8) -> I2c3sel {
8977 unsafe { core::mem::transmute(val & 0x03) }
8978 }
8979 #[inline(always)]
8980 pub const fn to_bits(self) -> u8 {
8981 unsafe { core::mem::transmute(self) }
8982 }
8983 }
8984 impl From<u8> for I2c3sel {
8985 #[inline(always)]
8986 fn from(val: u8) -> I2c3sel {
8987 I2c3sel::from_bits(val)
8988 }
8989 }
8990 impl From<I2c3sel> for u8 {
8991 #[inline(always)]
8992 fn from(val: I2c3sel) -> u8 {
8993 I2c3sel::to_bits(val)
8994 }
8995 }
8996 #[repr(u8)]
8997 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8998 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8999 pub enum I2csel {
9000 #[doc = "PCLK1 selected"]
9001 PCLK1 = 0x0,
9002 #[doc = "SYSCLK selected"]
9003 SYS = 0x01,
9004 #[doc = "HSI selected"]
9005 HSI = 0x02,
9006 #[doc = "MSIK selected"]
9007 MSIK = 0x03,
9008 }
9009 impl I2csel {
9010 #[inline(always)]
9011 pub const fn from_bits(val: u8) -> I2csel {
9012 unsafe { core::mem::transmute(val & 0x03) }
9013 }
9014 #[inline(always)]
9015 pub const fn to_bits(self) -> u8 {
9016 unsafe { core::mem::transmute(self) }
9017 }
9018 }
9019 impl From<u8> for I2csel {
9020 #[inline(always)]
9021 fn from(val: u8) -> I2csel {
9022 I2csel::from_bits(val)
9023 }
9024 }
9025 impl From<I2csel> for u8 {
9026 #[inline(always)]
9027 fn from(val: I2csel) -> u8 {
9028 I2csel::to_bits(val)
9029 }
9030 }
9031 #[repr(u8)]
9032 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9033 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9034 pub enum Iclksel {
9035 #[doc = "HSI48 clock selected"]
9036 HSI48 = 0x0,
9037 #[doc = "PLL2 Q (pll2_q_ck) selected"]
9038 PLL2_Q = 0x01,
9039 #[doc = "PLL1 Q (pll1_q_ck) selected"]
9040 PLL1_Q = 0x02,
9041 #[doc = "MSIK clock selected"]
9042 MSIK = 0x03,
9043 }
9044 impl Iclksel {
9045 #[inline(always)]
9046 pub const fn from_bits(val: u8) -> Iclksel {
9047 unsafe { core::mem::transmute(val & 0x03) }
9048 }
9049 #[inline(always)]
9050 pub const fn to_bits(self) -> u8 {
9051 unsafe { core::mem::transmute(self) }
9052 }
9053 }
9054 impl From<u8> for Iclksel {
9055 #[inline(always)]
9056 fn from(val: u8) -> Iclksel {
9057 Iclksel::from_bits(val)
9058 }
9059 }
9060 impl From<Iclksel> for u8 {
9061 #[inline(always)]
9062 fn from(val: Iclksel) -> u8 {
9063 Iclksel::to_bits(val)
9064 }
9065 }
9066 #[repr(u8)]
9067 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9068 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9069 pub enum Lptim2sel {
9070 #[doc = "PCLK1 selected"]
9071 PCLK1 = 0x0,
9072 #[doc = "LSI selected"]
9073 LSI = 0x01,
9074 #[doc = "HSI selected"]
9075 HSI = 0x02,
9076 #[doc = "LSE selected"]
9077 LSE = 0x03,
9078 }
9079 impl Lptim2sel {
9080 #[inline(always)]
9081 pub const fn from_bits(val: u8) -> Lptim2sel {
9082 unsafe { core::mem::transmute(val & 0x03) }
9083 }
9084 #[inline(always)]
9085 pub const fn to_bits(self) -> u8 {
9086 unsafe { core::mem::transmute(self) }
9087 }
9088 }
9089 impl From<u8> for Lptim2sel {
9090 #[inline(always)]
9091 fn from(val: u8) -> Lptim2sel {
9092 Lptim2sel::from_bits(val)
9093 }
9094 }
9095 impl From<Lptim2sel> for u8 {
9096 #[inline(always)]
9097 fn from(val: Lptim2sel) -> u8 {
9098 Lptim2sel::to_bits(val)
9099 }
9100 }
9101 #[repr(u8)]
9102 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9103 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9104 pub enum Lptimsel {
9105 #[doc = "MSIK selected"]
9106 MSIK = 0x0,
9107 #[doc = "LSI selected"]
9108 LSI = 0x01,
9109 #[doc = "HSI selected"]
9110 HSI = 0x02,
9111 #[doc = "LSE selected"]
9112 LSE = 0x03,
9113 }
9114 impl Lptimsel {
9115 #[inline(always)]
9116 pub const fn from_bits(val: u8) -> Lptimsel {
9117 unsafe { core::mem::transmute(val & 0x03) }
9118 }
9119 #[inline(always)]
9120 pub const fn to_bits(self) -> u8 {
9121 unsafe { core::mem::transmute(self) }
9122 }
9123 }
9124 impl From<u8> for Lptimsel {
9125 #[inline(always)]
9126 fn from(val: u8) -> Lptimsel {
9127 Lptimsel::from_bits(val)
9128 }
9129 }
9130 impl From<Lptimsel> for u8 {
9131 #[inline(always)]
9132 fn from(val: Lptimsel) -> u8 {
9133 Lptimsel::to_bits(val)
9134 }
9135 }
9136 #[repr(u8)]
9137 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9138 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9139 pub enum Lpusartsel {
9140 #[doc = "PCLK3 selected"]
9141 PCLK3 = 0x0,
9142 #[doc = "SYSCLK selected"]
9143 SYS = 0x01,
9144 #[doc = "HSI selected"]
9145 HSI = 0x02,
9146 #[doc = "LSE selected"]
9147 LSE = 0x03,
9148 #[doc = "MSIK selected"]
9149 MSIK = 0x04,
9150 _RESERVED_5 = 0x05,
9151 _RESERVED_6 = 0x06,
9152 _RESERVED_7 = 0x07,
9153 }
9154 impl Lpusartsel {
9155 #[inline(always)]
9156 pub const fn from_bits(val: u8) -> Lpusartsel {
9157 unsafe { core::mem::transmute(val & 0x07) }
9158 }
9159 #[inline(always)]
9160 pub const fn to_bits(self) -> u8 {
9161 unsafe { core::mem::transmute(self) }
9162 }
9163 }
9164 impl From<u8> for Lpusartsel {
9165 #[inline(always)]
9166 fn from(val: u8) -> Lpusartsel {
9167 Lpusartsel::from_bits(val)
9168 }
9169 }
9170 impl From<Lpusartsel> for u8 {
9171 #[inline(always)]
9172 fn from(val: Lpusartsel) -> u8 {
9173 Lpusartsel::to_bits(val)
9174 }
9175 }
9176 #[repr(u8)]
9177 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9178 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9179 pub enum Lscosel {
9180 #[doc = "LSI clock selected"]
9181 LSI = 0x0,
9182 #[doc = "LSE clock selected"]
9183 LSE = 0x01,
9184 }
9185 impl Lscosel {
9186 #[inline(always)]
9187 pub const fn from_bits(val: u8) -> Lscosel {
9188 unsafe { core::mem::transmute(val & 0x01) }
9189 }
9190 #[inline(always)]
9191 pub const fn to_bits(self) -> u8 {
9192 unsafe { core::mem::transmute(self) }
9193 }
9194 }
9195 impl From<u8> for Lscosel {
9196 #[inline(always)]
9197 fn from(val: u8) -> Lscosel {
9198 Lscosel::from_bits(val)
9199 }
9200 }
9201 impl From<Lscosel> for u8 {
9202 #[inline(always)]
9203 fn from(val: Lscosel) -> u8 {
9204 Lscosel::to_bits(val)
9205 }
9206 }
9207 #[repr(u8)]
9208 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9209 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9210 pub enum Lsedrv {
9211 #[doc = "Low driving capability"]
9212 LOW = 0x0,
9213 #[doc = "Medium low driving capability"]
9214 MEDIUM_LOW = 0x01,
9215 #[doc = "Medium high driving capability"]
9216 MEDIUM_HIGH = 0x02,
9217 #[doc = "High driving capability"]
9218 HIGH = 0x03,
9219 }
9220 impl Lsedrv {
9221 #[inline(always)]
9222 pub const fn from_bits(val: u8) -> Lsedrv {
9223 unsafe { core::mem::transmute(val & 0x03) }
9224 }
9225 #[inline(always)]
9226 pub const fn to_bits(self) -> u8 {
9227 unsafe { core::mem::transmute(self) }
9228 }
9229 }
9230 impl From<u8> for Lsedrv {
9231 #[inline(always)]
9232 fn from(val: u8) -> Lsedrv {
9233 Lsedrv::from_bits(val)
9234 }
9235 }
9236 impl From<Lsedrv> for u8 {
9237 #[inline(always)]
9238 fn from(val: Lsedrv) -> u8 {
9239 Lsedrv::to_bits(val)
9240 }
9241 }
9242 #[repr(u8)]
9243 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9244 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9245 pub enum Lsiprediv {
9246 #[doc = "LSI not divided"]
9247 DIV1 = 0x0,
9248 #[doc = "LSI divided by 128"]
9249 DIV128 = 0x01,
9250 }
9251 impl Lsiprediv {
9252 #[inline(always)]
9253 pub const fn from_bits(val: u8) -> Lsiprediv {
9254 unsafe { core::mem::transmute(val & 0x01) }
9255 }
9256 #[inline(always)]
9257 pub const fn to_bits(self) -> u8 {
9258 unsafe { core::mem::transmute(self) }
9259 }
9260 }
9261 impl From<u8> for Lsiprediv {
9262 #[inline(always)]
9263 fn from(val: u8) -> Lsiprediv {
9264 Lsiprediv::from_bits(val)
9265 }
9266 }
9267 impl From<Lsiprediv> for u8 {
9268 #[inline(always)]
9269 fn from(val: Lsiprediv) -> u8 {
9270 Lsiprediv::to_bits(val)
9271 }
9272 }
9273 #[repr(u8)]
9274 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9275 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9276 pub enum Ltdcsel {
9277 #[doc = "PLL3 “R” (pll3_r_ck) selected"]
9278 PLL3_R = 0x0,
9279 #[doc = "PLL2 “R” (pll2_r_ck) selected"]
9280 PLL2_R = 0x01,
9281 }
9282 impl Ltdcsel {
9283 #[inline(always)]
9284 pub const fn from_bits(val: u8) -> Ltdcsel {
9285 unsafe { core::mem::transmute(val & 0x01) }
9286 }
9287 #[inline(always)]
9288 pub const fn to_bits(self) -> u8 {
9289 unsafe { core::mem::transmute(self) }
9290 }
9291 }
9292 impl From<u8> for Ltdcsel {
9293 #[inline(always)]
9294 fn from(val: u8) -> Ltdcsel {
9295 Ltdcsel::from_bits(val)
9296 }
9297 }
9298 impl From<Ltdcsel> for u8 {
9299 #[inline(always)]
9300 fn from(val: Ltdcsel) -> u8 {
9301 Ltdcsel::to_bits(val)
9302 }
9303 }
9304 #[repr(u8)]
9305 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9306 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9307 pub enum Mcopre {
9308 #[doc = "MCO divided by 1"]
9309 DIV1 = 0x0,
9310 #[doc = "MCO divided by 2"]
9311 DIV2 = 0x01,
9312 #[doc = "MCO divided by 4"]
9313 DIV4 = 0x02,
9314 #[doc = "MCO divided by 8"]
9315 DIV8 = 0x03,
9316 #[doc = "MCO divided by 16"]
9317 DIV16 = 0x04,
9318 _RESERVED_5 = 0x05,
9319 _RESERVED_6 = 0x06,
9320 _RESERVED_7 = 0x07,
9321 }
9322 impl Mcopre {
9323 #[inline(always)]
9324 pub const fn from_bits(val: u8) -> Mcopre {
9325 unsafe { core::mem::transmute(val & 0x07) }
9326 }
9327 #[inline(always)]
9328 pub const fn to_bits(self) -> u8 {
9329 unsafe { core::mem::transmute(self) }
9330 }
9331 }
9332 impl From<u8> for Mcopre {
9333 #[inline(always)]
9334 fn from(val: u8) -> Mcopre {
9335 Mcopre::from_bits(val)
9336 }
9337 }
9338 impl From<Mcopre> for u8 {
9339 #[inline(always)]
9340 fn from(val: Mcopre) -> u8 {
9341 Mcopre::to_bits(val)
9342 }
9343 }
9344 #[repr(u8)]
9345 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9346 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9347 pub enum Mcosel {
9348 #[doc = "MCO output disabled, no clock on MCO"]
9349 DISABLE = 0x0,
9350 #[doc = "SYSCLK system clock selected"]
9351 SYS = 0x01,
9352 #[doc = "MSIS clock selected"]
9353 MSIS = 0x02,
9354 #[doc = "HSI clock selected"]
9355 HSI = 0x03,
9356 #[doc = "HSE clock selected"]
9357 HSE = 0x04,
9358 #[doc = "Main PLL clock pll1_r_ck selected"]
9359 PLL1_R = 0x05,
9360 #[doc = "LSI clock selected"]
9361 LSI = 0x06,
9362 #[doc = "LSE clock selected"]
9363 LSE = 0x07,
9364 #[doc = "Internal HSI48 clock selected"]
9365 HSI48 = 0x08,
9366 #[doc = "MSIK clock selected"]
9367 MSIK = 0x09,
9368 _RESERVED_a = 0x0a,
9369 _RESERVED_b = 0x0b,
9370 _RESERVED_c = 0x0c,
9371 _RESERVED_d = 0x0d,
9372 _RESERVED_e = 0x0e,
9373 _RESERVED_f = 0x0f,
9374 }
9375 impl Mcosel {
9376 #[inline(always)]
9377 pub const fn from_bits(val: u8) -> Mcosel {
9378 unsafe { core::mem::transmute(val & 0x0f) }
9379 }
9380 #[inline(always)]
9381 pub const fn to_bits(self) -> u8 {
9382 unsafe { core::mem::transmute(self) }
9383 }
9384 }
9385 impl From<u8> for Mcosel {
9386 #[inline(always)]
9387 fn from(val: u8) -> Mcosel {
9388 Mcosel::from_bits(val)
9389 }
9390 }
9391 impl From<Mcosel> for u8 {
9392 #[inline(always)]
9393 fn from(val: Mcosel) -> u8 {
9394 Mcosel::to_bits(val)
9395 }
9396 }
9397 #[repr(u8)]
9398 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9399 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9400 pub enum Mdfsel {
9401 #[doc = "HCLK selected"]
9402 HCLK1 = 0x0,
9403 #[doc = "PLL1 P (pll1_p_ck) selected"]
9404 PLL1_P = 0x01,
9405 #[doc = "PLL3 Q (pll3_q_ck) selected"]
9406 PLL3_Q = 0x02,
9407 #[doc = "input pin AUDIOCLK selected"]
9408 AUDIOCLK = 0x03,
9409 #[doc = "MSIK clock selected"]
9410 MSIK = 0x04,
9411 _RESERVED_5 = 0x05,
9412 _RESERVED_6 = 0x06,
9413 _RESERVED_7 = 0x07,
9414 }
9415 impl Mdfsel {
9416 #[inline(always)]
9417 pub const fn from_bits(val: u8) -> Mdfsel {
9418 unsafe { core::mem::transmute(val & 0x07) }
9419 }
9420 #[inline(always)]
9421 pub const fn to_bits(self) -> u8 {
9422 unsafe { core::mem::transmute(self) }
9423 }
9424 }
9425 impl From<u8> for Mdfsel {
9426 #[inline(always)]
9427 fn from(val: u8) -> Mdfsel {
9428 Mdfsel::from_bits(val)
9429 }
9430 }
9431 impl From<Mdfsel> for u8 {
9432 #[inline(always)]
9433 fn from(val: Mdfsel) -> u8 {
9434 Mdfsel::to_bits(val)
9435 }
9436 }
9437 #[repr(u8)]
9438 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9439 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9440 pub enum Msibias {
9441 #[doc = "MSI bias continuous mode (clock accuracy fast settling time)"]
9442 CONTINUOUS = 0x0,
9443 #[doc = "MSI bias sampling mode (ultra-low-power mode)"]
9444 SAMPLING = 0x01,
9445 }
9446 impl Msibias {
9447 #[inline(always)]
9448 pub const fn from_bits(val: u8) -> Msibias {
9449 unsafe { core::mem::transmute(val & 0x01) }
9450 }
9451 #[inline(always)]
9452 pub const fn to_bits(self) -> u8 {
9453 unsafe { core::mem::transmute(self) }
9454 }
9455 }
9456 impl From<u8> for Msibias {
9457 #[inline(always)]
9458 fn from(val: u8) -> Msibias {
9459 Msibias::from_bits(val)
9460 }
9461 }
9462 impl From<Msibias> for u8 {
9463 #[inline(always)]
9464 fn from(val: Msibias) -> u8 {
9465 Msibias::to_bits(val)
9466 }
9467 }
9468 #[repr(u8)]
9469 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9470 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9471 pub enum Msipllfast {
9472 #[doc = "MSI PLL normal start-up"]
9473 NORMAL = 0x0,
9474 #[doc = "MSI PLL fast start-up"]
9475 FAST = 0x01,
9476 }
9477 impl Msipllfast {
9478 #[inline(always)]
9479 pub const fn from_bits(val: u8) -> Msipllfast {
9480 unsafe { core::mem::transmute(val & 0x01) }
9481 }
9482 #[inline(always)]
9483 pub const fn to_bits(self) -> u8 {
9484 unsafe { core::mem::transmute(self) }
9485 }
9486 }
9487 impl From<u8> for Msipllfast {
9488 #[inline(always)]
9489 fn from(val: u8) -> Msipllfast {
9490 Msipllfast::from_bits(val)
9491 }
9492 }
9493 impl From<Msipllfast> for u8 {
9494 #[inline(always)]
9495 fn from(val: Msipllfast) -> u8 {
9496 Msipllfast::to_bits(val)
9497 }
9498 }
9499 #[repr(u8)]
9500 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9501 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9502 pub enum Msipllsel {
9503 #[doc = "PLL mode applied to MSIK (MSI kernel) clock output"]
9504 MSIK = 0x0,
9505 #[doc = "PLL mode applied to MSIS (MSI system) clock output"]
9506 MSIS = 0x01,
9507 }
9508 impl Msipllsel {
9509 #[inline(always)]
9510 pub const fn from_bits(val: u8) -> Msipllsel {
9511 unsafe { core::mem::transmute(val & 0x01) }
9512 }
9513 #[inline(always)]
9514 pub const fn to_bits(self) -> u8 {
9515 unsafe { core::mem::transmute(self) }
9516 }
9517 }
9518 impl From<u8> for Msipllsel {
9519 #[inline(always)]
9520 fn from(val: u8) -> Msipllsel {
9521 Msipllsel::from_bits(val)
9522 }
9523 }
9524 impl From<Msipllsel> for u8 {
9525 #[inline(always)]
9526 fn from(val: Msipllsel) -> u8 {
9527 Msipllsel::to_bits(val)
9528 }
9529 }
9530 #[repr(u8)]
9531 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9532 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9533 pub enum Msirange {
9534 #[doc = "range 0 around 48 MHz"]
9535 RANGE_48MHZ = 0x0,
9536 #[doc = "range 1 around 24 MHz"]
9537 RANGE_24MHZ = 0x01,
9538 #[doc = "range 2 around 16 MHz"]
9539 RANGE_16MHZ = 0x02,
9540 #[doc = "range 3 around 12 MHz"]
9541 RANGE_12MHZ = 0x03,
9542 #[doc = "range 4 around 4 MHz (reset value)"]
9543 RANGE_4MHZ = 0x04,
9544 #[doc = "range 5 around 2 MHz"]
9545 RANGE_2MHZ = 0x05,
9546 #[doc = "range 6 around 1.33 MHz"]
9547 RANGE_1_33MHZ = 0x06,
9548 #[doc = "range 7 around 1 MHz"]
9549 RANGE_1MHZ = 0x07,
9550 #[doc = "range 8 around 3.072 MHz"]
9551 RANGE_3_072MHZ = 0x08,
9552 #[doc = "range 9 around 1.536 MHz"]
9553 RANGE_1_536MHZ = 0x09,
9554 #[doc = "range 10 around 1.024 MHz"]
9555 RANGE_1_024MHZ = 0x0a,
9556 #[doc = "range 11 around 768 kHz"]
9557 RANGE_768KHZ = 0x0b,
9558 #[doc = "range 12 around 400 kHz"]
9559 RANGE_400KHZ = 0x0c,
9560 #[doc = "range 13 around 200 kHz"]
9561 RANGE_200KHZ = 0x0d,
9562 #[doc = "range 14 around 133 kHz"]
9563 RANGE_133KHZ = 0x0e,
9564 #[doc = "range 15 around 100 kHz"]
9565 RANGE_100KHZ = 0x0f,
9566 }
9567 impl Msirange {
9568 #[inline(always)]
9569 pub const fn from_bits(val: u8) -> Msirange {
9570 unsafe { core::mem::transmute(val & 0x0f) }
9571 }
9572 #[inline(always)]
9573 pub const fn to_bits(self) -> u8 {
9574 unsafe { core::mem::transmute(self) }
9575 }
9576 }
9577 impl From<u8> for Msirange {
9578 #[inline(always)]
9579 fn from(val: u8) -> Msirange {
9580 Msirange::from_bits(val)
9581 }
9582 }
9583 impl From<Msirange> for u8 {
9584 #[inline(always)]
9585 fn from(val: Msirange) -> u8 {
9586 Msirange::to_bits(val)
9587 }
9588 }
9589 #[repr(u8)]
9590 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9591 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9592 pub enum Msirgsel {
9593 #[doc = "MSIS/MSIK ranges provided by MSISSRANGE\\[3:0\\]
9594and MSIKSRANGE\\[3:0\\]
9595in RCC_CSR"]
9596 CSR = 0x0,
9597 #[doc = "MSIS/MSIK ranges provided by MSISRANGE\\[3:0\\]
9598and MSIKRANGE\\[3:0\\]
9599in RCC_ICSCR1"]
9600 ICSCR1 = 0x01,
9601 }
9602 impl Msirgsel {
9603 #[inline(always)]
9604 pub const fn from_bits(val: u8) -> Msirgsel {
9605 unsafe { core::mem::transmute(val & 0x01) }
9606 }
9607 #[inline(always)]
9608 pub const fn to_bits(self) -> u8 {
9609 unsafe { core::mem::transmute(self) }
9610 }
9611 }
9612 impl From<u8> for Msirgsel {
9613 #[inline(always)]
9614 fn from(val: u8) -> Msirgsel {
9615 Msirgsel::from_bits(val)
9616 }
9617 }
9618 impl From<Msirgsel> for u8 {
9619 #[inline(always)]
9620 fn from(val: Msirgsel) -> u8 {
9621 Msirgsel::to_bits(val)
9622 }
9623 }
9624 #[repr(u8)]
9625 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9626 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9627 pub enum Msixsrange {
9628 _RESERVED_0 = 0x0,
9629 _RESERVED_1 = 0x01,
9630 _RESERVED_2 = 0x02,
9631 _RESERVED_3 = 0x03,
9632 #[doc = "range 4 around 4M Hz (reset value)"]
9633 RANGE_4MHZ = 0x04,
9634 #[doc = "range 5 around 2 MHz"]
9635 RANGE_2MHZ = 0x05,
9636 #[doc = "range 6 around 1.5 MHz"]
9637 RANGE_1_5MHZ = 0x06,
9638 #[doc = "range 7 around 1 MHz"]
9639 RANGE_1MHZ = 0x07,
9640 #[doc = "range 8 around 3.072 MHz"]
9641 RANGE_3_072MHZ = 0x08,
9642 _RESERVED_9 = 0x09,
9643 _RESERVED_a = 0x0a,
9644 _RESERVED_b = 0x0b,
9645 _RESERVED_c = 0x0c,
9646 _RESERVED_d = 0x0d,
9647 _RESERVED_e = 0x0e,
9648 _RESERVED_f = 0x0f,
9649 }
9650 impl Msixsrange {
9651 #[inline(always)]
9652 pub const fn from_bits(val: u8) -> Msixsrange {
9653 unsafe { core::mem::transmute(val & 0x0f) }
9654 }
9655 #[inline(always)]
9656 pub const fn to_bits(self) -> u8 {
9657 unsafe { core::mem::transmute(self) }
9658 }
9659 }
9660 impl From<u8> for Msixsrange {
9661 #[inline(always)]
9662 fn from(val: u8) -> Msixsrange {
9663 Msixsrange::from_bits(val)
9664 }
9665 }
9666 impl From<Msixsrange> for u8 {
9667 #[inline(always)]
9668 fn from(val: Msixsrange) -> u8 {
9669 Msixsrange::to_bits(val)
9670 }
9671 }
9672 #[repr(u8)]
9673 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9674 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9675 pub enum Octospisel {
9676 #[doc = "SYSCLK selected"]
9677 SYS = 0x0,
9678 #[doc = "MSIK selected"]
9679 MSIK = 0x01,
9680 #[doc = "PLL1 Q (pll1_q_ck) selected, can be up to 200 MHz"]
9681 PLL1_Q = 0x02,
9682 #[doc = "PLL2 Q (pll2_q_ck) selected, can be up to 200 MHz"]
9683 PLL2_Q = 0x03,
9684 }
9685 impl Octospisel {
9686 #[inline(always)]
9687 pub const fn from_bits(val: u8) -> Octospisel {
9688 unsafe { core::mem::transmute(val & 0x03) }
9689 }
9690 #[inline(always)]
9691 pub const fn to_bits(self) -> u8 {
9692 unsafe { core::mem::transmute(self) }
9693 }
9694 }
9695 impl From<u8> for Octospisel {
9696 #[inline(always)]
9697 fn from(val: u8) -> Octospisel {
9698 Octospisel::from_bits(val)
9699 }
9700 }
9701 impl From<Octospisel> for u8 {
9702 #[inline(always)]
9703 fn from(val: Octospisel) -> u8 {
9704 Octospisel::to_bits(val)
9705 }
9706 }
9707 #[repr(u8)]
9708 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9709 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9710 pub enum Otghssel {
9711 #[doc = "HSE selected"]
9712 HSE = 0x0,
9713 #[doc = "PLL1 “P” (pll1_q_ck) selected,"]
9714 PLL1_P = 0x01,
9715 #[doc = "HSE/2 selected"]
9716 HSE_DIV_2 = 0x02,
9717 #[doc = "PLL1 “P” divided by 2 (pll1_p_ck/2) selected"]
9718 PLL1_P_DIV_2 = 0x03,
9719 }
9720 impl Otghssel {
9721 #[inline(always)]
9722 pub const fn from_bits(val: u8) -> Otghssel {
9723 unsafe { core::mem::transmute(val & 0x03) }
9724 }
9725 #[inline(always)]
9726 pub const fn to_bits(self) -> u8 {
9727 unsafe { core::mem::transmute(self) }
9728 }
9729 }
9730 impl From<u8> for Otghssel {
9731 #[inline(always)]
9732 fn from(val: u8) -> Otghssel {
9733 Otghssel::from_bits(val)
9734 }
9735 }
9736 impl From<Otghssel> for u8 {
9737 #[inline(always)]
9738 fn from(val: Otghssel) -> u8 {
9739 Otghssel::to_bits(val)
9740 }
9741 }
9742 #[repr(u8)]
9743 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9744 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9745 pub enum Plldiv {
9746 DIV1 = 0x0,
9747 DIV2 = 0x01,
9748 DIV3 = 0x02,
9749 DIV4 = 0x03,
9750 DIV5 = 0x04,
9751 DIV6 = 0x05,
9752 DIV7 = 0x06,
9753 DIV8 = 0x07,
9754 DIV9 = 0x08,
9755 DIV10 = 0x09,
9756 DIV11 = 0x0a,
9757 DIV12 = 0x0b,
9758 DIV13 = 0x0c,
9759 DIV14 = 0x0d,
9760 DIV15 = 0x0e,
9761 DIV16 = 0x0f,
9762 DIV17 = 0x10,
9763 DIV18 = 0x11,
9764 DIV19 = 0x12,
9765 DIV20 = 0x13,
9766 DIV21 = 0x14,
9767 DIV22 = 0x15,
9768 DIV23 = 0x16,
9769 DIV24 = 0x17,
9770 DIV25 = 0x18,
9771 DIV26 = 0x19,
9772 DIV27 = 0x1a,
9773 DIV28 = 0x1b,
9774 DIV29 = 0x1c,
9775 DIV30 = 0x1d,
9776 DIV31 = 0x1e,
9777 DIV32 = 0x1f,
9778 DIV33 = 0x20,
9779 DIV34 = 0x21,
9780 DIV35 = 0x22,
9781 DIV36 = 0x23,
9782 DIV37 = 0x24,
9783 DIV38 = 0x25,
9784 DIV39 = 0x26,
9785 DIV40 = 0x27,
9786 DIV41 = 0x28,
9787 DIV42 = 0x29,
9788 DIV43 = 0x2a,
9789 DIV44 = 0x2b,
9790 DIV45 = 0x2c,
9791 DIV46 = 0x2d,
9792 DIV47 = 0x2e,
9793 DIV48 = 0x2f,
9794 DIV49 = 0x30,
9795 DIV50 = 0x31,
9796 DIV51 = 0x32,
9797 DIV52 = 0x33,
9798 DIV53 = 0x34,
9799 DIV54 = 0x35,
9800 DIV55 = 0x36,
9801 DIV56 = 0x37,
9802 DIV57 = 0x38,
9803 DIV58 = 0x39,
9804 DIV59 = 0x3a,
9805 DIV60 = 0x3b,
9806 DIV61 = 0x3c,
9807 DIV62 = 0x3d,
9808 DIV63 = 0x3e,
9809 DIV64 = 0x3f,
9810 DIV65 = 0x40,
9811 DIV66 = 0x41,
9812 DIV67 = 0x42,
9813 DIV68 = 0x43,
9814 DIV69 = 0x44,
9815 DIV70 = 0x45,
9816 DIV71 = 0x46,
9817 DIV72 = 0x47,
9818 DIV73 = 0x48,
9819 DIV74 = 0x49,
9820 DIV75 = 0x4a,
9821 DIV76 = 0x4b,
9822 DIV77 = 0x4c,
9823 DIV78 = 0x4d,
9824 DIV79 = 0x4e,
9825 DIV80 = 0x4f,
9826 DIV81 = 0x50,
9827 DIV82 = 0x51,
9828 DIV83 = 0x52,
9829 DIV84 = 0x53,
9830 DIV85 = 0x54,
9831 DIV86 = 0x55,
9832 DIV87 = 0x56,
9833 DIV88 = 0x57,
9834 DIV89 = 0x58,
9835 DIV90 = 0x59,
9836 DIV91 = 0x5a,
9837 DIV92 = 0x5b,
9838 DIV93 = 0x5c,
9839 DIV94 = 0x5d,
9840 DIV95 = 0x5e,
9841 DIV96 = 0x5f,
9842 DIV97 = 0x60,
9843 DIV98 = 0x61,
9844 DIV99 = 0x62,
9845 DIV100 = 0x63,
9846 DIV101 = 0x64,
9847 DIV102 = 0x65,
9848 DIV103 = 0x66,
9849 DIV104 = 0x67,
9850 DIV105 = 0x68,
9851 DIV106 = 0x69,
9852 DIV107 = 0x6a,
9853 DIV108 = 0x6b,
9854 DIV109 = 0x6c,
9855 DIV110 = 0x6d,
9856 DIV111 = 0x6e,
9857 DIV112 = 0x6f,
9858 DIV113 = 0x70,
9859 DIV114 = 0x71,
9860 DIV115 = 0x72,
9861 DIV116 = 0x73,
9862 DIV117 = 0x74,
9863 DIV118 = 0x75,
9864 DIV119 = 0x76,
9865 DIV120 = 0x77,
9866 DIV121 = 0x78,
9867 DIV122 = 0x79,
9868 DIV123 = 0x7a,
9869 DIV124 = 0x7b,
9870 DIV125 = 0x7c,
9871 DIV126 = 0x7d,
9872 DIV127 = 0x7e,
9873 DIV128 = 0x7f,
9874 }
9875 impl Plldiv {
9876 #[inline(always)]
9877 pub const fn from_bits(val: u8) -> Plldiv {
9878 unsafe { core::mem::transmute(val & 0x7f) }
9879 }
9880 #[inline(always)]
9881 pub const fn to_bits(self) -> u8 {
9882 unsafe { core::mem::transmute(self) }
9883 }
9884 }
9885 impl From<u8> for Plldiv {
9886 #[inline(always)]
9887 fn from(val: u8) -> Plldiv {
9888 Plldiv::from_bits(val)
9889 }
9890 }
9891 impl From<Plldiv> for u8 {
9892 #[inline(always)]
9893 fn from(val: Plldiv) -> u8 {
9894 Plldiv::to_bits(val)
9895 }
9896 }
9897 #[repr(u8)]
9898 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9899 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9900 pub enum Pllm {
9901 DIV1 = 0x0,
9902 DIV2 = 0x01,
9903 DIV3 = 0x02,
9904 DIV4 = 0x03,
9905 DIV5 = 0x04,
9906 DIV6 = 0x05,
9907 DIV7 = 0x06,
9908 DIV8 = 0x07,
9909 DIV9 = 0x08,
9910 DIV10 = 0x09,
9911 DIV11 = 0x0a,
9912 DIV12 = 0x0b,
9913 DIV13 = 0x0c,
9914 DIV14 = 0x0d,
9915 DIV15 = 0x0e,
9916 DIV16 = 0x0f,
9917 }
9918 impl Pllm {
9919 #[inline(always)]
9920 pub const fn from_bits(val: u8) -> Pllm {
9921 unsafe { core::mem::transmute(val & 0x0f) }
9922 }
9923 #[inline(always)]
9924 pub const fn to_bits(self) -> u8 {
9925 unsafe { core::mem::transmute(self) }
9926 }
9927 }
9928 impl From<u8> for Pllm {
9929 #[inline(always)]
9930 fn from(val: u8) -> Pllm {
9931 Pllm::from_bits(val)
9932 }
9933 }
9934 impl From<Pllm> for u8 {
9935 #[inline(always)]
9936 fn from(val: Pllm) -> u8 {
9937 Pllm::to_bits(val)
9938 }
9939 }
9940 #[repr(u8)]
9941 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9942 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9943 pub enum Pllmboost {
9944 #[doc = "division by 1 (bypass)"]
9945 DIV1 = 0x0,
9946 #[doc = "division by 2"]
9947 DIV2 = 0x01,
9948 #[doc = "division by 4"]
9949 DIV4 = 0x02,
9950 #[doc = "division by 6"]
9951 DIV6 = 0x03,
9952 #[doc = "division by 8"]
9953 DIV8 = 0x04,
9954 #[doc = "division by 10"]
9955 DIV10 = 0x05,
9956 #[doc = "division by 12"]
9957 DIV12 = 0x06,
9958 #[doc = "division by 14"]
9959 DIV14 = 0x07,
9960 #[doc = "division by 16"]
9961 DIV16 = 0x08,
9962 _RESERVED_9 = 0x09,
9963 _RESERVED_a = 0x0a,
9964 _RESERVED_b = 0x0b,
9965 _RESERVED_c = 0x0c,
9966 _RESERVED_d = 0x0d,
9967 _RESERVED_e = 0x0e,
9968 _RESERVED_f = 0x0f,
9969 }
9970 impl Pllmboost {
9971 #[inline(always)]
9972 pub const fn from_bits(val: u8) -> Pllmboost {
9973 unsafe { core::mem::transmute(val & 0x0f) }
9974 }
9975 #[inline(always)]
9976 pub const fn to_bits(self) -> u8 {
9977 unsafe { core::mem::transmute(self) }
9978 }
9979 }
9980 impl From<u8> for Pllmboost {
9981 #[inline(always)]
9982 fn from(val: u8) -> Pllmboost {
9983 Pllmboost::from_bits(val)
9984 }
9985 }
9986 impl From<Pllmboost> for u8 {
9987 #[inline(always)]
9988 fn from(val: Pllmboost) -> u8 {
9989 Pllmboost::to_bits(val)
9990 }
9991 }
9992 #[repr(transparent)]
9993 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
9994 pub struct Plln(pub u16);
9995 impl Plln {
9996 pub const MUL4: Self = Self(0x03);
9997 pub const MUL5: Self = Self(0x04);
9998 pub const MUL6: Self = Self(0x05);
9999 pub const MUL7: Self = Self(0x06);
10000 pub const MUL8: Self = Self(0x07);
10001 pub const MUL9: Self = Self(0x08);
10002 pub const MUL10: Self = Self(0x09);
10003 pub const MUL11: Self = Self(0x0a);
10004 pub const MUL12: Self = Self(0x0b);
10005 pub const MUL13: Self = Self(0x0c);
10006 pub const MUL14: Self = Self(0x0d);
10007 pub const MUL15: Self = Self(0x0e);
10008 pub const MUL16: Self = Self(0x0f);
10009 pub const MUL17: Self = Self(0x10);
10010 pub const MUL18: Self = Self(0x11);
10011 pub const MUL19: Self = Self(0x12);
10012 pub const MUL20: Self = Self(0x13);
10013 pub const MUL21: Self = Self(0x14);
10014 pub const MUL22: Self = Self(0x15);
10015 pub const MUL23: Self = Self(0x16);
10016 pub const MUL24: Self = Self(0x17);
10017 pub const MUL25: Self = Self(0x18);
10018 pub const MUL26: Self = Self(0x19);
10019 pub const MUL27: Self = Self(0x1a);
10020 pub const MUL28: Self = Self(0x1b);
10021 pub const MUL29: Self = Self(0x1c);
10022 pub const MUL30: Self = Self(0x1d);
10023 pub const MUL31: Self = Self(0x1e);
10024 pub const MUL32: Self = Self(0x1f);
10025 pub const MUL33: Self = Self(0x20);
10026 pub const MUL34: Self = Self(0x21);
10027 pub const MUL35: Self = Self(0x22);
10028 pub const MUL36: Self = Self(0x23);
10029 pub const MUL37: Self = Self(0x24);
10030 pub const MUL38: Self = Self(0x25);
10031 pub const MUL39: Self = Self(0x26);
10032 pub const MUL40: Self = Self(0x27);
10033 pub const MUL41: Self = Self(0x28);
10034 pub const MUL42: Self = Self(0x29);
10035 pub const MUL43: Self = Self(0x2a);
10036 pub const MUL44: Self = Self(0x2b);
10037 pub const MUL45: Self = Self(0x2c);
10038 pub const MUL46: Self = Self(0x2d);
10039 pub const MUL47: Self = Self(0x2e);
10040 pub const MUL48: Self = Self(0x2f);
10041 pub const MUL49: Self = Self(0x30);
10042 pub const MUL50: Self = Self(0x31);
10043 pub const MUL51: Self = Self(0x32);
10044 pub const MUL52: Self = Self(0x33);
10045 pub const MUL53: Self = Self(0x34);
10046 pub const MUL54: Self = Self(0x35);
10047 pub const MUL55: Self = Self(0x36);
10048 pub const MUL56: Self = Self(0x37);
10049 pub const MUL57: Self = Self(0x38);
10050 pub const MUL58: Self = Self(0x39);
10051 pub const MUL59: Self = Self(0x3a);
10052 pub const MUL60: Self = Self(0x3b);
10053 pub const MUL61: Self = Self(0x3c);
10054 pub const MUL62: Self = Self(0x3d);
10055 pub const MUL63: Self = Self(0x3e);
10056 pub const MUL64: Self = Self(0x3f);
10057 pub const MUL65: Self = Self(0x40);
10058 pub const MUL66: Self = Self(0x41);
10059 pub const MUL67: Self = Self(0x42);
10060 pub const MUL68: Self = Self(0x43);
10061 pub const MUL69: Self = Self(0x44);
10062 pub const MUL70: Self = Self(0x45);
10063 pub const MUL71: Self = Self(0x46);
10064 pub const MUL72: Self = Self(0x47);
10065 pub const MUL73: Self = Self(0x48);
10066 pub const MUL74: Self = Self(0x49);
10067 pub const MUL75: Self = Self(0x4a);
10068 pub const MUL76: Self = Self(0x4b);
10069 pub const MUL77: Self = Self(0x4c);
10070 pub const MUL78: Self = Self(0x4d);
10071 pub const MUL79: Self = Self(0x4e);
10072 pub const MUL80: Self = Self(0x4f);
10073 pub const MUL81: Self = Self(0x50);
10074 pub const MUL82: Self = Self(0x51);
10075 pub const MUL83: Self = Self(0x52);
10076 pub const MUL84: Self = Self(0x53);
10077 pub const MUL85: Self = Self(0x54);
10078 pub const MUL86: Self = Self(0x55);
10079 pub const MUL87: Self = Self(0x56);
10080 pub const MUL88: Self = Self(0x57);
10081 pub const MUL89: Self = Self(0x58);
10082 pub const MUL90: Self = Self(0x59);
10083 pub const MUL91: Self = Self(0x5a);
10084 pub const MUL92: Self = Self(0x5b);
10085 pub const MUL93: Self = Self(0x5c);
10086 pub const MUL94: Self = Self(0x5d);
10087 pub const MUL95: Self = Self(0x5e);
10088 pub const MUL96: Self = Self(0x5f);
10089 pub const MUL97: Self = Self(0x60);
10090 pub const MUL98: Self = Self(0x61);
10091 pub const MUL99: Self = Self(0x62);
10092 pub const MUL100: Self = Self(0x63);
10093 pub const MUL101: Self = Self(0x64);
10094 pub const MUL102: Self = Self(0x65);
10095 pub const MUL103: Self = Self(0x66);
10096 pub const MUL104: Self = Self(0x67);
10097 pub const MUL105: Self = Self(0x68);
10098 pub const MUL106: Self = Self(0x69);
10099 pub const MUL107: Self = Self(0x6a);
10100 pub const MUL108: Self = Self(0x6b);
10101 pub const MUL109: Self = Self(0x6c);
10102 pub const MUL110: Self = Self(0x6d);
10103 pub const MUL111: Self = Self(0x6e);
10104 pub const MUL112: Self = Self(0x6f);
10105 pub const MUL113: Self = Self(0x70);
10106 pub const MUL114: Self = Self(0x71);
10107 pub const MUL115: Self = Self(0x72);
10108 pub const MUL116: Self = Self(0x73);
10109 pub const MUL117: Self = Self(0x74);
10110 pub const MUL118: Self = Self(0x75);
10111 pub const MUL119: Self = Self(0x76);
10112 pub const MUL120: Self = Self(0x77);
10113 pub const MUL121: Self = Self(0x78);
10114 pub const MUL122: Self = Self(0x79);
10115 pub const MUL123: Self = Self(0x7a);
10116 pub const MUL124: Self = Self(0x7b);
10117 pub const MUL125: Self = Self(0x7c);
10118 pub const MUL126: Self = Self(0x7d);
10119 pub const MUL127: Self = Self(0x7e);
10120 pub const MUL128: Self = Self(0x7f);
10121 pub const MUL129: Self = Self(0x80);
10122 pub const MUL130: Self = Self(0x81);
10123 pub const MUL131: Self = Self(0x82);
10124 pub const MUL132: Self = Self(0x83);
10125 pub const MUL133: Self = Self(0x84);
10126 pub const MUL134: Self = Self(0x85);
10127 pub const MUL135: Self = Self(0x86);
10128 pub const MUL136: Self = Self(0x87);
10129 pub const MUL137: Self = Self(0x88);
10130 pub const MUL138: Self = Self(0x89);
10131 pub const MUL139: Self = Self(0x8a);
10132 pub const MUL140: Self = Self(0x8b);
10133 pub const MUL141: Self = Self(0x8c);
10134 pub const MUL142: Self = Self(0x8d);
10135 pub const MUL143: Self = Self(0x8e);
10136 pub const MUL144: Self = Self(0x8f);
10137 pub const MUL145: Self = Self(0x90);
10138 pub const MUL146: Self = Self(0x91);
10139 pub const MUL147: Self = Self(0x92);
10140 pub const MUL148: Self = Self(0x93);
10141 pub const MUL149: Self = Self(0x94);
10142 pub const MUL150: Self = Self(0x95);
10143 pub const MUL151: Self = Self(0x96);
10144 pub const MUL152: Self = Self(0x97);
10145 pub const MUL153: Self = Self(0x98);
10146 pub const MUL154: Self = Self(0x99);
10147 pub const MUL155: Self = Self(0x9a);
10148 pub const MUL156: Self = Self(0x9b);
10149 pub const MUL157: Self = Self(0x9c);
10150 pub const MUL158: Self = Self(0x9d);
10151 pub const MUL159: Self = Self(0x9e);
10152 pub const MUL160: Self = Self(0x9f);
10153 pub const MUL161: Self = Self(0xa0);
10154 pub const MUL162: Self = Self(0xa1);
10155 pub const MUL163: Self = Self(0xa2);
10156 pub const MUL164: Self = Self(0xa3);
10157 pub const MUL165: Self = Self(0xa4);
10158 pub const MUL166: Self = Self(0xa5);
10159 pub const MUL167: Self = Self(0xa6);
10160 pub const MUL168: Self = Self(0xa7);
10161 pub const MUL169: Self = Self(0xa8);
10162 pub const MUL170: Self = Self(0xa9);
10163 pub const MUL171: Self = Self(0xaa);
10164 pub const MUL172: Self = Self(0xab);
10165 pub const MUL173: Self = Self(0xac);
10166 pub const MUL174: Self = Self(0xad);
10167 pub const MUL175: Self = Self(0xae);
10168 pub const MUL176: Self = Self(0xaf);
10169 pub const MUL177: Self = Self(0xb0);
10170 pub const MUL178: Self = Self(0xb1);
10171 pub const MUL179: Self = Self(0xb2);
10172 pub const MUL180: Self = Self(0xb3);
10173 pub const MUL181: Self = Self(0xb4);
10174 pub const MUL182: Self = Self(0xb5);
10175 pub const MUL183: Self = Self(0xb6);
10176 pub const MUL184: Self = Self(0xb7);
10177 pub const MUL185: Self = Self(0xb8);
10178 pub const MUL186: Self = Self(0xb9);
10179 pub const MUL187: Self = Self(0xba);
10180 pub const MUL188: Self = Self(0xbb);
10181 pub const MUL189: Self = Self(0xbc);
10182 pub const MUL190: Self = Self(0xbd);
10183 pub const MUL191: Self = Self(0xbe);
10184 pub const MUL192: Self = Self(0xbf);
10185 pub const MUL193: Self = Self(0xc0);
10186 pub const MUL194: Self = Self(0xc1);
10187 pub const MUL195: Self = Self(0xc2);
10188 pub const MUL196: Self = Self(0xc3);
10189 pub const MUL197: Self = Self(0xc4);
10190 pub const MUL198: Self = Self(0xc5);
10191 pub const MUL199: Self = Self(0xc6);
10192 pub const MUL200: Self = Self(0xc7);
10193 pub const MUL201: Self = Self(0xc8);
10194 pub const MUL202: Self = Self(0xc9);
10195 pub const MUL203: Self = Self(0xca);
10196 pub const MUL204: Self = Self(0xcb);
10197 pub const MUL205: Self = Self(0xcc);
10198 pub const MUL206: Self = Self(0xcd);
10199 pub const MUL207: Self = Self(0xce);
10200 pub const MUL208: Self = Self(0xcf);
10201 pub const MUL209: Self = Self(0xd0);
10202 pub const MUL210: Self = Self(0xd1);
10203 pub const MUL211: Self = Self(0xd2);
10204 pub const MUL212: Self = Self(0xd3);
10205 pub const MUL213: Self = Self(0xd4);
10206 pub const MUL214: Self = Self(0xd5);
10207 pub const MUL215: Self = Self(0xd6);
10208 pub const MUL216: Self = Self(0xd7);
10209 pub const MUL217: Self = Self(0xd8);
10210 pub const MUL218: Self = Self(0xd9);
10211 pub const MUL219: Self = Self(0xda);
10212 pub const MUL220: Self = Self(0xdb);
10213 pub const MUL221: Self = Self(0xdc);
10214 pub const MUL222: Self = Self(0xdd);
10215 pub const MUL223: Self = Self(0xde);
10216 pub const MUL224: Self = Self(0xdf);
10217 pub const MUL225: Self = Self(0xe0);
10218 pub const MUL226: Self = Self(0xe1);
10219 pub const MUL227: Self = Self(0xe2);
10220 pub const MUL228: Self = Self(0xe3);
10221 pub const MUL229: Self = Self(0xe4);
10222 pub const MUL230: Self = Self(0xe5);
10223 pub const MUL231: Self = Self(0xe6);
10224 pub const MUL232: Self = Self(0xe7);
10225 pub const MUL233: Self = Self(0xe8);
10226 pub const MUL234: Self = Self(0xe9);
10227 pub const MUL235: Self = Self(0xea);
10228 pub const MUL236: Self = Self(0xeb);
10229 pub const MUL237: Self = Self(0xec);
10230 pub const MUL238: Self = Self(0xed);
10231 pub const MUL239: Self = Self(0xee);
10232 pub const MUL240: Self = Self(0xef);
10233 pub const MUL241: Self = Self(0xf0);
10234 pub const MUL242: Self = Self(0xf1);
10235 pub const MUL243: Self = Self(0xf2);
10236 pub const MUL244: Self = Self(0xf3);
10237 pub const MUL245: Self = Self(0xf4);
10238 pub const MUL246: Self = Self(0xf5);
10239 pub const MUL247: Self = Self(0xf6);
10240 pub const MUL248: Self = Self(0xf7);
10241 pub const MUL249: Self = Self(0xf8);
10242 pub const MUL250: Self = Self(0xf9);
10243 pub const MUL251: Self = Self(0xfa);
10244 pub const MUL252: Self = Self(0xfb);
10245 pub const MUL253: Self = Self(0xfc);
10246 pub const MUL254: Self = Self(0xfd);
10247 pub const MUL255: Self = Self(0xfe);
10248 pub const MUL256: Self = Self(0xff);
10249 pub const MUL257: Self = Self(0x0100);
10250 pub const MUL258: Self = Self(0x0101);
10251 pub const MUL259: Self = Self(0x0102);
10252 pub const MUL260: Self = Self(0x0103);
10253 pub const MUL261: Self = Self(0x0104);
10254 pub const MUL262: Self = Self(0x0105);
10255 pub const MUL263: Self = Self(0x0106);
10256 pub const MUL264: Self = Self(0x0107);
10257 pub const MUL265: Self = Self(0x0108);
10258 pub const MUL266: Self = Self(0x0109);
10259 pub const MUL267: Self = Self(0x010a);
10260 pub const MUL268: Self = Self(0x010b);
10261 pub const MUL269: Self = Self(0x010c);
10262 pub const MUL270: Self = Self(0x010d);
10263 pub const MUL271: Self = Self(0x010e);
10264 pub const MUL272: Self = Self(0x010f);
10265 pub const MUL273: Self = Self(0x0110);
10266 pub const MUL274: Self = Self(0x0111);
10267 pub const MUL275: Self = Self(0x0112);
10268 pub const MUL276: Self = Self(0x0113);
10269 pub const MUL277: Self = Self(0x0114);
10270 pub const MUL278: Self = Self(0x0115);
10271 pub const MUL279: Self = Self(0x0116);
10272 pub const MUL280: Self = Self(0x0117);
10273 pub const MUL281: Self = Self(0x0118);
10274 pub const MUL282: Self = Self(0x0119);
10275 pub const MUL283: Self = Self(0x011a);
10276 pub const MUL284: Self = Self(0x011b);
10277 pub const MUL285: Self = Self(0x011c);
10278 pub const MUL286: Self = Self(0x011d);
10279 pub const MUL287: Self = Self(0x011e);
10280 pub const MUL288: Self = Self(0x011f);
10281 pub const MUL289: Self = Self(0x0120);
10282 pub const MUL290: Self = Self(0x0121);
10283 pub const MUL291: Self = Self(0x0122);
10284 pub const MUL292: Self = Self(0x0123);
10285 pub const MUL293: Self = Self(0x0124);
10286 pub const MUL294: Self = Self(0x0125);
10287 pub const MUL295: Self = Self(0x0126);
10288 pub const MUL296: Self = Self(0x0127);
10289 pub const MUL297: Self = Self(0x0128);
10290 pub const MUL298: Self = Self(0x0129);
10291 pub const MUL299: Self = Self(0x012a);
10292 pub const MUL300: Self = Self(0x012b);
10293 pub const MUL301: Self = Self(0x012c);
10294 pub const MUL302: Self = Self(0x012d);
10295 pub const MUL303: Self = Self(0x012e);
10296 pub const MUL304: Self = Self(0x012f);
10297 pub const MUL305: Self = Self(0x0130);
10298 pub const MUL306: Self = Self(0x0131);
10299 pub const MUL307: Self = Self(0x0132);
10300 pub const MUL308: Self = Self(0x0133);
10301 pub const MUL309: Self = Self(0x0134);
10302 pub const MUL310: Self = Self(0x0135);
10303 pub const MUL311: Self = Self(0x0136);
10304 pub const MUL312: Self = Self(0x0137);
10305 pub const MUL313: Self = Self(0x0138);
10306 pub const MUL314: Self = Self(0x0139);
10307 pub const MUL315: Self = Self(0x013a);
10308 pub const MUL316: Self = Self(0x013b);
10309 pub const MUL317: Self = Self(0x013c);
10310 pub const MUL318: Self = Self(0x013d);
10311 pub const MUL319: Self = Self(0x013e);
10312 pub const MUL320: Self = Self(0x013f);
10313 pub const MUL321: Self = Self(0x0140);
10314 pub const MUL322: Self = Self(0x0141);
10315 pub const MUL323: Self = Self(0x0142);
10316 pub const MUL324: Self = Self(0x0143);
10317 pub const MUL325: Self = Self(0x0144);
10318 pub const MUL326: Self = Self(0x0145);
10319 pub const MUL327: Self = Self(0x0146);
10320 pub const MUL328: Self = Self(0x0147);
10321 pub const MUL329: Self = Self(0x0148);
10322 pub const MUL330: Self = Self(0x0149);
10323 pub const MUL331: Self = Self(0x014a);
10324 pub const MUL332: Self = Self(0x014b);
10325 pub const MUL333: Self = Self(0x014c);
10326 pub const MUL334: Self = Self(0x014d);
10327 pub const MUL335: Self = Self(0x014e);
10328 pub const MUL336: Self = Self(0x014f);
10329 pub const MUL337: Self = Self(0x0150);
10330 pub const MUL338: Self = Self(0x0151);
10331 pub const MUL339: Self = Self(0x0152);
10332 pub const MUL340: Self = Self(0x0153);
10333 pub const MUL341: Self = Self(0x0154);
10334 pub const MUL342: Self = Self(0x0155);
10335 pub const MUL343: Self = Self(0x0156);
10336 pub const MUL344: Self = Self(0x0157);
10337 pub const MUL345: Self = Self(0x0158);
10338 pub const MUL346: Self = Self(0x0159);
10339 pub const MUL347: Self = Self(0x015a);
10340 pub const MUL348: Self = Self(0x015b);
10341 pub const MUL349: Self = Self(0x015c);
10342 pub const MUL350: Self = Self(0x015d);
10343 pub const MUL351: Self = Self(0x015e);
10344 pub const MUL352: Self = Self(0x015f);
10345 pub const MUL353: Self = Self(0x0160);
10346 pub const MUL354: Self = Self(0x0161);
10347 pub const MUL355: Self = Self(0x0162);
10348 pub const MUL356: Self = Self(0x0163);
10349 pub const MUL357: Self = Self(0x0164);
10350 pub const MUL358: Self = Self(0x0165);
10351 pub const MUL359: Self = Self(0x0166);
10352 pub const MUL360: Self = Self(0x0167);
10353 pub const MUL361: Self = Self(0x0168);
10354 pub const MUL362: Self = Self(0x0169);
10355 pub const MUL363: Self = Self(0x016a);
10356 pub const MUL364: Self = Self(0x016b);
10357 pub const MUL365: Self = Self(0x016c);
10358 pub const MUL366: Self = Self(0x016d);
10359 pub const MUL367: Self = Self(0x016e);
10360 pub const MUL368: Self = Self(0x016f);
10361 pub const MUL369: Self = Self(0x0170);
10362 pub const MUL370: Self = Self(0x0171);
10363 pub const MUL371: Self = Self(0x0172);
10364 pub const MUL372: Self = Self(0x0173);
10365 pub const MUL373: Self = Self(0x0174);
10366 pub const MUL374: Self = Self(0x0175);
10367 pub const MUL375: Self = Self(0x0176);
10368 pub const MUL376: Self = Self(0x0177);
10369 pub const MUL377: Self = Self(0x0178);
10370 pub const MUL378: Self = Self(0x0179);
10371 pub const MUL379: Self = Self(0x017a);
10372 pub const MUL380: Self = Self(0x017b);
10373 pub const MUL381: Self = Self(0x017c);
10374 pub const MUL382: Self = Self(0x017d);
10375 pub const MUL383: Self = Self(0x017e);
10376 pub const MUL384: Self = Self(0x017f);
10377 pub const MUL385: Self = Self(0x0180);
10378 pub const MUL386: Self = Self(0x0181);
10379 pub const MUL387: Self = Self(0x0182);
10380 pub const MUL388: Self = Self(0x0183);
10381 pub const MUL389: Self = Self(0x0184);
10382 pub const MUL390: Self = Self(0x0185);
10383 pub const MUL391: Self = Self(0x0186);
10384 pub const MUL392: Self = Self(0x0187);
10385 pub const MUL393: Self = Self(0x0188);
10386 pub const MUL394: Self = Self(0x0189);
10387 pub const MUL395: Self = Self(0x018a);
10388 pub const MUL396: Self = Self(0x018b);
10389 pub const MUL397: Self = Self(0x018c);
10390 pub const MUL398: Self = Self(0x018d);
10391 pub const MUL399: Self = Self(0x018e);
10392 pub const MUL400: Self = Self(0x018f);
10393 pub const MUL401: Self = Self(0x0190);
10394 pub const MUL402: Self = Self(0x0191);
10395 pub const MUL403: Self = Self(0x0192);
10396 pub const MUL404: Self = Self(0x0193);
10397 pub const MUL405: Self = Self(0x0194);
10398 pub const MUL406: Self = Self(0x0195);
10399 pub const MUL407: Self = Self(0x0196);
10400 pub const MUL408: Self = Self(0x0197);
10401 pub const MUL409: Self = Self(0x0198);
10402 pub const MUL410: Self = Self(0x0199);
10403 pub const MUL411: Self = Self(0x019a);
10404 pub const MUL412: Self = Self(0x019b);
10405 pub const MUL413: Self = Self(0x019c);
10406 pub const MUL414: Self = Self(0x019d);
10407 pub const MUL415: Self = Self(0x019e);
10408 pub const MUL416: Self = Self(0x019f);
10409 pub const MUL417: Self = Self(0x01a0);
10410 pub const MUL418: Self = Self(0x01a1);
10411 pub const MUL419: Self = Self(0x01a2);
10412 pub const MUL420: Self = Self(0x01a3);
10413 pub const MUL421: Self = Self(0x01a4);
10414 pub const MUL422: Self = Self(0x01a5);
10415 pub const MUL423: Self = Self(0x01a6);
10416 pub const MUL424: Self = Self(0x01a7);
10417 pub const MUL425: Self = Self(0x01a8);
10418 pub const MUL426: Self = Self(0x01a9);
10419 pub const MUL427: Self = Self(0x01aa);
10420 pub const MUL428: Self = Self(0x01ab);
10421 pub const MUL429: Self = Self(0x01ac);
10422 pub const MUL430: Self = Self(0x01ad);
10423 pub const MUL431: Self = Self(0x01ae);
10424 pub const MUL432: Self = Self(0x01af);
10425 pub const MUL433: Self = Self(0x01b0);
10426 pub const MUL434: Self = Self(0x01b1);
10427 pub const MUL435: Self = Self(0x01b2);
10428 pub const MUL436: Self = Self(0x01b3);
10429 pub const MUL437: Self = Self(0x01b4);
10430 pub const MUL438: Self = Self(0x01b5);
10431 pub const MUL439: Self = Self(0x01b6);
10432 pub const MUL440: Self = Self(0x01b7);
10433 pub const MUL441: Self = Self(0x01b8);
10434 pub const MUL442: Self = Self(0x01b9);
10435 pub const MUL443: Self = Self(0x01ba);
10436 pub const MUL444: Self = Self(0x01bb);
10437 pub const MUL445: Self = Self(0x01bc);
10438 pub const MUL446: Self = Self(0x01bd);
10439 pub const MUL447: Self = Self(0x01be);
10440 pub const MUL448: Self = Self(0x01bf);
10441 pub const MUL449: Self = Self(0x01c0);
10442 pub const MUL450: Self = Self(0x01c1);
10443 pub const MUL451: Self = Self(0x01c2);
10444 pub const MUL452: Self = Self(0x01c3);
10445 pub const MUL453: Self = Self(0x01c4);
10446 pub const MUL454: Self = Self(0x01c5);
10447 pub const MUL455: Self = Self(0x01c6);
10448 pub const MUL456: Self = Self(0x01c7);
10449 pub const MUL457: Self = Self(0x01c8);
10450 pub const MUL458: Self = Self(0x01c9);
10451 pub const MUL459: Self = Self(0x01ca);
10452 pub const MUL460: Self = Self(0x01cb);
10453 pub const MUL461: Self = Self(0x01cc);
10454 pub const MUL462: Self = Self(0x01cd);
10455 pub const MUL463: Self = Self(0x01ce);
10456 pub const MUL464: Self = Self(0x01cf);
10457 pub const MUL465: Self = Self(0x01d0);
10458 pub const MUL466: Self = Self(0x01d1);
10459 pub const MUL467: Self = Self(0x01d2);
10460 pub const MUL468: Self = Self(0x01d3);
10461 pub const MUL469: Self = Self(0x01d4);
10462 pub const MUL470: Self = Self(0x01d5);
10463 pub const MUL471: Self = Self(0x01d6);
10464 pub const MUL472: Self = Self(0x01d7);
10465 pub const MUL473: Self = Self(0x01d8);
10466 pub const MUL474: Self = Self(0x01d9);
10467 pub const MUL475: Self = Self(0x01da);
10468 pub const MUL476: Self = Self(0x01db);
10469 pub const MUL477: Self = Self(0x01dc);
10470 pub const MUL478: Self = Self(0x01dd);
10471 pub const MUL479: Self = Self(0x01de);
10472 pub const MUL480: Self = Self(0x01df);
10473 pub const MUL481: Self = Self(0x01e0);
10474 pub const MUL482: Self = Self(0x01e1);
10475 pub const MUL483: Self = Self(0x01e2);
10476 pub const MUL484: Self = Self(0x01e3);
10477 pub const MUL485: Self = Self(0x01e4);
10478 pub const MUL486: Self = Self(0x01e5);
10479 pub const MUL487: Self = Self(0x01e6);
10480 pub const MUL488: Self = Self(0x01e7);
10481 pub const MUL489: Self = Self(0x01e8);
10482 pub const MUL490: Self = Self(0x01e9);
10483 pub const MUL491: Self = Self(0x01ea);
10484 pub const MUL492: Self = Self(0x01eb);
10485 pub const MUL493: Self = Self(0x01ec);
10486 pub const MUL494: Self = Self(0x01ed);
10487 pub const MUL495: Self = Self(0x01ee);
10488 pub const MUL496: Self = Self(0x01ef);
10489 pub const MUL497: Self = Self(0x01f0);
10490 pub const MUL498: Self = Self(0x01f1);
10491 pub const MUL499: Self = Self(0x01f2);
10492 pub const MUL500: Self = Self(0x01f3);
10493 pub const MUL501: Self = Self(0x01f4);
10494 pub const MUL502: Self = Self(0x01f5);
10495 pub const MUL503: Self = Self(0x01f6);
10496 pub const MUL504: Self = Self(0x01f7);
10497 pub const MUL505: Self = Self(0x01f8);
10498 pub const MUL506: Self = Self(0x01f9);
10499 pub const MUL507: Self = Self(0x01fa);
10500 pub const MUL508: Self = Self(0x01fb);
10501 pub const MUL509: Self = Self(0x01fc);
10502 pub const MUL510: Self = Self(0x01fd);
10503 pub const MUL511: Self = Self(0x01fe);
10504 pub const MUL512: Self = Self(0x01ff);
10505 }
10506 impl Plln {
10507 pub const fn from_bits(val: u16) -> Plln {
10508 Self(val & 0x01ff)
10509 }
10510 pub const fn to_bits(self) -> u16 {
10511 self.0
10512 }
10513 }
10514 impl core::fmt::Debug for Plln {
10515 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
10516 match self.0 {
10517 0x03 => f.write_str("MUL4"),
10518 0x04 => f.write_str("MUL5"),
10519 0x05 => f.write_str("MUL6"),
10520 0x06 => f.write_str("MUL7"),
10521 0x07 => f.write_str("MUL8"),
10522 0x08 => f.write_str("MUL9"),
10523 0x09 => f.write_str("MUL10"),
10524 0x0a => f.write_str("MUL11"),
10525 0x0b => f.write_str("MUL12"),
10526 0x0c => f.write_str("MUL13"),
10527 0x0d => f.write_str("MUL14"),
10528 0x0e => f.write_str("MUL15"),
10529 0x0f => f.write_str("MUL16"),
10530 0x10 => f.write_str("MUL17"),
10531 0x11 => f.write_str("MUL18"),
10532 0x12 => f.write_str("MUL19"),
10533 0x13 => f.write_str("MUL20"),
10534 0x14 => f.write_str("MUL21"),
10535 0x15 => f.write_str("MUL22"),
10536 0x16 => f.write_str("MUL23"),
10537 0x17 => f.write_str("MUL24"),
10538 0x18 => f.write_str("MUL25"),
10539 0x19 => f.write_str("MUL26"),
10540 0x1a => f.write_str("MUL27"),
10541 0x1b => f.write_str("MUL28"),
10542 0x1c => f.write_str("MUL29"),
10543 0x1d => f.write_str("MUL30"),
10544 0x1e => f.write_str("MUL31"),
10545 0x1f => f.write_str("MUL32"),
10546 0x20 => f.write_str("MUL33"),
10547 0x21 => f.write_str("MUL34"),
10548 0x22 => f.write_str("MUL35"),
10549 0x23 => f.write_str("MUL36"),
10550 0x24 => f.write_str("MUL37"),
10551 0x25 => f.write_str("MUL38"),
10552 0x26 => f.write_str("MUL39"),
10553 0x27 => f.write_str("MUL40"),
10554 0x28 => f.write_str("MUL41"),
10555 0x29 => f.write_str("MUL42"),
10556 0x2a => f.write_str("MUL43"),
10557 0x2b => f.write_str("MUL44"),
10558 0x2c => f.write_str("MUL45"),
10559 0x2d => f.write_str("MUL46"),
10560 0x2e => f.write_str("MUL47"),
10561 0x2f => f.write_str("MUL48"),
10562 0x30 => f.write_str("MUL49"),
10563 0x31 => f.write_str("MUL50"),
10564 0x32 => f.write_str("MUL51"),
10565 0x33 => f.write_str("MUL52"),
10566 0x34 => f.write_str("MUL53"),
10567 0x35 => f.write_str("MUL54"),
10568 0x36 => f.write_str("MUL55"),
10569 0x37 => f.write_str("MUL56"),
10570 0x38 => f.write_str("MUL57"),
10571 0x39 => f.write_str("MUL58"),
10572 0x3a => f.write_str("MUL59"),
10573 0x3b => f.write_str("MUL60"),
10574 0x3c => f.write_str("MUL61"),
10575 0x3d => f.write_str("MUL62"),
10576 0x3e => f.write_str("MUL63"),
10577 0x3f => f.write_str("MUL64"),
10578 0x40 => f.write_str("MUL65"),
10579 0x41 => f.write_str("MUL66"),
10580 0x42 => f.write_str("MUL67"),
10581 0x43 => f.write_str("MUL68"),
10582 0x44 => f.write_str("MUL69"),
10583 0x45 => f.write_str("MUL70"),
10584 0x46 => f.write_str("MUL71"),
10585 0x47 => f.write_str("MUL72"),
10586 0x48 => f.write_str("MUL73"),
10587 0x49 => f.write_str("MUL74"),
10588 0x4a => f.write_str("MUL75"),
10589 0x4b => f.write_str("MUL76"),
10590 0x4c => f.write_str("MUL77"),
10591 0x4d => f.write_str("MUL78"),
10592 0x4e => f.write_str("MUL79"),
10593 0x4f => f.write_str("MUL80"),
10594 0x50 => f.write_str("MUL81"),
10595 0x51 => f.write_str("MUL82"),
10596 0x52 => f.write_str("MUL83"),
10597 0x53 => f.write_str("MUL84"),
10598 0x54 => f.write_str("MUL85"),
10599 0x55 => f.write_str("MUL86"),
10600 0x56 => f.write_str("MUL87"),
10601 0x57 => f.write_str("MUL88"),
10602 0x58 => f.write_str("MUL89"),
10603 0x59 => f.write_str("MUL90"),
10604 0x5a => f.write_str("MUL91"),
10605 0x5b => f.write_str("MUL92"),
10606 0x5c => f.write_str("MUL93"),
10607 0x5d => f.write_str("MUL94"),
10608 0x5e => f.write_str("MUL95"),
10609 0x5f => f.write_str("MUL96"),
10610 0x60 => f.write_str("MUL97"),
10611 0x61 => f.write_str("MUL98"),
10612 0x62 => f.write_str("MUL99"),
10613 0x63 => f.write_str("MUL100"),
10614 0x64 => f.write_str("MUL101"),
10615 0x65 => f.write_str("MUL102"),
10616 0x66 => f.write_str("MUL103"),
10617 0x67 => f.write_str("MUL104"),
10618 0x68 => f.write_str("MUL105"),
10619 0x69 => f.write_str("MUL106"),
10620 0x6a => f.write_str("MUL107"),
10621 0x6b => f.write_str("MUL108"),
10622 0x6c => f.write_str("MUL109"),
10623 0x6d => f.write_str("MUL110"),
10624 0x6e => f.write_str("MUL111"),
10625 0x6f => f.write_str("MUL112"),
10626 0x70 => f.write_str("MUL113"),
10627 0x71 => f.write_str("MUL114"),
10628 0x72 => f.write_str("MUL115"),
10629 0x73 => f.write_str("MUL116"),
10630 0x74 => f.write_str("MUL117"),
10631 0x75 => f.write_str("MUL118"),
10632 0x76 => f.write_str("MUL119"),
10633 0x77 => f.write_str("MUL120"),
10634 0x78 => f.write_str("MUL121"),
10635 0x79 => f.write_str("MUL122"),
10636 0x7a => f.write_str("MUL123"),
10637 0x7b => f.write_str("MUL124"),
10638 0x7c => f.write_str("MUL125"),
10639 0x7d => f.write_str("MUL126"),
10640 0x7e => f.write_str("MUL127"),
10641 0x7f => f.write_str("MUL128"),
10642 0x80 => f.write_str("MUL129"),
10643 0x81 => f.write_str("MUL130"),
10644 0x82 => f.write_str("MUL131"),
10645 0x83 => f.write_str("MUL132"),
10646 0x84 => f.write_str("MUL133"),
10647 0x85 => f.write_str("MUL134"),
10648 0x86 => f.write_str("MUL135"),
10649 0x87 => f.write_str("MUL136"),
10650 0x88 => f.write_str("MUL137"),
10651 0x89 => f.write_str("MUL138"),
10652 0x8a => f.write_str("MUL139"),
10653 0x8b => f.write_str("MUL140"),
10654 0x8c => f.write_str("MUL141"),
10655 0x8d => f.write_str("MUL142"),
10656 0x8e => f.write_str("MUL143"),
10657 0x8f => f.write_str("MUL144"),
10658 0x90 => f.write_str("MUL145"),
10659 0x91 => f.write_str("MUL146"),
10660 0x92 => f.write_str("MUL147"),
10661 0x93 => f.write_str("MUL148"),
10662 0x94 => f.write_str("MUL149"),
10663 0x95 => f.write_str("MUL150"),
10664 0x96 => f.write_str("MUL151"),
10665 0x97 => f.write_str("MUL152"),
10666 0x98 => f.write_str("MUL153"),
10667 0x99 => f.write_str("MUL154"),
10668 0x9a => f.write_str("MUL155"),
10669 0x9b => f.write_str("MUL156"),
10670 0x9c => f.write_str("MUL157"),
10671 0x9d => f.write_str("MUL158"),
10672 0x9e => f.write_str("MUL159"),
10673 0x9f => f.write_str("MUL160"),
10674 0xa0 => f.write_str("MUL161"),
10675 0xa1 => f.write_str("MUL162"),
10676 0xa2 => f.write_str("MUL163"),
10677 0xa3 => f.write_str("MUL164"),
10678 0xa4 => f.write_str("MUL165"),
10679 0xa5 => f.write_str("MUL166"),
10680 0xa6 => f.write_str("MUL167"),
10681 0xa7 => f.write_str("MUL168"),
10682 0xa8 => f.write_str("MUL169"),
10683 0xa9 => f.write_str("MUL170"),
10684 0xaa => f.write_str("MUL171"),
10685 0xab => f.write_str("MUL172"),
10686 0xac => f.write_str("MUL173"),
10687 0xad => f.write_str("MUL174"),
10688 0xae => f.write_str("MUL175"),
10689 0xaf => f.write_str("MUL176"),
10690 0xb0 => f.write_str("MUL177"),
10691 0xb1 => f.write_str("MUL178"),
10692 0xb2 => f.write_str("MUL179"),
10693 0xb3 => f.write_str("MUL180"),
10694 0xb4 => f.write_str("MUL181"),
10695 0xb5 => f.write_str("MUL182"),
10696 0xb6 => f.write_str("MUL183"),
10697 0xb7 => f.write_str("MUL184"),
10698 0xb8 => f.write_str("MUL185"),
10699 0xb9 => f.write_str("MUL186"),
10700 0xba => f.write_str("MUL187"),
10701 0xbb => f.write_str("MUL188"),
10702 0xbc => f.write_str("MUL189"),
10703 0xbd => f.write_str("MUL190"),
10704 0xbe => f.write_str("MUL191"),
10705 0xbf => f.write_str("MUL192"),
10706 0xc0 => f.write_str("MUL193"),
10707 0xc1 => f.write_str("MUL194"),
10708 0xc2 => f.write_str("MUL195"),
10709 0xc3 => f.write_str("MUL196"),
10710 0xc4 => f.write_str("MUL197"),
10711 0xc5 => f.write_str("MUL198"),
10712 0xc6 => f.write_str("MUL199"),
10713 0xc7 => f.write_str("MUL200"),
10714 0xc8 => f.write_str("MUL201"),
10715 0xc9 => f.write_str("MUL202"),
10716 0xca => f.write_str("MUL203"),
10717 0xcb => f.write_str("MUL204"),
10718 0xcc => f.write_str("MUL205"),
10719 0xcd => f.write_str("MUL206"),
10720 0xce => f.write_str("MUL207"),
10721 0xcf => f.write_str("MUL208"),
10722 0xd0 => f.write_str("MUL209"),
10723 0xd1 => f.write_str("MUL210"),
10724 0xd2 => f.write_str("MUL211"),
10725 0xd3 => f.write_str("MUL212"),
10726 0xd4 => f.write_str("MUL213"),
10727 0xd5 => f.write_str("MUL214"),
10728 0xd6 => f.write_str("MUL215"),
10729 0xd7 => f.write_str("MUL216"),
10730 0xd8 => f.write_str("MUL217"),
10731 0xd9 => f.write_str("MUL218"),
10732 0xda => f.write_str("MUL219"),
10733 0xdb => f.write_str("MUL220"),
10734 0xdc => f.write_str("MUL221"),
10735 0xdd => f.write_str("MUL222"),
10736 0xde => f.write_str("MUL223"),
10737 0xdf => f.write_str("MUL224"),
10738 0xe0 => f.write_str("MUL225"),
10739 0xe1 => f.write_str("MUL226"),
10740 0xe2 => f.write_str("MUL227"),
10741 0xe3 => f.write_str("MUL228"),
10742 0xe4 => f.write_str("MUL229"),
10743 0xe5 => f.write_str("MUL230"),
10744 0xe6 => f.write_str("MUL231"),
10745 0xe7 => f.write_str("MUL232"),
10746 0xe8 => f.write_str("MUL233"),
10747 0xe9 => f.write_str("MUL234"),
10748 0xea => f.write_str("MUL235"),
10749 0xeb => f.write_str("MUL236"),
10750 0xec => f.write_str("MUL237"),
10751 0xed => f.write_str("MUL238"),
10752 0xee => f.write_str("MUL239"),
10753 0xef => f.write_str("MUL240"),
10754 0xf0 => f.write_str("MUL241"),
10755 0xf1 => f.write_str("MUL242"),
10756 0xf2 => f.write_str("MUL243"),
10757 0xf3 => f.write_str("MUL244"),
10758 0xf4 => f.write_str("MUL245"),
10759 0xf5 => f.write_str("MUL246"),
10760 0xf6 => f.write_str("MUL247"),
10761 0xf7 => f.write_str("MUL248"),
10762 0xf8 => f.write_str("MUL249"),
10763 0xf9 => f.write_str("MUL250"),
10764 0xfa => f.write_str("MUL251"),
10765 0xfb => f.write_str("MUL252"),
10766 0xfc => f.write_str("MUL253"),
10767 0xfd => f.write_str("MUL254"),
10768 0xfe => f.write_str("MUL255"),
10769 0xff => f.write_str("MUL256"),
10770 0x0100 => f.write_str("MUL257"),
10771 0x0101 => f.write_str("MUL258"),
10772 0x0102 => f.write_str("MUL259"),
10773 0x0103 => f.write_str("MUL260"),
10774 0x0104 => f.write_str("MUL261"),
10775 0x0105 => f.write_str("MUL262"),
10776 0x0106 => f.write_str("MUL263"),
10777 0x0107 => f.write_str("MUL264"),
10778 0x0108 => f.write_str("MUL265"),
10779 0x0109 => f.write_str("MUL266"),
10780 0x010a => f.write_str("MUL267"),
10781 0x010b => f.write_str("MUL268"),
10782 0x010c => f.write_str("MUL269"),
10783 0x010d => f.write_str("MUL270"),
10784 0x010e => f.write_str("MUL271"),
10785 0x010f => f.write_str("MUL272"),
10786 0x0110 => f.write_str("MUL273"),
10787 0x0111 => f.write_str("MUL274"),
10788 0x0112 => f.write_str("MUL275"),
10789 0x0113 => f.write_str("MUL276"),
10790 0x0114 => f.write_str("MUL277"),
10791 0x0115 => f.write_str("MUL278"),
10792 0x0116 => f.write_str("MUL279"),
10793 0x0117 => f.write_str("MUL280"),
10794 0x0118 => f.write_str("MUL281"),
10795 0x0119 => f.write_str("MUL282"),
10796 0x011a => f.write_str("MUL283"),
10797 0x011b => f.write_str("MUL284"),
10798 0x011c => f.write_str("MUL285"),
10799 0x011d => f.write_str("MUL286"),
10800 0x011e => f.write_str("MUL287"),
10801 0x011f => f.write_str("MUL288"),
10802 0x0120 => f.write_str("MUL289"),
10803 0x0121 => f.write_str("MUL290"),
10804 0x0122 => f.write_str("MUL291"),
10805 0x0123 => f.write_str("MUL292"),
10806 0x0124 => f.write_str("MUL293"),
10807 0x0125 => f.write_str("MUL294"),
10808 0x0126 => f.write_str("MUL295"),
10809 0x0127 => f.write_str("MUL296"),
10810 0x0128 => f.write_str("MUL297"),
10811 0x0129 => f.write_str("MUL298"),
10812 0x012a => f.write_str("MUL299"),
10813 0x012b => f.write_str("MUL300"),
10814 0x012c => f.write_str("MUL301"),
10815 0x012d => f.write_str("MUL302"),
10816 0x012e => f.write_str("MUL303"),
10817 0x012f => f.write_str("MUL304"),
10818 0x0130 => f.write_str("MUL305"),
10819 0x0131 => f.write_str("MUL306"),
10820 0x0132 => f.write_str("MUL307"),
10821 0x0133 => f.write_str("MUL308"),
10822 0x0134 => f.write_str("MUL309"),
10823 0x0135 => f.write_str("MUL310"),
10824 0x0136 => f.write_str("MUL311"),
10825 0x0137 => f.write_str("MUL312"),
10826 0x0138 => f.write_str("MUL313"),
10827 0x0139 => f.write_str("MUL314"),
10828 0x013a => f.write_str("MUL315"),
10829 0x013b => f.write_str("MUL316"),
10830 0x013c => f.write_str("MUL317"),
10831 0x013d => f.write_str("MUL318"),
10832 0x013e => f.write_str("MUL319"),
10833 0x013f => f.write_str("MUL320"),
10834 0x0140 => f.write_str("MUL321"),
10835 0x0141 => f.write_str("MUL322"),
10836 0x0142 => f.write_str("MUL323"),
10837 0x0143 => f.write_str("MUL324"),
10838 0x0144 => f.write_str("MUL325"),
10839 0x0145 => f.write_str("MUL326"),
10840 0x0146 => f.write_str("MUL327"),
10841 0x0147 => f.write_str("MUL328"),
10842 0x0148 => f.write_str("MUL329"),
10843 0x0149 => f.write_str("MUL330"),
10844 0x014a => f.write_str("MUL331"),
10845 0x014b => f.write_str("MUL332"),
10846 0x014c => f.write_str("MUL333"),
10847 0x014d => f.write_str("MUL334"),
10848 0x014e => f.write_str("MUL335"),
10849 0x014f => f.write_str("MUL336"),
10850 0x0150 => f.write_str("MUL337"),
10851 0x0151 => f.write_str("MUL338"),
10852 0x0152 => f.write_str("MUL339"),
10853 0x0153 => f.write_str("MUL340"),
10854 0x0154 => f.write_str("MUL341"),
10855 0x0155 => f.write_str("MUL342"),
10856 0x0156 => f.write_str("MUL343"),
10857 0x0157 => f.write_str("MUL344"),
10858 0x0158 => f.write_str("MUL345"),
10859 0x0159 => f.write_str("MUL346"),
10860 0x015a => f.write_str("MUL347"),
10861 0x015b => f.write_str("MUL348"),
10862 0x015c => f.write_str("MUL349"),
10863 0x015d => f.write_str("MUL350"),
10864 0x015e => f.write_str("MUL351"),
10865 0x015f => f.write_str("MUL352"),
10866 0x0160 => f.write_str("MUL353"),
10867 0x0161 => f.write_str("MUL354"),
10868 0x0162 => f.write_str("MUL355"),
10869 0x0163 => f.write_str("MUL356"),
10870 0x0164 => f.write_str("MUL357"),
10871 0x0165 => f.write_str("MUL358"),
10872 0x0166 => f.write_str("MUL359"),
10873 0x0167 => f.write_str("MUL360"),
10874 0x0168 => f.write_str("MUL361"),
10875 0x0169 => f.write_str("MUL362"),
10876 0x016a => f.write_str("MUL363"),
10877 0x016b => f.write_str("MUL364"),
10878 0x016c => f.write_str("MUL365"),
10879 0x016d => f.write_str("MUL366"),
10880 0x016e => f.write_str("MUL367"),
10881 0x016f => f.write_str("MUL368"),
10882 0x0170 => f.write_str("MUL369"),
10883 0x0171 => f.write_str("MUL370"),
10884 0x0172 => f.write_str("MUL371"),
10885 0x0173 => f.write_str("MUL372"),
10886 0x0174 => f.write_str("MUL373"),
10887 0x0175 => f.write_str("MUL374"),
10888 0x0176 => f.write_str("MUL375"),
10889 0x0177 => f.write_str("MUL376"),
10890 0x0178 => f.write_str("MUL377"),
10891 0x0179 => f.write_str("MUL378"),
10892 0x017a => f.write_str("MUL379"),
10893 0x017b => f.write_str("MUL380"),
10894 0x017c => f.write_str("MUL381"),
10895 0x017d => f.write_str("MUL382"),
10896 0x017e => f.write_str("MUL383"),
10897 0x017f => f.write_str("MUL384"),
10898 0x0180 => f.write_str("MUL385"),
10899 0x0181 => f.write_str("MUL386"),
10900 0x0182 => f.write_str("MUL387"),
10901 0x0183 => f.write_str("MUL388"),
10902 0x0184 => f.write_str("MUL389"),
10903 0x0185 => f.write_str("MUL390"),
10904 0x0186 => f.write_str("MUL391"),
10905 0x0187 => f.write_str("MUL392"),
10906 0x0188 => f.write_str("MUL393"),
10907 0x0189 => f.write_str("MUL394"),
10908 0x018a => f.write_str("MUL395"),
10909 0x018b => f.write_str("MUL396"),
10910 0x018c => f.write_str("MUL397"),
10911 0x018d => f.write_str("MUL398"),
10912 0x018e => f.write_str("MUL399"),
10913 0x018f => f.write_str("MUL400"),
10914 0x0190 => f.write_str("MUL401"),
10915 0x0191 => f.write_str("MUL402"),
10916 0x0192 => f.write_str("MUL403"),
10917 0x0193 => f.write_str("MUL404"),
10918 0x0194 => f.write_str("MUL405"),
10919 0x0195 => f.write_str("MUL406"),
10920 0x0196 => f.write_str("MUL407"),
10921 0x0197 => f.write_str("MUL408"),
10922 0x0198 => f.write_str("MUL409"),
10923 0x0199 => f.write_str("MUL410"),
10924 0x019a => f.write_str("MUL411"),
10925 0x019b => f.write_str("MUL412"),
10926 0x019c => f.write_str("MUL413"),
10927 0x019d => f.write_str("MUL414"),
10928 0x019e => f.write_str("MUL415"),
10929 0x019f => f.write_str("MUL416"),
10930 0x01a0 => f.write_str("MUL417"),
10931 0x01a1 => f.write_str("MUL418"),
10932 0x01a2 => f.write_str("MUL419"),
10933 0x01a3 => f.write_str("MUL420"),
10934 0x01a4 => f.write_str("MUL421"),
10935 0x01a5 => f.write_str("MUL422"),
10936 0x01a6 => f.write_str("MUL423"),
10937 0x01a7 => f.write_str("MUL424"),
10938 0x01a8 => f.write_str("MUL425"),
10939 0x01a9 => f.write_str("MUL426"),
10940 0x01aa => f.write_str("MUL427"),
10941 0x01ab => f.write_str("MUL428"),
10942 0x01ac => f.write_str("MUL429"),
10943 0x01ad => f.write_str("MUL430"),
10944 0x01ae => f.write_str("MUL431"),
10945 0x01af => f.write_str("MUL432"),
10946 0x01b0 => f.write_str("MUL433"),
10947 0x01b1 => f.write_str("MUL434"),
10948 0x01b2 => f.write_str("MUL435"),
10949 0x01b3 => f.write_str("MUL436"),
10950 0x01b4 => f.write_str("MUL437"),
10951 0x01b5 => f.write_str("MUL438"),
10952 0x01b6 => f.write_str("MUL439"),
10953 0x01b7 => f.write_str("MUL440"),
10954 0x01b8 => f.write_str("MUL441"),
10955 0x01b9 => f.write_str("MUL442"),
10956 0x01ba => f.write_str("MUL443"),
10957 0x01bb => f.write_str("MUL444"),
10958 0x01bc => f.write_str("MUL445"),
10959 0x01bd => f.write_str("MUL446"),
10960 0x01be => f.write_str("MUL447"),
10961 0x01bf => f.write_str("MUL448"),
10962 0x01c0 => f.write_str("MUL449"),
10963 0x01c1 => f.write_str("MUL450"),
10964 0x01c2 => f.write_str("MUL451"),
10965 0x01c3 => f.write_str("MUL452"),
10966 0x01c4 => f.write_str("MUL453"),
10967 0x01c5 => f.write_str("MUL454"),
10968 0x01c6 => f.write_str("MUL455"),
10969 0x01c7 => f.write_str("MUL456"),
10970 0x01c8 => f.write_str("MUL457"),
10971 0x01c9 => f.write_str("MUL458"),
10972 0x01ca => f.write_str("MUL459"),
10973 0x01cb => f.write_str("MUL460"),
10974 0x01cc => f.write_str("MUL461"),
10975 0x01cd => f.write_str("MUL462"),
10976 0x01ce => f.write_str("MUL463"),
10977 0x01cf => f.write_str("MUL464"),
10978 0x01d0 => f.write_str("MUL465"),
10979 0x01d1 => f.write_str("MUL466"),
10980 0x01d2 => f.write_str("MUL467"),
10981 0x01d3 => f.write_str("MUL468"),
10982 0x01d4 => f.write_str("MUL469"),
10983 0x01d5 => f.write_str("MUL470"),
10984 0x01d6 => f.write_str("MUL471"),
10985 0x01d7 => f.write_str("MUL472"),
10986 0x01d8 => f.write_str("MUL473"),
10987 0x01d9 => f.write_str("MUL474"),
10988 0x01da => f.write_str("MUL475"),
10989 0x01db => f.write_str("MUL476"),
10990 0x01dc => f.write_str("MUL477"),
10991 0x01dd => f.write_str("MUL478"),
10992 0x01de => f.write_str("MUL479"),
10993 0x01df => f.write_str("MUL480"),
10994 0x01e0 => f.write_str("MUL481"),
10995 0x01e1 => f.write_str("MUL482"),
10996 0x01e2 => f.write_str("MUL483"),
10997 0x01e3 => f.write_str("MUL484"),
10998 0x01e4 => f.write_str("MUL485"),
10999 0x01e5 => f.write_str("MUL486"),
11000 0x01e6 => f.write_str("MUL487"),
11001 0x01e7 => f.write_str("MUL488"),
11002 0x01e8 => f.write_str("MUL489"),
11003 0x01e9 => f.write_str("MUL490"),
11004 0x01ea => f.write_str("MUL491"),
11005 0x01eb => f.write_str("MUL492"),
11006 0x01ec => f.write_str("MUL493"),
11007 0x01ed => f.write_str("MUL494"),
11008 0x01ee => f.write_str("MUL495"),
11009 0x01ef => f.write_str("MUL496"),
11010 0x01f0 => f.write_str("MUL497"),
11011 0x01f1 => f.write_str("MUL498"),
11012 0x01f2 => f.write_str("MUL499"),
11013 0x01f3 => f.write_str("MUL500"),
11014 0x01f4 => f.write_str("MUL501"),
11015 0x01f5 => f.write_str("MUL502"),
11016 0x01f6 => f.write_str("MUL503"),
11017 0x01f7 => f.write_str("MUL504"),
11018 0x01f8 => f.write_str("MUL505"),
11019 0x01f9 => f.write_str("MUL506"),
11020 0x01fa => f.write_str("MUL507"),
11021 0x01fb => f.write_str("MUL508"),
11022 0x01fc => f.write_str("MUL509"),
11023 0x01fd => f.write_str("MUL510"),
11024 0x01fe => f.write_str("MUL511"),
11025 0x01ff => f.write_str("MUL512"),
11026 other => core::write!(f, "0x{:02X}", other),
11027 }
11028 }
11029 }
11030 #[cfg(feature = "defmt")]
11031 impl defmt::Format for Plln {
11032 fn format(&self, f: defmt::Formatter) {
11033 match self.0 {
11034 0x03 => defmt::write!(f, "MUL4"),
11035 0x04 => defmt::write!(f, "MUL5"),
11036 0x05 => defmt::write!(f, "MUL6"),
11037 0x06 => defmt::write!(f, "MUL7"),
11038 0x07 => defmt::write!(f, "MUL8"),
11039 0x08 => defmt::write!(f, "MUL9"),
11040 0x09 => defmt::write!(f, "MUL10"),
11041 0x0a => defmt::write!(f, "MUL11"),
11042 0x0b => defmt::write!(f, "MUL12"),
11043 0x0c => defmt::write!(f, "MUL13"),
11044 0x0d => defmt::write!(f, "MUL14"),
11045 0x0e => defmt::write!(f, "MUL15"),
11046 0x0f => defmt::write!(f, "MUL16"),
11047 0x10 => defmt::write!(f, "MUL17"),
11048 0x11 => defmt::write!(f, "MUL18"),
11049 0x12 => defmt::write!(f, "MUL19"),
11050 0x13 => defmt::write!(f, "MUL20"),
11051 0x14 => defmt::write!(f, "MUL21"),
11052 0x15 => defmt::write!(f, "MUL22"),
11053 0x16 => defmt::write!(f, "MUL23"),
11054 0x17 => defmt::write!(f, "MUL24"),
11055 0x18 => defmt::write!(f, "MUL25"),
11056 0x19 => defmt::write!(f, "MUL26"),
11057 0x1a => defmt::write!(f, "MUL27"),
11058 0x1b => defmt::write!(f, "MUL28"),
11059 0x1c => defmt::write!(f, "MUL29"),
11060 0x1d => defmt::write!(f, "MUL30"),
11061 0x1e => defmt::write!(f, "MUL31"),
11062 0x1f => defmt::write!(f, "MUL32"),
11063 0x20 => defmt::write!(f, "MUL33"),
11064 0x21 => defmt::write!(f, "MUL34"),
11065 0x22 => defmt::write!(f, "MUL35"),
11066 0x23 => defmt::write!(f, "MUL36"),
11067 0x24 => defmt::write!(f, "MUL37"),
11068 0x25 => defmt::write!(f, "MUL38"),
11069 0x26 => defmt::write!(f, "MUL39"),
11070 0x27 => defmt::write!(f, "MUL40"),
11071 0x28 => defmt::write!(f, "MUL41"),
11072 0x29 => defmt::write!(f, "MUL42"),
11073 0x2a => defmt::write!(f, "MUL43"),
11074 0x2b => defmt::write!(f, "MUL44"),
11075 0x2c => defmt::write!(f, "MUL45"),
11076 0x2d => defmt::write!(f, "MUL46"),
11077 0x2e => defmt::write!(f, "MUL47"),
11078 0x2f => defmt::write!(f, "MUL48"),
11079 0x30 => defmt::write!(f, "MUL49"),
11080 0x31 => defmt::write!(f, "MUL50"),
11081 0x32 => defmt::write!(f, "MUL51"),
11082 0x33 => defmt::write!(f, "MUL52"),
11083 0x34 => defmt::write!(f, "MUL53"),
11084 0x35 => defmt::write!(f, "MUL54"),
11085 0x36 => defmt::write!(f, "MUL55"),
11086 0x37 => defmt::write!(f, "MUL56"),
11087 0x38 => defmt::write!(f, "MUL57"),
11088 0x39 => defmt::write!(f, "MUL58"),
11089 0x3a => defmt::write!(f, "MUL59"),
11090 0x3b => defmt::write!(f, "MUL60"),
11091 0x3c => defmt::write!(f, "MUL61"),
11092 0x3d => defmt::write!(f, "MUL62"),
11093 0x3e => defmt::write!(f, "MUL63"),
11094 0x3f => defmt::write!(f, "MUL64"),
11095 0x40 => defmt::write!(f, "MUL65"),
11096 0x41 => defmt::write!(f, "MUL66"),
11097 0x42 => defmt::write!(f, "MUL67"),
11098 0x43 => defmt::write!(f, "MUL68"),
11099 0x44 => defmt::write!(f, "MUL69"),
11100 0x45 => defmt::write!(f, "MUL70"),
11101 0x46 => defmt::write!(f, "MUL71"),
11102 0x47 => defmt::write!(f, "MUL72"),
11103 0x48 => defmt::write!(f, "MUL73"),
11104 0x49 => defmt::write!(f, "MUL74"),
11105 0x4a => defmt::write!(f, "MUL75"),
11106 0x4b => defmt::write!(f, "MUL76"),
11107 0x4c => defmt::write!(f, "MUL77"),
11108 0x4d => defmt::write!(f, "MUL78"),
11109 0x4e => defmt::write!(f, "MUL79"),
11110 0x4f => defmt::write!(f, "MUL80"),
11111 0x50 => defmt::write!(f, "MUL81"),
11112 0x51 => defmt::write!(f, "MUL82"),
11113 0x52 => defmt::write!(f, "MUL83"),
11114 0x53 => defmt::write!(f, "MUL84"),
11115 0x54 => defmt::write!(f, "MUL85"),
11116 0x55 => defmt::write!(f, "MUL86"),
11117 0x56 => defmt::write!(f, "MUL87"),
11118 0x57 => defmt::write!(f, "MUL88"),
11119 0x58 => defmt::write!(f, "MUL89"),
11120 0x59 => defmt::write!(f, "MUL90"),
11121 0x5a => defmt::write!(f, "MUL91"),
11122 0x5b => defmt::write!(f, "MUL92"),
11123 0x5c => defmt::write!(f, "MUL93"),
11124 0x5d => defmt::write!(f, "MUL94"),
11125 0x5e => defmt::write!(f, "MUL95"),
11126 0x5f => defmt::write!(f, "MUL96"),
11127 0x60 => defmt::write!(f, "MUL97"),
11128 0x61 => defmt::write!(f, "MUL98"),
11129 0x62 => defmt::write!(f, "MUL99"),
11130 0x63 => defmt::write!(f, "MUL100"),
11131 0x64 => defmt::write!(f, "MUL101"),
11132 0x65 => defmt::write!(f, "MUL102"),
11133 0x66 => defmt::write!(f, "MUL103"),
11134 0x67 => defmt::write!(f, "MUL104"),
11135 0x68 => defmt::write!(f, "MUL105"),
11136 0x69 => defmt::write!(f, "MUL106"),
11137 0x6a => defmt::write!(f, "MUL107"),
11138 0x6b => defmt::write!(f, "MUL108"),
11139 0x6c => defmt::write!(f, "MUL109"),
11140 0x6d => defmt::write!(f, "MUL110"),
11141 0x6e => defmt::write!(f, "MUL111"),
11142 0x6f => defmt::write!(f, "MUL112"),
11143 0x70 => defmt::write!(f, "MUL113"),
11144 0x71 => defmt::write!(f, "MUL114"),
11145 0x72 => defmt::write!(f, "MUL115"),
11146 0x73 => defmt::write!(f, "MUL116"),
11147 0x74 => defmt::write!(f, "MUL117"),
11148 0x75 => defmt::write!(f, "MUL118"),
11149 0x76 => defmt::write!(f, "MUL119"),
11150 0x77 => defmt::write!(f, "MUL120"),
11151 0x78 => defmt::write!(f, "MUL121"),
11152 0x79 => defmt::write!(f, "MUL122"),
11153 0x7a => defmt::write!(f, "MUL123"),
11154 0x7b => defmt::write!(f, "MUL124"),
11155 0x7c => defmt::write!(f, "MUL125"),
11156 0x7d => defmt::write!(f, "MUL126"),
11157 0x7e => defmt::write!(f, "MUL127"),
11158 0x7f => defmt::write!(f, "MUL128"),
11159 0x80 => defmt::write!(f, "MUL129"),
11160 0x81 => defmt::write!(f, "MUL130"),
11161 0x82 => defmt::write!(f, "MUL131"),
11162 0x83 => defmt::write!(f, "MUL132"),
11163 0x84 => defmt::write!(f, "MUL133"),
11164 0x85 => defmt::write!(f, "MUL134"),
11165 0x86 => defmt::write!(f, "MUL135"),
11166 0x87 => defmt::write!(f, "MUL136"),
11167 0x88 => defmt::write!(f, "MUL137"),
11168 0x89 => defmt::write!(f, "MUL138"),
11169 0x8a => defmt::write!(f, "MUL139"),
11170 0x8b => defmt::write!(f, "MUL140"),
11171 0x8c => defmt::write!(f, "MUL141"),
11172 0x8d => defmt::write!(f, "MUL142"),
11173 0x8e => defmt::write!(f, "MUL143"),
11174 0x8f => defmt::write!(f, "MUL144"),
11175 0x90 => defmt::write!(f, "MUL145"),
11176 0x91 => defmt::write!(f, "MUL146"),
11177 0x92 => defmt::write!(f, "MUL147"),
11178 0x93 => defmt::write!(f, "MUL148"),
11179 0x94 => defmt::write!(f, "MUL149"),
11180 0x95 => defmt::write!(f, "MUL150"),
11181 0x96 => defmt::write!(f, "MUL151"),
11182 0x97 => defmt::write!(f, "MUL152"),
11183 0x98 => defmt::write!(f, "MUL153"),
11184 0x99 => defmt::write!(f, "MUL154"),
11185 0x9a => defmt::write!(f, "MUL155"),
11186 0x9b => defmt::write!(f, "MUL156"),
11187 0x9c => defmt::write!(f, "MUL157"),
11188 0x9d => defmt::write!(f, "MUL158"),
11189 0x9e => defmt::write!(f, "MUL159"),
11190 0x9f => defmt::write!(f, "MUL160"),
11191 0xa0 => defmt::write!(f, "MUL161"),
11192 0xa1 => defmt::write!(f, "MUL162"),
11193 0xa2 => defmt::write!(f, "MUL163"),
11194 0xa3 => defmt::write!(f, "MUL164"),
11195 0xa4 => defmt::write!(f, "MUL165"),
11196 0xa5 => defmt::write!(f, "MUL166"),
11197 0xa6 => defmt::write!(f, "MUL167"),
11198 0xa7 => defmt::write!(f, "MUL168"),
11199 0xa8 => defmt::write!(f, "MUL169"),
11200 0xa9 => defmt::write!(f, "MUL170"),
11201 0xaa => defmt::write!(f, "MUL171"),
11202 0xab => defmt::write!(f, "MUL172"),
11203 0xac => defmt::write!(f, "MUL173"),
11204 0xad => defmt::write!(f, "MUL174"),
11205 0xae => defmt::write!(f, "MUL175"),
11206 0xaf => defmt::write!(f, "MUL176"),
11207 0xb0 => defmt::write!(f, "MUL177"),
11208 0xb1 => defmt::write!(f, "MUL178"),
11209 0xb2 => defmt::write!(f, "MUL179"),
11210 0xb3 => defmt::write!(f, "MUL180"),
11211 0xb4 => defmt::write!(f, "MUL181"),
11212 0xb5 => defmt::write!(f, "MUL182"),
11213 0xb6 => defmt::write!(f, "MUL183"),
11214 0xb7 => defmt::write!(f, "MUL184"),
11215 0xb8 => defmt::write!(f, "MUL185"),
11216 0xb9 => defmt::write!(f, "MUL186"),
11217 0xba => defmt::write!(f, "MUL187"),
11218 0xbb => defmt::write!(f, "MUL188"),
11219 0xbc => defmt::write!(f, "MUL189"),
11220 0xbd => defmt::write!(f, "MUL190"),
11221 0xbe => defmt::write!(f, "MUL191"),
11222 0xbf => defmt::write!(f, "MUL192"),
11223 0xc0 => defmt::write!(f, "MUL193"),
11224 0xc1 => defmt::write!(f, "MUL194"),
11225 0xc2 => defmt::write!(f, "MUL195"),
11226 0xc3 => defmt::write!(f, "MUL196"),
11227 0xc4 => defmt::write!(f, "MUL197"),
11228 0xc5 => defmt::write!(f, "MUL198"),
11229 0xc6 => defmt::write!(f, "MUL199"),
11230 0xc7 => defmt::write!(f, "MUL200"),
11231 0xc8 => defmt::write!(f, "MUL201"),
11232 0xc9 => defmt::write!(f, "MUL202"),
11233 0xca => defmt::write!(f, "MUL203"),
11234 0xcb => defmt::write!(f, "MUL204"),
11235 0xcc => defmt::write!(f, "MUL205"),
11236 0xcd => defmt::write!(f, "MUL206"),
11237 0xce => defmt::write!(f, "MUL207"),
11238 0xcf => defmt::write!(f, "MUL208"),
11239 0xd0 => defmt::write!(f, "MUL209"),
11240 0xd1 => defmt::write!(f, "MUL210"),
11241 0xd2 => defmt::write!(f, "MUL211"),
11242 0xd3 => defmt::write!(f, "MUL212"),
11243 0xd4 => defmt::write!(f, "MUL213"),
11244 0xd5 => defmt::write!(f, "MUL214"),
11245 0xd6 => defmt::write!(f, "MUL215"),
11246 0xd7 => defmt::write!(f, "MUL216"),
11247 0xd8 => defmt::write!(f, "MUL217"),
11248 0xd9 => defmt::write!(f, "MUL218"),
11249 0xda => defmt::write!(f, "MUL219"),
11250 0xdb => defmt::write!(f, "MUL220"),
11251 0xdc => defmt::write!(f, "MUL221"),
11252 0xdd => defmt::write!(f, "MUL222"),
11253 0xde => defmt::write!(f, "MUL223"),
11254 0xdf => defmt::write!(f, "MUL224"),
11255 0xe0 => defmt::write!(f, "MUL225"),
11256 0xe1 => defmt::write!(f, "MUL226"),
11257 0xe2 => defmt::write!(f, "MUL227"),
11258 0xe3 => defmt::write!(f, "MUL228"),
11259 0xe4 => defmt::write!(f, "MUL229"),
11260 0xe5 => defmt::write!(f, "MUL230"),
11261 0xe6 => defmt::write!(f, "MUL231"),
11262 0xe7 => defmt::write!(f, "MUL232"),
11263 0xe8 => defmt::write!(f, "MUL233"),
11264 0xe9 => defmt::write!(f, "MUL234"),
11265 0xea => defmt::write!(f, "MUL235"),
11266 0xeb => defmt::write!(f, "MUL236"),
11267 0xec => defmt::write!(f, "MUL237"),
11268 0xed => defmt::write!(f, "MUL238"),
11269 0xee => defmt::write!(f, "MUL239"),
11270 0xef => defmt::write!(f, "MUL240"),
11271 0xf0 => defmt::write!(f, "MUL241"),
11272 0xf1 => defmt::write!(f, "MUL242"),
11273 0xf2 => defmt::write!(f, "MUL243"),
11274 0xf3 => defmt::write!(f, "MUL244"),
11275 0xf4 => defmt::write!(f, "MUL245"),
11276 0xf5 => defmt::write!(f, "MUL246"),
11277 0xf6 => defmt::write!(f, "MUL247"),
11278 0xf7 => defmt::write!(f, "MUL248"),
11279 0xf8 => defmt::write!(f, "MUL249"),
11280 0xf9 => defmt::write!(f, "MUL250"),
11281 0xfa => defmt::write!(f, "MUL251"),
11282 0xfb => defmt::write!(f, "MUL252"),
11283 0xfc => defmt::write!(f, "MUL253"),
11284 0xfd => defmt::write!(f, "MUL254"),
11285 0xfe => defmt::write!(f, "MUL255"),
11286 0xff => defmt::write!(f, "MUL256"),
11287 0x0100 => defmt::write!(f, "MUL257"),
11288 0x0101 => defmt::write!(f, "MUL258"),
11289 0x0102 => defmt::write!(f, "MUL259"),
11290 0x0103 => defmt::write!(f, "MUL260"),
11291 0x0104 => defmt::write!(f, "MUL261"),
11292 0x0105 => defmt::write!(f, "MUL262"),
11293 0x0106 => defmt::write!(f, "MUL263"),
11294 0x0107 => defmt::write!(f, "MUL264"),
11295 0x0108 => defmt::write!(f, "MUL265"),
11296 0x0109 => defmt::write!(f, "MUL266"),
11297 0x010a => defmt::write!(f, "MUL267"),
11298 0x010b => defmt::write!(f, "MUL268"),
11299 0x010c => defmt::write!(f, "MUL269"),
11300 0x010d => defmt::write!(f, "MUL270"),
11301 0x010e => defmt::write!(f, "MUL271"),
11302 0x010f => defmt::write!(f, "MUL272"),
11303 0x0110 => defmt::write!(f, "MUL273"),
11304 0x0111 => defmt::write!(f, "MUL274"),
11305 0x0112 => defmt::write!(f, "MUL275"),
11306 0x0113 => defmt::write!(f, "MUL276"),
11307 0x0114 => defmt::write!(f, "MUL277"),
11308 0x0115 => defmt::write!(f, "MUL278"),
11309 0x0116 => defmt::write!(f, "MUL279"),
11310 0x0117 => defmt::write!(f, "MUL280"),
11311 0x0118 => defmt::write!(f, "MUL281"),
11312 0x0119 => defmt::write!(f, "MUL282"),
11313 0x011a => defmt::write!(f, "MUL283"),
11314 0x011b => defmt::write!(f, "MUL284"),
11315 0x011c => defmt::write!(f, "MUL285"),
11316 0x011d => defmt::write!(f, "MUL286"),
11317 0x011e => defmt::write!(f, "MUL287"),
11318 0x011f => defmt::write!(f, "MUL288"),
11319 0x0120 => defmt::write!(f, "MUL289"),
11320 0x0121 => defmt::write!(f, "MUL290"),
11321 0x0122 => defmt::write!(f, "MUL291"),
11322 0x0123 => defmt::write!(f, "MUL292"),
11323 0x0124 => defmt::write!(f, "MUL293"),
11324 0x0125 => defmt::write!(f, "MUL294"),
11325 0x0126 => defmt::write!(f, "MUL295"),
11326 0x0127 => defmt::write!(f, "MUL296"),
11327 0x0128 => defmt::write!(f, "MUL297"),
11328 0x0129 => defmt::write!(f, "MUL298"),
11329 0x012a => defmt::write!(f, "MUL299"),
11330 0x012b => defmt::write!(f, "MUL300"),
11331 0x012c => defmt::write!(f, "MUL301"),
11332 0x012d => defmt::write!(f, "MUL302"),
11333 0x012e => defmt::write!(f, "MUL303"),
11334 0x012f => defmt::write!(f, "MUL304"),
11335 0x0130 => defmt::write!(f, "MUL305"),
11336 0x0131 => defmt::write!(f, "MUL306"),
11337 0x0132 => defmt::write!(f, "MUL307"),
11338 0x0133 => defmt::write!(f, "MUL308"),
11339 0x0134 => defmt::write!(f, "MUL309"),
11340 0x0135 => defmt::write!(f, "MUL310"),
11341 0x0136 => defmt::write!(f, "MUL311"),
11342 0x0137 => defmt::write!(f, "MUL312"),
11343 0x0138 => defmt::write!(f, "MUL313"),
11344 0x0139 => defmt::write!(f, "MUL314"),
11345 0x013a => defmt::write!(f, "MUL315"),
11346 0x013b => defmt::write!(f, "MUL316"),
11347 0x013c => defmt::write!(f, "MUL317"),
11348 0x013d => defmt::write!(f, "MUL318"),
11349 0x013e => defmt::write!(f, "MUL319"),
11350 0x013f => defmt::write!(f, "MUL320"),
11351 0x0140 => defmt::write!(f, "MUL321"),
11352 0x0141 => defmt::write!(f, "MUL322"),
11353 0x0142 => defmt::write!(f, "MUL323"),
11354 0x0143 => defmt::write!(f, "MUL324"),
11355 0x0144 => defmt::write!(f, "MUL325"),
11356 0x0145 => defmt::write!(f, "MUL326"),
11357 0x0146 => defmt::write!(f, "MUL327"),
11358 0x0147 => defmt::write!(f, "MUL328"),
11359 0x0148 => defmt::write!(f, "MUL329"),
11360 0x0149 => defmt::write!(f, "MUL330"),
11361 0x014a => defmt::write!(f, "MUL331"),
11362 0x014b => defmt::write!(f, "MUL332"),
11363 0x014c => defmt::write!(f, "MUL333"),
11364 0x014d => defmt::write!(f, "MUL334"),
11365 0x014e => defmt::write!(f, "MUL335"),
11366 0x014f => defmt::write!(f, "MUL336"),
11367 0x0150 => defmt::write!(f, "MUL337"),
11368 0x0151 => defmt::write!(f, "MUL338"),
11369 0x0152 => defmt::write!(f, "MUL339"),
11370 0x0153 => defmt::write!(f, "MUL340"),
11371 0x0154 => defmt::write!(f, "MUL341"),
11372 0x0155 => defmt::write!(f, "MUL342"),
11373 0x0156 => defmt::write!(f, "MUL343"),
11374 0x0157 => defmt::write!(f, "MUL344"),
11375 0x0158 => defmt::write!(f, "MUL345"),
11376 0x0159 => defmt::write!(f, "MUL346"),
11377 0x015a => defmt::write!(f, "MUL347"),
11378 0x015b => defmt::write!(f, "MUL348"),
11379 0x015c => defmt::write!(f, "MUL349"),
11380 0x015d => defmt::write!(f, "MUL350"),
11381 0x015e => defmt::write!(f, "MUL351"),
11382 0x015f => defmt::write!(f, "MUL352"),
11383 0x0160 => defmt::write!(f, "MUL353"),
11384 0x0161 => defmt::write!(f, "MUL354"),
11385 0x0162 => defmt::write!(f, "MUL355"),
11386 0x0163 => defmt::write!(f, "MUL356"),
11387 0x0164 => defmt::write!(f, "MUL357"),
11388 0x0165 => defmt::write!(f, "MUL358"),
11389 0x0166 => defmt::write!(f, "MUL359"),
11390 0x0167 => defmt::write!(f, "MUL360"),
11391 0x0168 => defmt::write!(f, "MUL361"),
11392 0x0169 => defmt::write!(f, "MUL362"),
11393 0x016a => defmt::write!(f, "MUL363"),
11394 0x016b => defmt::write!(f, "MUL364"),
11395 0x016c => defmt::write!(f, "MUL365"),
11396 0x016d => defmt::write!(f, "MUL366"),
11397 0x016e => defmt::write!(f, "MUL367"),
11398 0x016f => defmt::write!(f, "MUL368"),
11399 0x0170 => defmt::write!(f, "MUL369"),
11400 0x0171 => defmt::write!(f, "MUL370"),
11401 0x0172 => defmt::write!(f, "MUL371"),
11402 0x0173 => defmt::write!(f, "MUL372"),
11403 0x0174 => defmt::write!(f, "MUL373"),
11404 0x0175 => defmt::write!(f, "MUL374"),
11405 0x0176 => defmt::write!(f, "MUL375"),
11406 0x0177 => defmt::write!(f, "MUL376"),
11407 0x0178 => defmt::write!(f, "MUL377"),
11408 0x0179 => defmt::write!(f, "MUL378"),
11409 0x017a => defmt::write!(f, "MUL379"),
11410 0x017b => defmt::write!(f, "MUL380"),
11411 0x017c => defmt::write!(f, "MUL381"),
11412 0x017d => defmt::write!(f, "MUL382"),
11413 0x017e => defmt::write!(f, "MUL383"),
11414 0x017f => defmt::write!(f, "MUL384"),
11415 0x0180 => defmt::write!(f, "MUL385"),
11416 0x0181 => defmt::write!(f, "MUL386"),
11417 0x0182 => defmt::write!(f, "MUL387"),
11418 0x0183 => defmt::write!(f, "MUL388"),
11419 0x0184 => defmt::write!(f, "MUL389"),
11420 0x0185 => defmt::write!(f, "MUL390"),
11421 0x0186 => defmt::write!(f, "MUL391"),
11422 0x0187 => defmt::write!(f, "MUL392"),
11423 0x0188 => defmt::write!(f, "MUL393"),
11424 0x0189 => defmt::write!(f, "MUL394"),
11425 0x018a => defmt::write!(f, "MUL395"),
11426 0x018b => defmt::write!(f, "MUL396"),
11427 0x018c => defmt::write!(f, "MUL397"),
11428 0x018d => defmt::write!(f, "MUL398"),
11429 0x018e => defmt::write!(f, "MUL399"),
11430 0x018f => defmt::write!(f, "MUL400"),
11431 0x0190 => defmt::write!(f, "MUL401"),
11432 0x0191 => defmt::write!(f, "MUL402"),
11433 0x0192 => defmt::write!(f, "MUL403"),
11434 0x0193 => defmt::write!(f, "MUL404"),
11435 0x0194 => defmt::write!(f, "MUL405"),
11436 0x0195 => defmt::write!(f, "MUL406"),
11437 0x0196 => defmt::write!(f, "MUL407"),
11438 0x0197 => defmt::write!(f, "MUL408"),
11439 0x0198 => defmt::write!(f, "MUL409"),
11440 0x0199 => defmt::write!(f, "MUL410"),
11441 0x019a => defmt::write!(f, "MUL411"),
11442 0x019b => defmt::write!(f, "MUL412"),
11443 0x019c => defmt::write!(f, "MUL413"),
11444 0x019d => defmt::write!(f, "MUL414"),
11445 0x019e => defmt::write!(f, "MUL415"),
11446 0x019f => defmt::write!(f, "MUL416"),
11447 0x01a0 => defmt::write!(f, "MUL417"),
11448 0x01a1 => defmt::write!(f, "MUL418"),
11449 0x01a2 => defmt::write!(f, "MUL419"),
11450 0x01a3 => defmt::write!(f, "MUL420"),
11451 0x01a4 => defmt::write!(f, "MUL421"),
11452 0x01a5 => defmt::write!(f, "MUL422"),
11453 0x01a6 => defmt::write!(f, "MUL423"),
11454 0x01a7 => defmt::write!(f, "MUL424"),
11455 0x01a8 => defmt::write!(f, "MUL425"),
11456 0x01a9 => defmt::write!(f, "MUL426"),
11457 0x01aa => defmt::write!(f, "MUL427"),
11458 0x01ab => defmt::write!(f, "MUL428"),
11459 0x01ac => defmt::write!(f, "MUL429"),
11460 0x01ad => defmt::write!(f, "MUL430"),
11461 0x01ae => defmt::write!(f, "MUL431"),
11462 0x01af => defmt::write!(f, "MUL432"),
11463 0x01b0 => defmt::write!(f, "MUL433"),
11464 0x01b1 => defmt::write!(f, "MUL434"),
11465 0x01b2 => defmt::write!(f, "MUL435"),
11466 0x01b3 => defmt::write!(f, "MUL436"),
11467 0x01b4 => defmt::write!(f, "MUL437"),
11468 0x01b5 => defmt::write!(f, "MUL438"),
11469 0x01b6 => defmt::write!(f, "MUL439"),
11470 0x01b7 => defmt::write!(f, "MUL440"),
11471 0x01b8 => defmt::write!(f, "MUL441"),
11472 0x01b9 => defmt::write!(f, "MUL442"),
11473 0x01ba => defmt::write!(f, "MUL443"),
11474 0x01bb => defmt::write!(f, "MUL444"),
11475 0x01bc => defmt::write!(f, "MUL445"),
11476 0x01bd => defmt::write!(f, "MUL446"),
11477 0x01be => defmt::write!(f, "MUL447"),
11478 0x01bf => defmt::write!(f, "MUL448"),
11479 0x01c0 => defmt::write!(f, "MUL449"),
11480 0x01c1 => defmt::write!(f, "MUL450"),
11481 0x01c2 => defmt::write!(f, "MUL451"),
11482 0x01c3 => defmt::write!(f, "MUL452"),
11483 0x01c4 => defmt::write!(f, "MUL453"),
11484 0x01c5 => defmt::write!(f, "MUL454"),
11485 0x01c6 => defmt::write!(f, "MUL455"),
11486 0x01c7 => defmt::write!(f, "MUL456"),
11487 0x01c8 => defmt::write!(f, "MUL457"),
11488 0x01c9 => defmt::write!(f, "MUL458"),
11489 0x01ca => defmt::write!(f, "MUL459"),
11490 0x01cb => defmt::write!(f, "MUL460"),
11491 0x01cc => defmt::write!(f, "MUL461"),
11492 0x01cd => defmt::write!(f, "MUL462"),
11493 0x01ce => defmt::write!(f, "MUL463"),
11494 0x01cf => defmt::write!(f, "MUL464"),
11495 0x01d0 => defmt::write!(f, "MUL465"),
11496 0x01d1 => defmt::write!(f, "MUL466"),
11497 0x01d2 => defmt::write!(f, "MUL467"),
11498 0x01d3 => defmt::write!(f, "MUL468"),
11499 0x01d4 => defmt::write!(f, "MUL469"),
11500 0x01d5 => defmt::write!(f, "MUL470"),
11501 0x01d6 => defmt::write!(f, "MUL471"),
11502 0x01d7 => defmt::write!(f, "MUL472"),
11503 0x01d8 => defmt::write!(f, "MUL473"),
11504 0x01d9 => defmt::write!(f, "MUL474"),
11505 0x01da => defmt::write!(f, "MUL475"),
11506 0x01db => defmt::write!(f, "MUL476"),
11507 0x01dc => defmt::write!(f, "MUL477"),
11508 0x01dd => defmt::write!(f, "MUL478"),
11509 0x01de => defmt::write!(f, "MUL479"),
11510 0x01df => defmt::write!(f, "MUL480"),
11511 0x01e0 => defmt::write!(f, "MUL481"),
11512 0x01e1 => defmt::write!(f, "MUL482"),
11513 0x01e2 => defmt::write!(f, "MUL483"),
11514 0x01e3 => defmt::write!(f, "MUL484"),
11515 0x01e4 => defmt::write!(f, "MUL485"),
11516 0x01e5 => defmt::write!(f, "MUL486"),
11517 0x01e6 => defmt::write!(f, "MUL487"),
11518 0x01e7 => defmt::write!(f, "MUL488"),
11519 0x01e8 => defmt::write!(f, "MUL489"),
11520 0x01e9 => defmt::write!(f, "MUL490"),
11521 0x01ea => defmt::write!(f, "MUL491"),
11522 0x01eb => defmt::write!(f, "MUL492"),
11523 0x01ec => defmt::write!(f, "MUL493"),
11524 0x01ed => defmt::write!(f, "MUL494"),
11525 0x01ee => defmt::write!(f, "MUL495"),
11526 0x01ef => defmt::write!(f, "MUL496"),
11527 0x01f0 => defmt::write!(f, "MUL497"),
11528 0x01f1 => defmt::write!(f, "MUL498"),
11529 0x01f2 => defmt::write!(f, "MUL499"),
11530 0x01f3 => defmt::write!(f, "MUL500"),
11531 0x01f4 => defmt::write!(f, "MUL501"),
11532 0x01f5 => defmt::write!(f, "MUL502"),
11533 0x01f6 => defmt::write!(f, "MUL503"),
11534 0x01f7 => defmt::write!(f, "MUL504"),
11535 0x01f8 => defmt::write!(f, "MUL505"),
11536 0x01f9 => defmt::write!(f, "MUL506"),
11537 0x01fa => defmt::write!(f, "MUL507"),
11538 0x01fb => defmt::write!(f, "MUL508"),
11539 0x01fc => defmt::write!(f, "MUL509"),
11540 0x01fd => defmt::write!(f, "MUL510"),
11541 0x01fe => defmt::write!(f, "MUL511"),
11542 0x01ff => defmt::write!(f, "MUL512"),
11543 other => defmt::write!(f, "0x{:02X}", other),
11544 }
11545 }
11546 }
11547 impl From<u16> for Plln {
11548 #[inline(always)]
11549 fn from(val: u16) -> Plln {
11550 Plln::from_bits(val)
11551 }
11552 }
11553 impl From<Plln> for u16 {
11554 #[inline(always)]
11555 fn from(val: Plln) -> u16 {
11556 Plln::to_bits(val)
11557 }
11558 }
11559 #[repr(u8)]
11560 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
11561 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
11562 pub enum Pllrge {
11563 #[doc = "PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz"]
11564 FREQ_4TO8MHZ = 0x0,
11565 _RESERVED_1 = 0x01,
11566 _RESERVED_2 = 0x02,
11567 #[doc = "PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz"]
11568 FREQ_8TO16MHZ = 0x03,
11569 }
11570 impl Pllrge {
11571 #[inline(always)]
11572 pub const fn from_bits(val: u8) -> Pllrge {
11573 unsafe { core::mem::transmute(val & 0x03) }
11574 }
11575 #[inline(always)]
11576 pub const fn to_bits(self) -> u8 {
11577 unsafe { core::mem::transmute(self) }
11578 }
11579 }
11580 impl From<u8> for Pllrge {
11581 #[inline(always)]
11582 fn from(val: u8) -> Pllrge {
11583 Pllrge::from_bits(val)
11584 }
11585 }
11586 impl From<Pllrge> for u8 {
11587 #[inline(always)]
11588 fn from(val: Pllrge) -> u8 {
11589 Pllrge::to_bits(val)
11590 }
11591 }
11592 #[repr(u8)]
11593 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
11594 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
11595 pub enum Pllsrc {
11596 #[doc = "No clock sent to PLL3"]
11597 DISABLE = 0x0,
11598 #[doc = "MSIS clock selected as PLL3 clock entry"]
11599 MSIS = 0x01,
11600 #[doc = "HSI clock selected as PLL3 clock entry"]
11601 HSI = 0x02,
11602 #[doc = "HSE clock selected as PLL3 clock entry"]
11603 HSE = 0x03,
11604 }
11605 impl Pllsrc {
11606 #[inline(always)]
11607 pub const fn from_bits(val: u8) -> Pllsrc {
11608 unsafe { core::mem::transmute(val & 0x03) }
11609 }
11610 #[inline(always)]
11611 pub const fn to_bits(self) -> u8 {
11612 unsafe { core::mem::transmute(self) }
11613 }
11614 }
11615 impl From<u8> for Pllsrc {
11616 #[inline(always)]
11617 fn from(val: u8) -> Pllsrc {
11618 Pllsrc::from_bits(val)
11619 }
11620 }
11621 impl From<Pllsrc> for u8 {
11622 #[inline(always)]
11623 fn from(val: Pllsrc) -> u8 {
11624 Pllsrc::to_bits(val)
11625 }
11626 }
11627 #[repr(u8)]
11628 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
11629 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
11630 pub enum Ppre {
11631 #[doc = "HCLK not divided"]
11632 DIV1 = 0x0,
11633 _RESERVED_1 = 0x01,
11634 _RESERVED_2 = 0x02,
11635 _RESERVED_3 = 0x03,
11636 #[doc = "HCLK divided by 2"]
11637 DIV2 = 0x04,
11638 #[doc = "HCLK divided by 4"]
11639 DIV4 = 0x05,
11640 #[doc = "HCLK divided by 8"]
11641 DIV8 = 0x06,
11642 #[doc = "HCLK divided by 16"]
11643 DIV16 = 0x07,
11644 }
11645 impl Ppre {
11646 #[inline(always)]
11647 pub const fn from_bits(val: u8) -> Ppre {
11648 unsafe { core::mem::transmute(val & 0x07) }
11649 }
11650 #[inline(always)]
11651 pub const fn to_bits(self) -> u8 {
11652 unsafe { core::mem::transmute(self) }
11653 }
11654 }
11655 impl From<u8> for Ppre {
11656 #[inline(always)]
11657 fn from(val: u8) -> Ppre {
11658 Ppre::from_bits(val)
11659 }
11660 }
11661 impl From<Ppre> for u8 {
11662 #[inline(always)]
11663 fn from(val: Ppre) -> u8 {
11664 Ppre::to_bits(val)
11665 }
11666 }
11667 #[repr(u8)]
11668 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
11669 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
11670 pub enum Rngsel {
11671 #[doc = "HSI48 selected"]
11672 HSI48 = 0x0,
11673 #[doc = "HSI48 / 2 selected, can be used in Range 4"]
11674 HSI48_DIV_2 = 0x01,
11675 #[doc = "HSI selected"]
11676 HSI = 0x02,
11677 _RESERVED_3 = 0x03,
11678 }
11679 impl Rngsel {
11680 #[inline(always)]
11681 pub const fn from_bits(val: u8) -> Rngsel {
11682 unsafe { core::mem::transmute(val & 0x03) }
11683 }
11684 #[inline(always)]
11685 pub const fn to_bits(self) -> u8 {
11686 unsafe { core::mem::transmute(self) }
11687 }
11688 }
11689 impl From<u8> for Rngsel {
11690 #[inline(always)]
11691 fn from(val: u8) -> Rngsel {
11692 Rngsel::from_bits(val)
11693 }
11694 }
11695 impl From<Rngsel> for u8 {
11696 #[inline(always)]
11697 fn from(val: Rngsel) -> u8 {
11698 Rngsel::to_bits(val)
11699 }
11700 }
11701 #[repr(u8)]
11702 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
11703 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
11704 pub enum Rtcsel {
11705 #[doc = "No clock selected"]
11706 DISABLE = 0x0,
11707 #[doc = "LSE oscillator clock selected"]
11708 LSE = 0x01,
11709 #[doc = "LSI oscillator clock selected"]
11710 LSI = 0x02,
11711 #[doc = "HSE oscillator clock divided by 32 selected"]
11712 HSE = 0x03,
11713 }
11714 impl Rtcsel {
11715 #[inline(always)]
11716 pub const fn from_bits(val: u8) -> Rtcsel {
11717 unsafe { core::mem::transmute(val & 0x03) }
11718 }
11719 #[inline(always)]
11720 pub const fn to_bits(self) -> u8 {
11721 unsafe { core::mem::transmute(self) }
11722 }
11723 }
11724 impl From<u8> for Rtcsel {
11725 #[inline(always)]
11726 fn from(val: u8) -> Rtcsel {
11727 Rtcsel::from_bits(val)
11728 }
11729 }
11730 impl From<Rtcsel> for u8 {
11731 #[inline(always)]
11732 fn from(val: Rtcsel) -> u8 {
11733 Rtcsel::to_bits(val)
11734 }
11735 }
11736 #[repr(u8)]
11737 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
11738 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
11739 pub enum Saessel {
11740 #[doc = "SHSI selected"]
11741 SHSI = 0x0,
11742 #[doc = "SHSI / 2 selected, can be used in Range 4"]
11743 SHSI_DIV_2 = 0x01,
11744 }
11745 impl Saessel {
11746 #[inline(always)]
11747 pub const fn from_bits(val: u8) -> Saessel {
11748 unsafe { core::mem::transmute(val & 0x01) }
11749 }
11750 #[inline(always)]
11751 pub const fn to_bits(self) -> u8 {
11752 unsafe { core::mem::transmute(self) }
11753 }
11754 }
11755 impl From<u8> for Saessel {
11756 #[inline(always)]
11757 fn from(val: u8) -> Saessel {
11758 Saessel::from_bits(val)
11759 }
11760 }
11761 impl From<Saessel> for u8 {
11762 #[inline(always)]
11763 fn from(val: Saessel) -> u8 {
11764 Saessel::to_bits(val)
11765 }
11766 }
11767 #[repr(u8)]
11768 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
11769 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
11770 pub enum Saisel {
11771 #[doc = "PLL2 P (pll2_p_ck) selected"]
11772 PLL2_P = 0x0,
11773 #[doc = "PLL3 P (pll3_p_ck) selected"]
11774 PLL3_P = 0x01,
11775 #[doc = "PLL1 P (pll1_p_ck) selected"]
11776 PLL1_P = 0x02,
11777 #[doc = "input pin AUDIOCLK selected"]
11778 AUDIOCLK = 0x03,
11779 #[doc = "HSI clock selected"]
11780 HSI = 0x04,
11781 _RESERVED_5 = 0x05,
11782 _RESERVED_6 = 0x06,
11783 _RESERVED_7 = 0x07,
11784 }
11785 impl Saisel {
11786 #[inline(always)]
11787 pub const fn from_bits(val: u8) -> Saisel {
11788 unsafe { core::mem::transmute(val & 0x07) }
11789 }
11790 #[inline(always)]
11791 pub const fn to_bits(self) -> u8 {
11792 unsafe { core::mem::transmute(self) }
11793 }
11794 }
11795 impl From<u8> for Saisel {
11796 #[inline(always)]
11797 fn from(val: u8) -> Saisel {
11798 Saisel::from_bits(val)
11799 }
11800 }
11801 impl From<Saisel> for u8 {
11802 #[inline(always)]
11803 fn from(val: Saisel) -> u8 {
11804 Saisel::to_bits(val)
11805 }
11806 }
11807 #[repr(u8)]
11808 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
11809 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
11810 pub enum Sdmmcsel {
11811 #[doc = "ICLK clock selected"]
11812 ICLK = 0x0,
11813 #[doc = "PLL1 P (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode)"]
11814 PLL1_P = 0x01,
11815 }
11816 impl Sdmmcsel {
11817 #[inline(always)]
11818 pub const fn from_bits(val: u8) -> Sdmmcsel {
11819 unsafe { core::mem::transmute(val & 0x01) }
11820 }
11821 #[inline(always)]
11822 pub const fn to_bits(self) -> u8 {
11823 unsafe { core::mem::transmute(self) }
11824 }
11825 }
11826 impl From<u8> for Sdmmcsel {
11827 #[inline(always)]
11828 fn from(val: u8) -> Sdmmcsel {
11829 Sdmmcsel::from_bits(val)
11830 }
11831 }
11832 impl From<Sdmmcsel> for u8 {
11833 #[inline(always)]
11834 fn from(val: Sdmmcsel) -> u8 {
11835 Sdmmcsel::to_bits(val)
11836 }
11837 }
11838 #[repr(u8)]
11839 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
11840 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
11841 pub enum Security {
11842 #[doc = "non secure"]
11843 NON_SECURE = 0x0,
11844 #[doc = "secure"]
11845 SECURE = 0x01,
11846 }
11847 impl Security {
11848 #[inline(always)]
11849 pub const fn from_bits(val: u8) -> Security {
11850 unsafe { core::mem::transmute(val & 0x01) }
11851 }
11852 #[inline(always)]
11853 pub const fn to_bits(self) -> u8 {
11854 unsafe { core::mem::transmute(self) }
11855 }
11856 }
11857 impl From<u8> for Security {
11858 #[inline(always)]
11859 fn from(val: u8) -> Security {
11860 Security::from_bits(val)
11861 }
11862 }
11863 impl From<Security> for u8 {
11864 #[inline(always)]
11865 fn from(val: Security) -> u8 {
11866 Security::to_bits(val)
11867 }
11868 }
11869 #[repr(u8)]
11870 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
11871 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
11872 pub enum Spi1sel {
11873 #[doc = "PCLK2 selected"]
11874 PCLK2 = 0x0,
11875 #[doc = "SYSCLK selected"]
11876 SYS = 0x01,
11877 #[doc = "HSI selected"]
11878 HSI = 0x02,
11879 #[doc = "MSIK selected"]
11880 MSIK = 0x03,
11881 }
11882 impl Spi1sel {
11883 #[inline(always)]
11884 pub const fn from_bits(val: u8) -> Spi1sel {
11885 unsafe { core::mem::transmute(val & 0x03) }
11886 }
11887 #[inline(always)]
11888 pub const fn to_bits(self) -> u8 {
11889 unsafe { core::mem::transmute(self) }
11890 }
11891 }
11892 impl From<u8> for Spi1sel {
11893 #[inline(always)]
11894 fn from(val: u8) -> Spi1sel {
11895 Spi1sel::from_bits(val)
11896 }
11897 }
11898 impl From<Spi1sel> for u8 {
11899 #[inline(always)]
11900 fn from(val: Spi1sel) -> u8 {
11901 Spi1sel::to_bits(val)
11902 }
11903 }
11904 #[repr(u8)]
11905 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
11906 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
11907 pub enum Spi2sel {
11908 #[doc = "PCLK2 selected"]
11909 PCLK1 = 0x0,
11910 #[doc = "SYSCLK selected"]
11911 SYS = 0x01,
11912 #[doc = "HSI selected"]
11913 HSI = 0x02,
11914 #[doc = "MSIK selected"]
11915 MSIK = 0x03,
11916 }
11917 impl Spi2sel {
11918 #[inline(always)]
11919 pub const fn from_bits(val: u8) -> Spi2sel {
11920 unsafe { core::mem::transmute(val & 0x03) }
11921 }
11922 #[inline(always)]
11923 pub const fn to_bits(self) -> u8 {
11924 unsafe { core::mem::transmute(self) }
11925 }
11926 }
11927 impl From<u8> for Spi2sel {
11928 #[inline(always)]
11929 fn from(val: u8) -> Spi2sel {
11930 Spi2sel::from_bits(val)
11931 }
11932 }
11933 impl From<Spi2sel> for u8 {
11934 #[inline(always)]
11935 fn from(val: Spi2sel) -> u8 {
11936 Spi2sel::to_bits(val)
11937 }
11938 }
11939 #[repr(u8)]
11940 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
11941 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
11942 pub enum Spi3sel {
11943 #[doc = "PCLK2 selected"]
11944 PCLK3 = 0x0,
11945 #[doc = "SYSCLK selected"]
11946 SYS = 0x01,
11947 #[doc = "HSI selected"]
11948 HSI = 0x02,
11949 #[doc = "MSIK selected"]
11950 MSIK = 0x03,
11951 }
11952 impl Spi3sel {
11953 #[inline(always)]
11954 pub const fn from_bits(val: u8) -> Spi3sel {
11955 unsafe { core::mem::transmute(val & 0x03) }
11956 }
11957 #[inline(always)]
11958 pub const fn to_bits(self) -> u8 {
11959 unsafe { core::mem::transmute(self) }
11960 }
11961 }
11962 impl From<u8> for Spi3sel {
11963 #[inline(always)]
11964 fn from(val: u8) -> Spi3sel {
11965 Spi3sel::from_bits(val)
11966 }
11967 }
11968 impl From<Spi3sel> for u8 {
11969 #[inline(always)]
11970 fn from(val: Spi3sel) -> u8 {
11971 Spi3sel::to_bits(val)
11972 }
11973 }
11974 #[repr(u8)]
11975 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
11976 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
11977 pub enum Stopkerwuck {
11978 #[doc = "MSIK oscillator automatically enabled when exiting Stop mode"]
11979 MSIK = 0x0,
11980 #[doc = "HSI oscillator automatically enabled when exiting Stop mode"]
11981 HSI = 0x01,
11982 }
11983 impl Stopkerwuck {
11984 #[inline(always)]
11985 pub const fn from_bits(val: u8) -> Stopkerwuck {
11986 unsafe { core::mem::transmute(val & 0x01) }
11987 }
11988 #[inline(always)]
11989 pub const fn to_bits(self) -> u8 {
11990 unsafe { core::mem::transmute(self) }
11991 }
11992 }
11993 impl From<u8> for Stopkerwuck {
11994 #[inline(always)]
11995 fn from(val: u8) -> Stopkerwuck {
11996 Stopkerwuck::from_bits(val)
11997 }
11998 }
11999 impl From<Stopkerwuck> for u8 {
12000 #[inline(always)]
12001 fn from(val: Stopkerwuck) -> u8 {
12002 Stopkerwuck::to_bits(val)
12003 }
12004 }
12005 #[repr(u8)]
12006 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
12007 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
12008 pub enum Stopwuck {
12009 #[doc = "MSIS oscillator selected as wakeup from stop clock and CSS backup clock"]
12010 MSIS = 0x0,
12011 #[doc = "HSI oscillator selected as wakeup from stop clock and CSS backup clock"]
12012 HSI = 0x01,
12013 }
12014 impl Stopwuck {
12015 #[inline(always)]
12016 pub const fn from_bits(val: u8) -> Stopwuck {
12017 unsafe { core::mem::transmute(val & 0x01) }
12018 }
12019 #[inline(always)]
12020 pub const fn to_bits(self) -> u8 {
12021 unsafe { core::mem::transmute(self) }
12022 }
12023 }
12024 impl From<u8> for Stopwuck {
12025 #[inline(always)]
12026 fn from(val: u8) -> Stopwuck {
12027 Stopwuck::from_bits(val)
12028 }
12029 }
12030 impl From<Stopwuck> for u8 {
12031 #[inline(always)]
12032 fn from(val: Stopwuck) -> u8 {
12033 Stopwuck::to_bits(val)
12034 }
12035 }
12036 #[repr(u8)]
12037 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
12038 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
12039 pub enum Sw {
12040 #[doc = "MSIS selected as system clock"]
12041 MSIS = 0x0,
12042 #[doc = "HSI selected as system clock"]
12043 HSI = 0x01,
12044 #[doc = "HSE selected as system clock"]
12045 HSE = 0x02,
12046 #[doc = "PLL pll1_r_ck selected as system clock"]
12047 PLL1_R = 0x03,
12048 }
12049 impl Sw {
12050 #[inline(always)]
12051 pub const fn from_bits(val: u8) -> Sw {
12052 unsafe { core::mem::transmute(val & 0x03) }
12053 }
12054 #[inline(always)]
12055 pub const fn to_bits(self) -> u8 {
12056 unsafe { core::mem::transmute(self) }
12057 }
12058 }
12059 impl From<u8> for Sw {
12060 #[inline(always)]
12061 fn from(val: u8) -> Sw {
12062 Sw::from_bits(val)
12063 }
12064 }
12065 impl From<Sw> for u8 {
12066 #[inline(always)]
12067 fn from(val: Sw) -> u8 {
12068 Sw::to_bits(val)
12069 }
12070 }
12071 #[repr(u8)]
12072 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
12073 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
12074 pub enum Systicksel {
12075 #[doc = "HCLK/8 selected"]
12076 HCLK1_DIV_8 = 0x0,
12077 #[doc = "LSI selected"]
12078 LSI = 0x01,
12079 #[doc = "LSE selected"]
12080 LSE = 0x02,
12081 _RESERVED_3 = 0x03,
12082 }
12083 impl Systicksel {
12084 #[inline(always)]
12085 pub const fn from_bits(val: u8) -> Systicksel {
12086 unsafe { core::mem::transmute(val & 0x03) }
12087 }
12088 #[inline(always)]
12089 pub const fn to_bits(self) -> u8 {
12090 unsafe { core::mem::transmute(self) }
12091 }
12092 }
12093 impl From<u8> for Systicksel {
12094 #[inline(always)]
12095 fn from(val: u8) -> Systicksel {
12096 Systicksel::from_bits(val)
12097 }
12098 }
12099 impl From<Systicksel> for u8 {
12100 #[inline(always)]
12101 fn from(val: Systicksel) -> u8 {
12102 Systicksel::to_bits(val)
12103 }
12104 }
12105 #[repr(u8)]
12106 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
12107 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
12108 pub enum Timicsel {
12109 #[doc = "No sources can be selected by TIM16, TIM17 and LPTIM2 as internal input capture"]
12110 DISABLE = 0x0,
12111 _RESERVED_1 = 0x01,
12112 _RESERVED_2 = 0x02,
12113 _RESERVED_3 = 0x03,
12114 #[doc = "HSI/256, MSIS/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture"]
12115 HSI256_MSIS1024_MSIS4 = 0x04,
12116 #[doc = "HSI/256, MSIS/1024 and MSIK/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture"]
12117 HSI256_MSIS1024_MSIK4 = 0x05,
12118 #[doc = "HSI/256, MSIK/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture"]
12119 HSI256_MSIK1024_MSIS4 = 0x06,
12120 #[doc = "HSI/256, MSIK/1024 and MSIK/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture"]
12121 HSI256_MSIK1024_MSIK4 = 0x07,
12122 }
12123 impl Timicsel {
12124 #[inline(always)]
12125 pub const fn from_bits(val: u8) -> Timicsel {
12126 unsafe { core::mem::transmute(val & 0x07) }
12127 }
12128 #[inline(always)]
12129 pub const fn to_bits(self) -> u8 {
12130 unsafe { core::mem::transmute(self) }
12131 }
12132 }
12133 impl From<u8> for Timicsel {
12134 #[inline(always)]
12135 fn from(val: u8) -> Timicsel {
12136 Timicsel::from_bits(val)
12137 }
12138 }
12139 impl From<Timicsel> for u8 {
12140 #[inline(always)]
12141 fn from(val: Timicsel) -> u8 {
12142 Timicsel::to_bits(val)
12143 }
12144 }
12145 #[repr(u8)]
12146 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
12147 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
12148 pub enum Usart1sel {
12149 #[doc = "PCLK2 selected"]
12150 PCLK2 = 0x0,
12151 #[doc = "SYSCLK selected"]
12152 SYS = 0x01,
12153 #[doc = "HSI selected"]
12154 HSI = 0x02,
12155 #[doc = "LSE selected"]
12156 LSE = 0x03,
12157 }
12158 impl Usart1sel {
12159 #[inline(always)]
12160 pub const fn from_bits(val: u8) -> Usart1sel {
12161 unsafe { core::mem::transmute(val & 0x03) }
12162 }
12163 #[inline(always)]
12164 pub const fn to_bits(self) -> u8 {
12165 unsafe { core::mem::transmute(self) }
12166 }
12167 }
12168 impl From<u8> for Usart1sel {
12169 #[inline(always)]
12170 fn from(val: u8) -> Usart1sel {
12171 Usart1sel::from_bits(val)
12172 }
12173 }
12174 impl From<Usart1sel> for u8 {
12175 #[inline(always)]
12176 fn from(val: Usart1sel) -> u8 {
12177 Usart1sel::to_bits(val)
12178 }
12179 }
12180 #[repr(u8)]
12181 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
12182 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
12183 pub enum Usartsel {
12184 #[doc = "PCLK1 selected"]
12185 PCLK1 = 0x0,
12186 #[doc = "SYSCLK selected"]
12187 SYS = 0x01,
12188 #[doc = "HSI selected"]
12189 HSI = 0x02,
12190 #[doc = "LSE selected"]
12191 LSE = 0x03,
12192 }
12193 impl Usartsel {
12194 #[inline(always)]
12195 pub const fn from_bits(val: u8) -> Usartsel {
12196 unsafe { core::mem::transmute(val & 0x03) }
12197 }
12198 #[inline(always)]
12199 pub const fn to_bits(self) -> u8 {
12200 unsafe { core::mem::transmute(self) }
12201 }
12202 }
12203 impl From<u8> for Usartsel {
12204 #[inline(always)]
12205 fn from(val: u8) -> Usartsel {
12206 Usartsel::from_bits(val)
12207 }
12208 }
12209 impl From<Usartsel> for u8 {
12210 #[inline(always)]
12211 fn from(val: Usartsel) -> u8 {
12212 Usartsel::to_bits(val)
12213 }
12214 }
12215}
12216