1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "Secure advanced encryption standard hardware accelerator."]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Saes {
9 ptr: *mut u8,
10}
11unsafe impl Send for Saes {}
12unsafe impl Sync for Saes {}
13impl Saes {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "SAES control register."]
23 #[inline(always)]
24 pub const fn cr(self) -> crate::common::Reg<regs::Cr, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "SAES status register."]
28 #[inline(always)]
29 pub const fn sr(self) -> crate::common::Reg<regs::Sr, crate::common::RW> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
31 }
32 #[doc = "SAES data input register."]
33 #[inline(always)]
34 pub const fn dinr(self) -> crate::common::Reg<u32, crate::common::RW> {
35 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
36 }
37 #[doc = "SAES data output register."]
38 #[inline(always)]
39 pub const fn doutr(self) -> crate::common::Reg<u32, crate::common::RW> {
40 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
41 }
42 #[doc = "SAES key register 0."]
43 #[inline(always)]
44 pub const fn keyr(self, n: usize) -> crate::common::Reg<u32, crate::common::RW> {
45 assert!(n < 8usize);
46 unsafe {
47 crate::common::Reg::from_ptr(
48 self.ptr.add(
49 0x10usize + ([0usize, 4usize, 8usize, 12usize, 32usize, 36usize, 40usize, 44usize][n] as usize),
50 ) as _,
51 )
52 }
53 }
54 #[doc = "SAES initialization vector register 0."]
55 #[inline(always)]
56 pub const fn ivr(self, n: usize) -> crate::common::Reg<u32, crate::common::RW> {
57 assert!(n < 4usize);
58 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize + n * 4usize) as _) }
59 }
60 #[doc = "SAES suspend registers."]
61 #[inline(always)]
62 pub const fn suspr(self, n: usize) -> crate::common::Reg<u32, crate::common::RW> {
63 assert!(n < 8usize);
64 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize + n * 4usize) as _) }
65 }
66 #[doc = "SAES interrupt enable register."]
67 #[inline(always)]
68 pub const fn ier(self) -> crate::common::Reg<regs::Ier, crate::common::RW> {
69 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0300usize) as _) }
70 }
71 #[doc = "SAES interrupt status register."]
72 #[inline(always)]
73 pub const fn isr(self) -> crate::common::Reg<regs::Isr, crate::common::RW> {
74 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0304usize) as _) }
75 }
76 #[doc = "SAES interrupt clear register."]
77 #[inline(always)]
78 pub const fn icr(self) -> crate::common::Reg<regs::Icr, crate::common::RW> {
79 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0308usize) as _) }
80 }
81}
82pub mod regs {
83 #[doc = "SAES control register."]
84 #[repr(transparent)]
85 #[derive(Copy, Clone, Eq, PartialEq)]
86 pub struct Cr(pub u32);
87 impl Cr {
88 #[doc = "SAES enable This bit enables/disables the SAES peripheral: At any moment, clearing then setting the bit re-initializes the SAES peripheral. This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2) and upon the completion of GCM/GMAC/CCM initial phase. The bit cannot be set as long as KEYVALID = 0 nor along with the following settings: KMOD = 01 + CHMOD = 011 and KMOD = 01 + CHMOD = 010 + MODE = 00. Note: With KMOD\\[1:0\\]
89other than 00, use the IPRST bit rather than the bit EN."]
90 #[inline(always)]
91 pub const fn en(&self) -> bool {
92 let val = (self.0 >> 0usize) & 0x01;
93 val != 0
94 }
95 #[doc = "SAES enable This bit enables/disables the SAES peripheral: At any moment, clearing then setting the bit re-initializes the SAES peripheral. This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2) and upon the completion of GCM/GMAC/CCM initial phase. The bit cannot be set as long as KEYVALID = 0 nor along with the following settings: KMOD = 01 + CHMOD = 011 and KMOD = 01 + CHMOD = 010 + MODE = 00. Note: With KMOD\\[1:0\\]
96other than 00, use the IPRST bit rather than the bit EN."]
97 #[inline(always)]
98 pub fn set_en(&mut self, val: bool) {
99 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
100 }
101 #[doc = "Data type selection This bitfield defines the format of data written in the SAES_DINR register or read from the SAES_DOUTR register, through selecting the mode of data swapping: For more details, refer to . Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access."]
102 #[inline(always)]
103 pub const fn datatype(&self) -> super::vals::Datatype {
104 let val = (self.0 >> 1usize) & 0x03;
105 super::vals::Datatype::from_bits(val as u8)
106 }
107 #[doc = "Data type selection This bitfield defines the format of data written in the SAES_DINR register or read from the SAES_DOUTR register, through selecting the mode of data swapping: For more details, refer to . Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access."]
108 #[inline(always)]
109 pub fn set_datatype(&mut self, val: super::vals::Datatype) {
110 self.0 = (self.0 & !(0x03 << 1usize)) | (((val.to_bits() as u32) & 0x03) << 1usize);
111 }
112 #[doc = "SAES operating mode This bitfield selects the SAES operating mode: Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access."]
113 #[inline(always)]
114 pub const fn mode(&self) -> super::vals::Mode {
115 let val = (self.0 >> 3usize) & 0x03;
116 super::vals::Mode::from_bits(val as u8)
117 }
118 #[doc = "SAES operating mode This bitfield selects the SAES operating mode: Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access."]
119 #[inline(always)]
120 pub fn set_mode(&mut self, val: super::vals::Mode) {
121 self.0 = (self.0 & !(0x03 << 3usize)) | (((val.to_bits() as u32) & 0x03) << 3usize);
122 }
123 #[doc = "Chaining mode selection This bitfield selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access."]
124 #[inline(always)]
125 pub const fn chmod(&self) -> super::vals::Chmod {
126 let mut val = 0;
127 val += (((self.0 >> 5usize) & 0x03) << 0usize);
128 val += (((self.0 >> 16usize) & 0x01) << 2usize);
129 super::vals::Chmod::from_bits(val as u8)
130 }
131 #[doc = "Chaining mode selection This bitfield selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access."]
132 #[inline(always)]
133 pub fn set_chmod(&mut self, val: super::vals::Chmod) {
134 self.0 = (self.0 & !(0x03 << 5usize)) | (((val.to_bits() as u32 >> 0usize) & 0x03) << 5usize);
135 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.to_bits() as u32 >> 2usize) & 0x01) << 16usize);
136 }
137 #[doc = "DMA input enable This bit enables/disables data transferring with DMA, in the input phase: When the bit is set, DMA requests are automatically generated by SAES during the input data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE\\[1:0\\]
138bitfield. It is not effective for Mode 2 (key derivation)."]
139 #[inline(always)]
140 pub const fn dmainen(&self) -> bool {
141 let val = (self.0 >> 11usize) & 0x01;
142 val != 0
143 }
144 #[doc = "DMA input enable This bit enables/disables data transferring with DMA, in the input phase: When the bit is set, DMA requests are automatically generated by SAES during the input data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE\\[1:0\\]
145bitfield. It is not effective for Mode 2 (key derivation)."]
146 #[inline(always)]
147 pub fn set_dmainen(&mut self, val: bool) {
148 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
149 }
150 #[doc = "DMA output enable This bit enables/disables data transferring with DMA, in the output phase: When the bit is set, DMA requests are automatically generated by SAES during the output data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE\\[1:0\\]
151bitfield. It is not effective for Mode 2 (key derivation)."]
152 #[inline(always)]
153 pub const fn dmaouten(&self) -> bool {
154 let val = (self.0 >> 12usize) & 0x01;
155 val != 0
156 }
157 #[doc = "DMA output enable This bit enables/disables data transferring with DMA, in the output phase: When the bit is set, DMA requests are automatically generated by SAES during the output data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE\\[1:0\\]
158bitfield. It is not effective for Mode 2 (key derivation)."]
159 #[inline(always)]
160 pub fn set_dmaouten(&mut self, val: bool) {
161 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
162 }
163 #[doc = "Key size selection This bitfield defines the length of the key used in the SAES cryptographic core, in bits: When KMOD\\[1:0\\]=01 or 10 KEYSIZE also defines the length of the key to encrypt or decrypt. Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access."]
164 #[inline(always)]
165 pub const fn keysize(&self) -> super::vals::Keysize {
166 let val = (self.0 >> 18usize) & 0x01;
167 super::vals::Keysize::from_bits(val as u8)
168 }
169 #[doc = "Key size selection This bitfield defines the length of the key used in the SAES cryptographic core, in bits: When KMOD\\[1:0\\]=01 or 10 KEYSIZE also defines the length of the key to encrypt or decrypt. Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access."]
170 #[inline(always)]
171 pub fn set_keysize(&mut self, val: super::vals::Keysize) {
172 self.0 = (self.0 & !(0x01 << 18usize)) | (((val.to_bits() as u32) & 0x01) << 18usize);
173 }
174 #[doc = "Key protection When set, hardware-based key protection is enabled. Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access."]
175 #[inline(always)]
176 pub const fn keyprot(&self) -> bool {
177 let val = (self.0 >> 19usize) & 0x01;
178 val != 0
179 }
180 #[doc = "Key protection When set, hardware-based key protection is enabled. Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access."]
181 #[inline(always)]
182 pub fn set_keyprot(&mut self, val: bool) {
183 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
184 }
185 #[doc = "Key mode selection The bitfield defines how the SAES key can be used by the application: Others: Reserved With normal key selection, the key registers are freely usable, no specific usage or protection applies to SAES_DIN and SAES_DOUT registers. With wrapped key selection, the key loaded in key registers can only be used to encrypt or decrypt AES keys. Hence, when a decryption is selected in Wrapped-key mode read-as-zero SAES_DOUT register is automatically loaded into SAES key registers after a successful decryption process. With shared key selection, after a successful decryption process, SAES key registers are shared with the peripheral described in KSHAREID(1:0\\]
186bitfield. This sharing is valid only while KMOD\\[1:0\\]=10 and KEYVALID = 1. When a decryption is selected, read-as-zero SAES_DOUT register is automatically loaded into SAES key registers after a successful decryption process. With KMOD\\[1:0\\]
187other than zero, any attempt to configure the SAES peripheral for use by an application belonging to a different security domain (secure or non-secure) results in automatic key erasure and setting of the KEIF flag. Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access."]
188 #[inline(always)]
189 pub const fn kmod(&self) -> super::vals::Kmod {
190 let val = (self.0 >> 24usize) & 0x03;
191 super::vals::Kmod::from_bits(val as u8)
192 }
193 #[doc = "Key mode selection The bitfield defines how the SAES key can be used by the application: Others: Reserved With normal key selection, the key registers are freely usable, no specific usage or protection applies to SAES_DIN and SAES_DOUT registers. With wrapped key selection, the key loaded in key registers can only be used to encrypt or decrypt AES keys. Hence, when a decryption is selected in Wrapped-key mode read-as-zero SAES_DOUT register is automatically loaded into SAES key registers after a successful decryption process. With shared key selection, after a successful decryption process, SAES key registers are shared with the peripheral described in KSHAREID(1:0\\]
194bitfield. This sharing is valid only while KMOD\\[1:0\\]=10 and KEYVALID = 1. When a decryption is selected, read-as-zero SAES_DOUT register is automatically loaded into SAES key registers after a successful decryption process. With KMOD\\[1:0\\]
195other than zero, any attempt to configure the SAES peripheral for use by an application belonging to a different security domain (secure or non-secure) results in automatic key erasure and setting of the KEIF flag. Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access."]
196 #[inline(always)]
197 pub fn set_kmod(&mut self, val: super::vals::Kmod) {
198 self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize);
199 }
200 #[doc = "Key share identification This bitfield defines, at the end of a decryption process with KMOD\\[1:0\\]=10 (shared key), which target can read the SAES key registers using a dedicated hardware bus. Others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access."]
201 #[inline(always)]
202 pub const fn kshareid(&self) -> super::vals::Kshareid {
203 let val = (self.0 >> 26usize) & 0x03;
204 super::vals::Kshareid::from_bits(val as u8)
205 }
206 #[doc = "Key share identification This bitfield defines, at the end of a decryption process with KMOD\\[1:0\\]=10 (shared key), which target can read the SAES key registers using a dedicated hardware bus. Others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access."]
207 #[inline(always)]
208 pub fn set_kshareid(&mut self, val: super::vals::Kshareid) {
209 self.0 = (self.0 & !(0x03 << 26usize)) | (((val.to_bits() as u32) & 0x03) << 26usize);
210 }
211 #[doc = "Key selection The bitfield defines the source of the key information to use in the AES cryptographic core. Others: Reserved (if used, unfreeze SAES with IPRST) When KEYSEL is different from zero, selected key value is available in key registers when BUSY bit is cleared and KEYVALID is set in the SAES_SR register. Otherwise, the key error flag KEIF is set. Repeated writing of KEYSEL\\[2:0\\]
212with the same non-zero value only triggers the loading of DHUK or BHK if KEYVALID = 0. When the application software changes the key selection by writing the KEYSEL\\[2:0\\]
213bitfield, the key registers are immediately erased and the KEYVALID flag cleared. At the end of the decryption process, if KMOD\\[1:0\\]
214is other than zero, KEYSEL\\[2:0\\]
215is cleared. With the bitfield value other than zero and KEYVALID set, the application cannot transfer the ownership of SAES with a loaded key to an application running in another security context (such as secure, non-secure). More specifically, when security of an access to any register does not match the information recorded by SAES, the KEIF flag is set. Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access."]
216 #[inline(always)]
217 pub const fn keysel(&self) -> super::vals::Keysel {
218 let val = (self.0 >> 28usize) & 0x07;
219 super::vals::Keysel::from_bits(val as u8)
220 }
221 #[doc = "Key selection The bitfield defines the source of the key information to use in the AES cryptographic core. Others: Reserved (if used, unfreeze SAES with IPRST) When KEYSEL is different from zero, selected key value is available in key registers when BUSY bit is cleared and KEYVALID is set in the SAES_SR register. Otherwise, the key error flag KEIF is set. Repeated writing of KEYSEL\\[2:0\\]
222with the same non-zero value only triggers the loading of DHUK or BHK if KEYVALID = 0. When the application software changes the key selection by writing the KEYSEL\\[2:0\\]
223bitfield, the key registers are immediately erased and the KEYVALID flag cleared. At the end of the decryption process, if KMOD\\[1:0\\]
224is other than zero, KEYSEL\\[2:0\\]
225is cleared. With the bitfield value other than zero and KEYVALID set, the application cannot transfer the ownership of SAES with a loaded key to an application running in another security context (such as secure, non-secure). More specifically, when security of an access to any register does not match the information recorded by SAES, the KEIF flag is set. Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access."]
226 #[inline(always)]
227 pub fn set_keysel(&mut self, val: super::vals::Keysel) {
228 self.0 = (self.0 & !(0x07 << 28usize)) | (((val.to_bits() as u32) & 0x07) << 28usize);
229 }
230 #[doc = "SAES peripheral software reset Setting the bit resets the SAES peripheral, putting all registers to their default values, except the IPRST bit itself and the SAES_DPACFG register. Hence, any key-relative data is lost. For this reason, it is recommended to set the bit before handing over the SAES to a less secure application. The bit must be low while writing any configuration registers."]
231 #[inline(always)]
232 pub const fn iprst(&self) -> bool {
233 let val = (self.0 >> 31usize) & 0x01;
234 val != 0
235 }
236 #[doc = "SAES peripheral software reset Setting the bit resets the SAES peripheral, putting all registers to their default values, except the IPRST bit itself and the SAES_DPACFG register. Hence, any key-relative data is lost. For this reason, it is recommended to set the bit before handing over the SAES to a less secure application. The bit must be low while writing any configuration registers."]
237 #[inline(always)]
238 pub fn set_iprst(&mut self, val: bool) {
239 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
240 }
241 }
242 impl Default for Cr {
243 #[inline(always)]
244 fn default() -> Cr {
245 Cr(0)
246 }
247 }
248 impl core::fmt::Debug for Cr {
249 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
250 f.debug_struct("Cr")
251 .field("en", &self.en())
252 .field("datatype", &self.datatype())
253 .field("mode", &self.mode())
254 .field("chmod", &self.chmod())
255 .field("dmainen", &self.dmainen())
256 .field("dmaouten", &self.dmaouten())
257 .field("keysize", &self.keysize())
258 .field("keyprot", &self.keyprot())
259 .field("kmod", &self.kmod())
260 .field("kshareid", &self.kshareid())
261 .field("keysel", &self.keysel())
262 .field("iprst", &self.iprst())
263 .finish()
264 }
265 }
266 #[cfg(feature = "defmt")]
267 impl defmt::Format for Cr {
268 fn format(&self, f: defmt::Formatter) {
269 #[derive(defmt :: Format)]
270 struct Cr {
271 en: bool,
272 datatype: super::vals::Datatype,
273 mode: super::vals::Mode,
274 chmod: super::vals::Chmod,
275 dmainen: bool,
276 dmaouten: bool,
277 keysize: super::vals::Keysize,
278 keyprot: bool,
279 kmod: super::vals::Kmod,
280 kshareid: super::vals::Kshareid,
281 keysel: super::vals::Keysel,
282 iprst: bool,
283 }
284 let proxy = Cr {
285 en: self.en(),
286 datatype: self.datatype(),
287 mode: self.mode(),
288 chmod: self.chmod(),
289 dmainen: self.dmainen(),
290 dmaouten: self.dmaouten(),
291 keysize: self.keysize(),
292 keyprot: self.keyprot(),
293 kmod: self.kmod(),
294 kshareid: self.kshareid(),
295 keysel: self.keysel(),
296 iprst: self.iprst(),
297 };
298 defmt::write!(f, "{}", proxy)
299 }
300 }
301 #[doc = "SAES interrupt clear register."]
302 #[repr(transparent)]
303 #[derive(Copy, Clone, Eq, PartialEq)]
304 pub struct Icr(pub u32);
305 impl Icr {
306 #[doc = "Computation complete flag clear Setting this bit clears the CCF status bit of the SAES_SR and SAES_ISR registers."]
307 #[inline(always)]
308 pub const fn ccf(&self) -> bool {
309 let val = (self.0 >> 0usize) & 0x01;
310 val != 0
311 }
312 #[doc = "Computation complete flag clear Setting this bit clears the CCF status bit of the SAES_SR and SAES_ISR registers."]
313 #[inline(always)]
314 pub fn set_ccf(&mut self, val: bool) {
315 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
316 }
317 #[doc = "Read or write error interrupt flag clear Setting this bit clears the RWEIF status bit of the SAES_ISR register, and both RDERR and WRERR flags in the SAES_SR register."]
318 #[inline(always)]
319 pub const fn rweif(&self) -> bool {
320 let val = (self.0 >> 1usize) & 0x01;
321 val != 0
322 }
323 #[doc = "Read or write error interrupt flag clear Setting this bit clears the RWEIF status bit of the SAES_ISR register, and both RDERR and WRERR flags in the SAES_SR register."]
324 #[inline(always)]
325 pub fn set_rweif(&mut self, val: bool) {
326 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
327 }
328 #[doc = "Key error interrupt flag clear Setting this bit clears the KEIF status bit of the SAES_ISR register."]
329 #[inline(always)]
330 pub const fn keif(&self) -> bool {
331 let val = (self.0 >> 2usize) & 0x01;
332 val != 0
333 }
334 #[doc = "Key error interrupt flag clear Setting this bit clears the KEIF status bit of the SAES_ISR register."]
335 #[inline(always)]
336 pub fn set_keif(&mut self, val: bool) {
337 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
338 }
339 #[doc = "RNG error interrupt flag clear Application must set this bit to clear the RNGEIF status bit in SAES_ISR register."]
340 #[inline(always)]
341 pub const fn rngeif(&self) -> bool {
342 let val = (self.0 >> 3usize) & 0x01;
343 val != 0
344 }
345 #[doc = "RNG error interrupt flag clear Application must set this bit to clear the RNGEIF status bit in SAES_ISR register."]
346 #[inline(always)]
347 pub fn set_rngeif(&mut self, val: bool) {
348 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
349 }
350 }
351 impl Default for Icr {
352 #[inline(always)]
353 fn default() -> Icr {
354 Icr(0)
355 }
356 }
357 impl core::fmt::Debug for Icr {
358 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
359 f.debug_struct("Icr")
360 .field("ccf", &self.ccf())
361 .field("rweif", &self.rweif())
362 .field("keif", &self.keif())
363 .field("rngeif", &self.rngeif())
364 .finish()
365 }
366 }
367 #[cfg(feature = "defmt")]
368 impl defmt::Format for Icr {
369 fn format(&self, f: defmt::Formatter) {
370 #[derive(defmt :: Format)]
371 struct Icr {
372 ccf: bool,
373 rweif: bool,
374 keif: bool,
375 rngeif: bool,
376 }
377 let proxy = Icr {
378 ccf: self.ccf(),
379 rweif: self.rweif(),
380 keif: self.keif(),
381 rngeif: self.rngeif(),
382 };
383 defmt::write!(f, "{}", proxy)
384 }
385 }
386 #[doc = "SAES interrupt enable register."]
387 #[repr(transparent)]
388 #[derive(Copy, Clone, Eq, PartialEq)]
389 pub struct Ier(pub u32);
390 impl Ier {
391 #[doc = "Computation complete flag interrupt enable This bit enables or disables (masks) the SAES interrupt generation when CCF (computation complete flag) is set."]
392 #[inline(always)]
393 pub const fn ccfie(&self) -> bool {
394 let val = (self.0 >> 0usize) & 0x01;
395 val != 0
396 }
397 #[doc = "Computation complete flag interrupt enable This bit enables or disables (masks) the SAES interrupt generation when CCF (computation complete flag) is set."]
398 #[inline(always)]
399 pub fn set_ccfie(&mut self, val: bool) {
400 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
401 }
402 #[doc = "Read or write error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when RWEIF (read and/or write error flag) is set."]
403 #[inline(always)]
404 pub const fn rweie(&self) -> bool {
405 let val = (self.0 >> 1usize) & 0x01;
406 val != 0
407 }
408 #[doc = "Read or write error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when RWEIF (read and/or write error flag) is set."]
409 #[inline(always)]
410 pub fn set_rweie(&mut self, val: bool) {
411 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
412 }
413 #[doc = "Key error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when KEIF (key error flag) is set."]
414 #[inline(always)]
415 pub const fn keie(&self) -> bool {
416 let val = (self.0 >> 2usize) & 0x01;
417 val != 0
418 }
419 #[doc = "Key error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when KEIF (key error flag) is set."]
420 #[inline(always)]
421 pub fn set_keie(&mut self, val: bool) {
422 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
423 }
424 #[doc = "RNG error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when RNGEIF (RNG error flag) is set."]
425 #[inline(always)]
426 pub const fn rngeie(&self) -> bool {
427 let val = (self.0 >> 3usize) & 0x01;
428 val != 0
429 }
430 #[doc = "RNG error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when RNGEIF (RNG error flag) is set."]
431 #[inline(always)]
432 pub fn set_rngeie(&mut self, val: bool) {
433 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
434 }
435 }
436 impl Default for Ier {
437 #[inline(always)]
438 fn default() -> Ier {
439 Ier(0)
440 }
441 }
442 impl core::fmt::Debug for Ier {
443 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
444 f.debug_struct("Ier")
445 .field("ccfie", &self.ccfie())
446 .field("rweie", &self.rweie())
447 .field("keie", &self.keie())
448 .field("rngeie", &self.rngeie())
449 .finish()
450 }
451 }
452 #[cfg(feature = "defmt")]
453 impl defmt::Format for Ier {
454 fn format(&self, f: defmt::Formatter) {
455 #[derive(defmt :: Format)]
456 struct Ier {
457 ccfie: bool,
458 rweie: bool,
459 keie: bool,
460 rngeie: bool,
461 }
462 let proxy = Ier {
463 ccfie: self.ccfie(),
464 rweie: self.rweie(),
465 keie: self.keie(),
466 rngeie: self.rngeie(),
467 };
468 defmt::write!(f, "{}", proxy)
469 }
470 }
471 #[doc = "SAES interrupt status register."]
472 #[repr(transparent)]
473 #[derive(Copy, Clone, Eq, PartialEq)]
474 pub struct Isr(pub u32);
475 impl Isr {
476 #[doc = "Computation complete flag This flag indicates whether the computation is completed: The flag is set by hardware upon the completion of the computation. It is cleared by software, upon setting the CCF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the SAES_IER register. The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1."]
477 #[inline(always)]
478 pub const fn ccf(&self) -> bool {
479 let val = (self.0 >> 0usize) & 0x01;
480 val != 0
481 }
482 #[doc = "Computation complete flag This flag indicates whether the computation is completed: The flag is set by hardware upon the completion of the computation. It is cleared by software, upon setting the CCF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the SAES_IER register. The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1."]
483 #[inline(always)]
484 pub fn set_ccf(&mut self, val: bool) {
485 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
486 }
487 #[doc = "Read or write error interrupt flag This read-only bit is set by hardware when a RDERR or a WRERR error flag is set in the SAES_SR register. RWEIF bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RWEIE bit has been previously set in the SAES_IER register. This flags has no meaning when key derivation mode is selected."]
488 #[inline(always)]
489 pub const fn rweif(&self) -> bool {
490 let val = (self.0 >> 1usize) & 0x01;
491 val != 0
492 }
493 #[doc = "Read or write error interrupt flag This read-only bit is set by hardware when a RDERR or a WRERR error flag is set in the SAES_SR register. RWEIF bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RWEIE bit has been previously set in the SAES_IER register. This flags has no meaning when key derivation mode is selected."]
494 #[inline(always)]
495 pub fn set_rweif(&mut self, val: bool) {
496 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
497 }
498 #[doc = "Key error interrupt flag This read-only bit is set by hardware when key information failed to load into key registers or key register usage is forbidden. Setting the corresponding bit of the SAES_ICR register clears the KEIF and generates interrupt if the KEIE bit of the SAES_IER register is set. KEIF is triggered upon any of the following errors: SAES fails to load the DHUK (KEYSEL = 001 or 100). SAES fails to load the BHK (KEYSEL = 010 or 100) respecting the correct order. AES fails to load the key shared by SAES peripheral (KMOD=10). When KEYVALID = 1 and (KEYPROT = 1 or KEYSEL is not 0x0), the security context of the application that loads the key (secure or non-secure) does not match the security attribute of the access to SAES_CR or SAES_DOUT. In this case, KEYVALID and EN bits are cleared. SAES_KEYRx register write does not respect the correct order. (For KEYSIZE = 0, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 register, or reverse. For KEYSIZE = 1, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 then SAES_KEYR4 then SAES_KEYR5 then SAES_KEYR6 then SAES_KEYR7, or reverse). KEIF must be cleared by the application software, otherwise KEYVALID cannot be set."]
499 #[inline(always)]
500 pub const fn keif(&self) -> bool {
501 let val = (self.0 >> 2usize) & 0x01;
502 val != 0
503 }
504 #[doc = "Key error interrupt flag This read-only bit is set by hardware when key information failed to load into key registers or key register usage is forbidden. Setting the corresponding bit of the SAES_ICR register clears the KEIF and generates interrupt if the KEIE bit of the SAES_IER register is set. KEIF is triggered upon any of the following errors: SAES fails to load the DHUK (KEYSEL = 001 or 100). SAES fails to load the BHK (KEYSEL = 010 or 100) respecting the correct order. AES fails to load the key shared by SAES peripheral (KMOD=10). When KEYVALID = 1 and (KEYPROT = 1 or KEYSEL is not 0x0), the security context of the application that loads the key (secure or non-secure) does not match the security attribute of the access to SAES_CR or SAES_DOUT. In this case, KEYVALID and EN bits are cleared. SAES_KEYRx register write does not respect the correct order. (For KEYSIZE = 0, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 register, or reverse. For KEYSIZE = 1, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 then SAES_KEYR4 then SAES_KEYR5 then SAES_KEYR6 then SAES_KEYR7, or reverse). KEIF must be cleared by the application software, otherwise KEYVALID cannot be set."]
505 #[inline(always)]
506 pub fn set_keif(&mut self, val: bool) {
507 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
508 }
509 #[doc = "RNG error interrupt flag This read-only bit is set by hardware when an error is detected on RNG bus interface (e.g. bad entropy). RNGEIE bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RNGEIE bit has been previously set in the SAES_IER register. Clearing this bit triggers the reload of a new random number from RNG peripheral."]
510 #[inline(always)]
511 pub const fn rngeif(&self) -> bool {
512 let val = (self.0 >> 3usize) & 0x01;
513 val != 0
514 }
515 #[doc = "RNG error interrupt flag This read-only bit is set by hardware when an error is detected on RNG bus interface (e.g. bad entropy). RNGEIE bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RNGEIE bit has been previously set in the SAES_IER register. Clearing this bit triggers the reload of a new random number from RNG peripheral."]
516 #[inline(always)]
517 pub fn set_rngeif(&mut self, val: bool) {
518 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
519 }
520 }
521 impl Default for Isr {
522 #[inline(always)]
523 fn default() -> Isr {
524 Isr(0)
525 }
526 }
527 impl core::fmt::Debug for Isr {
528 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
529 f.debug_struct("Isr")
530 .field("ccf", &self.ccf())
531 .field("rweif", &self.rweif())
532 .field("keif", &self.keif())
533 .field("rngeif", &self.rngeif())
534 .finish()
535 }
536 }
537 #[cfg(feature = "defmt")]
538 impl defmt::Format for Isr {
539 fn format(&self, f: defmt::Formatter) {
540 #[derive(defmt :: Format)]
541 struct Isr {
542 ccf: bool,
543 rweif: bool,
544 keif: bool,
545 rngeif: bool,
546 }
547 let proxy = Isr {
548 ccf: self.ccf(),
549 rweif: self.rweif(),
550 keif: self.keif(),
551 rngeif: self.rngeif(),
552 };
553 defmt::write!(f, "{}", proxy)
554 }
555 }
556 #[doc = "SAES status register."]
557 #[repr(transparent)]
558 #[derive(Copy, Clone, Eq, PartialEq)]
559 pub struct Sr(pub u32);
560 impl Sr {
561 #[doc = "Computation completed flag. This bit mirrors the CCF bit of the SAES_ISR register."]
562 #[inline(always)]
563 pub const fn ccf(&self) -> bool {
564 let val = (self.0 >> 1usize) & 0x01;
565 val != 0
566 }
567 #[doc = "Computation completed flag. This bit mirrors the CCF bit of the SAES_ISR register."]
568 #[inline(always)]
569 pub fn set_ccf(&mut self, val: bool) {
570 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
571 }
572 #[doc = "Read error flag This flag indicates the detection of an unexpected read operation from the SAES_DOUTR register (during computation or data input phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. The flag setting has no impact on the SAES operation. Unexpected read returns zero."]
573 #[inline(always)]
574 pub const fn rderr(&self) -> bool {
575 let val = (self.0 >> 1usize) & 0x01;
576 val != 0
577 }
578 #[doc = "Read error flag This flag indicates the detection of an unexpected read operation from the SAES_DOUTR register (during computation or data input phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. The flag setting has no impact on the SAES operation. Unexpected read returns zero."]
579 #[inline(always)]
580 pub fn set_rderr(&mut self, val: bool) {
581 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
582 }
583 #[doc = "Write error This flag indicates the detection of an unexpected write operation to the SAES_DINR register (during computation or data output phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. The flag setting has no impact on the SAES operation. Unexpected write is ignored."]
584 #[inline(always)]
585 pub const fn wrerr(&self) -> bool {
586 let val = (self.0 >> 2usize) & 0x01;
587 val != 0
588 }
589 #[doc = "Write error This flag indicates the detection of an unexpected write operation to the SAES_DINR register (during computation or data output phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. The flag setting has no impact on the SAES operation. Unexpected write is ignored."]
590 #[inline(always)]
591 pub fn set_wrerr(&mut self, val: bool) {
592 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
593 }
594 #[doc = "Busy This flag indicates whether SAES is idle or busy during GCM payload encryption phase: The flag is set upon SAES initialization, upon fetching random number from the RNG, or upon transferring a shared key to a target peripheral. When GCM encryption is selected, the flag must be at zero before selecting the GCM final phase."]
595 #[inline(always)]
596 pub const fn busy(&self) -> bool {
597 let val = (self.0 >> 3usize) & 0x01;
598 val != 0
599 }
600 #[doc = "Busy This flag indicates whether SAES is idle or busy during GCM payload encryption phase: The flag is set upon SAES initialization, upon fetching random number from the RNG, or upon transferring a shared key to a target peripheral. When GCM encryption is selected, the flag must be at zero before selecting the GCM final phase."]
601 #[inline(always)]
602 pub fn set_busy(&mut self, val: bool) {
603 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
604 }
605 #[doc = "Key Valid flag This bit is set by hardware when the amount of key information defined by KEYSIZE in SAES_CR has been loaded in SAES_KEYx key registers. In normal mode when KEYSEL equals to zero, the application must write the key registers in the correct sequence, otherwise the KEIF flag of the SAES_ISR register is set and KEYVALID stays at zero. When KEYSEL is different from zero the BUSY flag is automatically set by SAES. When key is loaded successfully, the BUSY flag is cleared and KEYVALID set. Upon an error, the KEIF flag of the SAES_ISR register is set, the BUSY flag cleared and KEYVALID kept at zero. When the KEIF flag is set, the application must clear it through the SAES_ICR register, otherwise KEYVALID cannot be set. See the KEIF bit description for more details. For more information on key loading please refer to."]
606 #[inline(always)]
607 pub const fn keyvalid(&self) -> bool {
608 let val = (self.0 >> 7usize) & 0x01;
609 val != 0
610 }
611 #[doc = "Key Valid flag This bit is set by hardware when the amount of key information defined by KEYSIZE in SAES_CR has been loaded in SAES_KEYx key registers. In normal mode when KEYSEL equals to zero, the application must write the key registers in the correct sequence, otherwise the KEIF flag of the SAES_ISR register is set and KEYVALID stays at zero. When KEYSEL is different from zero the BUSY flag is automatically set by SAES. When key is loaded successfully, the BUSY flag is cleared and KEYVALID set. Upon an error, the KEIF flag of the SAES_ISR register is set, the BUSY flag cleared and KEYVALID kept at zero. When the KEIF flag is set, the application must clear it through the SAES_ICR register, otherwise KEYVALID cannot be set. See the KEIF bit description for more details. For more information on key loading please refer to."]
612 #[inline(always)]
613 pub fn set_keyvalid(&mut self, val: bool) {
614 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
615 }
616 }
617 impl Default for Sr {
618 #[inline(always)]
619 fn default() -> Sr {
620 Sr(0)
621 }
622 }
623 impl core::fmt::Debug for Sr {
624 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
625 f.debug_struct("Sr")
626 .field("ccf", &self.ccf())
627 .field("rderr", &self.rderr())
628 .field("wrerr", &self.wrerr())
629 .field("busy", &self.busy())
630 .field("keyvalid", &self.keyvalid())
631 .finish()
632 }
633 }
634 #[cfg(feature = "defmt")]
635 impl defmt::Format for Sr {
636 fn format(&self, f: defmt::Formatter) {
637 #[derive(defmt :: Format)]
638 struct Sr {
639 ccf: bool,
640 rderr: bool,
641 wrerr: bool,
642 busy: bool,
643 keyvalid: bool,
644 }
645 let proxy = Sr {
646 ccf: self.ccf(),
647 rderr: self.rderr(),
648 wrerr: self.wrerr(),
649 busy: self.busy(),
650 keyvalid: self.keyvalid(),
651 };
652 defmt::write!(f, "{}", proxy)
653 }
654 }
655}
656pub mod vals {
657 #[repr(u8)]
658 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
659 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
660 pub enum Chmod {
661 #[doc = "Electronic codebook"]
662 ECB = 0x0,
663 #[doc = "Cipher-block chaining"]
664 CBC = 0x01,
665 #[doc = "Counter mode"]
666 CTR = 0x02,
667 #[doc = "Galois counter mode and Galois message authentication code"]
668 GCM_GMAC = 0x03,
669 #[doc = "Counter with CBC-MAC"]
670 CCM = 0x04,
671 _RESERVED_5 = 0x05,
672 _RESERVED_6 = 0x06,
673 _RESERVED_7 = 0x07,
674 }
675 impl Chmod {
676 #[inline(always)]
677 pub const fn from_bits(val: u8) -> Chmod {
678 unsafe { core::mem::transmute(val & 0x07) }
679 }
680 #[inline(always)]
681 pub const fn to_bits(self) -> u8 {
682 unsafe { core::mem::transmute(self) }
683 }
684 }
685 impl From<u8> for Chmod {
686 #[inline(always)]
687 fn from(val: u8) -> Chmod {
688 Chmod::from_bits(val)
689 }
690 }
691 impl From<Chmod> for u8 {
692 #[inline(always)]
693 fn from(val: Chmod) -> u8 {
694 Chmod::to_bits(val)
695 }
696 }
697 #[repr(u8)]
698 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
699 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
700 pub enum Datatype {
701 #[doc = "No swapping (32-bit data)."]
702 NONE = 0x0,
703 #[doc = "Half-word swapping (16-bit data)"]
704 HALF_WORD = 0x01,
705 #[doc = "Byte swapping (8-bit data)"]
706 BYTE = 0x02,
707 #[doc = "Bit-level swapping"]
708 BIT = 0x03,
709 }
710 impl Datatype {
711 #[inline(always)]
712 pub const fn from_bits(val: u8) -> Datatype {
713 unsafe { core::mem::transmute(val & 0x03) }
714 }
715 #[inline(always)]
716 pub const fn to_bits(self) -> u8 {
717 unsafe { core::mem::transmute(self) }
718 }
719 }
720 impl From<u8> for Datatype {
721 #[inline(always)]
722 fn from(val: u8) -> Datatype {
723 Datatype::from_bits(val)
724 }
725 }
726 impl From<Datatype> for u8 {
727 #[inline(always)]
728 fn from(val: Datatype) -> u8 {
729 Datatype::to_bits(val)
730 }
731 }
732 #[repr(u8)]
733 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
734 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
735 pub enum Keysel {
736 #[doc = "Software key, loaded in key registers SAES_KEYx"]
737 SOFTWARE_KEY = 0x0,
738 #[doc = "Derived hardware unique key"]
739 DHUK = 0x01,
740 #[doc = "Boot hardware key"]
741 BHK = 0x02,
742 _RESERVED_3 = 0x03,
743 #[doc = "XOR of DHUK and BHK"]
744 XOR_DHUK_BHK = 0x04,
745 _RESERVED_5 = 0x05,
746 _RESERVED_6 = 0x06,
747 _RESERVED_7 = 0x07,
748 }
749 impl Keysel {
750 #[inline(always)]
751 pub const fn from_bits(val: u8) -> Keysel {
752 unsafe { core::mem::transmute(val & 0x07) }
753 }
754 #[inline(always)]
755 pub const fn to_bits(self) -> u8 {
756 unsafe { core::mem::transmute(self) }
757 }
758 }
759 impl From<u8> for Keysel {
760 #[inline(always)]
761 fn from(val: u8) -> Keysel {
762 Keysel::from_bits(val)
763 }
764 }
765 impl From<Keysel> for u8 {
766 #[inline(always)]
767 fn from(val: Keysel) -> u8 {
768 Keysel::to_bits(val)
769 }
770 }
771 #[repr(u8)]
772 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
773 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
774 pub enum Keysize {
775 #[doc = "128-bit"]
776 BITS128 = 0x0,
777 #[doc = "256-bit"]
778 BITS256 = 0x01,
779 }
780 impl Keysize {
781 #[inline(always)]
782 pub const fn from_bits(val: u8) -> Keysize {
783 unsafe { core::mem::transmute(val & 0x01) }
784 }
785 #[inline(always)]
786 pub const fn to_bits(self) -> u8 {
787 unsafe { core::mem::transmute(self) }
788 }
789 }
790 impl From<u8> for Keysize {
791 #[inline(always)]
792 fn from(val: u8) -> Keysize {
793 Keysize::from_bits(val)
794 }
795 }
796 impl From<Keysize> for u8 {
797 #[inline(always)]
798 fn from(val: Keysize) -> u8 {
799 Keysize::to_bits(val)
800 }
801 }
802 #[repr(u8)]
803 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
804 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
805 pub enum Kmod {
806 #[doc = "AES peripheral"]
807 NORMAL = 0x0,
808 #[doc = "Wrapped key for SAES mode. Key loaded in key registers can only be used to encrypt or decrypt AES keys. Hence, when a decryption is selected, read-as-zero SAES_DOUTR register is automatically loaded into SAES key registers after a successful decryption process."]
809 WRAPPED_KEY = 0x01,
810 #[doc = "Shared key mode. After a successful decryption process (unwrapping), SAES key registers are shared with the peripheral described in KSHAREID\\[1:0\\]
811bitfield. This sharing is valid only while KMOD\\[1:0\\]
812at 0x2 and KEYVALID=1. When a decryption is selected, read-as-zero SAES_DOUTR register is automatically loaded into SAES key registers after a successful decryption process."]
813 SHARED_KEY = 0x02,
814 _RESERVED_3 = 0x03,
815 }
816 impl Kmod {
817 #[inline(always)]
818 pub const fn from_bits(val: u8) -> Kmod {
819 unsafe { core::mem::transmute(val & 0x03) }
820 }
821 #[inline(always)]
822 pub const fn to_bits(self) -> u8 {
823 unsafe { core::mem::transmute(self) }
824 }
825 }
826 impl From<u8> for Kmod {
827 #[inline(always)]
828 fn from(val: u8) -> Kmod {
829 Kmod::from_bits(val)
830 }
831 }
832 impl From<Kmod> for u8 {
833 #[inline(always)]
834 fn from(val: Kmod) -> u8 {
835 Kmod::to_bits(val)
836 }
837 }
838 #[repr(u8)]
839 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
840 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
841 pub enum Kshareid {
842 #[doc = "AES peripheral"]
843 AES = 0x0,
844 _RESERVED_1 = 0x01,
845 _RESERVED_2 = 0x02,
846 _RESERVED_3 = 0x03,
847 }
848 impl Kshareid {
849 #[inline(always)]
850 pub const fn from_bits(val: u8) -> Kshareid {
851 unsafe { core::mem::transmute(val & 0x03) }
852 }
853 #[inline(always)]
854 pub const fn to_bits(self) -> u8 {
855 unsafe { core::mem::transmute(self) }
856 }
857 }
858 impl From<u8> for Kshareid {
859 #[inline(always)]
860 fn from(val: u8) -> Kshareid {
861 Kshareid::from_bits(val)
862 }
863 }
864 impl From<Kshareid> for u8 {
865 #[inline(always)]
866 fn from(val: Kshareid) -> u8 {
867 Kshareid::to_bits(val)
868 }
869 }
870 #[repr(u8)]
871 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
872 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
873 pub enum Mode {
874 ENCRYPTION = 0x0,
875 #[doc = "Key derivation (or key preparation), for ECB/CBC decryption only"]
876 KEY_DERIVATION = 0x01,
877 DECRYPTION = 0x02,
878 _RESERVED_3 = 0x03,
879 }
880 impl Mode {
881 #[inline(always)]
882 pub const fn from_bits(val: u8) -> Mode {
883 unsafe { core::mem::transmute(val & 0x03) }
884 }
885 #[inline(always)]
886 pub const fn to_bits(self) -> u8 {
887 unsafe { core::mem::transmute(self) }
888 }
889 }
890 impl From<u8> for Mode {
891 #[inline(always)]
892 fn from(val: u8) -> Mode {
893 Mode::from_bits(val)
894 }
895 }
896 impl From<Mode> for u8 {
897 #[inline(always)]
898 fn from(val: Mode) -> u8 {
899 Mode::to_bits(val)
900 }
901 }
902}
903