1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR"]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Ch {
9 ptr: *mut u8,
10}
11unsafe impl Send for Ch {}
12unsafe impl Sync for Ch {}
13impl Ch {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "Configuration register 1"]
23 #[inline(always)]
24 pub const fn cr1(self) -> crate::common::Reg<regs::Cr1, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "Configuration register 2"]
28 #[inline(always)]
29 pub const fn cr2(self) -> crate::common::Reg<regs::Cr2, crate::common::RW> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
31 }
32 #[doc = "This register has no meaning in AC97 and SPDIF audio protocol"]
33 #[inline(always)]
34 pub const fn frcr(self) -> crate::common::Reg<regs::Frcr, crate::common::RW> {
35 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
36 }
37 #[doc = "This register has no meaning in AC97 and SPDIF audio protocol"]
38 #[inline(always)]
39 pub const fn slotr(self) -> crate::common::Reg<regs::Slotr, crate::common::RW> {
40 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
41 }
42 #[doc = "Interrupt mask register 2"]
43 #[inline(always)]
44 pub const fn im(self) -> crate::common::Reg<regs::Im, crate::common::RW> {
45 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
46 }
47 #[doc = "Status register"]
48 #[inline(always)]
49 pub const fn sr(self) -> crate::common::Reg<regs::Sr, crate::common::R> {
50 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
51 }
52 #[doc = "Clear flag register"]
53 #[inline(always)]
54 pub const fn clrfr(self) -> crate::common::Reg<regs::Clrfr, crate::common::W> {
55 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) }
56 }
57 #[doc = "Data register"]
58 #[inline(always)]
59 pub const fn dr(self) -> crate::common::Reg<regs::Dr, crate::common::RW> {
60 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) }
61 }
62}
63#[doc = "Serial audio interface"]
64#[derive(Copy, Clone, Eq, PartialEq)]
65pub struct Sai {
66 ptr: *mut u8,
67}
68unsafe impl Send for Sai {}
69unsafe impl Sync for Sai {}
70impl Sai {
71 #[inline(always)]
72 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
73 Self { ptr: ptr as _ }
74 }
75 #[inline(always)]
76 pub const fn as_ptr(&self) -> *mut () {
77 self.ptr as _
78 }
79 #[doc = "Global configuration register"]
80 #[inline(always)]
81 pub const fn gcr(self) -> crate::common::Reg<regs::Gcr, crate::common::RW> {
82 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
83 }
84 #[doc = "Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR"]
85 #[inline(always)]
86 pub const fn ch(self, n: usize) -> Ch {
87 assert!(n < 2usize);
88 unsafe { Ch::from_ptr(self.ptr.add(0x04usize + n * 32usize) as _) }
89 }
90 #[doc = "PDM control register"]
91 #[inline(always)]
92 pub const fn pdmcr(self) -> crate::common::Reg<regs::Pdmcr, crate::common::RW> {
93 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) }
94 }
95 #[doc = "PDM delay register"]
96 #[inline(always)]
97 pub const fn pdmdly(self) -> crate::common::Reg<regs::Pdmdly, crate::common::RW> {
98 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) }
99 }
100}
101pub mod regs {
102 #[doc = "Clear flag register"]
103 #[repr(transparent)]
104 #[derive(Copy, Clone, Eq, PartialEq)]
105 pub struct Clrfr(pub u32);
106 impl Clrfr {
107 #[doc = "Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0."]
108 #[inline(always)]
109 pub const fn covrudr(&self) -> bool {
110 let val = (self.0 >> 0usize) & 0x01;
111 val != 0
112 }
113 #[doc = "Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0."]
114 #[inline(always)]
115 pub fn set_covrudr(&mut self, val: bool) {
116 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
117 }
118 #[doc = "Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0."]
119 #[inline(always)]
120 pub const fn cmutedet(&self) -> bool {
121 let val = (self.0 >> 1usize) & 0x01;
122 val != 0
123 }
124 #[doc = "Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0."]
125 #[inline(always)]
126 pub fn set_cmutedet(&mut self, val: bool) {
127 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
128 }
129 #[doc = "Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE\\[1\\]
130= 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0."]
131 #[inline(always)]
132 pub const fn cwckcfg(&self) -> bool {
133 let val = (self.0 >> 2usize) & 0x01;
134 val != 0
135 }
136 #[doc = "Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE\\[1\\]
137= 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0."]
138 #[inline(always)]
139 pub fn set_cwckcfg(&mut self, val: bool) {
140 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
141 }
142 #[doc = "Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0."]
143 #[inline(always)]
144 pub const fn ccnrdy(&self) -> bool {
145 let val = (self.0 >> 4usize) & 0x01;
146 val != 0
147 }
148 #[doc = "Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0."]
149 #[inline(always)]
150 pub fn set_ccnrdy(&mut self, val: bool) {
151 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
152 }
153 #[doc = "Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0."]
154 #[inline(always)]
155 pub const fn cafsdet(&self) -> bool {
156 let val = (self.0 >> 5usize) & 0x01;
157 val != 0
158 }
159 #[doc = "Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0."]
160 #[inline(always)]
161 pub fn set_cafsdet(&mut self, val: bool) {
162 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
163 }
164 #[doc = "Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0."]
165 #[inline(always)]
166 pub const fn clfsdet(&self) -> bool {
167 let val = (self.0 >> 6usize) & 0x01;
168 val != 0
169 }
170 #[doc = "Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0."]
171 #[inline(always)]
172 pub fn set_clfsdet(&mut self, val: bool) {
173 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
174 }
175 }
176 impl Default for Clrfr {
177 #[inline(always)]
178 fn default() -> Clrfr {
179 Clrfr(0)
180 }
181 }
182 impl core::fmt::Debug for Clrfr {
183 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
184 f.debug_struct("Clrfr")
185 .field("covrudr", &self.covrudr())
186 .field("cmutedet", &self.cmutedet())
187 .field("cwckcfg", &self.cwckcfg())
188 .field("ccnrdy", &self.ccnrdy())
189 .field("cafsdet", &self.cafsdet())
190 .field("clfsdet", &self.clfsdet())
191 .finish()
192 }
193 }
194 #[cfg(feature = "defmt")]
195 impl defmt::Format for Clrfr {
196 fn format(&self, f: defmt::Formatter) {
197 #[derive(defmt :: Format)]
198 struct Clrfr {
199 covrudr: bool,
200 cmutedet: bool,
201 cwckcfg: bool,
202 ccnrdy: bool,
203 cafsdet: bool,
204 clfsdet: bool,
205 }
206 let proxy = Clrfr {
207 covrudr: self.covrudr(),
208 cmutedet: self.cmutedet(),
209 cwckcfg: self.cwckcfg(),
210 ccnrdy: self.ccnrdy(),
211 cafsdet: self.cafsdet(),
212 clfsdet: self.clfsdet(),
213 };
214 defmt::write!(f, "{}", proxy)
215 }
216 }
217 #[doc = "Configuration register 1"]
218 #[repr(transparent)]
219 #[derive(Copy, Clone, Eq, PartialEq)]
220 pub struct Cr1(pub u32);
221 impl Cr1 {
222 #[doc = "SAIx audio block mode immediately"]
223 #[inline(always)]
224 pub const fn mode(&self) -> super::vals::Mode {
225 let val = (self.0 >> 0usize) & 0x03;
226 super::vals::Mode::from_bits(val as u8)
227 }
228 #[doc = "SAIx audio block mode immediately"]
229 #[inline(always)]
230 pub fn set_mode(&mut self, val: super::vals::Mode) {
231 self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
232 }
233 #[doc = "Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled."]
234 #[inline(always)]
235 pub const fn prtcfg(&self) -> super::vals::Prtcfg {
236 let val = (self.0 >> 2usize) & 0x03;
237 super::vals::Prtcfg::from_bits(val as u8)
238 }
239 #[doc = "Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled."]
240 #[inline(always)]
241 pub fn set_prtcfg(&mut self, val: super::vals::Prtcfg) {
242 self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
243 }
244 #[doc = "Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG\\[1:0\\]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP\\[1:0\\]
245bits, DS\\[1:0\\]
246are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled."]
247 #[inline(always)]
248 pub const fn ds(&self) -> super::vals::Ds {
249 let val = (self.0 >> 5usize) & 0x07;
250 super::vals::Ds::from_bits(val as u8)
251 }
252 #[doc = "Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG\\[1:0\\]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP\\[1:0\\]
253bits, DS\\[1:0\\]
254are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled."]
255 #[inline(always)]
256 pub fn set_ds(&mut self, val: super::vals::Ds) {
257 self.0 = (self.0 & !(0x07 << 5usize)) | (((val.to_bits() as u32) & 0x07) << 5usize);
258 }
259 #[doc = "Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first."]
260 #[inline(always)]
261 pub const fn lsbfirst(&self) -> super::vals::Lsbfirst {
262 let val = (self.0 >> 8usize) & 0x01;
263 super::vals::Lsbfirst::from_bits(val as u8)
264 }
265 #[doc = "Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first."]
266 #[inline(always)]
267 pub fn set_lsbfirst(&mut self, val: super::vals::Lsbfirst) {
268 self.0 = (self.0 & !(0x01 << 8usize)) | (((val.to_bits() as u32) & 0x01) << 8usize);
269 }
270 #[doc = "Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol."]
271 #[inline(always)]
272 pub const fn ckstr(&self) -> super::vals::Ckstr {
273 let val = (self.0 >> 9usize) & 0x01;
274 super::vals::Ckstr::from_bits(val as u8)
275 }
276 #[doc = "Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol."]
277 #[inline(always)]
278 pub fn set_ckstr(&mut self, val: super::vals::Ckstr) {
279 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.to_bits() as u32) & 0x01) << 9usize);
280 }
281 #[doc = "Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled."]
282 #[inline(always)]
283 pub const fn syncen(&self) -> super::vals::Syncen {
284 let val = (self.0 >> 10usize) & 0x03;
285 super::vals::Syncen::from_bits(val as u8)
286 }
287 #[doc = "Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled."]
288 #[inline(always)]
289 pub fn set_syncen(&mut self, val: super::vals::Syncen) {
290 self.0 = (self.0 & !(0x03 << 10usize)) | (((val.to_bits() as u32) & 0x03) << 10usize);
291 }
292 #[doc = "Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details."]
293 #[inline(always)]
294 pub const fn mono(&self) -> super::vals::Mono {
295 let val = (self.0 >> 12usize) & 0x01;
296 super::vals::Mono::from_bits(val as u8)
297 }
298 #[doc = "Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details."]
299 #[inline(always)]
300 pub fn set_mono(&mut self, val: super::vals::Mono) {
301 self.0 = (self.0 & !(0x01 << 12usize)) | (((val.to_bits() as u32) & 0x01) << 12usize);
302 }
303 #[doc = "Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration."]
304 #[inline(always)]
305 pub const fn outdriv(&self) -> super::vals::Outdriv {
306 let val = (self.0 >> 13usize) & 0x01;
307 super::vals::Outdriv::from_bits(val as u8)
308 }
309 #[doc = "Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration."]
310 #[inline(always)]
311 pub fn set_outdriv(&mut self, val: super::vals::Outdriv) {
312 self.0 = (self.0 & !(0x01 << 13usize)) | (((val.to_bits() as u32) & 0x01) << 13usize);
313 }
314 #[doc = "Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit."]
315 #[inline(always)]
316 pub const fn saien(&self) -> bool {
317 let val = (self.0 >> 16usize) & 0x01;
318 val != 0
319 }
320 #[doc = "Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit."]
321 #[inline(always)]
322 pub fn set_saien(&mut self, val: bool) {
323 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
324 }
325 #[doc = "DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE\\[1:0\\]
326bits must be configured before setting DMAEN to avoid a DMA request in receiver mode."]
327 #[inline(always)]
328 pub const fn dmaen(&self) -> bool {
329 let val = (self.0 >> 17usize) & 0x01;
330 val != 0
331 }
332 #[doc = "DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE\\[1:0\\]
333bits must be configured before setting DMAEN to avoid a DMA request in receiver mode."]
334 #[inline(always)]
335 pub fn set_dmaen(&mut self, val: bool) {
336 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
337 }
338 #[doc = "No fixed divider between MCLK and FS"]
339 #[inline(always)]
340 pub const fn nodiv(&self) -> super::vals::Nodiv {
341 let val = (self.0 >> 19usize) & 0x01;
342 super::vals::Nodiv::from_bits(val as u8)
343 }
344 #[doc = "No fixed divider between MCLK and FS"]
345 #[inline(always)]
346 pub fn set_nodiv(&mut self, val: super::vals::Nodiv) {
347 self.0 = (self.0 & !(0x01 << 19usize)) | (((val.to_bits() as u32) & 0x01) << 19usize);
348 }
349 #[doc = "Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula:"]
350 #[inline(always)]
351 pub const fn mckdiv(&self) -> u8 {
352 let val = (self.0 >> 20usize) & 0x3f;
353 val as u8
354 }
355 #[doc = "Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula:"]
356 #[inline(always)]
357 pub fn set_mckdiv(&mut self, val: u8) {
358 self.0 = (self.0 & !(0x3f << 20usize)) | (((val as u32) & 0x3f) << 20usize);
359 }
360 #[doc = "Oversampling ratio for master clock"]
361 #[inline(always)]
362 pub const fn osr(&self) -> bool {
363 let val = (self.0 >> 26usize) & 0x01;
364 val != 0
365 }
366 #[doc = "Oversampling ratio for master clock"]
367 #[inline(always)]
368 pub fn set_osr(&mut self, val: bool) {
369 self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
370 }
371 #[doc = "Master clock generation enable"]
372 #[inline(always)]
373 pub const fn mcken(&self) -> bool {
374 let val = (self.0 >> 27usize) & 0x01;
375 val != 0
376 }
377 #[doc = "Master clock generation enable"]
378 #[inline(always)]
379 pub fn set_mcken(&mut self, val: bool) {
380 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
381 }
382 }
383 impl Default for Cr1 {
384 #[inline(always)]
385 fn default() -> Cr1 {
386 Cr1(0)
387 }
388 }
389 impl core::fmt::Debug for Cr1 {
390 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
391 f.debug_struct("Cr1")
392 .field("mode", &self.mode())
393 .field("prtcfg", &self.prtcfg())
394 .field("ds", &self.ds())
395 .field("lsbfirst", &self.lsbfirst())
396 .field("ckstr", &self.ckstr())
397 .field("syncen", &self.syncen())
398 .field("mono", &self.mono())
399 .field("outdriv", &self.outdriv())
400 .field("saien", &self.saien())
401 .field("dmaen", &self.dmaen())
402 .field("nodiv", &self.nodiv())
403 .field("mckdiv", &self.mckdiv())
404 .field("osr", &self.osr())
405 .field("mcken", &self.mcken())
406 .finish()
407 }
408 }
409 #[cfg(feature = "defmt")]
410 impl defmt::Format for Cr1 {
411 fn format(&self, f: defmt::Formatter) {
412 #[derive(defmt :: Format)]
413 struct Cr1 {
414 mode: super::vals::Mode,
415 prtcfg: super::vals::Prtcfg,
416 ds: super::vals::Ds,
417 lsbfirst: super::vals::Lsbfirst,
418 ckstr: super::vals::Ckstr,
419 syncen: super::vals::Syncen,
420 mono: super::vals::Mono,
421 outdriv: super::vals::Outdriv,
422 saien: bool,
423 dmaen: bool,
424 nodiv: super::vals::Nodiv,
425 mckdiv: u8,
426 osr: bool,
427 mcken: bool,
428 }
429 let proxy = Cr1 {
430 mode: self.mode(),
431 prtcfg: self.prtcfg(),
432 ds: self.ds(),
433 lsbfirst: self.lsbfirst(),
434 ckstr: self.ckstr(),
435 syncen: self.syncen(),
436 mono: self.mono(),
437 outdriv: self.outdriv(),
438 saien: self.saien(),
439 dmaen: self.dmaen(),
440 nodiv: self.nodiv(),
441 mckdiv: self.mckdiv(),
442 osr: self.osr(),
443 mcken: self.mcken(),
444 };
445 defmt::write!(f, "{}", proxy)
446 }
447 }
448 #[doc = "Configuration register 2"]
449 #[repr(transparent)]
450 #[derive(Copy, Clone, Eq, PartialEq)]
451 pub struct Cr2(pub u32);
452 impl Cr2 {
453 #[doc = "FIFO threshold. This bit is set and cleared by software."]
454 #[inline(always)]
455 pub const fn fth(&self) -> super::vals::Fth {
456 let val = (self.0 >> 0usize) & 0x07;
457 super::vals::Fth::from_bits(val as u8)
458 }
459 #[doc = "FIFO threshold. This bit is set and cleared by software."]
460 #[inline(always)]
461 pub fn set_fth(&mut self, val: super::vals::Fth) {
462 self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize);
463 }
464 #[doc = "FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled."]
465 #[inline(always)]
466 pub const fn fflush(&self) -> bool {
467 let val = (self.0 >> 3usize) & 0x01;
468 val != 0
469 }
470 #[doc = "FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled."]
471 #[inline(always)]
472 pub fn set_fflush(&mut self, val: bool) {
473 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
474 }
475 #[doc = "Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details."]
476 #[inline(always)]
477 pub const fn tris(&self) -> bool {
478 let val = (self.0 >> 4usize) & 0x01;
479 val != 0
480 }
481 #[doc = "Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details."]
482 #[inline(always)]
483 pub fn set_tris(&mut self, val: bool) {
484 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
485 }
486 #[doc = "Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks."]
487 #[inline(always)]
488 pub const fn mute(&self) -> bool {
489 let val = (self.0 >> 5usize) & 0x01;
490 val != 0
491 }
492 #[doc = "Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks."]
493 #[inline(always)]
494 pub fn set_mute(&mut self, val: bool) {
495 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
496 }
497 #[doc = "Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks."]
498 #[inline(always)]
499 pub const fn muteval(&self) -> super::vals::Muteval {
500 let val = (self.0 >> 6usize) & 0x01;
501 super::vals::Muteval::from_bits(val as u8)
502 }
503 #[doc = "Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks."]
504 #[inline(always)]
505 pub fn set_muteval(&mut self, val: super::vals::Muteval) {
506 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
507 }
508 #[doc = "Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details."]
509 #[inline(always)]
510 pub const fn mutecnt(&self) -> u8 {
511 let val = (self.0 >> 7usize) & 0x3f;
512 val as u8
513 }
514 #[doc = "Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details."]
515 #[inline(always)]
516 pub fn set_mutecnt(&mut self, val: u8) {
517 self.0 = (self.0 & !(0x3f << 7usize)) | (((val as u32) & 0x3f) << 7usize);
518 }
519 #[doc = "Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm."]
520 #[inline(always)]
521 pub const fn cpl(&self) -> super::vals::Cpl {
522 let val = (self.0 >> 13usize) & 0x01;
523 super::vals::Cpl::from_bits(val as u8)
524 }
525 #[doc = "Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm."]
526 #[inline(always)]
527 pub fn set_cpl(&mut self, val: super::vals::Cpl) {
528 self.0 = (self.0 & !(0x01 << 13usize)) | (((val.to_bits() as u32) & 0x01) << 13usize);
529 }
530 #[doc = "Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE\\[0\\]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected."]
531 #[inline(always)]
532 pub const fn comp(&self) -> super::vals::Comp {
533 let val = (self.0 >> 14usize) & 0x03;
534 super::vals::Comp::from_bits(val as u8)
535 }
536 #[doc = "Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE\\[0\\]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected."]
537 #[inline(always)]
538 pub fn set_comp(&mut self, val: super::vals::Comp) {
539 self.0 = (self.0 & !(0x03 << 14usize)) | (((val.to_bits() as u32) & 0x03) << 14usize);
540 }
541 }
542 impl Default for Cr2 {
543 #[inline(always)]
544 fn default() -> Cr2 {
545 Cr2(0)
546 }
547 }
548 impl core::fmt::Debug for Cr2 {
549 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
550 f.debug_struct("Cr2")
551 .field("fth", &self.fth())
552 .field("fflush", &self.fflush())
553 .field("tris", &self.tris())
554 .field("mute", &self.mute())
555 .field("muteval", &self.muteval())
556 .field("mutecnt", &self.mutecnt())
557 .field("cpl", &self.cpl())
558 .field("comp", &self.comp())
559 .finish()
560 }
561 }
562 #[cfg(feature = "defmt")]
563 impl defmt::Format for Cr2 {
564 fn format(&self, f: defmt::Formatter) {
565 #[derive(defmt :: Format)]
566 struct Cr2 {
567 fth: super::vals::Fth,
568 fflush: bool,
569 tris: bool,
570 mute: bool,
571 muteval: super::vals::Muteval,
572 mutecnt: u8,
573 cpl: super::vals::Cpl,
574 comp: super::vals::Comp,
575 }
576 let proxy = Cr2 {
577 fth: self.fth(),
578 fflush: self.fflush(),
579 tris: self.tris(),
580 mute: self.mute(),
581 muteval: self.muteval(),
582 mutecnt: self.mutecnt(),
583 cpl: self.cpl(),
584 comp: self.comp(),
585 };
586 defmt::write!(f, "{}", proxy)
587 }
588 }
589 #[doc = "Data register"]
590 #[repr(transparent)]
591 #[derive(Copy, Clone, Eq, PartialEq)]
592 pub struct Dr(pub u32);
593 impl Dr {
594 #[doc = "Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty."]
595 #[inline(always)]
596 pub const fn data(&self) -> u32 {
597 let val = (self.0 >> 0usize) & 0xffff_ffff;
598 val as u32
599 }
600 #[doc = "Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty."]
601 #[inline(always)]
602 pub fn set_data(&mut self, val: u32) {
603 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
604 }
605 }
606 impl Default for Dr {
607 #[inline(always)]
608 fn default() -> Dr {
609 Dr(0)
610 }
611 }
612 impl core::fmt::Debug for Dr {
613 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
614 f.debug_struct("Dr").field("data", &self.data()).finish()
615 }
616 }
617 #[cfg(feature = "defmt")]
618 impl defmt::Format for Dr {
619 fn format(&self, f: defmt::Formatter) {
620 #[derive(defmt :: Format)]
621 struct Dr {
622 data: u32,
623 }
624 let proxy = Dr { data: self.data() };
625 defmt::write!(f, "{}", proxy)
626 }
627 }
628 #[doc = "This register has no meaning in AC97 and SPDIF audio protocol"]
629 #[repr(transparent)]
630 #[derive(Copy, Clone, Eq, PartialEq)]
631 pub struct Frcr(pub u32);
632 impl Frcr {
633 #[doc = "Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL\\[7:0\\]
634+ 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT\\[4:0\\]
635of SAI_xSLOTR register (NBSLOT\\[3:0\\]
636= 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration."]
637 #[inline(always)]
638 pub const fn frl(&self) -> u8 {
639 let val = (self.0 >> 0usize) & 0xff;
640 val as u8
641 }
642 #[doc = "Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL\\[7:0\\]
643+ 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT\\[4:0\\]
644of SAI_xSLOTR register (NBSLOT\\[3:0\\]
645= 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration."]
646 #[inline(always)]
647 pub fn set_frl(&mut self, val: u8) {
648 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
649 }
650 #[doc = "Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL\\[6:0\\]
651+ 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled."]
652 #[inline(always)]
653 pub const fn fsall(&self) -> u8 {
654 let val = (self.0 >> 8usize) & 0x7f;
655 val as u8
656 }
657 #[doc = "Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL\\[6:0\\]
658+ 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled."]
659 #[inline(always)]
660 pub fn set_fsall(&mut self, val: u8) {
661 self.0 = (self.0 & !(0x7f << 8usize)) | (((val as u32) & 0x7f) << 8usize);
662 }
663 #[doc = "Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled."]
664 #[inline(always)]
665 pub const fn fsdef(&self) -> bool {
666 let val = (self.0 >> 16usize) & 0x01;
667 val != 0
668 }
669 #[doc = "Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled."]
670 #[inline(always)]
671 pub fn set_fsdef(&mut self, val: bool) {
672 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
673 }
674 #[doc = "Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled."]
675 #[inline(always)]
676 pub const fn fspol(&self) -> super::vals::Fspol {
677 let val = (self.0 >> 17usize) & 0x01;
678 super::vals::Fspol::from_bits(val as u8)
679 }
680 #[doc = "Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled."]
681 #[inline(always)]
682 pub fn set_fspol(&mut self, val: super::vals::Fspol) {
683 self.0 = (self.0 & !(0x01 << 17usize)) | (((val.to_bits() as u32) & 0x01) << 17usize);
684 }
685 #[doc = "Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled."]
686 #[inline(always)]
687 pub const fn fsoff(&self) -> super::vals::Fsoff {
688 let val = (self.0 >> 18usize) & 0x01;
689 super::vals::Fsoff::from_bits(val as u8)
690 }
691 #[doc = "Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled."]
692 #[inline(always)]
693 pub fn set_fsoff(&mut self, val: super::vals::Fsoff) {
694 self.0 = (self.0 & !(0x01 << 18usize)) | (((val.to_bits() as u32) & 0x01) << 18usize);
695 }
696 }
697 impl Default for Frcr {
698 #[inline(always)]
699 fn default() -> Frcr {
700 Frcr(0)
701 }
702 }
703 impl core::fmt::Debug for Frcr {
704 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
705 f.debug_struct("Frcr")
706 .field("frl", &self.frl())
707 .field("fsall", &self.fsall())
708 .field("fsdef", &self.fsdef())
709 .field("fspol", &self.fspol())
710 .field("fsoff", &self.fsoff())
711 .finish()
712 }
713 }
714 #[cfg(feature = "defmt")]
715 impl defmt::Format for Frcr {
716 fn format(&self, f: defmt::Formatter) {
717 #[derive(defmt :: Format)]
718 struct Frcr {
719 frl: u8,
720 fsall: u8,
721 fsdef: bool,
722 fspol: super::vals::Fspol,
723 fsoff: super::vals::Fsoff,
724 }
725 let proxy = Frcr {
726 frl: self.frl(),
727 fsall: self.fsall(),
728 fsdef: self.fsdef(),
729 fspol: self.fspol(),
730 fsoff: self.fsoff(),
731 };
732 defmt::write!(f, "{}", proxy)
733 }
734 }
735 #[doc = "Global configuration register"]
736 #[repr(transparent)]
737 #[derive(Copy, Clone, Eq, PartialEq)]
738 pub struct Gcr(pub u32);
739 impl Gcr {
740 #[doc = "Synchronization inputs"]
741 #[inline(always)]
742 pub const fn syncin(&self) -> u8 {
743 let val = (self.0 >> 0usize) & 0x03;
744 val as u8
745 }
746 #[doc = "Synchronization inputs"]
747 #[inline(always)]
748 pub fn set_syncin(&mut self, val: u8) {
749 self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
750 }
751 #[doc = "Synchronization outputs These bits are set and cleared by software."]
752 #[inline(always)]
753 pub const fn syncout(&self) -> u8 {
754 let val = (self.0 >> 4usize) & 0x03;
755 val as u8
756 }
757 #[doc = "Synchronization outputs These bits are set and cleared by software."]
758 #[inline(always)]
759 pub fn set_syncout(&mut self, val: u8) {
760 self.0 = (self.0 & !(0x03 << 4usize)) | (((val as u32) & 0x03) << 4usize);
761 }
762 }
763 impl Default for Gcr {
764 #[inline(always)]
765 fn default() -> Gcr {
766 Gcr(0)
767 }
768 }
769 impl core::fmt::Debug for Gcr {
770 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
771 f.debug_struct("Gcr")
772 .field("syncin", &self.syncin())
773 .field("syncout", &self.syncout())
774 .finish()
775 }
776 }
777 #[cfg(feature = "defmt")]
778 impl defmt::Format for Gcr {
779 fn format(&self, f: defmt::Formatter) {
780 #[derive(defmt :: Format)]
781 struct Gcr {
782 syncin: u8,
783 syncout: u8,
784 }
785 let proxy = Gcr {
786 syncin: self.syncin(),
787 syncout: self.syncout(),
788 };
789 defmt::write!(f, "{}", proxy)
790 }
791 }
792 #[doc = "Interrupt mask register 2"]
793 #[repr(transparent)]
794 #[derive(Copy, Clone, Eq, PartialEq)]
795 pub struct Im(pub u32);
796 impl Im {
797 #[doc = "Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set."]
798 #[inline(always)]
799 pub const fn ovrudrie(&self) -> bool {
800 let val = (self.0 >> 0usize) & 0x01;
801 val != 0
802 }
803 #[doc = "Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set."]
804 #[inline(always)]
805 pub fn set_ovrudrie(&mut self, val: bool) {
806 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
807 }
808 #[doc = "Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode."]
809 #[inline(always)]
810 pub const fn mutedetie(&self) -> bool {
811 let val = (self.0 >> 1usize) & 0x01;
812 val != 0
813 }
814 #[doc = "Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode."]
815 #[inline(always)]
816 pub fn set_mutedetie(&mut self, val: bool) {
817 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
818 }
819 #[doc = "Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE\\[1\\]
820= 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes."]
821 #[inline(always)]
822 pub const fn wckcfgie(&self) -> bool {
823 let val = (self.0 >> 2usize) & 0x01;
824 val != 0
825 }
826 #[doc = "Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE\\[1\\]
827= 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes."]
828 #[inline(always)]
829 pub fn set_wckcfgie(&mut self, val: bool) {
830 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
831 }
832 #[doc = "FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode,"]
833 #[inline(always)]
834 pub const fn freqie(&self) -> bool {
835 let val = (self.0 >> 3usize) & 0x01;
836 val != 0
837 }
838 #[doc = "FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode,"]
839 #[inline(always)]
840 pub fn set_freqie(&mut self, val: bool) {
841 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
842 }
843 #[doc = "Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG\\[1:0\\]
844bits and the audio block is operates as a receiver."]
845 #[inline(always)]
846 pub const fn cnrdyie(&self) -> bool {
847 let val = (self.0 >> 4usize) & 0x01;
848 val != 0
849 }
850 #[doc = "Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG\\[1:0\\]
851bits and the audio block is operates as a receiver."]
852 #[inline(always)]
853 pub fn set_cnrdyie(&mut self, val: bool) {
854 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
855 }
856 #[doc = "Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master."]
857 #[inline(always)]
858 pub const fn afsdetie(&self) -> bool {
859 let val = (self.0 >> 5usize) & 0x01;
860 val != 0
861 }
862 #[doc = "Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master."]
863 #[inline(always)]
864 pub fn set_afsdetie(&mut self, val: bool) {
865 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
866 }
867 #[doc = "Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master."]
868 #[inline(always)]
869 pub const fn lfsdetie(&self) -> bool {
870 let val = (self.0 >> 6usize) & 0x01;
871 val != 0
872 }
873 #[doc = "Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master."]
874 #[inline(always)]
875 pub fn set_lfsdetie(&mut self, val: bool) {
876 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
877 }
878 }
879 impl Default for Im {
880 #[inline(always)]
881 fn default() -> Im {
882 Im(0)
883 }
884 }
885 impl core::fmt::Debug for Im {
886 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
887 f.debug_struct("Im")
888 .field("ovrudrie", &self.ovrudrie())
889 .field("mutedetie", &self.mutedetie())
890 .field("wckcfgie", &self.wckcfgie())
891 .field("freqie", &self.freqie())
892 .field("cnrdyie", &self.cnrdyie())
893 .field("afsdetie", &self.afsdetie())
894 .field("lfsdetie", &self.lfsdetie())
895 .finish()
896 }
897 }
898 #[cfg(feature = "defmt")]
899 impl defmt::Format for Im {
900 fn format(&self, f: defmt::Formatter) {
901 #[derive(defmt :: Format)]
902 struct Im {
903 ovrudrie: bool,
904 mutedetie: bool,
905 wckcfgie: bool,
906 freqie: bool,
907 cnrdyie: bool,
908 afsdetie: bool,
909 lfsdetie: bool,
910 }
911 let proxy = Im {
912 ovrudrie: self.ovrudrie(),
913 mutedetie: self.mutedetie(),
914 wckcfgie: self.wckcfgie(),
915 freqie: self.freqie(),
916 cnrdyie: self.cnrdyie(),
917 afsdetie: self.afsdetie(),
918 lfsdetie: self.lfsdetie(),
919 };
920 defmt::write!(f, "{}", proxy)
921 }
922 }
923 #[doc = "PDM control register"]
924 #[repr(transparent)]
925 #[derive(Copy, Clone, Eq, PartialEq)]
926 pub struct Pdmcr(pub u32);
927 impl Pdmcr {
928 #[doc = "PDM enable"]
929 #[inline(always)]
930 pub const fn pdmen(&self) -> bool {
931 let val = (self.0 >> 0usize) & 0x01;
932 val != 0
933 }
934 #[doc = "PDM enable"]
935 #[inline(always)]
936 pub fn set_pdmen(&mut self, val: bool) {
937 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
938 }
939 #[doc = "Number of microphones"]
940 #[inline(always)]
941 pub const fn micnbr(&self) -> u8 {
942 let val = (self.0 >> 4usize) & 0x03;
943 val as u8
944 }
945 #[doc = "Number of microphones"]
946 #[inline(always)]
947 pub fn set_micnbr(&mut self, val: u8) {
948 self.0 = (self.0 & !(0x03 << 4usize)) | (((val as u32) & 0x03) << 4usize);
949 }
950 #[doc = "Clock enable of bitstream clock number 1"]
951 #[inline(always)]
952 pub const fn cken(&self, n: usize) -> bool {
953 assert!(n < 2usize);
954 let offs = 8usize + n * 1usize;
955 let val = (self.0 >> offs) & 0x01;
956 val != 0
957 }
958 #[doc = "Clock enable of bitstream clock number 1"]
959 #[inline(always)]
960 pub fn set_cken(&mut self, n: usize, val: bool) {
961 assert!(n < 2usize);
962 let offs = 8usize + n * 1usize;
963 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
964 }
965 }
966 impl Default for Pdmcr {
967 #[inline(always)]
968 fn default() -> Pdmcr {
969 Pdmcr(0)
970 }
971 }
972 impl core::fmt::Debug for Pdmcr {
973 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
974 f.debug_struct("Pdmcr")
975 .field("pdmen", &self.pdmen())
976 .field("micnbr", &self.micnbr())
977 .field("cken", &[self.cken(0usize), self.cken(1usize)])
978 .finish()
979 }
980 }
981 #[cfg(feature = "defmt")]
982 impl defmt::Format for Pdmcr {
983 fn format(&self, f: defmt::Formatter) {
984 #[derive(defmt :: Format)]
985 struct Pdmcr {
986 pdmen: bool,
987 micnbr: u8,
988 cken: [bool; 2usize],
989 }
990 let proxy = Pdmcr {
991 pdmen: self.pdmen(),
992 micnbr: self.micnbr(),
993 cken: [self.cken(0usize), self.cken(1usize)],
994 };
995 defmt::write!(f, "{}", proxy)
996 }
997 }
998 #[doc = "PDM delay register"]
999 #[repr(transparent)]
1000 #[derive(Copy, Clone, Eq, PartialEq)]
1001 pub struct Pdmdly(pub u32);
1002 impl Pdmdly {
1003 #[doc = "Delay line adjust for first microphone of pair 1"]
1004 #[inline(always)]
1005 pub const fn dlyml(&self, n: usize) -> u8 {
1006 assert!(n < 4usize);
1007 let offs = 0usize + n * 8usize;
1008 let val = (self.0 >> offs) & 0x07;
1009 val as u8
1010 }
1011 #[doc = "Delay line adjust for first microphone of pair 1"]
1012 #[inline(always)]
1013 pub fn set_dlyml(&mut self, n: usize, val: u8) {
1014 assert!(n < 4usize);
1015 let offs = 0usize + n * 8usize;
1016 self.0 = (self.0 & !(0x07 << offs)) | (((val as u32) & 0x07) << offs);
1017 }
1018 #[doc = "Delay line adjust for second microphone of pair 1"]
1019 #[inline(always)]
1020 pub const fn dlymr(&self, n: usize) -> u8 {
1021 assert!(n < 4usize);
1022 let offs = 4usize + n * 8usize;
1023 let val = (self.0 >> offs) & 0x07;
1024 val as u8
1025 }
1026 #[doc = "Delay line adjust for second microphone of pair 1"]
1027 #[inline(always)]
1028 pub fn set_dlymr(&mut self, n: usize, val: u8) {
1029 assert!(n < 4usize);
1030 let offs = 4usize + n * 8usize;
1031 self.0 = (self.0 & !(0x07 << offs)) | (((val as u32) & 0x07) << offs);
1032 }
1033 }
1034 impl Default for Pdmdly {
1035 #[inline(always)]
1036 fn default() -> Pdmdly {
1037 Pdmdly(0)
1038 }
1039 }
1040 impl core::fmt::Debug for Pdmdly {
1041 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1042 f.debug_struct("Pdmdly")
1043 .field(
1044 "dlyml",
1045 &[
1046 self.dlyml(0usize),
1047 self.dlyml(1usize),
1048 self.dlyml(2usize),
1049 self.dlyml(3usize),
1050 ],
1051 )
1052 .field(
1053 "dlymr",
1054 &[
1055 self.dlymr(0usize),
1056 self.dlymr(1usize),
1057 self.dlymr(2usize),
1058 self.dlymr(3usize),
1059 ],
1060 )
1061 .finish()
1062 }
1063 }
1064 #[cfg(feature = "defmt")]
1065 impl defmt::Format for Pdmdly {
1066 fn format(&self, f: defmt::Formatter) {
1067 #[derive(defmt :: Format)]
1068 struct Pdmdly {
1069 dlyml: [u8; 4usize],
1070 dlymr: [u8; 4usize],
1071 }
1072 let proxy = Pdmdly {
1073 dlyml: [
1074 self.dlyml(0usize),
1075 self.dlyml(1usize),
1076 self.dlyml(2usize),
1077 self.dlyml(3usize),
1078 ],
1079 dlymr: [
1080 self.dlymr(0usize),
1081 self.dlymr(1usize),
1082 self.dlymr(2usize),
1083 self.dlymr(3usize),
1084 ],
1085 };
1086 defmt::write!(f, "{}", proxy)
1087 }
1088 }
1089 #[doc = "This register has no meaning in AC97 and SPDIF audio protocol"]
1090 #[repr(transparent)]
1091 #[derive(Copy, Clone, Eq, PartialEq)]
1092 pub struct Slotr(pub u32);
1093 impl Slotr {
1094 #[doc = "First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode."]
1095 #[inline(always)]
1096 pub const fn fboff(&self) -> u8 {
1097 let val = (self.0 >> 0usize) & 0x1f;
1098 val as u8
1099 }
1100 #[doc = "First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode."]
1101 #[inline(always)]
1102 pub fn set_fboff(&mut self, val: u8) {
1103 self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
1104 }
1105 #[doc = "Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode."]
1106 #[inline(always)]
1107 pub const fn slotsz(&self) -> super::vals::Slotsz {
1108 let val = (self.0 >> 6usize) & 0x03;
1109 super::vals::Slotsz::from_bits(val as u8)
1110 }
1111 #[doc = "Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode."]
1112 #[inline(always)]
1113 pub fn set_slotsz(&mut self, val: super::vals::Slotsz) {
1114 self.0 = (self.0 & !(0x03 << 6usize)) | (((val.to_bits() as u32) & 0x03) << 6usize);
1115 }
1116 #[doc = "Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode."]
1117 #[inline(always)]
1118 pub const fn nbslot(&self) -> u8 {
1119 let val = (self.0 >> 8usize) & 0x0f;
1120 val as u8
1121 }
1122 #[doc = "Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode."]
1123 #[inline(always)]
1124 pub fn set_nbslot(&mut self, val: u8) {
1125 self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize);
1126 }
1127 #[doc = "Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode."]
1128 #[inline(always)]
1129 pub const fn sloten(&self) -> super::vals::Sloten {
1130 let val = (self.0 >> 16usize) & 0xffff;
1131 super::vals::Sloten::from_bits(val as u16)
1132 }
1133 #[doc = "Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode."]
1134 #[inline(always)]
1135 pub fn set_sloten(&mut self, val: super::vals::Sloten) {
1136 self.0 = (self.0 & !(0xffff << 16usize)) | (((val.to_bits() as u32) & 0xffff) << 16usize);
1137 }
1138 }
1139 impl Default for Slotr {
1140 #[inline(always)]
1141 fn default() -> Slotr {
1142 Slotr(0)
1143 }
1144 }
1145 impl core::fmt::Debug for Slotr {
1146 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1147 f.debug_struct("Slotr")
1148 .field("fboff", &self.fboff())
1149 .field("slotsz", &self.slotsz())
1150 .field("nbslot", &self.nbslot())
1151 .field("sloten", &self.sloten())
1152 .finish()
1153 }
1154 }
1155 #[cfg(feature = "defmt")]
1156 impl defmt::Format for Slotr {
1157 fn format(&self, f: defmt::Formatter) {
1158 #[derive(defmt :: Format)]
1159 struct Slotr {
1160 fboff: u8,
1161 slotsz: super::vals::Slotsz,
1162 nbslot: u8,
1163 sloten: super::vals::Sloten,
1164 }
1165 let proxy = Slotr {
1166 fboff: self.fboff(),
1167 slotsz: self.slotsz(),
1168 nbslot: self.nbslot(),
1169 sloten: self.sloten(),
1170 };
1171 defmt::write!(f, "{}", proxy)
1172 }
1173 }
1174 #[doc = "Status register"]
1175 #[repr(transparent)]
1176 #[derive(Copy, Clone, Eq, PartialEq)]
1177 pub struct Sr(pub u32);
1178 impl Sr {
1179 #[doc = "Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register."]
1180 #[inline(always)]
1181 pub const fn ovrudr(&self) -> bool {
1182 let val = (self.0 >> 0usize) & 0x01;
1183 val != 0
1184 }
1185 #[doc = "Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register."]
1186 #[inline(always)]
1187 pub fn set_ovrudr(&mut self, val: bool) {
1188 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1189 }
1190 #[doc = "Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register."]
1191 #[inline(always)]
1192 pub const fn mutedet(&self) -> bool {
1193 let val = (self.0 >> 1usize) & 0x01;
1194 val != 0
1195 }
1196 #[doc = "Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register."]
1197 #[inline(always)]
1198 pub fn set_mutedet(&mut self, val: bool) {
1199 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1200 }
1201 #[doc = "Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE\\[1\\]
1202= 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register."]
1203 #[inline(always)]
1204 pub const fn wckcfg(&self) -> super::vals::Wckcfg {
1205 let val = (self.0 >> 2usize) & 0x01;
1206 super::vals::Wckcfg::from_bits(val as u8)
1207 }
1208 #[doc = "Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE\\[1\\]
1209= 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register."]
1210 #[inline(always)]
1211 pub fn set_wckcfg(&mut self, val: super::vals::Wckcfg) {
1212 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize);
1213 }
1214 #[doc = "FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register."]
1215 #[inline(always)]
1216 pub const fn freq(&self) -> bool {
1217 let val = (self.0 >> 3usize) & 0x01;
1218 val != 0
1219 }
1220 #[doc = "FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register."]
1221 #[inline(always)]
1222 pub fn set_freq(&mut self, val: bool) {
1223 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1224 }
1225 #[doc = "Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register."]
1226 #[inline(always)]
1227 pub const fn cnrdy(&self) -> super::vals::Cnrdy {
1228 let val = (self.0 >> 4usize) & 0x01;
1229 super::vals::Cnrdy::from_bits(val as u8)
1230 }
1231 #[doc = "Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register."]
1232 #[inline(always)]
1233 pub fn set_cnrdy(&mut self, val: super::vals::Cnrdy) {
1234 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize);
1235 }
1236 #[doc = "Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register."]
1237 #[inline(always)]
1238 pub const fn afsdet(&self) -> bool {
1239 let val = (self.0 >> 5usize) & 0x01;
1240 val != 0
1241 }
1242 #[doc = "Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register."]
1243 #[inline(always)]
1244 pub fn set_afsdet(&mut self, val: bool) {
1245 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
1246 }
1247 #[doc = "Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register"]
1248 #[inline(always)]
1249 pub const fn lfsdet(&self) -> bool {
1250 let val = (self.0 >> 6usize) & 0x01;
1251 val != 0
1252 }
1253 #[doc = "Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register"]
1254 #[inline(always)]
1255 pub fn set_lfsdet(&mut self, val: bool) {
1256 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
1257 }
1258 #[doc = "FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:"]
1259 #[inline(always)]
1260 pub const fn flvl(&self) -> super::vals::Flvl {
1261 let val = (self.0 >> 16usize) & 0x07;
1262 super::vals::Flvl::from_bits(val as u8)
1263 }
1264 #[doc = "FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:"]
1265 #[inline(always)]
1266 pub fn set_flvl(&mut self, val: super::vals::Flvl) {
1267 self.0 = (self.0 & !(0x07 << 16usize)) | (((val.to_bits() as u32) & 0x07) << 16usize);
1268 }
1269 }
1270 impl Default for Sr {
1271 #[inline(always)]
1272 fn default() -> Sr {
1273 Sr(0)
1274 }
1275 }
1276 impl core::fmt::Debug for Sr {
1277 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1278 f.debug_struct("Sr")
1279 .field("ovrudr", &self.ovrudr())
1280 .field("mutedet", &self.mutedet())
1281 .field("wckcfg", &self.wckcfg())
1282 .field("freq", &self.freq())
1283 .field("cnrdy", &self.cnrdy())
1284 .field("afsdet", &self.afsdet())
1285 .field("lfsdet", &self.lfsdet())
1286 .field("flvl", &self.flvl())
1287 .finish()
1288 }
1289 }
1290 #[cfg(feature = "defmt")]
1291 impl defmt::Format for Sr {
1292 fn format(&self, f: defmt::Formatter) {
1293 #[derive(defmt :: Format)]
1294 struct Sr {
1295 ovrudr: bool,
1296 mutedet: bool,
1297 wckcfg: super::vals::Wckcfg,
1298 freq: bool,
1299 cnrdy: super::vals::Cnrdy,
1300 afsdet: bool,
1301 lfsdet: bool,
1302 flvl: super::vals::Flvl,
1303 }
1304 let proxy = Sr {
1305 ovrudr: self.ovrudr(),
1306 mutedet: self.mutedet(),
1307 wckcfg: self.wckcfg(),
1308 freq: self.freq(),
1309 cnrdy: self.cnrdy(),
1310 afsdet: self.afsdet(),
1311 lfsdet: self.lfsdet(),
1312 flvl: self.flvl(),
1313 };
1314 defmt::write!(f, "{}", proxy)
1315 }
1316 }
1317}
1318pub mod vals {
1319 #[repr(u8)]
1320 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1321 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1322 pub enum Ckstr {
1323 #[doc = "Data strobing edge is falling edge of SCK"]
1324 FALLING_EDGE = 0x0,
1325 #[doc = "Data strobing edge is rising edge of SCK"]
1326 RISING_EDGE = 0x01,
1327 }
1328 impl Ckstr {
1329 #[inline(always)]
1330 pub const fn from_bits(val: u8) -> Ckstr {
1331 unsafe { core::mem::transmute(val & 0x01) }
1332 }
1333 #[inline(always)]
1334 pub const fn to_bits(self) -> u8 {
1335 unsafe { core::mem::transmute(self) }
1336 }
1337 }
1338 impl From<u8> for Ckstr {
1339 #[inline(always)]
1340 fn from(val: u8) -> Ckstr {
1341 Ckstr::from_bits(val)
1342 }
1343 }
1344 impl From<Ckstr> for u8 {
1345 #[inline(always)]
1346 fn from(val: Ckstr) -> u8 {
1347 Ckstr::to_bits(val)
1348 }
1349 }
1350 #[repr(u8)]
1351 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1352 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1353 pub enum Cnrdy {
1354 #[doc = "External AC’97 Codec is ready"]
1355 READY = 0x0,
1356 #[doc = "External AC’97 Codec is not ready"]
1357 NOT_READY = 0x01,
1358 }
1359 impl Cnrdy {
1360 #[inline(always)]
1361 pub const fn from_bits(val: u8) -> Cnrdy {
1362 unsafe { core::mem::transmute(val & 0x01) }
1363 }
1364 #[inline(always)]
1365 pub const fn to_bits(self) -> u8 {
1366 unsafe { core::mem::transmute(self) }
1367 }
1368 }
1369 impl From<u8> for Cnrdy {
1370 #[inline(always)]
1371 fn from(val: u8) -> Cnrdy {
1372 Cnrdy::from_bits(val)
1373 }
1374 }
1375 impl From<Cnrdy> for u8 {
1376 #[inline(always)]
1377 fn from(val: Cnrdy) -> u8 {
1378 Cnrdy::to_bits(val)
1379 }
1380 }
1381 #[repr(u8)]
1382 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1383 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1384 pub enum Comp {
1385 #[doc = "No companding algorithm"]
1386 NO_COMPANDING = 0x0,
1387 _RESERVED_1 = 0x01,
1388 #[doc = "μ-Law algorithm"]
1389 MU_LAW = 0x02,
1390 #[doc = "A-Law algorithm"]
1391 ALAW = 0x03,
1392 }
1393 impl Comp {
1394 #[inline(always)]
1395 pub const fn from_bits(val: u8) -> Comp {
1396 unsafe { core::mem::transmute(val & 0x03) }
1397 }
1398 #[inline(always)]
1399 pub const fn to_bits(self) -> u8 {
1400 unsafe { core::mem::transmute(self) }
1401 }
1402 }
1403 impl From<u8> for Comp {
1404 #[inline(always)]
1405 fn from(val: u8) -> Comp {
1406 Comp::from_bits(val)
1407 }
1408 }
1409 impl From<Comp> for u8 {
1410 #[inline(always)]
1411 fn from(val: Comp) -> u8 {
1412 Comp::to_bits(val)
1413 }
1414 }
1415 #[repr(u8)]
1416 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1417 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1418 pub enum Cpl {
1419 #[doc = "1’s complement representation"]
1420 ONES_COMPLEMENT = 0x0,
1421 #[doc = "2’s complement representation"]
1422 TWOS_COMPLEMENT = 0x01,
1423 }
1424 impl Cpl {
1425 #[inline(always)]
1426 pub const fn from_bits(val: u8) -> Cpl {
1427 unsafe { core::mem::transmute(val & 0x01) }
1428 }
1429 #[inline(always)]
1430 pub const fn to_bits(self) -> u8 {
1431 unsafe { core::mem::transmute(self) }
1432 }
1433 }
1434 impl From<u8> for Cpl {
1435 #[inline(always)]
1436 fn from(val: u8) -> Cpl {
1437 Cpl::from_bits(val)
1438 }
1439 }
1440 impl From<Cpl> for u8 {
1441 #[inline(always)]
1442 fn from(val: Cpl) -> u8 {
1443 Cpl::to_bits(val)
1444 }
1445 }
1446 #[repr(u8)]
1447 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1448 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1449 pub enum Ds {
1450 _RESERVED_0 = 0x0,
1451 _RESERVED_1 = 0x01,
1452 #[doc = "8 bits"]
1453 BIT8 = 0x02,
1454 #[doc = "10 bits"]
1455 BIT10 = 0x03,
1456 #[doc = "16 bits"]
1457 BIT16 = 0x04,
1458 #[doc = "20 bits"]
1459 BIT20 = 0x05,
1460 #[doc = "24 bits"]
1461 BIT24 = 0x06,
1462 #[doc = "32 bits"]
1463 BIT32 = 0x07,
1464 }
1465 impl Ds {
1466 #[inline(always)]
1467 pub const fn from_bits(val: u8) -> Ds {
1468 unsafe { core::mem::transmute(val & 0x07) }
1469 }
1470 #[inline(always)]
1471 pub const fn to_bits(self) -> u8 {
1472 unsafe { core::mem::transmute(self) }
1473 }
1474 }
1475 impl From<u8> for Ds {
1476 #[inline(always)]
1477 fn from(val: u8) -> Ds {
1478 Ds::from_bits(val)
1479 }
1480 }
1481 impl From<Ds> for u8 {
1482 #[inline(always)]
1483 fn from(val: Ds) -> u8 {
1484 Ds::to_bits(val)
1485 }
1486 }
1487 #[repr(u8)]
1488 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1489 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1490 pub enum Flvl {
1491 #[doc = "FIFO empty"]
1492 EMPTY = 0x0,
1493 #[doc = "FIFO <= 1⁄4 but not empty"]
1494 QUARTER1 = 0x01,
1495 #[doc = "1⁄4 < FIFO <= 1⁄2"]
1496 QUARTER2 = 0x02,
1497 #[doc = "1⁄2 < FIFO <= 3⁄4"]
1498 QUARTER3 = 0x03,
1499 #[doc = "3⁄4 < FIFO but not full"]
1500 QUARTER4 = 0x04,
1501 #[doc = "FIFO full"]
1502 FULL = 0x05,
1503 _RESERVED_6 = 0x06,
1504 _RESERVED_7 = 0x07,
1505 }
1506 impl Flvl {
1507 #[inline(always)]
1508 pub const fn from_bits(val: u8) -> Flvl {
1509 unsafe { core::mem::transmute(val & 0x07) }
1510 }
1511 #[inline(always)]
1512 pub const fn to_bits(self) -> u8 {
1513 unsafe { core::mem::transmute(self) }
1514 }
1515 }
1516 impl From<u8> for Flvl {
1517 #[inline(always)]
1518 fn from(val: u8) -> Flvl {
1519 Flvl::from_bits(val)
1520 }
1521 }
1522 impl From<Flvl> for u8 {
1523 #[inline(always)]
1524 fn from(val: Flvl) -> u8 {
1525 Flvl::to_bits(val)
1526 }
1527 }
1528 #[repr(u8)]
1529 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1530 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1531 pub enum Fsoff {
1532 #[doc = "FS is asserted on the first bit of the slot 0"]
1533 ON_FIRST = 0x0,
1534 #[doc = "FS is asserted one bit before the first bit of the slot 0"]
1535 BEFORE_FIRST = 0x01,
1536 }
1537 impl Fsoff {
1538 #[inline(always)]
1539 pub const fn from_bits(val: u8) -> Fsoff {
1540 unsafe { core::mem::transmute(val & 0x01) }
1541 }
1542 #[inline(always)]
1543 pub const fn to_bits(self) -> u8 {
1544 unsafe { core::mem::transmute(self) }
1545 }
1546 }
1547 impl From<u8> for Fsoff {
1548 #[inline(always)]
1549 fn from(val: u8) -> Fsoff {
1550 Fsoff::from_bits(val)
1551 }
1552 }
1553 impl From<Fsoff> for u8 {
1554 #[inline(always)]
1555 fn from(val: Fsoff) -> u8 {
1556 Fsoff::to_bits(val)
1557 }
1558 }
1559 #[repr(u8)]
1560 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1561 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1562 pub enum Fspol {
1563 #[doc = "FS is active low (falling edge)"]
1564 FALLING_EDGE = 0x0,
1565 #[doc = "FS is active high (rising edge)"]
1566 RISING_EDGE = 0x01,
1567 }
1568 impl Fspol {
1569 #[inline(always)]
1570 pub const fn from_bits(val: u8) -> Fspol {
1571 unsafe { core::mem::transmute(val & 0x01) }
1572 }
1573 #[inline(always)]
1574 pub const fn to_bits(self) -> u8 {
1575 unsafe { core::mem::transmute(self) }
1576 }
1577 }
1578 impl From<u8> for Fspol {
1579 #[inline(always)]
1580 fn from(val: u8) -> Fspol {
1581 Fspol::from_bits(val)
1582 }
1583 }
1584 impl From<Fspol> for u8 {
1585 #[inline(always)]
1586 fn from(val: Fspol) -> u8 {
1587 Fspol::to_bits(val)
1588 }
1589 }
1590 #[repr(u8)]
1591 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1592 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1593 pub enum Fth {
1594 #[doc = "FIFO empty"]
1595 EMPTY = 0x0,
1596 #[doc = "1⁄4 FIFO"]
1597 QUARTER1 = 0x01,
1598 #[doc = "1⁄2 FIFO"]
1599 QUARTER2 = 0x02,
1600 #[doc = "3⁄4 FIFO"]
1601 QUARTER3 = 0x03,
1602 #[doc = "FIFO full"]
1603 FULL = 0x04,
1604 _RESERVED_5 = 0x05,
1605 _RESERVED_6 = 0x06,
1606 _RESERVED_7 = 0x07,
1607 }
1608 impl Fth {
1609 #[inline(always)]
1610 pub const fn from_bits(val: u8) -> Fth {
1611 unsafe { core::mem::transmute(val & 0x07) }
1612 }
1613 #[inline(always)]
1614 pub const fn to_bits(self) -> u8 {
1615 unsafe { core::mem::transmute(self) }
1616 }
1617 }
1618 impl From<u8> for Fth {
1619 #[inline(always)]
1620 fn from(val: u8) -> Fth {
1621 Fth::from_bits(val)
1622 }
1623 }
1624 impl From<Fth> for u8 {
1625 #[inline(always)]
1626 fn from(val: Fth) -> u8 {
1627 Fth::to_bits(val)
1628 }
1629 }
1630 #[repr(u8)]
1631 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1632 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1633 pub enum Lsbfirst {
1634 #[doc = "Data are transferred with MSB first"]
1635 MSB_FIRST = 0x0,
1636 #[doc = "Data are transferred with LSB first"]
1637 LSB_FIRST = 0x01,
1638 }
1639 impl Lsbfirst {
1640 #[inline(always)]
1641 pub const fn from_bits(val: u8) -> Lsbfirst {
1642 unsafe { core::mem::transmute(val & 0x01) }
1643 }
1644 #[inline(always)]
1645 pub const fn to_bits(self) -> u8 {
1646 unsafe { core::mem::transmute(self) }
1647 }
1648 }
1649 impl From<u8> for Lsbfirst {
1650 #[inline(always)]
1651 fn from(val: u8) -> Lsbfirst {
1652 Lsbfirst::from_bits(val)
1653 }
1654 }
1655 impl From<Lsbfirst> for u8 {
1656 #[inline(always)]
1657 fn from(val: Lsbfirst) -> u8 {
1658 Lsbfirst::to_bits(val)
1659 }
1660 }
1661 #[repr(u8)]
1662 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1663 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1664 pub enum Mode {
1665 #[doc = "Master transmitter"]
1666 MASTER_TX = 0x0,
1667 #[doc = "Master receiver"]
1668 MASTER_RX = 0x01,
1669 #[doc = "Slave transmitter"]
1670 SLAVE_TX = 0x02,
1671 #[doc = "Slave receiver"]
1672 SLAVE_RX = 0x03,
1673 }
1674 impl Mode {
1675 #[inline(always)]
1676 pub const fn from_bits(val: u8) -> Mode {
1677 unsafe { core::mem::transmute(val & 0x03) }
1678 }
1679 #[inline(always)]
1680 pub const fn to_bits(self) -> u8 {
1681 unsafe { core::mem::transmute(self) }
1682 }
1683 }
1684 impl From<u8> for Mode {
1685 #[inline(always)]
1686 fn from(val: u8) -> Mode {
1687 Mode::from_bits(val)
1688 }
1689 }
1690 impl From<Mode> for u8 {
1691 #[inline(always)]
1692 fn from(val: Mode) -> u8 {
1693 Mode::to_bits(val)
1694 }
1695 }
1696 #[repr(u8)]
1697 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1698 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1699 pub enum Mono {
1700 #[doc = "Stereo mode"]
1701 STEREO = 0x0,
1702 #[doc = "Mono mode"]
1703 MONO = 0x01,
1704 }
1705 impl Mono {
1706 #[inline(always)]
1707 pub const fn from_bits(val: u8) -> Mono {
1708 unsafe { core::mem::transmute(val & 0x01) }
1709 }
1710 #[inline(always)]
1711 pub const fn to_bits(self) -> u8 {
1712 unsafe { core::mem::transmute(self) }
1713 }
1714 }
1715 impl From<u8> for Mono {
1716 #[inline(always)]
1717 fn from(val: u8) -> Mono {
1718 Mono::from_bits(val)
1719 }
1720 }
1721 impl From<Mono> for u8 {
1722 #[inline(always)]
1723 fn from(val: Mono) -> u8 {
1724 Mono::to_bits(val)
1725 }
1726 }
1727 #[repr(u8)]
1728 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1729 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1730 pub enum Muteval {
1731 #[doc = "Bit value 0 is sent during the mute mode"]
1732 SEND_ZERO = 0x0,
1733 #[doc = "Last values are sent during the mute mode"]
1734 SEND_LAST = 0x01,
1735 }
1736 impl Muteval {
1737 #[inline(always)]
1738 pub const fn from_bits(val: u8) -> Muteval {
1739 unsafe { core::mem::transmute(val & 0x01) }
1740 }
1741 #[inline(always)]
1742 pub const fn to_bits(self) -> u8 {
1743 unsafe { core::mem::transmute(self) }
1744 }
1745 }
1746 impl From<u8> for Muteval {
1747 #[inline(always)]
1748 fn from(val: u8) -> Muteval {
1749 Muteval::from_bits(val)
1750 }
1751 }
1752 impl From<Muteval> for u8 {
1753 #[inline(always)]
1754 fn from(val: Muteval) -> u8 {
1755 Muteval::to_bits(val)
1756 }
1757 }
1758 #[repr(u8)]
1759 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1760 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1761 pub enum Nodiv {
1762 #[doc = "MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value"]
1763 MASTER_CLOCK = 0x0,
1764 #[doc = "MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL."]
1765 NO_DIV = 0x01,
1766 }
1767 impl Nodiv {
1768 #[inline(always)]
1769 pub const fn from_bits(val: u8) -> Nodiv {
1770 unsafe { core::mem::transmute(val & 0x01) }
1771 }
1772 #[inline(always)]
1773 pub const fn to_bits(self) -> u8 {
1774 unsafe { core::mem::transmute(self) }
1775 }
1776 }
1777 impl From<u8> for Nodiv {
1778 #[inline(always)]
1779 fn from(val: u8) -> Nodiv {
1780 Nodiv::from_bits(val)
1781 }
1782 }
1783 impl From<Nodiv> for u8 {
1784 #[inline(always)]
1785 fn from(val: Nodiv) -> u8 {
1786 Nodiv::to_bits(val)
1787 }
1788 }
1789 #[repr(u8)]
1790 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1791 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1792 pub enum Outdriv {
1793 #[doc = "Audio block output driven when SAIEN is set"]
1794 ON_START = 0x0,
1795 #[doc = "Audio block output driven immediately after the setting of this bit"]
1796 IMMEDIATELY = 0x01,
1797 }
1798 impl Outdriv {
1799 #[inline(always)]
1800 pub const fn from_bits(val: u8) -> Outdriv {
1801 unsafe { core::mem::transmute(val & 0x01) }
1802 }
1803 #[inline(always)]
1804 pub const fn to_bits(self) -> u8 {
1805 unsafe { core::mem::transmute(self) }
1806 }
1807 }
1808 impl From<u8> for Outdriv {
1809 #[inline(always)]
1810 fn from(val: u8) -> Outdriv {
1811 Outdriv::from_bits(val)
1812 }
1813 }
1814 impl From<Outdriv> for u8 {
1815 #[inline(always)]
1816 fn from(val: Outdriv) -> u8 {
1817 Outdriv::to_bits(val)
1818 }
1819 }
1820 #[repr(u8)]
1821 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1822 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1823 pub enum Prtcfg {
1824 #[doc = "Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol"]
1825 FREE = 0x0,
1826 #[doc = "SPDIF protocol"]
1827 SPDIF = 0x01,
1828 #[doc = "AC’97 protocol"]
1829 AC97 = 0x02,
1830 _RESERVED_3 = 0x03,
1831 }
1832 impl Prtcfg {
1833 #[inline(always)]
1834 pub const fn from_bits(val: u8) -> Prtcfg {
1835 unsafe { core::mem::transmute(val & 0x03) }
1836 }
1837 #[inline(always)]
1838 pub const fn to_bits(self) -> u8 {
1839 unsafe { core::mem::transmute(self) }
1840 }
1841 }
1842 impl From<u8> for Prtcfg {
1843 #[inline(always)]
1844 fn from(val: u8) -> Prtcfg {
1845 Prtcfg::from_bits(val)
1846 }
1847 }
1848 impl From<Prtcfg> for u8 {
1849 #[inline(always)]
1850 fn from(val: Prtcfg) -> u8 {
1851 Prtcfg::to_bits(val)
1852 }
1853 }
1854 #[repr(transparent)]
1855 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1856 pub struct Sloten(pub u16);
1857 impl Sloten {
1858 #[doc = "Inactive slot"]
1859 pub const INACTIVE: Self = Self(0x0);
1860 #[doc = "Active slot"]
1861 pub const ACTIVE: Self = Self(0x01);
1862 }
1863 impl Sloten {
1864 pub const fn from_bits(val: u16) -> Sloten {
1865 Self(val & 0xffff)
1866 }
1867 pub const fn to_bits(self) -> u16 {
1868 self.0
1869 }
1870 }
1871 impl core::fmt::Debug for Sloten {
1872 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1873 match self.0 {
1874 0x0 => f.write_str("INACTIVE"),
1875 0x01 => f.write_str("ACTIVE"),
1876 other => core::write!(f, "0x{:02X}", other),
1877 }
1878 }
1879 }
1880 #[cfg(feature = "defmt")]
1881 impl defmt::Format for Sloten {
1882 fn format(&self, f: defmt::Formatter) {
1883 match self.0 {
1884 0x0 => defmt::write!(f, "INACTIVE"),
1885 0x01 => defmt::write!(f, "ACTIVE"),
1886 other => defmt::write!(f, "0x{:02X}", other),
1887 }
1888 }
1889 }
1890 impl From<u16> for Sloten {
1891 #[inline(always)]
1892 fn from(val: u16) -> Sloten {
1893 Sloten::from_bits(val)
1894 }
1895 }
1896 impl From<Sloten> for u16 {
1897 #[inline(always)]
1898 fn from(val: Sloten) -> u16 {
1899 Sloten::to_bits(val)
1900 }
1901 }
1902 #[repr(u8)]
1903 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1904 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1905 pub enum Slotsz {
1906 #[doc = "The slot size is equivalent to the data size (specified in DS\\[3:0\\]
1907in the SAI_xCR1 register)"]
1908 DATA_SIZE = 0x0,
1909 #[doc = "16-bit"]
1910 BIT16 = 0x01,
1911 #[doc = "32-bit"]
1912 BIT32 = 0x02,
1913 _RESERVED_3 = 0x03,
1914 }
1915 impl Slotsz {
1916 #[inline(always)]
1917 pub const fn from_bits(val: u8) -> Slotsz {
1918 unsafe { core::mem::transmute(val & 0x03) }
1919 }
1920 #[inline(always)]
1921 pub const fn to_bits(self) -> u8 {
1922 unsafe { core::mem::transmute(self) }
1923 }
1924 }
1925 impl From<u8> for Slotsz {
1926 #[inline(always)]
1927 fn from(val: u8) -> Slotsz {
1928 Slotsz::from_bits(val)
1929 }
1930 }
1931 impl From<Slotsz> for u8 {
1932 #[inline(always)]
1933 fn from(val: Slotsz) -> u8 {
1934 Slotsz::to_bits(val)
1935 }
1936 }
1937 #[repr(u8)]
1938 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1939 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1940 pub enum Syncen {
1941 #[doc = "audio sub-block in asynchronous mode"]
1942 ASYNCHRONOUS = 0x0,
1943 #[doc = "audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode"]
1944 INTERNAL = 0x01,
1945 #[doc = "audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode"]
1946 EXTERNAL = 0x02,
1947 _RESERVED_3 = 0x03,
1948 }
1949 impl Syncen {
1950 #[inline(always)]
1951 pub const fn from_bits(val: u8) -> Syncen {
1952 unsafe { core::mem::transmute(val & 0x03) }
1953 }
1954 #[inline(always)]
1955 pub const fn to_bits(self) -> u8 {
1956 unsafe { core::mem::transmute(self) }
1957 }
1958 }
1959 impl From<u8> for Syncen {
1960 #[inline(always)]
1961 fn from(val: u8) -> Syncen {
1962 Syncen::from_bits(val)
1963 }
1964 }
1965 impl From<Syncen> for u8 {
1966 #[inline(always)]
1967 fn from(val: Syncen) -> u8 {
1968 Syncen::to_bits(val)
1969 }
1970 }
1971 #[repr(u8)]
1972 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1973 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1974 pub enum Wckcfg {
1975 #[doc = "Clock configuration is correct"]
1976 CORRECT = 0x0,
1977 #[doc = "Clock configuration does not respect the rule concerning the frame length specification"]
1978 WRONG = 0x01,
1979 }
1980 impl Wckcfg {
1981 #[inline(always)]
1982 pub const fn from_bits(val: u8) -> Wckcfg {
1983 unsafe { core::mem::transmute(val & 0x01) }
1984 }
1985 #[inline(always)]
1986 pub const fn to_bits(self) -> u8 {
1987 unsafe { core::mem::transmute(self) }
1988 }
1989 }
1990 impl From<u8> for Wckcfg {
1991 #[inline(always)]
1992 fn from(val: u8) -> Wckcfg {
1993 Wckcfg::from_bits(val)
1994 }
1995 }
1996 impl From<Wckcfg> for u8 {
1997 #[inline(always)]
1998 fn from(val: Wckcfg) -> u8 {
1999 Wckcfg::to_bits(val)
2000 }
2001 }
2002}
2003