1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "SDMMC"]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Sdmmc {
9 ptr: *mut u8,
10}
11unsafe impl Send for Sdmmc {}
12unsafe impl Sync for Sdmmc {}
13impl Sdmmc {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "SDMMC power control register"]
23 #[inline(always)]
24 pub const fn power(self) -> crate::common::Reg<regs::Power, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width."]
28 #[inline(always)]
29 pub const fn clkcr(self) -> crate::common::Reg<regs::Clkcr, crate::common::RW> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
31 }
32 #[doc = "The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message."]
33 #[inline(always)]
34 pub const fn argr(self) -> crate::common::Reg<regs::Argr, crate::common::RW> {
35 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
36 }
37 #[doc = "The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM)."]
38 #[inline(always)]
39 pub const fn cmdr(self) -> crate::common::Reg<regs::Cmdr, crate::common::RW> {
40 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
41 }
42 #[doc = "SDMMC command response register"]
43 #[inline(always)]
44 pub const fn respcmdr(self) -> crate::common::Reg<regs::Respcmdr, crate::common::R> {
45 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
46 }
47 #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."]
48 #[inline(always)]
49 pub const fn respr(self, n: usize) -> crate::common::Reg<regs::RespxR, crate::common::R> {
50 assert!(n < 4usize);
51 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize + n * 4usize) as _) }
52 }
53 #[doc = "The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set."]
54 #[inline(always)]
55 pub const fn dtimer(self) -> crate::common::Reg<regs::Dtimer, crate::common::RW> {
56 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
57 }
58 #[doc = "The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts."]
59 #[inline(always)]
60 pub const fn dlenr(self) -> crate::common::Reg<regs::Dlenr, crate::common::RW> {
61 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
62 }
63 #[doc = "The SDMMC_DCTRL register control the data path state machine (DPSM)."]
64 #[inline(always)]
65 pub const fn dctrl(self) -> crate::common::Reg<regs::Dctrl, crate::common::RW> {
66 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
67 }
68 #[doc = "The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set."]
69 #[inline(always)]
70 pub const fn dcntr(self) -> crate::common::Reg<regs::Dcntr, crate::common::R> {
71 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) }
72 }
73 #[doc = "The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits \\[29,21,11:0\\]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits \\[20:12\\]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)"]
74 #[inline(always)]
75 pub const fn star(self) -> crate::common::Reg<regs::Star, crate::common::R> {
76 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) }
77 }
78 #[doc = "The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register."]
79 #[inline(always)]
80 pub const fn icr(self) -> crate::common::Reg<regs::Icr, crate::common::RW> {
81 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) }
82 }
83 #[doc = "The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1."]
84 #[inline(always)]
85 pub const fn maskr(self) -> crate::common::Reg<regs::Maskr, crate::common::RW> {
86 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x3cusize) as _) }
87 }
88 #[doc = "The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set."]
89 #[inline(always)]
90 pub const fn acktimer(self) -> crate::common::Reg<regs::Acktimer, crate::common::RW> {
91 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) }
92 }
93 #[doc = "The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO."]
94 #[inline(always)]
95 pub const fn idmactrlr(self) -> crate::common::Reg<regs::Idmactrlr, crate::common::RW> {
96 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x50usize) as _) }
97 }
98 #[doc = "The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration."]
99 #[inline(always)]
100 pub const fn idmabsizer(self) -> crate::common::Reg<regs::Idmabsizer, crate::common::RW> {
101 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x54usize) as _) }
102 }
103 #[doc = "The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration."]
104 #[inline(always)]
105 pub const fn idmabase0r(self) -> crate::common::Reg<regs::Idmabase0r, crate::common::RW> {
106 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x58usize) as _) }
107 }
108 #[doc = "The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address."]
109 #[inline(always)]
110 pub const fn idmabase1r(self) -> crate::common::Reg<regs::Idmabase1r, crate::common::RW> {
111 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) }
112 }
113 #[doc = "The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated."]
114 #[inline(always)]
115 pub const fn fifor(self) -> crate::common::Reg<regs::Fifor, crate::common::RW> {
116 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x80usize) as _) }
117 }
118 #[doc = "SDMMC IP version register"]
119 #[inline(always)]
120 pub const fn ver(self) -> crate::common::Reg<regs::Ver, crate::common::R> {
121 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x03f4usize) as _) }
122 }
123 #[doc = "SDMMC IP identification register"]
124 #[inline(always)]
125 pub const fn id(self) -> crate::common::Reg<regs::Id, crate::common::R> {
126 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x03f8usize) as _) }
127 }
128}
129pub mod regs {
130 #[doc = "The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set."]
131 #[repr(transparent)]
132 #[derive(Copy, Clone, Eq, PartialEq)]
133 pub struct Acktimer(pub u32);
134 impl Acktimer {
135 #[doc = "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods."]
136 #[inline(always)]
137 pub const fn acktime(&self) -> u32 {
138 let val = (self.0 >> 0usize) & 0x01ff_ffff;
139 val as u32
140 }
141 #[doc = "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods."]
142 #[inline(always)]
143 pub fn set_acktime(&mut self, val: u32) {
144 self.0 = (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize);
145 }
146 }
147 impl Default for Acktimer {
148 #[inline(always)]
149 fn default() -> Acktimer {
150 Acktimer(0)
151 }
152 }
153 impl core::fmt::Debug for Acktimer {
154 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
155 f.debug_struct("Acktimer").field("acktime", &self.acktime()).finish()
156 }
157 }
158 #[cfg(feature = "defmt")]
159 impl defmt::Format for Acktimer {
160 fn format(&self, f: defmt::Formatter) {
161 #[derive(defmt :: Format)]
162 struct Acktimer {
163 acktime: u32,
164 }
165 let proxy = Acktimer {
166 acktime: self.acktime(),
167 };
168 defmt::write!(f, "{}", proxy)
169 }
170 }
171 #[doc = "The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message."]
172 #[repr(transparent)]
173 #[derive(Copy, Clone, Eq, PartialEq)]
174 pub struct Argr(pub u32);
175 impl Argr {
176 #[doc = "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register."]
177 #[inline(always)]
178 pub const fn cmdarg(&self) -> u32 {
179 let val = (self.0 >> 0usize) & 0xffff_ffff;
180 val as u32
181 }
182 #[doc = "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register."]
183 #[inline(always)]
184 pub fn set_cmdarg(&mut self, val: u32) {
185 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
186 }
187 }
188 impl Default for Argr {
189 #[inline(always)]
190 fn default() -> Argr {
191 Argr(0)
192 }
193 }
194 impl core::fmt::Debug for Argr {
195 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
196 f.debug_struct("Argr").field("cmdarg", &self.cmdarg()).finish()
197 }
198 }
199 #[cfg(feature = "defmt")]
200 impl defmt::Format for Argr {
201 fn format(&self, f: defmt::Formatter) {
202 #[derive(defmt :: Format)]
203 struct Argr {
204 cmdarg: u32,
205 }
206 let proxy = Argr { cmdarg: self.cmdarg() };
207 defmt::write!(f, "{}", proxy)
208 }
209 }
210 #[doc = "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width."]
211 #[repr(transparent)]
212 #[derive(Copy, Clone, Eq, PartialEq)]
213 pub struct Clkcr(pub u32);
214 impl Clkcr {
215 #[doc = "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / \\[2 * CLKDIV\\]. 0xx: etc.. xxx: etc.."]
216 #[inline(always)]
217 pub const fn clkdiv(&self) -> u16 {
218 let val = (self.0 >> 0usize) & 0x03ff;
219 val as u16
220 }
221 #[doc = "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / \\[2 * CLKDIV\\]. 0xx: etc.. xxx: etc.."]
222 #[inline(always)]
223 pub fn set_clkdiv(&mut self, val: u16) {
224 self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize);
225 }
226 #[doc = "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:"]
227 #[inline(always)]
228 pub const fn pwrsav(&self) -> bool {
229 let val = (self.0 >> 12usize) & 0x01;
230 val != 0
231 }
232 #[doc = "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:"]
233 #[inline(always)]
234 pub fn set_pwrsav(&mut self, val: bool) {
235 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
236 }
237 #[doc = "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"]
238 #[inline(always)]
239 pub const fn widbus(&self) -> u8 {
240 let val = (self.0 >> 14usize) & 0x03;
241 val as u8
242 }
243 #[doc = "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"]
244 #[inline(always)]
245 pub fn set_widbus(&mut self, val: u8) {
246 self.0 = (self.0 & !(0x03 << 14usize)) | (((val as u32) & 0x03) << 14usize);
247 }
248 #[doc = "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division &gt;1 (CLKDIV &gt; 0) &amp; DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge."]
249 #[inline(always)]
250 pub const fn negedge(&self) -> bool {
251 let val = (self.0 >> 16usize) & 0x01;
252 val != 0
253 }
254 #[doc = "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division &gt;1 (CLKDIV &gt; 0) &amp; DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge."]
255 #[inline(always)]
256 pub fn set_negedge(&mut self, val: bool) {
257 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
258 }
259 #[doc = "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11."]
260 #[inline(always)]
261 pub const fn hwfc_en(&self) -> bool {
262 let val = (self.0 >> 17usize) & 0x01;
263 val != 0
264 }
265 #[doc = "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11."]
266 #[inline(always)]
267 pub fn set_hwfc_en(&mut self, val: bool) {
268 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
269 }
270 #[doc = "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS &gt; 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division &gt;1. (CLKDIV &gt; 0)"]
271 #[inline(always)]
272 pub const fn ddr(&self) -> bool {
273 let val = (self.0 >> 18usize) & 0x01;
274 val != 0
275 }
276 #[doc = "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS &gt; 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division &gt;1. (CLKDIV &gt; 0)"]
277 #[inline(always)]
278 pub fn set_ddr(&mut self, val: bool) {
279 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
280 }
281 #[doc = "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"]
282 #[inline(always)]
283 pub const fn busspeed(&self) -> bool {
284 let val = (self.0 >> 19usize) & 0x01;
285 val != 0
286 }
287 #[doc = "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"]
288 #[inline(always)]
289 pub fn set_busspeed(&mut self, val: bool) {
290 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
291 }
292 #[doc = "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"]
293 #[inline(always)]
294 pub const fn selclkrx(&self) -> u8 {
295 let val = (self.0 >> 20usize) & 0x03;
296 val as u8
297 }
298 #[doc = "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"]
299 #[inline(always)]
300 pub fn set_selclkrx(&mut self, val: u8) {
301 self.0 = (self.0 & !(0x03 << 20usize)) | (((val as u32) & 0x03) << 20usize);
302 }
303 }
304 impl Default for Clkcr {
305 #[inline(always)]
306 fn default() -> Clkcr {
307 Clkcr(0)
308 }
309 }
310 impl core::fmt::Debug for Clkcr {
311 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
312 f.debug_struct("Clkcr")
313 .field("clkdiv", &self.clkdiv())
314 .field("pwrsav", &self.pwrsav())
315 .field("widbus", &self.widbus())
316 .field("negedge", &self.negedge())
317 .field("hwfc_en", &self.hwfc_en())
318 .field("ddr", &self.ddr())
319 .field("busspeed", &self.busspeed())
320 .field("selclkrx", &self.selclkrx())
321 .finish()
322 }
323 }
324 #[cfg(feature = "defmt")]
325 impl defmt::Format for Clkcr {
326 fn format(&self, f: defmt::Formatter) {
327 #[derive(defmt :: Format)]
328 struct Clkcr {
329 clkdiv: u16,
330 pwrsav: bool,
331 widbus: u8,
332 negedge: bool,
333 hwfc_en: bool,
334 ddr: bool,
335 busspeed: bool,
336 selclkrx: u8,
337 }
338 let proxy = Clkcr {
339 clkdiv: self.clkdiv(),
340 pwrsav: self.pwrsav(),
341 widbus: self.widbus(),
342 negedge: self.negedge(),
343 hwfc_en: self.hwfc_en(),
344 ddr: self.ddr(),
345 busspeed: self.busspeed(),
346 selclkrx: self.selclkrx(),
347 };
348 defmt::write!(f, "{}", proxy)
349 }
350 }
351 #[doc = "The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM)."]
352 #[repr(transparent)]
353 #[derive(Copy, Clone, Eq, PartialEq)]
354 pub struct Cmdr(pub u32);
355 impl Cmdr {
356 #[doc = "Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message."]
357 #[inline(always)]
358 pub const fn cmdindex(&self) -> u8 {
359 let val = (self.0 >> 0usize) & 0x3f;
360 val as u8
361 }
362 #[doc = "Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message."]
363 #[inline(always)]
364 pub fn set_cmdindex(&mut self, val: u8) {
365 self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
366 }
367 #[doc = "The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent."]
368 #[inline(always)]
369 pub const fn cmdtrans(&self) -> bool {
370 let val = (self.0 >> 6usize) & 0x01;
371 val != 0
372 }
373 #[doc = "The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent."]
374 #[inline(always)]
375 pub fn set_cmdtrans(&mut self, val: bool) {
376 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
377 }
378 #[doc = "The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent."]
379 #[inline(always)]
380 pub const fn cmdstop(&self) -> bool {
381 let val = (self.0 >> 7usize) & 0x01;
382 val != 0
383 }
384 #[doc = "The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent."]
385 #[inline(always)]
386 pub fn set_cmdstop(&mut self, val: bool) {
387 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
388 }
389 #[doc = "Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response."]
390 #[inline(always)]
391 pub const fn waitresp(&self) -> u8 {
392 let val = (self.0 >> 8usize) & 0x03;
393 val as u8
394 }
395 #[doc = "Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response."]
396 #[inline(always)]
397 pub fn set_waitresp(&mut self, val: u8) {
398 self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize);
399 }
400 #[doc = "CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode."]
401 #[inline(always)]
402 pub const fn waitint(&self) -> bool {
403 let val = (self.0 >> 10usize) & 0x01;
404 val != 0
405 }
406 #[doc = "CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode."]
407 #[inline(always)]
408 pub fn set_waitint(&mut self, val: bool) {
409 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
410 }
411 #[doc = "CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card."]
412 #[inline(always)]
413 pub const fn waitpend(&self) -> bool {
414 let val = (self.0 >> 11usize) & 0x01;
415 val != 0
416 }
417 #[doc = "CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card."]
418 #[inline(always)]
419 pub fn set_waitpend(&mut self, val: bool) {
420 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
421 }
422 #[doc = "Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0."]
423 #[inline(always)]
424 pub const fn cpsmen(&self) -> bool {
425 let val = (self.0 >> 12usize) & 0x01;
426 val != 0
427 }
428 #[doc = "Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0."]
429 #[inline(always)]
430 pub fn set_cpsmen(&mut self, val: bool) {
431 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
432 }
433 #[doc = "Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state."]
434 #[inline(always)]
435 pub const fn dthold(&self) -> bool {
436 let val = (self.0 >> 13usize) & 0x01;
437 val != 0
438 }
439 #[doc = "Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state."]
440 #[inline(always)]
441 pub fn set_dthold(&mut self, val: bool) {
442 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
443 }
444 #[doc = "Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)"]
445 #[inline(always)]
446 pub const fn bootmode(&self) -> bool {
447 let val = (self.0 >> 14usize) & 0x01;
448 val != 0
449 }
450 #[doc = "Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)"]
451 #[inline(always)]
452 pub fn set_bootmode(&mut self, val: bool) {
453 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
454 }
455 #[doc = "Enable boot mode procedure."]
456 #[inline(always)]
457 pub const fn booten(&self) -> bool {
458 let val = (self.0 >> 15usize) & 0x01;
459 val != 0
460 }
461 #[doc = "Enable boot mode procedure."]
462 #[inline(always)]
463 pub fn set_booten(&mut self, val: bool) {
464 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
465 }
466 #[doc = "The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1."]
467 #[inline(always)]
468 pub const fn cmdsuspend(&self) -> bool {
469 let val = (self.0 >> 16usize) & 0x01;
470 val != 0
471 }
472 #[doc = "The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1."]
473 #[inline(always)]
474 pub fn set_cmdsuspend(&mut self, val: bool) {
475 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
476 }
477 }
478 impl Default for Cmdr {
479 #[inline(always)]
480 fn default() -> Cmdr {
481 Cmdr(0)
482 }
483 }
484 impl core::fmt::Debug for Cmdr {
485 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
486 f.debug_struct("Cmdr")
487 .field("cmdindex", &self.cmdindex())
488 .field("cmdtrans", &self.cmdtrans())
489 .field("cmdstop", &self.cmdstop())
490 .field("waitresp", &self.waitresp())
491 .field("waitint", &self.waitint())
492 .field("waitpend", &self.waitpend())
493 .field("cpsmen", &self.cpsmen())
494 .field("dthold", &self.dthold())
495 .field("bootmode", &self.bootmode())
496 .field("booten", &self.booten())
497 .field("cmdsuspend", &self.cmdsuspend())
498 .finish()
499 }
500 }
501 #[cfg(feature = "defmt")]
502 impl defmt::Format for Cmdr {
503 fn format(&self, f: defmt::Formatter) {
504 #[derive(defmt :: Format)]
505 struct Cmdr {
506 cmdindex: u8,
507 cmdtrans: bool,
508 cmdstop: bool,
509 waitresp: u8,
510 waitint: bool,
511 waitpend: bool,
512 cpsmen: bool,
513 dthold: bool,
514 bootmode: bool,
515 booten: bool,
516 cmdsuspend: bool,
517 }
518 let proxy = Cmdr {
519 cmdindex: self.cmdindex(),
520 cmdtrans: self.cmdtrans(),
521 cmdstop: self.cmdstop(),
522 waitresp: self.waitresp(),
523 waitint: self.waitint(),
524 waitpend: self.waitpend(),
525 cpsmen: self.cpsmen(),
526 dthold: self.dthold(),
527 bootmode: self.bootmode(),
528 booten: self.booten(),
529 cmdsuspend: self.cmdsuspend(),
530 };
531 defmt::write!(f, "{}", proxy)
532 }
533 }
534 #[doc = "The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set."]
535 #[repr(transparent)]
536 #[derive(Copy, Clone, Eq, PartialEq)]
537 pub struct Dcntr(pub u32);
538 impl Dcntr {
539 #[doc = "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect."]
540 #[inline(always)]
541 pub const fn datacount(&self) -> u32 {
542 let val = (self.0 >> 0usize) & 0x01ff_ffff;
543 val as u32
544 }
545 #[doc = "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect."]
546 #[inline(always)]
547 pub fn set_datacount(&mut self, val: u32) {
548 self.0 = (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize);
549 }
550 }
551 impl Default for Dcntr {
552 #[inline(always)]
553 fn default() -> Dcntr {
554 Dcntr(0)
555 }
556 }
557 impl core::fmt::Debug for Dcntr {
558 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
559 f.debug_struct("Dcntr").field("datacount", &self.datacount()).finish()
560 }
561 }
562 #[cfg(feature = "defmt")]
563 impl defmt::Format for Dcntr {
564 fn format(&self, f: defmt::Formatter) {
565 #[derive(defmt :: Format)]
566 struct Dcntr {
567 datacount: u32,
568 }
569 let proxy = Dcntr {
570 datacount: self.datacount(),
571 };
572 defmt::write!(f, "{}", proxy)
573 }
574 }
575 #[doc = "The SDMMC_DCTRL register control the data path state machine (DPSM)."]
576 #[repr(transparent)]
577 #[derive(Copy, Clone, Eq, PartialEq)]
578 pub struct Dctrl(pub u32);
579 impl Dctrl {
580 #[doc = "Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards."]
581 #[inline(always)]
582 pub const fn dten(&self) -> bool {
583 let val = (self.0 >> 0usize) & 0x01;
584 val != 0
585 }
586 #[doc = "Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards."]
587 #[inline(always)]
588 pub fn set_dten(&mut self, val: bool) {
589 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
590 }
591 #[doc = "Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
592 #[inline(always)]
593 pub const fn dtdir(&self) -> bool {
594 let val = (self.0 >> 1usize) & 0x01;
595 val != 0
596 }
597 #[doc = "Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
598 #[inline(always)]
599 pub fn set_dtdir(&mut self, val: bool) {
600 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
601 }
602 #[doc = "Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
603 #[inline(always)]
604 pub const fn dtmode(&self) -> u8 {
605 let val = (self.0 >> 2usize) & 0x03;
606 val as u8
607 }
608 #[doc = "Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
609 #[inline(always)]
610 pub fn set_dtmode(&mut self, val: u8) {
611 self.0 = (self.0 & !(0x03 << 2usize)) | (((val as u32) & 0x03) << 2usize);
612 }
613 #[doc = "Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)"]
614 #[inline(always)]
615 pub const fn dblocksize(&self) -> u8 {
616 let val = (self.0 >> 4usize) & 0x0f;
617 val as u8
618 }
619 #[doc = "Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)"]
620 #[inline(always)]
621 pub fn set_dblocksize(&mut self, val: u8) {
622 self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
623 }
624 #[doc = "Read wait start. If this bit is set, read wait operation starts."]
625 #[inline(always)]
626 pub const fn rwstart(&self) -> bool {
627 let val = (self.0 >> 8usize) & 0x01;
628 val != 0
629 }
630 #[doc = "Read wait start. If this bit is set, read wait operation starts."]
631 #[inline(always)]
632 pub fn set_rwstart(&mut self, val: bool) {
633 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
634 }
635 #[doc = "Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state."]
636 #[inline(always)]
637 pub const fn rwstop(&self) -> bool {
638 let val = (self.0 >> 9usize) & 0x01;
639 val != 0
640 }
641 #[doc = "Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state."]
642 #[inline(always)]
643 pub fn set_rwstop(&mut self, val: bool) {
644 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
645 }
646 #[doc = "Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
647 #[inline(always)]
648 pub const fn rwmod(&self) -> bool {
649 let val = (self.0 >> 10usize) & 0x01;
650 val != 0
651 }
652 #[doc = "Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
653 #[inline(always)]
654 pub fn set_rwmod(&mut self, val: bool) {
655 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
656 }
657 #[doc = "SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation."]
658 #[inline(always)]
659 pub const fn sdioen(&self) -> bool {
660 let val = (self.0 >> 11usize) & 0x01;
661 val != 0
662 }
663 #[doc = "SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation."]
664 #[inline(always)]
665 pub fn set_sdioen(&mut self, val: bool) {
666 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
667 }
668 #[doc = "Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
669 #[inline(always)]
670 pub const fn bootacken(&self) -> bool {
671 let val = (self.0 >> 12usize) & 0x01;
672 val != 0
673 }
674 #[doc = "Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
675 #[inline(always)]
676 pub fn set_bootacken(&mut self, val: bool) {
677 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
678 }
679 #[doc = "FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs."]
680 #[inline(always)]
681 pub const fn fiforst(&self) -> bool {
682 let val = (self.0 >> 13usize) & 0x01;
683 val != 0
684 }
685 #[doc = "FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs."]
686 #[inline(always)]
687 pub fn set_fiforst(&mut self, val: bool) {
688 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
689 }
690 }
691 impl Default for Dctrl {
692 #[inline(always)]
693 fn default() -> Dctrl {
694 Dctrl(0)
695 }
696 }
697 impl core::fmt::Debug for Dctrl {
698 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
699 f.debug_struct("Dctrl")
700 .field("dten", &self.dten())
701 .field("dtdir", &self.dtdir())
702 .field("dtmode", &self.dtmode())
703 .field("dblocksize", &self.dblocksize())
704 .field("rwstart", &self.rwstart())
705 .field("rwstop", &self.rwstop())
706 .field("rwmod", &self.rwmod())
707 .field("sdioen", &self.sdioen())
708 .field("bootacken", &self.bootacken())
709 .field("fiforst", &self.fiforst())
710 .finish()
711 }
712 }
713 #[cfg(feature = "defmt")]
714 impl defmt::Format for Dctrl {
715 fn format(&self, f: defmt::Formatter) {
716 #[derive(defmt :: Format)]
717 struct Dctrl {
718 dten: bool,
719 dtdir: bool,
720 dtmode: u8,
721 dblocksize: u8,
722 rwstart: bool,
723 rwstop: bool,
724 rwmod: bool,
725 sdioen: bool,
726 bootacken: bool,
727 fiforst: bool,
728 }
729 let proxy = Dctrl {
730 dten: self.dten(),
731 dtdir: self.dtdir(),
732 dtmode: self.dtmode(),
733 dblocksize: self.dblocksize(),
734 rwstart: self.rwstart(),
735 rwstop: self.rwstop(),
736 rwmod: self.rwmod(),
737 sdioen: self.sdioen(),
738 bootacken: self.bootacken(),
739 fiforst: self.fiforst(),
740 };
741 defmt::write!(f, "{}", proxy)
742 }
743 }
744 #[doc = "The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts."]
745 #[repr(transparent)]
746 #[derive(Copy, Clone, Eq, PartialEq)]
747 pub struct Dlenr(pub u32);
748 impl Dlenr {
749 #[doc = "Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0."]
750 #[inline(always)]
751 pub const fn datalength(&self) -> u32 {
752 let val = (self.0 >> 0usize) & 0x01ff_ffff;
753 val as u32
754 }
755 #[doc = "Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0."]
756 #[inline(always)]
757 pub fn set_datalength(&mut self, val: u32) {
758 self.0 = (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize);
759 }
760 }
761 impl Default for Dlenr {
762 #[inline(always)]
763 fn default() -> Dlenr {
764 Dlenr(0)
765 }
766 }
767 impl core::fmt::Debug for Dlenr {
768 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
769 f.debug_struct("Dlenr").field("datalength", &self.datalength()).finish()
770 }
771 }
772 #[cfg(feature = "defmt")]
773 impl defmt::Format for Dlenr {
774 fn format(&self, f: defmt::Formatter) {
775 #[derive(defmt :: Format)]
776 struct Dlenr {
777 datalength: u32,
778 }
779 let proxy = Dlenr {
780 datalength: self.datalength(),
781 };
782 defmt::write!(f, "{}", proxy)
783 }
784 }
785 #[doc = "The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set."]
786 #[repr(transparent)]
787 #[derive(Copy, Clone, Eq, PartialEq)]
788 pub struct Dtimer(pub u32);
789 impl Dtimer {
790 #[doc = "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods."]
791 #[inline(always)]
792 pub const fn datatime(&self) -> u32 {
793 let val = (self.0 >> 0usize) & 0xffff_ffff;
794 val as u32
795 }
796 #[doc = "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods."]
797 #[inline(always)]
798 pub fn set_datatime(&mut self, val: u32) {
799 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
800 }
801 }
802 impl Default for Dtimer {
803 #[inline(always)]
804 fn default() -> Dtimer {
805 Dtimer(0)
806 }
807 }
808 impl core::fmt::Debug for Dtimer {
809 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
810 f.debug_struct("Dtimer").field("datatime", &self.datatime()).finish()
811 }
812 }
813 #[cfg(feature = "defmt")]
814 impl defmt::Format for Dtimer {
815 fn format(&self, f: defmt::Formatter) {
816 #[derive(defmt :: Format)]
817 struct Dtimer {
818 datatime: u32,
819 }
820 let proxy = Dtimer {
821 datatime: self.datatime(),
822 };
823 defmt::write!(f, "{}", proxy)
824 }
825 }
826 #[doc = "The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated."]
827 #[repr(transparent)]
828 #[derive(Copy, Clone, Eq, PartialEq)]
829 pub struct Fifor(pub u32);
830 impl Fifor {
831 #[doc = "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words."]
832 #[inline(always)]
833 pub const fn fifodata(&self) -> u32 {
834 let val = (self.0 >> 0usize) & 0xffff_ffff;
835 val as u32
836 }
837 #[doc = "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words."]
838 #[inline(always)]
839 pub fn set_fifodata(&mut self, val: u32) {
840 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
841 }
842 }
843 impl Default for Fifor {
844 #[inline(always)]
845 fn default() -> Fifor {
846 Fifor(0)
847 }
848 }
849 impl core::fmt::Debug for Fifor {
850 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
851 f.debug_struct("Fifor").field("fifodata", &self.fifodata()).finish()
852 }
853 }
854 #[cfg(feature = "defmt")]
855 impl defmt::Format for Fifor {
856 fn format(&self, f: defmt::Formatter) {
857 #[derive(defmt :: Format)]
858 struct Fifor {
859 fifodata: u32,
860 }
861 let proxy = Fifor {
862 fifodata: self.fifodata(),
863 };
864 defmt::write!(f, "{}", proxy)
865 }
866 }
867 #[doc = "The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register."]
868 #[repr(transparent)]
869 #[derive(Copy, Clone, Eq, PartialEq)]
870 pub struct Icr(pub u32);
871 impl Icr {
872 #[doc = "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag."]
873 #[inline(always)]
874 pub const fn ccrcfailc(&self) -> bool {
875 let val = (self.0 >> 0usize) & 0x01;
876 val != 0
877 }
878 #[doc = "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag."]
879 #[inline(always)]
880 pub fn set_ccrcfailc(&mut self, val: bool) {
881 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
882 }
883 #[doc = "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag."]
884 #[inline(always)]
885 pub const fn dcrcfailc(&self) -> bool {
886 let val = (self.0 >> 1usize) & 0x01;
887 val != 0
888 }
889 #[doc = "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag."]
890 #[inline(always)]
891 pub fn set_dcrcfailc(&mut self, val: bool) {
892 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
893 }
894 #[doc = "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag."]
895 #[inline(always)]
896 pub const fn ctimeoutc(&self) -> bool {
897 let val = (self.0 >> 2usize) & 0x01;
898 val != 0
899 }
900 #[doc = "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag."]
901 #[inline(always)]
902 pub fn set_ctimeoutc(&mut self, val: bool) {
903 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
904 }
905 #[doc = "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag."]
906 #[inline(always)]
907 pub const fn dtimeoutc(&self) -> bool {
908 let val = (self.0 >> 3usize) & 0x01;
909 val != 0
910 }
911 #[doc = "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag."]
912 #[inline(always)]
913 pub fn set_dtimeoutc(&mut self, val: bool) {
914 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
915 }
916 #[doc = "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag."]
917 #[inline(always)]
918 pub const fn txunderrc(&self) -> bool {
919 let val = (self.0 >> 4usize) & 0x01;
920 val != 0
921 }
922 #[doc = "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag."]
923 #[inline(always)]
924 pub fn set_txunderrc(&mut self, val: bool) {
925 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
926 }
927 #[doc = "RXOVERR flag clear bit Set by software to clear the RXOVERR flag."]
928 #[inline(always)]
929 pub const fn rxoverrc(&self) -> bool {
930 let val = (self.0 >> 5usize) & 0x01;
931 val != 0
932 }
933 #[doc = "RXOVERR flag clear bit Set by software to clear the RXOVERR flag."]
934 #[inline(always)]
935 pub fn set_rxoverrc(&mut self, val: bool) {
936 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
937 }
938 #[doc = "CMDREND flag clear bit Set by software to clear the CMDREND flag."]
939 #[inline(always)]
940 pub const fn cmdrendc(&self) -> bool {
941 let val = (self.0 >> 6usize) & 0x01;
942 val != 0
943 }
944 #[doc = "CMDREND flag clear bit Set by software to clear the CMDREND flag."]
945 #[inline(always)]
946 pub fn set_cmdrendc(&mut self, val: bool) {
947 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
948 }
949 #[doc = "CMDSENT flag clear bit Set by software to clear the CMDSENT flag."]
950 #[inline(always)]
951 pub const fn cmdsentc(&self) -> bool {
952 let val = (self.0 >> 7usize) & 0x01;
953 val != 0
954 }
955 #[doc = "CMDSENT flag clear bit Set by software to clear the CMDSENT flag."]
956 #[inline(always)]
957 pub fn set_cmdsentc(&mut self, val: bool) {
958 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
959 }
960 #[doc = "DATAEND flag clear bit Set by software to clear the DATAEND flag."]
961 #[inline(always)]
962 pub const fn dataendc(&self) -> bool {
963 let val = (self.0 >> 8usize) & 0x01;
964 val != 0
965 }
966 #[doc = "DATAEND flag clear bit Set by software to clear the DATAEND flag."]
967 #[inline(always)]
968 pub fn set_dataendc(&mut self, val: bool) {
969 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
970 }
971 #[doc = "DHOLD flag clear bit Set by software to clear the DHOLD flag."]
972 #[inline(always)]
973 pub const fn dholdc(&self) -> bool {
974 let val = (self.0 >> 9usize) & 0x01;
975 val != 0
976 }
977 #[doc = "DHOLD flag clear bit Set by software to clear the DHOLD flag."]
978 #[inline(always)]
979 pub fn set_dholdc(&mut self, val: bool) {
980 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
981 }
982 #[doc = "DBCKEND flag clear bit Set by software to clear the DBCKEND flag."]
983 #[inline(always)]
984 pub const fn dbckendc(&self) -> bool {
985 let val = (self.0 >> 10usize) & 0x01;
986 val != 0
987 }
988 #[doc = "DBCKEND flag clear bit Set by software to clear the DBCKEND flag."]
989 #[inline(always)]
990 pub fn set_dbckendc(&mut self, val: bool) {
991 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
992 }
993 #[doc = "DABORT flag clear bit Set by software to clear the DABORT flag."]
994 #[inline(always)]
995 pub const fn dabortc(&self) -> bool {
996 let val = (self.0 >> 11usize) & 0x01;
997 val != 0
998 }
999 #[doc = "DABORT flag clear bit Set by software to clear the DABORT flag."]
1000 #[inline(always)]
1001 pub fn set_dabortc(&mut self, val: bool) {
1002 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
1003 }
1004 #[doc = "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag."]
1005 #[inline(always)]
1006 pub const fn busyd0endc(&self) -> bool {
1007 let val = (self.0 >> 21usize) & 0x01;
1008 val != 0
1009 }
1010 #[doc = "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag."]
1011 #[inline(always)]
1012 pub fn set_busyd0endc(&mut self, val: bool) {
1013 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
1014 }
1015 #[doc = "SDIOIT flag clear bit Set by software to clear the SDIOIT flag."]
1016 #[inline(always)]
1017 pub const fn sdioitc(&self) -> bool {
1018 let val = (self.0 >> 22usize) & 0x01;
1019 val != 0
1020 }
1021 #[doc = "SDIOIT flag clear bit Set by software to clear the SDIOIT flag."]
1022 #[inline(always)]
1023 pub fn set_sdioitc(&mut self, val: bool) {
1024 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
1025 }
1026 #[doc = "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag."]
1027 #[inline(always)]
1028 pub const fn ackfailc(&self) -> bool {
1029 let val = (self.0 >> 23usize) & 0x01;
1030 val != 0
1031 }
1032 #[doc = "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag."]
1033 #[inline(always)]
1034 pub fn set_ackfailc(&mut self, val: bool) {
1035 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
1036 }
1037 #[doc = "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag."]
1038 #[inline(always)]
1039 pub const fn acktimeoutc(&self) -> bool {
1040 let val = (self.0 >> 24usize) & 0x01;
1041 val != 0
1042 }
1043 #[doc = "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag."]
1044 #[inline(always)]
1045 pub fn set_acktimeoutc(&mut self, val: bool) {
1046 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
1047 }
1048 #[doc = "VSWEND flag clear bit Set by software to clear the VSWEND flag."]
1049 #[inline(always)]
1050 pub const fn vswendc(&self) -> bool {
1051 let val = (self.0 >> 25usize) & 0x01;
1052 val != 0
1053 }
1054 #[doc = "VSWEND flag clear bit Set by software to clear the VSWEND flag."]
1055 #[inline(always)]
1056 pub fn set_vswendc(&mut self, val: bool) {
1057 self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
1058 }
1059 #[doc = "CKSTOP flag clear bit Set by software to clear the CKSTOP flag."]
1060 #[inline(always)]
1061 pub const fn ckstopc(&self) -> bool {
1062 let val = (self.0 >> 26usize) & 0x01;
1063 val != 0
1064 }
1065 #[doc = "CKSTOP flag clear bit Set by software to clear the CKSTOP flag."]
1066 #[inline(always)]
1067 pub fn set_ckstopc(&mut self, val: bool) {
1068 self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
1069 }
1070 #[doc = "IDMA transfer error clear bit Set by software to clear the IDMATE flag."]
1071 #[inline(always)]
1072 pub const fn idmatec(&self) -> bool {
1073 let val = (self.0 >> 27usize) & 0x01;
1074 val != 0
1075 }
1076 #[doc = "IDMA transfer error clear bit Set by software to clear the IDMATE flag."]
1077 #[inline(always)]
1078 pub fn set_idmatec(&mut self, val: bool) {
1079 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
1080 }
1081 #[doc = "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag."]
1082 #[inline(always)]
1083 pub const fn idmabtcc(&self) -> bool {
1084 let val = (self.0 >> 28usize) & 0x01;
1085 val != 0
1086 }
1087 #[doc = "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag."]
1088 #[inline(always)]
1089 pub fn set_idmabtcc(&mut self, val: bool) {
1090 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
1091 }
1092 }
1093 impl Default for Icr {
1094 #[inline(always)]
1095 fn default() -> Icr {
1096 Icr(0)
1097 }
1098 }
1099 impl core::fmt::Debug for Icr {
1100 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1101 f.debug_struct("Icr")
1102 .field("ccrcfailc", &self.ccrcfailc())
1103 .field("dcrcfailc", &self.dcrcfailc())
1104 .field("ctimeoutc", &self.ctimeoutc())
1105 .field("dtimeoutc", &self.dtimeoutc())
1106 .field("txunderrc", &self.txunderrc())
1107 .field("rxoverrc", &self.rxoverrc())
1108 .field("cmdrendc", &self.cmdrendc())
1109 .field("cmdsentc", &self.cmdsentc())
1110 .field("dataendc", &self.dataendc())
1111 .field("dholdc", &self.dholdc())
1112 .field("dbckendc", &self.dbckendc())
1113 .field("dabortc", &self.dabortc())
1114 .field("busyd0endc", &self.busyd0endc())
1115 .field("sdioitc", &self.sdioitc())
1116 .field("ackfailc", &self.ackfailc())
1117 .field("acktimeoutc", &self.acktimeoutc())
1118 .field("vswendc", &self.vswendc())
1119 .field("ckstopc", &self.ckstopc())
1120 .field("idmatec", &self.idmatec())
1121 .field("idmabtcc", &self.idmabtcc())
1122 .finish()
1123 }
1124 }
1125 #[cfg(feature = "defmt")]
1126 impl defmt::Format for Icr {
1127 fn format(&self, f: defmt::Formatter) {
1128 #[derive(defmt :: Format)]
1129 struct Icr {
1130 ccrcfailc: bool,
1131 dcrcfailc: bool,
1132 ctimeoutc: bool,
1133 dtimeoutc: bool,
1134 txunderrc: bool,
1135 rxoverrc: bool,
1136 cmdrendc: bool,
1137 cmdsentc: bool,
1138 dataendc: bool,
1139 dholdc: bool,
1140 dbckendc: bool,
1141 dabortc: bool,
1142 busyd0endc: bool,
1143 sdioitc: bool,
1144 ackfailc: bool,
1145 acktimeoutc: bool,
1146 vswendc: bool,
1147 ckstopc: bool,
1148 idmatec: bool,
1149 idmabtcc: bool,
1150 }
1151 let proxy = Icr {
1152 ccrcfailc: self.ccrcfailc(),
1153 dcrcfailc: self.dcrcfailc(),
1154 ctimeoutc: self.ctimeoutc(),
1155 dtimeoutc: self.dtimeoutc(),
1156 txunderrc: self.txunderrc(),
1157 rxoverrc: self.rxoverrc(),
1158 cmdrendc: self.cmdrendc(),
1159 cmdsentc: self.cmdsentc(),
1160 dataendc: self.dataendc(),
1161 dholdc: self.dholdc(),
1162 dbckendc: self.dbckendc(),
1163 dabortc: self.dabortc(),
1164 busyd0endc: self.busyd0endc(),
1165 sdioitc: self.sdioitc(),
1166 ackfailc: self.ackfailc(),
1167 acktimeoutc: self.acktimeoutc(),
1168 vswendc: self.vswendc(),
1169 ckstopc: self.ckstopc(),
1170 idmatec: self.idmatec(),
1171 idmabtcc: self.idmabtcc(),
1172 };
1173 defmt::write!(f, "{}", proxy)
1174 }
1175 }
1176 #[doc = "SDMMC IP identification register"]
1177 #[repr(transparent)]
1178 #[derive(Copy, Clone, Eq, PartialEq)]
1179 pub struct Id(pub u32);
1180 impl Id {
1181 #[doc = "SDMMC IP identification."]
1182 #[inline(always)]
1183 pub const fn ip_id(&self) -> u32 {
1184 let val = (self.0 >> 0usize) & 0xffff_ffff;
1185 val as u32
1186 }
1187 #[doc = "SDMMC IP identification."]
1188 #[inline(always)]
1189 pub fn set_ip_id(&mut self, val: u32) {
1190 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1191 }
1192 }
1193 impl Default for Id {
1194 #[inline(always)]
1195 fn default() -> Id {
1196 Id(0)
1197 }
1198 }
1199 impl core::fmt::Debug for Id {
1200 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1201 f.debug_struct("Id").field("ip_id", &self.ip_id()).finish()
1202 }
1203 }
1204 #[cfg(feature = "defmt")]
1205 impl defmt::Format for Id {
1206 fn format(&self, f: defmt::Formatter) {
1207 #[derive(defmt :: Format)]
1208 struct Id {
1209 ip_id: u32,
1210 }
1211 let proxy = Id { ip_id: self.ip_id() };
1212 defmt::write!(f, "{}", proxy)
1213 }
1214 }
1215 #[doc = "The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration."]
1216 #[repr(transparent)]
1217 #[derive(Copy, Clone, Eq, PartialEq)]
1218 pub struct Idmabase0r(pub u32);
1219 impl Idmabase0r {
1220 #[doc = "Buffer 0 memory base address bits \\[31:2\\], shall be word aligned (bit \\[1:0\\]
1221are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)."]
1222 #[inline(always)]
1223 pub const fn idmabase0(&self) -> u32 {
1224 let val = (self.0 >> 0usize) & 0xffff_ffff;
1225 val as u32
1226 }
1227 #[doc = "Buffer 0 memory base address bits \\[31:2\\], shall be word aligned (bit \\[1:0\\]
1228are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)."]
1229 #[inline(always)]
1230 pub fn set_idmabase0(&mut self, val: u32) {
1231 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1232 }
1233 }
1234 impl Default for Idmabase0r {
1235 #[inline(always)]
1236 fn default() -> Idmabase0r {
1237 Idmabase0r(0)
1238 }
1239 }
1240 impl core::fmt::Debug for Idmabase0r {
1241 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1242 f.debug_struct("Idmabase0r")
1243 .field("idmabase0", &self.idmabase0())
1244 .finish()
1245 }
1246 }
1247 #[cfg(feature = "defmt")]
1248 impl defmt::Format for Idmabase0r {
1249 fn format(&self, f: defmt::Formatter) {
1250 #[derive(defmt :: Format)]
1251 struct Idmabase0r {
1252 idmabase0: u32,
1253 }
1254 let proxy = Idmabase0r {
1255 idmabase0: self.idmabase0(),
1256 };
1257 defmt::write!(f, "{}", proxy)
1258 }
1259 }
1260 #[doc = "The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address."]
1261 #[repr(transparent)]
1262 #[derive(Copy, Clone, Eq, PartialEq)]
1263 pub struct Idmabase1r(pub u32);
1264 impl Idmabase1r {
1265 #[doc = "Buffer 1 memory base address, shall be word aligned (bit \\[1:0\\]
1266are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."]
1267 #[inline(always)]
1268 pub const fn idmabase1(&self) -> u32 {
1269 let val = (self.0 >> 0usize) & 0xffff_ffff;
1270 val as u32
1271 }
1272 #[doc = "Buffer 1 memory base address, shall be word aligned (bit \\[1:0\\]
1273are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."]
1274 #[inline(always)]
1275 pub fn set_idmabase1(&mut self, val: u32) {
1276 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1277 }
1278 }
1279 impl Default for Idmabase1r {
1280 #[inline(always)]
1281 fn default() -> Idmabase1r {
1282 Idmabase1r(0)
1283 }
1284 }
1285 impl core::fmt::Debug for Idmabase1r {
1286 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1287 f.debug_struct("Idmabase1r")
1288 .field("idmabase1", &self.idmabase1())
1289 .finish()
1290 }
1291 }
1292 #[cfg(feature = "defmt")]
1293 impl defmt::Format for Idmabase1r {
1294 fn format(&self, f: defmt::Formatter) {
1295 #[derive(defmt :: Format)]
1296 struct Idmabase1r {
1297 idmabase1: u32,
1298 }
1299 let proxy = Idmabase1r {
1300 idmabase1: self.idmabase1(),
1301 };
1302 defmt::write!(f, "{}", proxy)
1303 }
1304 }
1305 #[doc = "The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration."]
1306 #[repr(transparent)]
1307 #[derive(Copy, Clone, Eq, PartialEq)]
1308 pub struct Idmabsizer(pub u32);
1309 impl Idmabsizer {
1310 #[doc = "Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
1311 #[inline(always)]
1312 pub const fn idmabndt(&self) -> u8 {
1313 let val = (self.0 >> 5usize) & 0xff;
1314 val as u8
1315 }
1316 #[doc = "Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
1317 #[inline(always)]
1318 pub fn set_idmabndt(&mut self, val: u8) {
1319 self.0 = (self.0 & !(0xff << 5usize)) | (((val as u32) & 0xff) << 5usize);
1320 }
1321 }
1322 impl Default for Idmabsizer {
1323 #[inline(always)]
1324 fn default() -> Idmabsizer {
1325 Idmabsizer(0)
1326 }
1327 }
1328 impl core::fmt::Debug for Idmabsizer {
1329 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1330 f.debug_struct("Idmabsizer")
1331 .field("idmabndt", &self.idmabndt())
1332 .finish()
1333 }
1334 }
1335 #[cfg(feature = "defmt")]
1336 impl defmt::Format for Idmabsizer {
1337 fn format(&self, f: defmt::Formatter) {
1338 #[derive(defmt :: Format)]
1339 struct Idmabsizer {
1340 idmabndt: u8,
1341 }
1342 let proxy = Idmabsizer {
1343 idmabndt: self.idmabndt(),
1344 };
1345 defmt::write!(f, "{}", proxy)
1346 }
1347 }
1348 #[doc = "The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO."]
1349 #[repr(transparent)]
1350 #[derive(Copy, Clone, Eq, PartialEq)]
1351 pub struct Idmactrlr(pub u32);
1352 impl Idmactrlr {
1353 #[doc = "IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
1354 #[inline(always)]
1355 pub const fn idmaen(&self) -> bool {
1356 let val = (self.0 >> 0usize) & 0x01;
1357 val != 0
1358 }
1359 #[doc = "IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
1360 #[inline(always)]
1361 pub fn set_idmaen(&mut self, val: bool) {
1362 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1363 }
1364 #[doc = "Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
1365 #[inline(always)]
1366 pub const fn idmabmode(&self) -> bool {
1367 let val = (self.0 >> 1usize) & 0x01;
1368 val != 0
1369 }
1370 #[doc = "Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
1371 #[inline(always)]
1372 pub fn set_idmabmode(&mut self, val: bool) {
1373 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1374 }
1375 #[doc = "Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware."]
1376 #[inline(always)]
1377 pub const fn idmabact(&self) -> bool {
1378 let val = (self.0 >> 2usize) & 0x01;
1379 val != 0
1380 }
1381 #[doc = "Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware."]
1382 #[inline(always)]
1383 pub fn set_idmabact(&mut self, val: bool) {
1384 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1385 }
1386 }
1387 impl Default for Idmactrlr {
1388 #[inline(always)]
1389 fn default() -> Idmactrlr {
1390 Idmactrlr(0)
1391 }
1392 }
1393 impl core::fmt::Debug for Idmactrlr {
1394 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1395 f.debug_struct("Idmactrlr")
1396 .field("idmaen", &self.idmaen())
1397 .field("idmabmode", &self.idmabmode())
1398 .field("idmabact", &self.idmabact())
1399 .finish()
1400 }
1401 }
1402 #[cfg(feature = "defmt")]
1403 impl defmt::Format for Idmactrlr {
1404 fn format(&self, f: defmt::Formatter) {
1405 #[derive(defmt :: Format)]
1406 struct Idmactrlr {
1407 idmaen: bool,
1408 idmabmode: bool,
1409 idmabact: bool,
1410 }
1411 let proxy = Idmactrlr {
1412 idmaen: self.idmaen(),
1413 idmabmode: self.idmabmode(),
1414 idmabact: self.idmabact(),
1415 };
1416 defmt::write!(f, "{}", proxy)
1417 }
1418 }
1419 #[doc = "The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1."]
1420 #[repr(transparent)]
1421 #[derive(Copy, Clone, Eq, PartialEq)]
1422 pub struct Maskr(pub u32);
1423 impl Maskr {
1424 #[doc = "Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure."]
1425 #[inline(always)]
1426 pub const fn ccrcfailie(&self) -> bool {
1427 let val = (self.0 >> 0usize) & 0x01;
1428 val != 0
1429 }
1430 #[doc = "Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure."]
1431 #[inline(always)]
1432 pub fn set_ccrcfailie(&mut self, val: bool) {
1433 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1434 }
1435 #[doc = "Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure."]
1436 #[inline(always)]
1437 pub const fn dcrcfailie(&self) -> bool {
1438 let val = (self.0 >> 1usize) & 0x01;
1439 val != 0
1440 }
1441 #[doc = "Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure."]
1442 #[inline(always)]
1443 pub fn set_dcrcfailie(&mut self, val: bool) {
1444 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1445 }
1446 #[doc = "Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout."]
1447 #[inline(always)]
1448 pub const fn ctimeoutie(&self) -> bool {
1449 let val = (self.0 >> 2usize) & 0x01;
1450 val != 0
1451 }
1452 #[doc = "Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout."]
1453 #[inline(always)]
1454 pub fn set_ctimeoutie(&mut self, val: bool) {
1455 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1456 }
1457 #[doc = "Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout."]
1458 #[inline(always)]
1459 pub const fn dtimeoutie(&self) -> bool {
1460 let val = (self.0 >> 3usize) & 0x01;
1461 val != 0
1462 }
1463 #[doc = "Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout."]
1464 #[inline(always)]
1465 pub fn set_dtimeoutie(&mut self, val: bool) {
1466 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1467 }
1468 #[doc = "Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error."]
1469 #[inline(always)]
1470 pub const fn txunderrie(&self) -> bool {
1471 let val = (self.0 >> 4usize) & 0x01;
1472 val != 0
1473 }
1474 #[doc = "Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error."]
1475 #[inline(always)]
1476 pub fn set_txunderrie(&mut self, val: bool) {
1477 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1478 }
1479 #[doc = "Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error."]
1480 #[inline(always)]
1481 pub const fn rxoverrie(&self) -> bool {
1482 let val = (self.0 >> 5usize) & 0x01;
1483 val != 0
1484 }
1485 #[doc = "Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error."]
1486 #[inline(always)]
1487 pub fn set_rxoverrie(&mut self, val: bool) {
1488 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
1489 }
1490 #[doc = "Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response."]
1491 #[inline(always)]
1492 pub const fn cmdrendie(&self) -> bool {
1493 let val = (self.0 >> 6usize) & 0x01;
1494 val != 0
1495 }
1496 #[doc = "Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response."]
1497 #[inline(always)]
1498 pub fn set_cmdrendie(&mut self, val: bool) {
1499 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
1500 }
1501 #[doc = "Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command."]
1502 #[inline(always)]
1503 pub const fn cmdsentie(&self) -> bool {
1504 let val = (self.0 >> 7usize) & 0x01;
1505 val != 0
1506 }
1507 #[doc = "Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command."]
1508 #[inline(always)]
1509 pub fn set_cmdsentie(&mut self, val: bool) {
1510 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
1511 }
1512 #[doc = "Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end."]
1513 #[inline(always)]
1514 pub const fn dataendie(&self) -> bool {
1515 let val = (self.0 >> 8usize) & 0x01;
1516 val != 0
1517 }
1518 #[doc = "Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end."]
1519 #[inline(always)]
1520 pub fn set_dataendie(&mut self, val: bool) {
1521 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
1522 }
1523 #[doc = "Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state."]
1524 #[inline(always)]
1525 pub const fn dholdie(&self) -> bool {
1526 let val = (self.0 >> 9usize) & 0x01;
1527 val != 0
1528 }
1529 #[doc = "Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state."]
1530 #[inline(always)]
1531 pub fn set_dholdie(&mut self, val: bool) {
1532 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
1533 }
1534 #[doc = "Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end."]
1535 #[inline(always)]
1536 pub const fn dbckendie(&self) -> bool {
1537 let val = (self.0 >> 10usize) & 0x01;
1538 val != 0
1539 }
1540 #[doc = "Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end."]
1541 #[inline(always)]
1542 pub fn set_dbckendie(&mut self, val: bool) {
1543 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
1544 }
1545 #[doc = "Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted."]
1546 #[inline(always)]
1547 pub const fn dabortie(&self) -> bool {
1548 let val = (self.0 >> 11usize) & 0x01;
1549 val != 0
1550 }
1551 #[doc = "Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted."]
1552 #[inline(always)]
1553 pub fn set_dabortie(&mut self, val: bool) {
1554 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
1555 }
1556 #[doc = "Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty."]
1557 #[inline(always)]
1558 pub const fn txfifoheie(&self) -> bool {
1559 let val = (self.0 >> 14usize) & 0x01;
1560 val != 0
1561 }
1562 #[doc = "Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty."]
1563 #[inline(always)]
1564 pub fn set_txfifoheie(&mut self, val: bool) {
1565 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
1566 }
1567 #[doc = "Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full."]
1568 #[inline(always)]
1569 pub const fn rxfifohfie(&self) -> bool {
1570 let val = (self.0 >> 15usize) & 0x01;
1571 val != 0
1572 }
1573 #[doc = "Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full."]
1574 #[inline(always)]
1575 pub fn set_rxfifohfie(&mut self, val: bool) {
1576 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
1577 }
1578 #[doc = "Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full."]
1579 #[inline(always)]
1580 pub const fn rxfifofie(&self) -> bool {
1581 let val = (self.0 >> 17usize) & 0x01;
1582 val != 0
1583 }
1584 #[doc = "Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full."]
1585 #[inline(always)]
1586 pub fn set_rxfifofie(&mut self, val: bool) {
1587 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
1588 }
1589 #[doc = "Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty."]
1590 #[inline(always)]
1591 pub const fn txfifoeie(&self) -> bool {
1592 let val = (self.0 >> 18usize) & 0x01;
1593 val != 0
1594 }
1595 #[doc = "Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty."]
1596 #[inline(always)]
1597 pub fn set_txfifoeie(&mut self, val: bool) {
1598 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
1599 }
1600 #[doc = "BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response."]
1601 #[inline(always)]
1602 pub const fn busyd0endie(&self) -> bool {
1603 let val = (self.0 >> 21usize) & 0x01;
1604 val != 0
1605 }
1606 #[doc = "BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response."]
1607 #[inline(always)]
1608 pub fn set_busyd0endie(&mut self, val: bool) {
1609 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
1610 }
1611 #[doc = "SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt."]
1612 #[inline(always)]
1613 pub const fn sdioitie(&self) -> bool {
1614 let val = (self.0 >> 22usize) & 0x01;
1615 val != 0
1616 }
1617 #[doc = "SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt."]
1618 #[inline(always)]
1619 pub fn set_sdioitie(&mut self, val: bool) {
1620 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
1621 }
1622 #[doc = "Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail."]
1623 #[inline(always)]
1624 pub const fn ackfailie(&self) -> bool {
1625 let val = (self.0 >> 23usize) & 0x01;
1626 val != 0
1627 }
1628 #[doc = "Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail."]
1629 #[inline(always)]
1630 pub fn set_ackfailie(&mut self, val: bool) {
1631 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
1632 }
1633 #[doc = "Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout."]
1634 #[inline(always)]
1635 pub const fn acktimeoutie(&self) -> bool {
1636 let val = (self.0 >> 24usize) & 0x01;
1637 val != 0
1638 }
1639 #[doc = "Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout."]
1640 #[inline(always)]
1641 pub fn set_acktimeoutie(&mut self, val: bool) {
1642 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
1643 }
1644 #[doc = "Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion."]
1645 #[inline(always)]
1646 pub const fn vswendie(&self) -> bool {
1647 let val = (self.0 >> 25usize) & 0x01;
1648 val != 0
1649 }
1650 #[doc = "Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion."]
1651 #[inline(always)]
1652 pub fn set_vswendie(&mut self, val: bool) {
1653 self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
1654 }
1655 #[doc = "Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped."]
1656 #[inline(always)]
1657 pub const fn ckstopie(&self) -> bool {
1658 let val = (self.0 >> 26usize) & 0x01;
1659 val != 0
1660 }
1661 #[doc = "Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped."]
1662 #[inline(always)]
1663 pub fn set_ckstopie(&mut self, val: bool) {
1664 self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
1665 }
1666 #[doc = "IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer."]
1667 #[inline(always)]
1668 pub const fn idmabtcie(&self) -> bool {
1669 let val = (self.0 >> 28usize) & 0x01;
1670 val != 0
1671 }
1672 #[doc = "IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer."]
1673 #[inline(always)]
1674 pub fn set_idmabtcie(&mut self, val: bool) {
1675 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
1676 }
1677 }
1678 impl Default for Maskr {
1679 #[inline(always)]
1680 fn default() -> Maskr {
1681 Maskr(0)
1682 }
1683 }
1684 impl core::fmt::Debug for Maskr {
1685 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1686 f.debug_struct("Maskr")
1687 .field("ccrcfailie", &self.ccrcfailie())
1688 .field("dcrcfailie", &self.dcrcfailie())
1689 .field("ctimeoutie", &self.ctimeoutie())
1690 .field("dtimeoutie", &self.dtimeoutie())
1691 .field("txunderrie", &self.txunderrie())
1692 .field("rxoverrie", &self.rxoverrie())
1693 .field("cmdrendie", &self.cmdrendie())
1694 .field("cmdsentie", &self.cmdsentie())
1695 .field("dataendie", &self.dataendie())
1696 .field("dholdie", &self.dholdie())
1697 .field("dbckendie", &self.dbckendie())
1698 .field("dabortie", &self.dabortie())
1699 .field("txfifoheie", &self.txfifoheie())
1700 .field("rxfifohfie", &self.rxfifohfie())
1701 .field("rxfifofie", &self.rxfifofie())
1702 .field("txfifoeie", &self.txfifoeie())
1703 .field("busyd0endie", &self.busyd0endie())
1704 .field("sdioitie", &self.sdioitie())
1705 .field("ackfailie", &self.ackfailie())
1706 .field("acktimeoutie", &self.acktimeoutie())
1707 .field("vswendie", &self.vswendie())
1708 .field("ckstopie", &self.ckstopie())
1709 .field("idmabtcie", &self.idmabtcie())
1710 .finish()
1711 }
1712 }
1713 #[cfg(feature = "defmt")]
1714 impl defmt::Format for Maskr {
1715 fn format(&self, f: defmt::Formatter) {
1716 #[derive(defmt :: Format)]
1717 struct Maskr {
1718 ccrcfailie: bool,
1719 dcrcfailie: bool,
1720 ctimeoutie: bool,
1721 dtimeoutie: bool,
1722 txunderrie: bool,
1723 rxoverrie: bool,
1724 cmdrendie: bool,
1725 cmdsentie: bool,
1726 dataendie: bool,
1727 dholdie: bool,
1728 dbckendie: bool,
1729 dabortie: bool,
1730 txfifoheie: bool,
1731 rxfifohfie: bool,
1732 rxfifofie: bool,
1733 txfifoeie: bool,
1734 busyd0endie: bool,
1735 sdioitie: bool,
1736 ackfailie: bool,
1737 acktimeoutie: bool,
1738 vswendie: bool,
1739 ckstopie: bool,
1740 idmabtcie: bool,
1741 }
1742 let proxy = Maskr {
1743 ccrcfailie: self.ccrcfailie(),
1744 dcrcfailie: self.dcrcfailie(),
1745 ctimeoutie: self.ctimeoutie(),
1746 dtimeoutie: self.dtimeoutie(),
1747 txunderrie: self.txunderrie(),
1748 rxoverrie: self.rxoverrie(),
1749 cmdrendie: self.cmdrendie(),
1750 cmdsentie: self.cmdsentie(),
1751 dataendie: self.dataendie(),
1752 dholdie: self.dholdie(),
1753 dbckendie: self.dbckendie(),
1754 dabortie: self.dabortie(),
1755 txfifoheie: self.txfifoheie(),
1756 rxfifohfie: self.rxfifohfie(),
1757 rxfifofie: self.rxfifofie(),
1758 txfifoeie: self.txfifoeie(),
1759 busyd0endie: self.busyd0endie(),
1760 sdioitie: self.sdioitie(),
1761 ackfailie: self.ackfailie(),
1762 acktimeoutie: self.acktimeoutie(),
1763 vswendie: self.vswendie(),
1764 ckstopie: self.ckstopie(),
1765 idmabtcie: self.idmabtcie(),
1766 };
1767 defmt::write!(f, "{}", proxy)
1768 }
1769 }
1770 #[doc = "SDMMC power control register"]
1771 #[repr(transparent)]
1772 #[derive(Copy, Clone, Eq, PartialEq)]
1773 pub struct Power(pub u32);
1774 impl Power {
1775 #[doc = "SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11."]
1776 #[inline(always)]
1777 pub const fn pwrctrl(&self) -> u8 {
1778 let val = (self.0 >> 0usize) & 0x03;
1779 val as u8
1780 }
1781 #[doc = "SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11."]
1782 #[inline(always)]
1783 pub fn set_pwrctrl(&mut self, val: u8) {
1784 self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
1785 }
1786 #[doc = "Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:"]
1787 #[inline(always)]
1788 pub const fn vswitch(&self) -> bool {
1789 let val = (self.0 >> 2usize) & 0x01;
1790 val != 0
1791 }
1792 #[doc = "Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:"]
1793 #[inline(always)]
1794 pub fn set_vswitch(&mut self, val: bool) {
1795 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1796 }
1797 #[doc = "Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:"]
1798 #[inline(always)]
1799 pub const fn vswitchen(&self) -> bool {
1800 let val = (self.0 >> 3usize) & 0x01;
1801 val != 0
1802 }
1803 #[doc = "Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:"]
1804 #[inline(always)]
1805 pub fn set_vswitchen(&mut self, val: bool) {
1806 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1807 }
1808 #[doc = "Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00)."]
1809 #[inline(always)]
1810 pub const fn dirpol(&self) -> bool {
1811 let val = (self.0 >> 4usize) & 0x01;
1812 val != 0
1813 }
1814 #[doc = "Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00)."]
1815 #[inline(always)]
1816 pub fn set_dirpol(&mut self, val: bool) {
1817 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1818 }
1819 }
1820 impl Default for Power {
1821 #[inline(always)]
1822 fn default() -> Power {
1823 Power(0)
1824 }
1825 }
1826 impl core::fmt::Debug for Power {
1827 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1828 f.debug_struct("Power")
1829 .field("pwrctrl", &self.pwrctrl())
1830 .field("vswitch", &self.vswitch())
1831 .field("vswitchen", &self.vswitchen())
1832 .field("dirpol", &self.dirpol())
1833 .finish()
1834 }
1835 }
1836 #[cfg(feature = "defmt")]
1837 impl defmt::Format for Power {
1838 fn format(&self, f: defmt::Formatter) {
1839 #[derive(defmt :: Format)]
1840 struct Power {
1841 pwrctrl: u8,
1842 vswitch: bool,
1843 vswitchen: bool,
1844 dirpol: bool,
1845 }
1846 let proxy = Power {
1847 pwrctrl: self.pwrctrl(),
1848 vswitch: self.vswitch(),
1849 vswitchen: self.vswitchen(),
1850 dirpol: self.dirpol(),
1851 };
1852 defmt::write!(f, "{}", proxy)
1853 }
1854 }
1855 #[doc = "SDMMC command response register"]
1856 #[repr(transparent)]
1857 #[derive(Copy, Clone, Eq, PartialEq)]
1858 pub struct Respcmdr(pub u32);
1859 impl Respcmdr {
1860 #[doc = "Response command index"]
1861 #[inline(always)]
1862 pub const fn respcmd(&self) -> u8 {
1863 let val = (self.0 >> 0usize) & 0x3f;
1864 val as u8
1865 }
1866 #[doc = "Response command index"]
1867 #[inline(always)]
1868 pub fn set_respcmd(&mut self, val: u8) {
1869 self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
1870 }
1871 }
1872 impl Default for Respcmdr {
1873 #[inline(always)]
1874 fn default() -> Respcmdr {
1875 Respcmdr(0)
1876 }
1877 }
1878 impl core::fmt::Debug for Respcmdr {
1879 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1880 f.debug_struct("Respcmdr").field("respcmd", &self.respcmd()).finish()
1881 }
1882 }
1883 #[cfg(feature = "defmt")]
1884 impl defmt::Format for Respcmdr {
1885 fn format(&self, f: defmt::Formatter) {
1886 #[derive(defmt :: Format)]
1887 struct Respcmdr {
1888 respcmd: u8,
1889 }
1890 let proxy = Respcmdr {
1891 respcmd: self.respcmd(),
1892 };
1893 defmt::write!(f, "{}", proxy)
1894 }
1895 }
1896 #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."]
1897 #[repr(transparent)]
1898 #[derive(Copy, Clone, Eq, PartialEq)]
1899 pub struct RespxR(pub u32);
1900 impl RespxR {
1901 #[doc = "see Table 432"]
1902 #[inline(always)]
1903 pub const fn cardstatus(&self) -> u32 {
1904 let val = (self.0 >> 0usize) & 0xffff_ffff;
1905 val as u32
1906 }
1907 #[doc = "see Table 432"]
1908 #[inline(always)]
1909 pub fn set_cardstatus(&mut self, val: u32) {
1910 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1911 }
1912 }
1913 impl Default for RespxR {
1914 #[inline(always)]
1915 fn default() -> RespxR {
1916 RespxR(0)
1917 }
1918 }
1919 impl core::fmt::Debug for RespxR {
1920 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1921 f.debug_struct("RespxR")
1922 .field("cardstatus", &self.cardstatus())
1923 .finish()
1924 }
1925 }
1926 #[cfg(feature = "defmt")]
1927 impl defmt::Format for RespxR {
1928 fn format(&self, f: defmt::Formatter) {
1929 #[derive(defmt :: Format)]
1930 struct RespxR {
1931 cardstatus: u32,
1932 }
1933 let proxy = RespxR {
1934 cardstatus: self.cardstatus(),
1935 };
1936 defmt::write!(f, "{}", proxy)
1937 }
1938 }
1939 #[doc = "The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits \\[29,21,11:0\\]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits \\[20:12\\]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)"]
1940 #[repr(transparent)]
1941 #[derive(Copy, Clone, Eq, PartialEq)]
1942 pub struct Star(pub u32);
1943 impl Star {
1944 #[doc = "Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
1945 #[inline(always)]
1946 pub const fn ccrcfail(&self) -> bool {
1947 let val = (self.0 >> 0usize) & 0x01;
1948 val != 0
1949 }
1950 #[doc = "Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
1951 #[inline(always)]
1952 pub fn set_ccrcfail(&mut self, val: bool) {
1953 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1954 }
1955 #[doc = "Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
1956 #[inline(always)]
1957 pub const fn dcrcfail(&self) -> bool {
1958 let val = (self.0 >> 1usize) & 0x01;
1959 val != 0
1960 }
1961 #[doc = "Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
1962 #[inline(always)]
1963 pub fn set_dcrcfail(&mut self, val: bool) {
1964 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1965 }
1966 #[doc = "Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods."]
1967 #[inline(always)]
1968 pub const fn ctimeout(&self) -> bool {
1969 let val = (self.0 >> 2usize) & 0x01;
1970 val != 0
1971 }
1972 #[doc = "Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods."]
1973 #[inline(always)]
1974 pub fn set_ctimeout(&mut self, val: bool) {
1975 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1976 }
1977 #[doc = "Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
1978 #[inline(always)]
1979 pub const fn dtimeout(&self) -> bool {
1980 let val = (self.0 >> 3usize) & 0x01;
1981 val != 0
1982 }
1983 #[doc = "Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
1984 #[inline(always)]
1985 pub fn set_dtimeout(&mut self, val: bool) {
1986 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1987 }
1988 #[doc = "Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
1989 #[inline(always)]
1990 pub const fn txunderr(&self) -> bool {
1991 let val = (self.0 >> 4usize) & 0x01;
1992 val != 0
1993 }
1994 #[doc = "Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
1995 #[inline(always)]
1996 pub fn set_txunderr(&mut self, val: bool) {
1997 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1998 }
1999 #[doc = "Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2000 #[inline(always)]
2001 pub const fn rxoverr(&self) -> bool {
2002 let val = (self.0 >> 5usize) & 0x01;
2003 val != 0
2004 }
2005 #[doc = "Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2006 #[inline(always)]
2007 pub fn set_rxoverr(&mut self, val: bool) {
2008 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
2009 }
2010 #[doc = "Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2011 #[inline(always)]
2012 pub const fn cmdrend(&self) -> bool {
2013 let val = (self.0 >> 6usize) & 0x01;
2014 val != 0
2015 }
2016 #[doc = "Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2017 #[inline(always)]
2018 pub fn set_cmdrend(&mut self, val: bool) {
2019 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
2020 }
2021 #[doc = "Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2022 #[inline(always)]
2023 pub const fn cmdsent(&self) -> bool {
2024 let val = (self.0 >> 7usize) & 0x01;
2025 val != 0
2026 }
2027 #[doc = "Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2028 #[inline(always)]
2029 pub fn set_cmdsent(&mut self, val: bool) {
2030 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
2031 }
2032 #[doc = "Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2033 #[inline(always)]
2034 pub const fn dataend(&self) -> bool {
2035 let val = (self.0 >> 8usize) & 0x01;
2036 val != 0
2037 }
2038 #[doc = "Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2039 #[inline(always)]
2040 pub fn set_dataend(&mut self, val: bool) {
2041 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
2042 }
2043 #[doc = "Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2044 #[inline(always)]
2045 pub const fn dhold(&self) -> bool {
2046 let val = (self.0 >> 9usize) & 0x01;
2047 val != 0
2048 }
2049 #[doc = "Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2050 #[inline(always)]
2051 pub fn set_dhold(&mut self, val: bool) {
2052 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
2053 }
2054 #[doc = "Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2055 #[inline(always)]
2056 pub const fn dbckend(&self) -> bool {
2057 let val = (self.0 >> 10usize) & 0x01;
2058 val != 0
2059 }
2060 #[doc = "Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2061 #[inline(always)]
2062 pub fn set_dbckend(&mut self, val: bool) {
2063 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
2064 }
2065 #[doc = "Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2066 #[inline(always)]
2067 pub const fn dabort(&self) -> bool {
2068 let val = (self.0 >> 11usize) & 0x01;
2069 val != 0
2070 }
2071 #[doc = "Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2072 #[inline(always)]
2073 pub fn set_dabort(&mut self, val: bool) {
2074 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
2075 }
2076 #[doc = "Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt."]
2077 #[inline(always)]
2078 pub const fn dpsmact(&self) -> bool {
2079 let val = (self.0 >> 12usize) & 0x01;
2080 val != 0
2081 }
2082 #[doc = "Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt."]
2083 #[inline(always)]
2084 pub fn set_dpsmact(&mut self, val: bool) {
2085 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
2086 }
2087 #[doc = "Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt."]
2088 #[inline(always)]
2089 pub const fn cpsmact(&self) -> bool {
2090 let val = (self.0 >> 13usize) & 0x01;
2091 val != 0
2092 }
2093 #[doc = "Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt."]
2094 #[inline(always)]
2095 pub fn set_cpsmact(&mut self, val: bool) {
2096 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
2097 }
2098 #[doc = "Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full."]
2099 #[inline(always)]
2100 pub const fn txfifohe(&self) -> bool {
2101 let val = (self.0 >> 14usize) & 0x01;
2102 val != 0
2103 }
2104 #[doc = "Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full."]
2105 #[inline(always)]
2106 pub fn set_txfifohe(&mut self, val: bool) {
2107 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
2108 }
2109 #[doc = "Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty."]
2110 #[inline(always)]
2111 pub const fn rxfifohf(&self) -> bool {
2112 let val = (self.0 >> 15usize) & 0x01;
2113 val != 0
2114 }
2115 #[doc = "Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty."]
2116 #[inline(always)]
2117 pub fn set_rxfifohf(&mut self, val: bool) {
2118 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
2119 }
2120 #[doc = "Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty."]
2121 #[inline(always)]
2122 pub const fn txfifof(&self) -> bool {
2123 let val = (self.0 >> 16usize) & 0x01;
2124 val != 0
2125 }
2126 #[doc = "Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty."]
2127 #[inline(always)]
2128 pub fn set_txfifof(&mut self, val: bool) {
2129 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
2130 }
2131 #[doc = "Receive FIFO full This bit is cleared when one FIFO location becomes empty."]
2132 #[inline(always)]
2133 pub const fn rxfifof(&self) -> bool {
2134 let val = (self.0 >> 17usize) & 0x01;
2135 val != 0
2136 }
2137 #[doc = "Receive FIFO full This bit is cleared when one FIFO location becomes empty."]
2138 #[inline(always)]
2139 pub fn set_rxfifof(&mut self, val: bool) {
2140 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
2141 }
2142 #[doc = "Transmit FIFO empty This bit is cleared when one FIFO location becomes full."]
2143 #[inline(always)]
2144 pub const fn txfifoe(&self) -> bool {
2145 let val = (self.0 >> 18usize) & 0x01;
2146 val != 0
2147 }
2148 #[doc = "Transmit FIFO empty This bit is cleared when one FIFO location becomes full."]
2149 #[inline(always)]
2150 pub fn set_txfifoe(&mut self, val: bool) {
2151 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
2152 }
2153 #[doc = "Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full."]
2154 #[inline(always)]
2155 pub const fn rxfifoe(&self) -> bool {
2156 let val = (self.0 >> 19usize) & 0x01;
2157 val != 0
2158 }
2159 #[doc = "Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full."]
2160 #[inline(always)]
2161 pub fn set_rxfifoe(&mut self, val: bool) {
2162 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
2163 }
2164 #[doc = "Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt."]
2165 #[inline(always)]
2166 pub const fn busyd0(&self) -> bool {
2167 let val = (self.0 >> 20usize) & 0x01;
2168 val != 0
2169 }
2170 #[doc = "Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt."]
2171 #[inline(always)]
2172 pub fn set_busyd0(&mut self, val: bool) {
2173 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
2174 }
2175 #[doc = "end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2176 #[inline(always)]
2177 pub const fn busyd0end(&self) -> bool {
2178 let val = (self.0 >> 21usize) & 0x01;
2179 val != 0
2180 }
2181 #[doc = "end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2182 #[inline(always)]
2183 pub fn set_busyd0end(&mut self, val: bool) {
2184 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
2185 }
2186 #[doc = "SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2187 #[inline(always)]
2188 pub const fn sdioit(&self) -> bool {
2189 let val = (self.0 >> 22usize) & 0x01;
2190 val != 0
2191 }
2192 #[doc = "SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2193 #[inline(always)]
2194 pub fn set_sdioit(&mut self, val: bool) {
2195 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
2196 }
2197 #[doc = "Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2198 #[inline(always)]
2199 pub const fn ackfail(&self) -> bool {
2200 let val = (self.0 >> 23usize) & 0x01;
2201 val != 0
2202 }
2203 #[doc = "Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2204 #[inline(always)]
2205 pub fn set_ackfail(&mut self, val: bool) {
2206 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
2207 }
2208 #[doc = "Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2209 #[inline(always)]
2210 pub const fn acktimeout(&self) -> bool {
2211 let val = (self.0 >> 24usize) & 0x01;
2212 val != 0
2213 }
2214 #[doc = "Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2215 #[inline(always)]
2216 pub fn set_acktimeout(&mut self, val: bool) {
2217 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
2218 }
2219 #[doc = "Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2220 #[inline(always)]
2221 pub const fn vswend(&self) -> bool {
2222 let val = (self.0 >> 25usize) & 0x01;
2223 val != 0
2224 }
2225 #[doc = "Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2226 #[inline(always)]
2227 pub fn set_vswend(&mut self, val: bool) {
2228 self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
2229 }
2230 #[doc = "SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2231 #[inline(always)]
2232 pub const fn ckstop(&self) -> bool {
2233 let val = (self.0 >> 26usize) & 0x01;
2234 val != 0
2235 }
2236 #[doc = "SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2237 #[inline(always)]
2238 pub fn set_ckstop(&mut self, val: bool) {
2239 self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
2240 }
2241 #[doc = "IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2242 #[inline(always)]
2243 pub const fn idmate(&self) -> bool {
2244 let val = (self.0 >> 27usize) & 0x01;
2245 val != 0
2246 }
2247 #[doc = "IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2248 #[inline(always)]
2249 pub fn set_idmate(&mut self, val: bool) {
2250 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
2251 }
2252 #[doc = "IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2253 #[inline(always)]
2254 pub const fn idmabtc(&self) -> bool {
2255 let val = (self.0 >> 28usize) & 0x01;
2256 val != 0
2257 }
2258 #[doc = "IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
2259 #[inline(always)]
2260 pub fn set_idmabtc(&mut self, val: bool) {
2261 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
2262 }
2263 }
2264 impl Default for Star {
2265 #[inline(always)]
2266 fn default() -> Star {
2267 Star(0)
2268 }
2269 }
2270 impl core::fmt::Debug for Star {
2271 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2272 f.debug_struct("Star")
2273 .field("ccrcfail", &self.ccrcfail())
2274 .field("dcrcfail", &self.dcrcfail())
2275 .field("ctimeout", &self.ctimeout())
2276 .field("dtimeout", &self.dtimeout())
2277 .field("txunderr", &self.txunderr())
2278 .field("rxoverr", &self.rxoverr())
2279 .field("cmdrend", &self.cmdrend())
2280 .field("cmdsent", &self.cmdsent())
2281 .field("dataend", &self.dataend())
2282 .field("dhold", &self.dhold())
2283 .field("dbckend", &self.dbckend())
2284 .field("dabort", &self.dabort())
2285 .field("dpsmact", &self.dpsmact())
2286 .field("cpsmact", &self.cpsmact())
2287 .field("txfifohe", &self.txfifohe())
2288 .field("rxfifohf", &self.rxfifohf())
2289 .field("txfifof", &self.txfifof())
2290 .field("rxfifof", &self.rxfifof())
2291 .field("txfifoe", &self.txfifoe())
2292 .field("rxfifoe", &self.rxfifoe())
2293 .field("busyd0", &self.busyd0())
2294 .field("busyd0end", &self.busyd0end())
2295 .field("sdioit", &self.sdioit())
2296 .field("ackfail", &self.ackfail())
2297 .field("acktimeout", &self.acktimeout())
2298 .field("vswend", &self.vswend())
2299 .field("ckstop", &self.ckstop())
2300 .field("idmate", &self.idmate())
2301 .field("idmabtc", &self.idmabtc())
2302 .finish()
2303 }
2304 }
2305 #[cfg(feature = "defmt")]
2306 impl defmt::Format for Star {
2307 fn format(&self, f: defmt::Formatter) {
2308 #[derive(defmt :: Format)]
2309 struct Star {
2310 ccrcfail: bool,
2311 dcrcfail: bool,
2312 ctimeout: bool,
2313 dtimeout: bool,
2314 txunderr: bool,
2315 rxoverr: bool,
2316 cmdrend: bool,
2317 cmdsent: bool,
2318 dataend: bool,
2319 dhold: bool,
2320 dbckend: bool,
2321 dabort: bool,
2322 dpsmact: bool,
2323 cpsmact: bool,
2324 txfifohe: bool,
2325 rxfifohf: bool,
2326 txfifof: bool,
2327 rxfifof: bool,
2328 txfifoe: bool,
2329 rxfifoe: bool,
2330 busyd0: bool,
2331 busyd0end: bool,
2332 sdioit: bool,
2333 ackfail: bool,
2334 acktimeout: bool,
2335 vswend: bool,
2336 ckstop: bool,
2337 idmate: bool,
2338 idmabtc: bool,
2339 }
2340 let proxy = Star {
2341 ccrcfail: self.ccrcfail(),
2342 dcrcfail: self.dcrcfail(),
2343 ctimeout: self.ctimeout(),
2344 dtimeout: self.dtimeout(),
2345 txunderr: self.txunderr(),
2346 rxoverr: self.rxoverr(),
2347 cmdrend: self.cmdrend(),
2348 cmdsent: self.cmdsent(),
2349 dataend: self.dataend(),
2350 dhold: self.dhold(),
2351 dbckend: self.dbckend(),
2352 dabort: self.dabort(),
2353 dpsmact: self.dpsmact(),
2354 cpsmact: self.cpsmact(),
2355 txfifohe: self.txfifohe(),
2356 rxfifohf: self.rxfifohf(),
2357 txfifof: self.txfifof(),
2358 rxfifof: self.rxfifof(),
2359 txfifoe: self.txfifoe(),
2360 rxfifoe: self.rxfifoe(),
2361 busyd0: self.busyd0(),
2362 busyd0end: self.busyd0end(),
2363 sdioit: self.sdioit(),
2364 ackfail: self.ackfail(),
2365 acktimeout: self.acktimeout(),
2366 vswend: self.vswend(),
2367 ckstop: self.ckstop(),
2368 idmate: self.idmate(),
2369 idmabtc: self.idmabtc(),
2370 };
2371 defmt::write!(f, "{}", proxy)
2372 }
2373 }
2374 #[doc = "SDMMC IP version register"]
2375 #[repr(transparent)]
2376 #[derive(Copy, Clone, Eq, PartialEq)]
2377 pub struct Ver(pub u32);
2378 impl Ver {
2379 #[doc = "IP minor revision number."]
2380 #[inline(always)]
2381 pub const fn minrev(&self) -> u8 {
2382 let val = (self.0 >> 0usize) & 0x0f;
2383 val as u8
2384 }
2385 #[doc = "IP minor revision number."]
2386 #[inline(always)]
2387 pub fn set_minrev(&mut self, val: u8) {
2388 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
2389 }
2390 #[doc = "IP major revision number."]
2391 #[inline(always)]
2392 pub const fn majrev(&self) -> u8 {
2393 let val = (self.0 >> 4usize) & 0x0f;
2394 val as u8
2395 }
2396 #[doc = "IP major revision number."]
2397 #[inline(always)]
2398 pub fn set_majrev(&mut self, val: u8) {
2399 self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
2400 }
2401 }
2402 impl Default for Ver {
2403 #[inline(always)]
2404 fn default() -> Ver {
2405 Ver(0)
2406 }
2407 }
2408 impl core::fmt::Debug for Ver {
2409 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2410 f.debug_struct("Ver")
2411 .field("minrev", &self.minrev())
2412 .field("majrev", &self.majrev())
2413 .finish()
2414 }
2415 }
2416 #[cfg(feature = "defmt")]
2417 impl defmt::Format for Ver {
2418 fn format(&self, f: defmt::Formatter) {
2419 #[derive(defmt :: Format)]
2420 struct Ver {
2421 minrev: u8,
2422 majrev: u8,
2423 }
2424 let proxy = Ver {
2425 minrev: self.minrev(),
2426 majrev: self.majrev(),
2427 };
2428 defmt::write!(f, "{}", proxy)
2429 }
2430 }
2431}
2432