1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "Serial peripheral interface"]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Spi {
9 ptr: *mut u8,
10}
11unsafe impl Send for Spi {}
12unsafe impl Sync for Spi {}
13impl Spi {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "control register 1"]
23 #[inline(always)]
24 pub const fn cr1(self) -> crate::common::Reg<regs::Cr1, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "control register 2"]
28 #[inline(always)]
29 pub const fn cr2(self) -> crate::common::Reg<regs::Cr2, crate::common::RW> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
31 }
32 #[doc = "configuration register 1"]
33 #[inline(always)]
34 pub const fn cfg1(self) -> crate::common::Reg<regs::Cfg1, crate::common::RW> {
35 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
36 }
37 #[doc = "configuration register 2"]
38 #[inline(always)]
39 pub const fn cfg2(self) -> crate::common::Reg<regs::Cfg2, crate::common::RW> {
40 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
41 }
42 #[doc = "Interrupt Enable Register"]
43 #[inline(always)]
44 pub const fn ier(self) -> crate::common::Reg<regs::Ier, crate::common::RW> {
45 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
46 }
47 #[doc = "Status Register"]
48 #[inline(always)]
49 pub const fn sr(self) -> crate::common::Reg<regs::Sr, crate::common::R> {
50 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
51 }
52 #[doc = "Interrupt/Status Flags Clear Register"]
53 #[inline(always)]
54 pub const fn ifcr(self) -> crate::common::Reg<regs::Ifcr, crate::common::W> {
55 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) }
56 }
57 #[inline(always)]
58 pub const fn autocr(self) -> crate::common::Reg<regs::Autocr, crate::common::RW> {
59 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) }
60 }
61 #[doc = "Transmit Data Register - half-word sized"]
62 #[inline(always)]
63 pub const fn txdr16(self) -> crate::common::Reg<u16, crate::common::W> {
64 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
65 }
66 #[doc = "Transmit Data Register"]
67 #[inline(always)]
68 pub const fn txdr32(self) -> crate::common::Reg<u32, crate::common::W> {
69 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
70 }
71 #[doc = "Transmit Data Register - byte sized"]
72 #[inline(always)]
73 pub const fn txdr8(self) -> crate::common::Reg<u8, crate::common::W> {
74 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
75 }
76 #[doc = "Receive Data Register - half-word sized"]
77 #[inline(always)]
78 pub const fn rxdr16(self) -> crate::common::Reg<u16, crate::common::R> {
79 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) }
80 }
81 #[doc = "Receive Data Register"]
82 #[inline(always)]
83 pub const fn rxdr32(self) -> crate::common::Reg<u32, crate::common::R> {
84 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) }
85 }
86 #[doc = "Receive Data Register - byte sized"]
87 #[inline(always)]
88 pub const fn rxdr8(self) -> crate::common::Reg<u8, crate::common::R> {
89 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) }
90 }
91 #[doc = "Polynomial Register"]
92 #[inline(always)]
93 pub const fn crcpoly(self) -> crate::common::Reg<regs::Crcpoly, crate::common::RW> {
94 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x40usize) as _) }
95 }
96 #[doc = "Transmitter CRC Register"]
97 #[inline(always)]
98 pub const fn txcrc(self) -> crate::common::Reg<regs::Txcrc, crate::common::RW> {
99 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) }
100 }
101 #[doc = "Receiver CRC Register"]
102 #[inline(always)]
103 pub const fn rxcrc(self) -> crate::common::Reg<regs::Rxcrc, crate::common::RW> {
104 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) }
105 }
106 #[doc = "Underrun Data Register"]
107 #[inline(always)]
108 pub const fn udrdr(self) -> crate::common::Reg<regs::Udrdr, crate::common::RW> {
109 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x4cusize) as _) }
110 }
111}
112pub mod regs {
113 #[repr(transparent)]
114 #[derive(Copy, Clone, Eq, PartialEq)]
115 pub struct Autocr(pub u32);
116 impl Autocr {
117 #[doc = "trigger selection (refer ). ... Note: these bits can be written only when SPE = 0."]
118 #[inline(always)]
119 pub const fn trigsel(&self) -> u8 {
120 let val = (self.0 >> 16usize) & 0x0f;
121 val as u8
122 }
123 #[doc = "trigger selection (refer ). ... Note: these bits can be written only when SPE = 0."]
124 #[inline(always)]
125 pub fn set_trigsel(&mut self, val: u8) {
126 self.0 = (self.0 & !(0x0f << 16usize)) | (((val as u32) & 0x0f) << 16usize);
127 }
128 #[doc = "trigger polarity Note: This bit can be written only when SPE = 0."]
129 #[inline(always)]
130 pub const fn trigpol(&self) -> super::vals::Trigpol {
131 let val = (self.0 >> 20usize) & 0x01;
132 super::vals::Trigpol::from_bits(val as u8)
133 }
134 #[doc = "trigger polarity Note: This bit can be written only when SPE = 0."]
135 #[inline(always)]
136 pub fn set_trigpol(&mut self, val: super::vals::Trigpol) {
137 self.0 = (self.0 & !(0x01 << 20usize)) | (((val.to_bits() as u32) & 0x01) << 20usize);
138 }
139 #[doc = "trigger of CSTART control enable Note: if user can't prevent trigger event during write, the TRIGEN has to be changed when SPI is disabled"]
140 #[inline(always)]
141 pub const fn trigen(&self) -> bool {
142 let val = (self.0 >> 21usize) & 0x01;
143 val != 0
144 }
145 #[doc = "trigger of CSTART control enable Note: if user can't prevent trigger event during write, the TRIGEN has to be changed when SPI is disabled"]
146 #[inline(always)]
147 pub fn set_trigen(&mut self, val: bool) {
148 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
149 }
150 }
151 impl Default for Autocr {
152 #[inline(always)]
153 fn default() -> Autocr {
154 Autocr(0)
155 }
156 }
157 impl core::fmt::Debug for Autocr {
158 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
159 f.debug_struct("Autocr")
160 .field("trigsel", &self.trigsel())
161 .field("trigpol", &self.trigpol())
162 .field("trigen", &self.trigen())
163 .finish()
164 }
165 }
166 #[cfg(feature = "defmt")]
167 impl defmt::Format for Autocr {
168 fn format(&self, f: defmt::Formatter) {
169 #[derive(defmt :: Format)]
170 struct Autocr {
171 trigsel: u8,
172 trigpol: super::vals::Trigpol,
173 trigen: bool,
174 }
175 let proxy = Autocr {
176 trigsel: self.trigsel(),
177 trigpol: self.trigpol(),
178 trigen: self.trigen(),
179 };
180 defmt::write!(f, "{}", proxy)
181 }
182 }
183 #[doc = "configuration register 1"]
184 #[repr(transparent)]
185 #[derive(Copy, Clone, Eq, PartialEq)]
186 pub struct Cfg1(pub u32);
187 impl Cfg1 {
188 #[doc = "Number of bits in at single SPI data frame"]
189 #[inline(always)]
190 pub const fn dsize(&self) -> u8 {
191 let val = (self.0 >> 0usize) & 0x1f;
192 val as u8
193 }
194 #[doc = "Number of bits in at single SPI data frame"]
195 #[inline(always)]
196 pub fn set_dsize(&mut self, val: u8) {
197 self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
198 }
199 #[doc = "threshold level"]
200 #[inline(always)]
201 pub const fn fthlv(&self) -> super::vals::Fthlv {
202 let val = (self.0 >> 5usize) & 0x0f;
203 super::vals::Fthlv::from_bits(val as u8)
204 }
205 #[doc = "threshold level"]
206 #[inline(always)]
207 pub fn set_fthlv(&mut self, val: super::vals::Fthlv) {
208 self.0 = (self.0 & !(0x0f << 5usize)) | (((val.to_bits() as u32) & 0x0f) << 5usize);
209 }
210 #[doc = "Behavior of slave transmitter at underrun condition"]
211 #[inline(always)]
212 pub const fn udrcfg(&self) -> super::vals::Udrcfg {
213 let val = (self.0 >> 9usize) & 0x03;
214 super::vals::Udrcfg::from_bits(val as u8)
215 }
216 #[doc = "Behavior of slave transmitter at underrun condition"]
217 #[inline(always)]
218 pub fn set_udrcfg(&mut self, val: super::vals::Udrcfg) {
219 self.0 = (self.0 & !(0x03 << 9usize)) | (((val.to_bits() as u32) & 0x03) << 9usize);
220 }
221 #[doc = "Rx DMA stream enable"]
222 #[inline(always)]
223 pub const fn rxdmaen(&self) -> bool {
224 let val = (self.0 >> 14usize) & 0x01;
225 val != 0
226 }
227 #[doc = "Rx DMA stream enable"]
228 #[inline(always)]
229 pub fn set_rxdmaen(&mut self, val: bool) {
230 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
231 }
232 #[doc = "Tx DMA stream enable"]
233 #[inline(always)]
234 pub const fn txdmaen(&self) -> bool {
235 let val = (self.0 >> 15usize) & 0x01;
236 val != 0
237 }
238 #[doc = "Tx DMA stream enable"]
239 #[inline(always)]
240 pub fn set_txdmaen(&mut self, val: bool) {
241 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
242 }
243 #[doc = "Length of CRC frame to be transacted and compared"]
244 #[inline(always)]
245 pub const fn crcsize(&self) -> u8 {
246 let val = (self.0 >> 16usize) & 0x1f;
247 val as u8
248 }
249 #[doc = "Length of CRC frame to be transacted and compared"]
250 #[inline(always)]
251 pub fn set_crcsize(&mut self, val: u8) {
252 self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize);
253 }
254 #[doc = "Hardware CRC computation enable"]
255 #[inline(always)]
256 pub const fn crcen(&self) -> bool {
257 let val = (self.0 >> 22usize) & 0x01;
258 val != 0
259 }
260 #[doc = "Hardware CRC computation enable"]
261 #[inline(always)]
262 pub fn set_crcen(&mut self, val: bool) {
263 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
264 }
265 #[doc = "Master baud rate"]
266 #[inline(always)]
267 pub const fn mbr(&self) -> super::vals::Mbr {
268 let val = (self.0 >> 28usize) & 0x07;
269 super::vals::Mbr::from_bits(val as u8)
270 }
271 #[doc = "Master baud rate"]
272 #[inline(always)]
273 pub fn set_mbr(&mut self, val: super::vals::Mbr) {
274 self.0 = (self.0 & !(0x07 << 28usize)) | (((val.to_bits() as u32) & 0x07) << 28usize);
275 }
276 #[doc = "bypass of the prescaler at master baud rate clock generator"]
277 #[inline(always)]
278 pub const fn bpass(&self) -> bool {
279 let val = (self.0 >> 31usize) & 0x01;
280 val != 0
281 }
282 #[doc = "bypass of the prescaler at master baud rate clock generator"]
283 #[inline(always)]
284 pub fn set_bpass(&mut self, val: bool) {
285 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
286 }
287 }
288 impl Default for Cfg1 {
289 #[inline(always)]
290 fn default() -> Cfg1 {
291 Cfg1(0)
292 }
293 }
294 impl core::fmt::Debug for Cfg1 {
295 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
296 f.debug_struct("Cfg1")
297 .field("dsize", &self.dsize())
298 .field("fthlv", &self.fthlv())
299 .field("udrcfg", &self.udrcfg())
300 .field("rxdmaen", &self.rxdmaen())
301 .field("txdmaen", &self.txdmaen())
302 .field("crcsize", &self.crcsize())
303 .field("crcen", &self.crcen())
304 .field("mbr", &self.mbr())
305 .field("bpass", &self.bpass())
306 .finish()
307 }
308 }
309 #[cfg(feature = "defmt")]
310 impl defmt::Format for Cfg1 {
311 fn format(&self, f: defmt::Formatter) {
312 #[derive(defmt :: Format)]
313 struct Cfg1 {
314 dsize: u8,
315 fthlv: super::vals::Fthlv,
316 udrcfg: super::vals::Udrcfg,
317 rxdmaen: bool,
318 txdmaen: bool,
319 crcsize: u8,
320 crcen: bool,
321 mbr: super::vals::Mbr,
322 bpass: bool,
323 }
324 let proxy = Cfg1 {
325 dsize: self.dsize(),
326 fthlv: self.fthlv(),
327 udrcfg: self.udrcfg(),
328 rxdmaen: self.rxdmaen(),
329 txdmaen: self.txdmaen(),
330 crcsize: self.crcsize(),
331 crcen: self.crcen(),
332 mbr: self.mbr(),
333 bpass: self.bpass(),
334 };
335 defmt::write!(f, "{}", proxy)
336 }
337 }
338 #[doc = "configuration register 2"]
339 #[repr(transparent)]
340 #[derive(Copy, Clone, Eq, PartialEq)]
341 pub struct Cfg2(pub u32);
342 impl Cfg2 {
343 #[doc = "Master SS Idleness"]
344 #[inline(always)]
345 pub const fn mssi(&self) -> u8 {
346 let val = (self.0 >> 0usize) & 0x0f;
347 val as u8
348 }
349 #[doc = "Master SS Idleness"]
350 #[inline(always)]
351 pub fn set_mssi(&mut self, val: u8) {
352 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
353 }
354 #[doc = "Master Inter-Data Idleness"]
355 #[inline(always)]
356 pub const fn midi(&self) -> u8 {
357 let val = (self.0 >> 4usize) & 0x0f;
358 val as u8
359 }
360 #[doc = "Master Inter-Data Idleness"]
361 #[inline(always)]
362 pub fn set_midi(&mut self, val: u8) {
363 self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
364 }
365 #[doc = "RDY signal input/output management Note: When DSIZE at the CFG1 register is configured shorter than 8-bit, the RDIOM bit has to be kept at zero."]
366 #[inline(always)]
367 pub const fn rdiom(&self) -> super::vals::Rdiom {
368 let val = (self.0 >> 13usize) & 0x01;
369 super::vals::Rdiom::from_bits(val as u8)
370 }
371 #[doc = "RDY signal input/output management Note: When DSIZE at the CFG1 register is configured shorter than 8-bit, the RDIOM bit has to be kept at zero."]
372 #[inline(always)]
373 pub fn set_rdiom(&mut self, val: super::vals::Rdiom) {
374 self.0 = (self.0 & !(0x01 << 13usize)) | (((val.to_bits() as u32) & 0x01) << 13usize);
375 }
376 #[doc = "RDY signal input/output polarity"]
377 #[inline(always)]
378 pub const fn rdiop(&self) -> super::vals::Rdiop {
379 let val = (self.0 >> 14usize) & 0x01;
380 super::vals::Rdiop::from_bits(val as u8)
381 }
382 #[doc = "RDY signal input/output polarity"]
383 #[inline(always)]
384 pub fn set_rdiop(&mut self, val: super::vals::Rdiop) {
385 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.to_bits() as u32) & 0x01) << 14usize);
386 }
387 #[doc = "Swap functionality of MISO and MOSI pins"]
388 #[inline(always)]
389 pub const fn ioswp(&self) -> bool {
390 let val = (self.0 >> 15usize) & 0x01;
391 val != 0
392 }
393 #[doc = "Swap functionality of MISO and MOSI pins"]
394 #[inline(always)]
395 pub fn set_ioswp(&mut self, val: bool) {
396 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
397 }
398 #[doc = "SPI Communication Mode"]
399 #[inline(always)]
400 pub const fn comm(&self) -> super::vals::Comm {
401 let val = (self.0 >> 17usize) & 0x03;
402 super::vals::Comm::from_bits(val as u8)
403 }
404 #[doc = "SPI Communication Mode"]
405 #[inline(always)]
406 pub fn set_comm(&mut self, val: super::vals::Comm) {
407 self.0 = (self.0 & !(0x03 << 17usize)) | (((val.to_bits() as u32) & 0x03) << 17usize);
408 }
409 #[doc = "Serial Protocol"]
410 #[inline(always)]
411 pub const fn sp(&self) -> super::vals::Sp {
412 let val = (self.0 >> 19usize) & 0x07;
413 super::vals::Sp::from_bits(val as u8)
414 }
415 #[doc = "Serial Protocol"]
416 #[inline(always)]
417 pub fn set_sp(&mut self, val: super::vals::Sp) {
418 self.0 = (self.0 & !(0x07 << 19usize)) | (((val.to_bits() as u32) & 0x07) << 19usize);
419 }
420 #[doc = "SPI Master"]
421 #[inline(always)]
422 pub const fn master(&self) -> super::vals::Master {
423 let val = (self.0 >> 22usize) & 0x01;
424 super::vals::Master::from_bits(val as u8)
425 }
426 #[doc = "SPI Master"]
427 #[inline(always)]
428 pub fn set_master(&mut self, val: super::vals::Master) {
429 self.0 = (self.0 & !(0x01 << 22usize)) | (((val.to_bits() as u32) & 0x01) << 22usize);
430 }
431 #[doc = "Data frame format"]
432 #[inline(always)]
433 pub const fn lsbfirst(&self) -> super::vals::Lsbfirst {
434 let val = (self.0 >> 23usize) & 0x01;
435 super::vals::Lsbfirst::from_bits(val as u8)
436 }
437 #[doc = "Data frame format"]
438 #[inline(always)]
439 pub fn set_lsbfirst(&mut self, val: super::vals::Lsbfirst) {
440 self.0 = (self.0 & !(0x01 << 23usize)) | (((val.to_bits() as u32) & 0x01) << 23usize);
441 }
442 #[doc = "Clock phase"]
443 #[inline(always)]
444 pub const fn cpha(&self) -> super::vals::Cpha {
445 let val = (self.0 >> 24usize) & 0x01;
446 super::vals::Cpha::from_bits(val as u8)
447 }
448 #[doc = "Clock phase"]
449 #[inline(always)]
450 pub fn set_cpha(&mut self, val: super::vals::Cpha) {
451 self.0 = (self.0 & !(0x01 << 24usize)) | (((val.to_bits() as u32) & 0x01) << 24usize);
452 }
453 #[doc = "Clock polarity"]
454 #[inline(always)]
455 pub const fn cpol(&self) -> super::vals::Cpol {
456 let val = (self.0 >> 25usize) & 0x01;
457 super::vals::Cpol::from_bits(val as u8)
458 }
459 #[doc = "Clock polarity"]
460 #[inline(always)]
461 pub fn set_cpol(&mut self, val: super::vals::Cpol) {
462 self.0 = (self.0 & !(0x01 << 25usize)) | (((val.to_bits() as u32) & 0x01) << 25usize);
463 }
464 #[doc = "Software management of SS signal input"]
465 #[inline(always)]
466 pub const fn ssm(&self) -> bool {
467 let val = (self.0 >> 26usize) & 0x01;
468 val != 0
469 }
470 #[doc = "Software management of SS signal input"]
471 #[inline(always)]
472 pub fn set_ssm(&mut self, val: bool) {
473 self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
474 }
475 #[doc = "SS input/output polarity"]
476 #[inline(always)]
477 pub const fn ssiop(&self) -> super::vals::Ssiop {
478 let val = (self.0 >> 28usize) & 0x01;
479 super::vals::Ssiop::from_bits(val as u8)
480 }
481 #[doc = "SS input/output polarity"]
482 #[inline(always)]
483 pub fn set_ssiop(&mut self, val: super::vals::Ssiop) {
484 self.0 = (self.0 & !(0x01 << 28usize)) | (((val.to_bits() as u32) & 0x01) << 28usize);
485 }
486 #[doc = "SS output enable"]
487 #[inline(always)]
488 pub const fn ssoe(&self) -> bool {
489 let val = (self.0 >> 29usize) & 0x01;
490 val != 0
491 }
492 #[doc = "SS output enable"]
493 #[inline(always)]
494 pub fn set_ssoe(&mut self, val: bool) {
495 self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
496 }
497 #[doc = "SS output management in master mode"]
498 #[inline(always)]
499 pub const fn ssom(&self) -> super::vals::Ssom {
500 let val = (self.0 >> 30usize) & 0x01;
501 super::vals::Ssom::from_bits(val as u8)
502 }
503 #[doc = "SS output management in master mode"]
504 #[inline(always)]
505 pub fn set_ssom(&mut self, val: super::vals::Ssom) {
506 self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize);
507 }
508 #[doc = "Alternate function always control GPIOs"]
509 #[inline(always)]
510 pub const fn afcntr(&self) -> bool {
511 let val = (self.0 >> 31usize) & 0x01;
512 val != 0
513 }
514 #[doc = "Alternate function always control GPIOs"]
515 #[inline(always)]
516 pub fn set_afcntr(&mut self, val: bool) {
517 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
518 }
519 }
520 impl Default for Cfg2 {
521 #[inline(always)]
522 fn default() -> Cfg2 {
523 Cfg2(0)
524 }
525 }
526 impl core::fmt::Debug for Cfg2 {
527 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
528 f.debug_struct("Cfg2")
529 .field("mssi", &self.mssi())
530 .field("midi", &self.midi())
531 .field("rdiom", &self.rdiom())
532 .field("rdiop", &self.rdiop())
533 .field("ioswp", &self.ioswp())
534 .field("comm", &self.comm())
535 .field("sp", &self.sp())
536 .field("master", &self.master())
537 .field("lsbfirst", &self.lsbfirst())
538 .field("cpha", &self.cpha())
539 .field("cpol", &self.cpol())
540 .field("ssm", &self.ssm())
541 .field("ssiop", &self.ssiop())
542 .field("ssoe", &self.ssoe())
543 .field("ssom", &self.ssom())
544 .field("afcntr", &self.afcntr())
545 .finish()
546 }
547 }
548 #[cfg(feature = "defmt")]
549 impl defmt::Format for Cfg2 {
550 fn format(&self, f: defmt::Formatter) {
551 #[derive(defmt :: Format)]
552 struct Cfg2 {
553 mssi: u8,
554 midi: u8,
555 rdiom: super::vals::Rdiom,
556 rdiop: super::vals::Rdiop,
557 ioswp: bool,
558 comm: super::vals::Comm,
559 sp: super::vals::Sp,
560 master: super::vals::Master,
561 lsbfirst: super::vals::Lsbfirst,
562 cpha: super::vals::Cpha,
563 cpol: super::vals::Cpol,
564 ssm: bool,
565 ssiop: super::vals::Ssiop,
566 ssoe: bool,
567 ssom: super::vals::Ssom,
568 afcntr: bool,
569 }
570 let proxy = Cfg2 {
571 mssi: self.mssi(),
572 midi: self.midi(),
573 rdiom: self.rdiom(),
574 rdiop: self.rdiop(),
575 ioswp: self.ioswp(),
576 comm: self.comm(),
577 sp: self.sp(),
578 master: self.master(),
579 lsbfirst: self.lsbfirst(),
580 cpha: self.cpha(),
581 cpol: self.cpol(),
582 ssm: self.ssm(),
583 ssiop: self.ssiop(),
584 ssoe: self.ssoe(),
585 ssom: self.ssom(),
586 afcntr: self.afcntr(),
587 };
588 defmt::write!(f, "{}", proxy)
589 }
590 }
591 #[doc = "control register 1"]
592 #[repr(transparent)]
593 #[derive(Copy, Clone, Eq, PartialEq)]
594 pub struct Cr1(pub u32);
595 impl Cr1 {
596 #[doc = "Serial Peripheral Enable"]
597 #[inline(always)]
598 pub const fn spe(&self) -> bool {
599 let val = (self.0 >> 0usize) & 0x01;
600 val != 0
601 }
602 #[doc = "Serial Peripheral Enable"]
603 #[inline(always)]
604 pub fn set_spe(&mut self, val: bool) {
605 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
606 }
607 #[doc = "Master automatic SUSP in Receive mode"]
608 #[inline(always)]
609 pub const fn masrx(&self) -> bool {
610 let val = (self.0 >> 8usize) & 0x01;
611 val != 0
612 }
613 #[doc = "Master automatic SUSP in Receive mode"]
614 #[inline(always)]
615 pub fn set_masrx(&mut self, val: bool) {
616 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
617 }
618 #[doc = "Master transfer start"]
619 #[inline(always)]
620 pub const fn cstart(&self) -> bool {
621 let val = (self.0 >> 9usize) & 0x01;
622 val != 0
623 }
624 #[doc = "Master transfer start"]
625 #[inline(always)]
626 pub fn set_cstart(&mut self, val: bool) {
627 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
628 }
629 #[doc = "Master SUSPend request"]
630 #[inline(always)]
631 pub const fn csusp(&self) -> bool {
632 let val = (self.0 >> 10usize) & 0x01;
633 val != 0
634 }
635 #[doc = "Master SUSPend request"]
636 #[inline(always)]
637 pub fn set_csusp(&mut self, val: bool) {
638 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
639 }
640 #[doc = "Rx/Tx direction at Half-duplex mode"]
641 #[inline(always)]
642 pub const fn hddir(&self) -> super::vals::Hddir {
643 let val = (self.0 >> 11usize) & 0x01;
644 super::vals::Hddir::from_bits(val as u8)
645 }
646 #[doc = "Rx/Tx direction at Half-duplex mode"]
647 #[inline(always)]
648 pub fn set_hddir(&mut self, val: super::vals::Hddir) {
649 self.0 = (self.0 & !(0x01 << 11usize)) | (((val.to_bits() as u32) & 0x01) << 11usize);
650 }
651 #[doc = "Internal SS signal input level"]
652 #[inline(always)]
653 pub const fn ssi(&self) -> bool {
654 let val = (self.0 >> 12usize) & 0x01;
655 val != 0
656 }
657 #[doc = "Internal SS signal input level"]
658 #[inline(always)]
659 pub fn set_ssi(&mut self, val: bool) {
660 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
661 }
662 #[doc = "Full size (33-bit or 17-bit) CRC polynomial is used"]
663 #[inline(always)]
664 pub const fn crc33_17(&self) -> bool {
665 let val = (self.0 >> 13usize) & 0x01;
666 val != 0
667 }
668 #[doc = "Full size (33-bit or 17-bit) CRC polynomial is used"]
669 #[inline(always)]
670 pub fn set_crc33_17(&mut self, val: bool) {
671 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
672 }
673 #[doc = "CRC calculation initialization pattern control for receiver"]
674 #[inline(always)]
675 pub const fn rcrcini(&self) -> super::vals::Rcrcini {
676 let val = (self.0 >> 14usize) & 0x01;
677 super::vals::Rcrcini::from_bits(val as u8)
678 }
679 #[doc = "CRC calculation initialization pattern control for receiver"]
680 #[inline(always)]
681 pub fn set_rcrcini(&mut self, val: super::vals::Rcrcini) {
682 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.to_bits() as u32) & 0x01) << 14usize);
683 }
684 #[doc = "CRC calculation initialization pattern control for transmitter"]
685 #[inline(always)]
686 pub const fn tcrcini(&self) -> super::vals::Tcrcini {
687 let val = (self.0 >> 15usize) & 0x01;
688 super::vals::Tcrcini::from_bits(val as u8)
689 }
690 #[doc = "CRC calculation initialization pattern control for transmitter"]
691 #[inline(always)]
692 pub fn set_tcrcini(&mut self, val: super::vals::Tcrcini) {
693 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.to_bits() as u32) & 0x01) << 15usize);
694 }
695 #[doc = "Locking the AF configuration of associated IOs"]
696 #[inline(always)]
697 pub const fn iolock(&self) -> bool {
698 let val = (self.0 >> 16usize) & 0x01;
699 val != 0
700 }
701 #[doc = "Locking the AF configuration of associated IOs"]
702 #[inline(always)]
703 pub fn set_iolock(&mut self, val: bool) {
704 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
705 }
706 }
707 impl Default for Cr1 {
708 #[inline(always)]
709 fn default() -> Cr1 {
710 Cr1(0)
711 }
712 }
713 impl core::fmt::Debug for Cr1 {
714 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
715 f.debug_struct("Cr1")
716 .field("spe", &self.spe())
717 .field("masrx", &self.masrx())
718 .field("cstart", &self.cstart())
719 .field("csusp", &self.csusp())
720 .field("hddir", &self.hddir())
721 .field("ssi", &self.ssi())
722 .field("crc33_17", &self.crc33_17())
723 .field("rcrcini", &self.rcrcini())
724 .field("tcrcini", &self.tcrcini())
725 .field("iolock", &self.iolock())
726 .finish()
727 }
728 }
729 #[cfg(feature = "defmt")]
730 impl defmt::Format for Cr1 {
731 fn format(&self, f: defmt::Formatter) {
732 #[derive(defmt :: Format)]
733 struct Cr1 {
734 spe: bool,
735 masrx: bool,
736 cstart: bool,
737 csusp: bool,
738 hddir: super::vals::Hddir,
739 ssi: bool,
740 crc33_17: bool,
741 rcrcini: super::vals::Rcrcini,
742 tcrcini: super::vals::Tcrcini,
743 iolock: bool,
744 }
745 let proxy = Cr1 {
746 spe: self.spe(),
747 masrx: self.masrx(),
748 cstart: self.cstart(),
749 csusp: self.csusp(),
750 hddir: self.hddir(),
751 ssi: self.ssi(),
752 crc33_17: self.crc33_17(),
753 rcrcini: self.rcrcini(),
754 tcrcini: self.tcrcini(),
755 iolock: self.iolock(),
756 };
757 defmt::write!(f, "{}", proxy)
758 }
759 }
760 #[doc = "control register 2"]
761 #[repr(transparent)]
762 #[derive(Copy, Clone, Eq, PartialEq)]
763 pub struct Cr2(pub u32);
764 impl Cr2 {
765 #[doc = "Number of data at current transfer"]
766 #[inline(always)]
767 pub const fn tsize(&self) -> u16 {
768 let val = (self.0 >> 0usize) & 0xffff;
769 val as u16
770 }
771 #[doc = "Number of data at current transfer"]
772 #[inline(always)]
773 pub fn set_tsize(&mut self, val: u16) {
774 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
775 }
776 }
777 impl Default for Cr2 {
778 #[inline(always)]
779 fn default() -> Cr2 {
780 Cr2(0)
781 }
782 }
783 impl core::fmt::Debug for Cr2 {
784 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
785 f.debug_struct("Cr2").field("tsize", &self.tsize()).finish()
786 }
787 }
788 #[cfg(feature = "defmt")]
789 impl defmt::Format for Cr2 {
790 fn format(&self, f: defmt::Formatter) {
791 #[derive(defmt :: Format)]
792 struct Cr2 {
793 tsize: u16,
794 }
795 let proxy = Cr2 { tsize: self.tsize() };
796 defmt::write!(f, "{}", proxy)
797 }
798 }
799 #[doc = "Polynomial Register"]
800 #[repr(transparent)]
801 #[derive(Copy, Clone, Eq, PartialEq)]
802 pub struct Crcpoly(pub u32);
803 impl Crcpoly {
804 #[doc = "CRC polynomial register"]
805 #[inline(always)]
806 pub const fn crcpoly(&self) -> u32 {
807 let val = (self.0 >> 0usize) & 0xffff_ffff;
808 val as u32
809 }
810 #[doc = "CRC polynomial register"]
811 #[inline(always)]
812 pub fn set_crcpoly(&mut self, val: u32) {
813 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
814 }
815 }
816 impl Default for Crcpoly {
817 #[inline(always)]
818 fn default() -> Crcpoly {
819 Crcpoly(0)
820 }
821 }
822 impl core::fmt::Debug for Crcpoly {
823 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
824 f.debug_struct("Crcpoly").field("crcpoly", &self.crcpoly()).finish()
825 }
826 }
827 #[cfg(feature = "defmt")]
828 impl defmt::Format for Crcpoly {
829 fn format(&self, f: defmt::Formatter) {
830 #[derive(defmt :: Format)]
831 struct Crcpoly {
832 crcpoly: u32,
833 }
834 let proxy = Crcpoly {
835 crcpoly: self.crcpoly(),
836 };
837 defmt::write!(f, "{}", proxy)
838 }
839 }
840 #[doc = "Interrupt Enable Register"]
841 #[repr(transparent)]
842 #[derive(Copy, Clone, Eq, PartialEq)]
843 pub struct Ier(pub u32);
844 impl Ier {
845 #[doc = "RXP Interrupt Enable"]
846 #[inline(always)]
847 pub const fn rxpie(&self) -> bool {
848 let val = (self.0 >> 0usize) & 0x01;
849 val != 0
850 }
851 #[doc = "RXP Interrupt Enable"]
852 #[inline(always)]
853 pub fn set_rxpie(&mut self, val: bool) {
854 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
855 }
856 #[doc = "TXP interrupt enable"]
857 #[inline(always)]
858 pub const fn txpie(&self) -> bool {
859 let val = (self.0 >> 1usize) & 0x01;
860 val != 0
861 }
862 #[doc = "TXP interrupt enable"]
863 #[inline(always)]
864 pub fn set_txpie(&mut self, val: bool) {
865 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
866 }
867 #[doc = "DXP interrupt enabled"]
868 #[inline(always)]
869 pub const fn dxpie(&self) -> bool {
870 let val = (self.0 >> 2usize) & 0x01;
871 val != 0
872 }
873 #[doc = "DXP interrupt enabled"]
874 #[inline(always)]
875 pub fn set_dxpie(&mut self, val: bool) {
876 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
877 }
878 #[doc = "EOT, SUSP and TXC interrupt enable"]
879 #[inline(always)]
880 pub const fn eotie(&self) -> bool {
881 let val = (self.0 >> 3usize) & 0x01;
882 val != 0
883 }
884 #[doc = "EOT, SUSP and TXC interrupt enable"]
885 #[inline(always)]
886 pub fn set_eotie(&mut self, val: bool) {
887 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
888 }
889 #[doc = "TXTFIE interrupt enable"]
890 #[inline(always)]
891 pub const fn txtfie(&self) -> bool {
892 let val = (self.0 >> 4usize) & 0x01;
893 val != 0
894 }
895 #[doc = "TXTFIE interrupt enable"]
896 #[inline(always)]
897 pub fn set_txtfie(&mut self, val: bool) {
898 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
899 }
900 #[doc = "UDR interrupt enable"]
901 #[inline(always)]
902 pub const fn udrie(&self) -> bool {
903 let val = (self.0 >> 5usize) & 0x01;
904 val != 0
905 }
906 #[doc = "UDR interrupt enable"]
907 #[inline(always)]
908 pub fn set_udrie(&mut self, val: bool) {
909 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
910 }
911 #[doc = "OVR interrupt enable"]
912 #[inline(always)]
913 pub const fn ovrie(&self) -> bool {
914 let val = (self.0 >> 6usize) & 0x01;
915 val != 0
916 }
917 #[doc = "OVR interrupt enable"]
918 #[inline(always)]
919 pub fn set_ovrie(&mut self, val: bool) {
920 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
921 }
922 #[doc = "CRC Interrupt enable"]
923 #[inline(always)]
924 pub const fn crceie(&self) -> bool {
925 let val = (self.0 >> 7usize) & 0x01;
926 val != 0
927 }
928 #[doc = "CRC Interrupt enable"]
929 #[inline(always)]
930 pub fn set_crceie(&mut self, val: bool) {
931 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
932 }
933 #[doc = "TIFRE interrupt enable"]
934 #[inline(always)]
935 pub const fn tifreie(&self) -> bool {
936 let val = (self.0 >> 8usize) & 0x01;
937 val != 0
938 }
939 #[doc = "TIFRE interrupt enable"]
940 #[inline(always)]
941 pub fn set_tifreie(&mut self, val: bool) {
942 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
943 }
944 #[doc = "Mode Fault interrupt enable"]
945 #[inline(always)]
946 pub const fn modfie(&self) -> bool {
947 let val = (self.0 >> 9usize) & 0x01;
948 val != 0
949 }
950 #[doc = "Mode Fault interrupt enable"]
951 #[inline(always)]
952 pub fn set_modfie(&mut self, val: bool) {
953 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
954 }
955 }
956 impl Default for Ier {
957 #[inline(always)]
958 fn default() -> Ier {
959 Ier(0)
960 }
961 }
962 impl core::fmt::Debug for Ier {
963 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
964 f.debug_struct("Ier")
965 .field("rxpie", &self.rxpie())
966 .field("txpie", &self.txpie())
967 .field("dxpie", &self.dxpie())
968 .field("eotie", &self.eotie())
969 .field("txtfie", &self.txtfie())
970 .field("udrie", &self.udrie())
971 .field("ovrie", &self.ovrie())
972 .field("crceie", &self.crceie())
973 .field("tifreie", &self.tifreie())
974 .field("modfie", &self.modfie())
975 .finish()
976 }
977 }
978 #[cfg(feature = "defmt")]
979 impl defmt::Format for Ier {
980 fn format(&self, f: defmt::Formatter) {
981 #[derive(defmt :: Format)]
982 struct Ier {
983 rxpie: bool,
984 txpie: bool,
985 dxpie: bool,
986 eotie: bool,
987 txtfie: bool,
988 udrie: bool,
989 ovrie: bool,
990 crceie: bool,
991 tifreie: bool,
992 modfie: bool,
993 }
994 let proxy = Ier {
995 rxpie: self.rxpie(),
996 txpie: self.txpie(),
997 dxpie: self.dxpie(),
998 eotie: self.eotie(),
999 txtfie: self.txtfie(),
1000 udrie: self.udrie(),
1001 ovrie: self.ovrie(),
1002 crceie: self.crceie(),
1003 tifreie: self.tifreie(),
1004 modfie: self.modfie(),
1005 };
1006 defmt::write!(f, "{}", proxy)
1007 }
1008 }
1009 #[doc = "Interrupt/Status Flags Clear Register"]
1010 #[repr(transparent)]
1011 #[derive(Copy, Clone, Eq, PartialEq)]
1012 pub struct Ifcr(pub u32);
1013 impl Ifcr {
1014 #[doc = "End Of Transfer flag clear"]
1015 #[inline(always)]
1016 pub const fn eotc(&self) -> bool {
1017 let val = (self.0 >> 3usize) & 0x01;
1018 val != 0
1019 }
1020 #[doc = "End Of Transfer flag clear"]
1021 #[inline(always)]
1022 pub fn set_eotc(&mut self, val: bool) {
1023 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1024 }
1025 #[doc = "Transmission Transfer Filled flag clear"]
1026 #[inline(always)]
1027 pub const fn txtfc(&self) -> bool {
1028 let val = (self.0 >> 4usize) & 0x01;
1029 val != 0
1030 }
1031 #[doc = "Transmission Transfer Filled flag clear"]
1032 #[inline(always)]
1033 pub fn set_txtfc(&mut self, val: bool) {
1034 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1035 }
1036 #[doc = "Underrun flag clear"]
1037 #[inline(always)]
1038 pub const fn udrc(&self) -> bool {
1039 let val = (self.0 >> 5usize) & 0x01;
1040 val != 0
1041 }
1042 #[doc = "Underrun flag clear"]
1043 #[inline(always)]
1044 pub fn set_udrc(&mut self, val: bool) {
1045 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
1046 }
1047 #[doc = "Overrun flag clear"]
1048 #[inline(always)]
1049 pub const fn ovrc(&self) -> bool {
1050 let val = (self.0 >> 6usize) & 0x01;
1051 val != 0
1052 }
1053 #[doc = "Overrun flag clear"]
1054 #[inline(always)]
1055 pub fn set_ovrc(&mut self, val: bool) {
1056 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
1057 }
1058 #[doc = "CRC Error flag clear"]
1059 #[inline(always)]
1060 pub const fn crcec(&self) -> bool {
1061 let val = (self.0 >> 7usize) & 0x01;
1062 val != 0
1063 }
1064 #[doc = "CRC Error flag clear"]
1065 #[inline(always)]
1066 pub fn set_crcec(&mut self, val: bool) {
1067 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
1068 }
1069 #[doc = "TI frame format error flag clear"]
1070 #[inline(always)]
1071 pub const fn tifrec(&self) -> bool {
1072 let val = (self.0 >> 8usize) & 0x01;
1073 val != 0
1074 }
1075 #[doc = "TI frame format error flag clear"]
1076 #[inline(always)]
1077 pub fn set_tifrec(&mut self, val: bool) {
1078 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
1079 }
1080 #[doc = "Mode Fault flag clear"]
1081 #[inline(always)]
1082 pub const fn modfc(&self) -> bool {
1083 let val = (self.0 >> 9usize) & 0x01;
1084 val != 0
1085 }
1086 #[doc = "Mode Fault flag clear"]
1087 #[inline(always)]
1088 pub fn set_modfc(&mut self, val: bool) {
1089 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
1090 }
1091 #[doc = "SUSPend flag clear"]
1092 #[inline(always)]
1093 pub const fn suspc(&self) -> bool {
1094 let val = (self.0 >> 11usize) & 0x01;
1095 val != 0
1096 }
1097 #[doc = "SUSPend flag clear"]
1098 #[inline(always)]
1099 pub fn set_suspc(&mut self, val: bool) {
1100 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
1101 }
1102 }
1103 impl Default for Ifcr {
1104 #[inline(always)]
1105 fn default() -> Ifcr {
1106 Ifcr(0)
1107 }
1108 }
1109 impl core::fmt::Debug for Ifcr {
1110 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1111 f.debug_struct("Ifcr")
1112 .field("eotc", &self.eotc())
1113 .field("txtfc", &self.txtfc())
1114 .field("udrc", &self.udrc())
1115 .field("ovrc", &self.ovrc())
1116 .field("crcec", &self.crcec())
1117 .field("tifrec", &self.tifrec())
1118 .field("modfc", &self.modfc())
1119 .field("suspc", &self.suspc())
1120 .finish()
1121 }
1122 }
1123 #[cfg(feature = "defmt")]
1124 impl defmt::Format for Ifcr {
1125 fn format(&self, f: defmt::Formatter) {
1126 #[derive(defmt :: Format)]
1127 struct Ifcr {
1128 eotc: bool,
1129 txtfc: bool,
1130 udrc: bool,
1131 ovrc: bool,
1132 crcec: bool,
1133 tifrec: bool,
1134 modfc: bool,
1135 suspc: bool,
1136 }
1137 let proxy = Ifcr {
1138 eotc: self.eotc(),
1139 txtfc: self.txtfc(),
1140 udrc: self.udrc(),
1141 ovrc: self.ovrc(),
1142 crcec: self.crcec(),
1143 tifrec: self.tifrec(),
1144 modfc: self.modfc(),
1145 suspc: self.suspc(),
1146 };
1147 defmt::write!(f, "{}", proxy)
1148 }
1149 }
1150 #[doc = "Receiver CRC Register"]
1151 #[repr(transparent)]
1152 #[derive(Copy, Clone, Eq, PartialEq)]
1153 pub struct Rxcrc(pub u32);
1154 impl Rxcrc {
1155 #[doc = "CRC register for receiver"]
1156 #[inline(always)]
1157 pub const fn rxcrc(&self) -> u32 {
1158 let val = (self.0 >> 0usize) & 0xffff_ffff;
1159 val as u32
1160 }
1161 #[doc = "CRC register for receiver"]
1162 #[inline(always)]
1163 pub fn set_rxcrc(&mut self, val: u32) {
1164 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1165 }
1166 }
1167 impl Default for Rxcrc {
1168 #[inline(always)]
1169 fn default() -> Rxcrc {
1170 Rxcrc(0)
1171 }
1172 }
1173 impl core::fmt::Debug for Rxcrc {
1174 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1175 f.debug_struct("Rxcrc").field("rxcrc", &self.rxcrc()).finish()
1176 }
1177 }
1178 #[cfg(feature = "defmt")]
1179 impl defmt::Format for Rxcrc {
1180 fn format(&self, f: defmt::Formatter) {
1181 #[derive(defmt :: Format)]
1182 struct Rxcrc {
1183 rxcrc: u32,
1184 }
1185 let proxy = Rxcrc { rxcrc: self.rxcrc() };
1186 defmt::write!(f, "{}", proxy)
1187 }
1188 }
1189 #[doc = "Status Register"]
1190 #[repr(transparent)]
1191 #[derive(Copy, Clone, Eq, PartialEq)]
1192 pub struct Sr(pub u32);
1193 impl Sr {
1194 #[doc = "Rx-Packet available"]
1195 #[inline(always)]
1196 pub const fn rxp(&self) -> bool {
1197 let val = (self.0 >> 0usize) & 0x01;
1198 val != 0
1199 }
1200 #[doc = "Rx-Packet available"]
1201 #[inline(always)]
1202 pub fn set_rxp(&mut self, val: bool) {
1203 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1204 }
1205 #[doc = "Tx-Packet space available"]
1206 #[inline(always)]
1207 pub const fn txp(&self) -> bool {
1208 let val = (self.0 >> 1usize) & 0x01;
1209 val != 0
1210 }
1211 #[doc = "Tx-Packet space available"]
1212 #[inline(always)]
1213 pub fn set_txp(&mut self, val: bool) {
1214 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1215 }
1216 #[doc = "Duplex Packet"]
1217 #[inline(always)]
1218 pub const fn dxp(&self) -> bool {
1219 let val = (self.0 >> 2usize) & 0x01;
1220 val != 0
1221 }
1222 #[doc = "Duplex Packet"]
1223 #[inline(always)]
1224 pub fn set_dxp(&mut self, val: bool) {
1225 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1226 }
1227 #[doc = "End Of Transfer"]
1228 #[inline(always)]
1229 pub const fn eot(&self) -> bool {
1230 let val = (self.0 >> 3usize) & 0x01;
1231 val != 0
1232 }
1233 #[doc = "End Of Transfer"]
1234 #[inline(always)]
1235 pub fn set_eot(&mut self, val: bool) {
1236 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1237 }
1238 #[doc = "Transmission Transfer Filled"]
1239 #[inline(always)]
1240 pub const fn txtf(&self) -> bool {
1241 let val = (self.0 >> 4usize) & 0x01;
1242 val != 0
1243 }
1244 #[doc = "Transmission Transfer Filled"]
1245 #[inline(always)]
1246 pub fn set_txtf(&mut self, val: bool) {
1247 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1248 }
1249 #[doc = "Underrun at slave transmission mode"]
1250 #[inline(always)]
1251 pub const fn udr(&self) -> bool {
1252 let val = (self.0 >> 5usize) & 0x01;
1253 val != 0
1254 }
1255 #[doc = "Underrun at slave transmission mode"]
1256 #[inline(always)]
1257 pub fn set_udr(&mut self, val: bool) {
1258 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
1259 }
1260 #[doc = "Overrun"]
1261 #[inline(always)]
1262 pub const fn ovr(&self) -> bool {
1263 let val = (self.0 >> 6usize) & 0x01;
1264 val != 0
1265 }
1266 #[doc = "Overrun"]
1267 #[inline(always)]
1268 pub fn set_ovr(&mut self, val: bool) {
1269 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
1270 }
1271 #[doc = "CRC Error"]
1272 #[inline(always)]
1273 pub const fn crce(&self) -> bool {
1274 let val = (self.0 >> 7usize) & 0x01;
1275 val != 0
1276 }
1277 #[doc = "CRC Error"]
1278 #[inline(always)]
1279 pub fn set_crce(&mut self, val: bool) {
1280 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
1281 }
1282 #[doc = "TI frame format error"]
1283 #[inline(always)]
1284 pub const fn tifre(&self) -> bool {
1285 let val = (self.0 >> 8usize) & 0x01;
1286 val != 0
1287 }
1288 #[doc = "TI frame format error"]
1289 #[inline(always)]
1290 pub fn set_tifre(&mut self, val: bool) {
1291 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
1292 }
1293 #[doc = "Mode Fault"]
1294 #[inline(always)]
1295 pub const fn modf(&self) -> bool {
1296 let val = (self.0 >> 9usize) & 0x01;
1297 val != 0
1298 }
1299 #[doc = "Mode Fault"]
1300 #[inline(always)]
1301 pub fn set_modf(&mut self, val: bool) {
1302 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
1303 }
1304 #[doc = "SUSPend"]
1305 #[inline(always)]
1306 pub const fn susp(&self) -> bool {
1307 let val = (self.0 >> 11usize) & 0x01;
1308 val != 0
1309 }
1310 #[doc = "SUSPend"]
1311 #[inline(always)]
1312 pub fn set_susp(&mut self, val: bool) {
1313 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
1314 }
1315 #[doc = "TxFIFO transmission complete"]
1316 #[inline(always)]
1317 pub const fn txc(&self) -> bool {
1318 let val = (self.0 >> 12usize) & 0x01;
1319 val != 0
1320 }
1321 #[doc = "TxFIFO transmission complete"]
1322 #[inline(always)]
1323 pub fn set_txc(&mut self, val: bool) {
1324 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
1325 }
1326 #[doc = "RxFIFO Packing LeVeL"]
1327 #[inline(always)]
1328 pub const fn rxplvl(&self) -> super::vals::Rxplvl {
1329 let val = (self.0 >> 13usize) & 0x03;
1330 super::vals::Rxplvl::from_bits(val as u8)
1331 }
1332 #[doc = "RxFIFO Packing LeVeL"]
1333 #[inline(always)]
1334 pub fn set_rxplvl(&mut self, val: super::vals::Rxplvl) {
1335 self.0 = (self.0 & !(0x03 << 13usize)) | (((val.to_bits() as u32) & 0x03) << 13usize);
1336 }
1337 #[doc = "RxFIFO Word Not Empty"]
1338 #[inline(always)]
1339 pub const fn rxwne(&self) -> super::vals::Rxwne {
1340 let val = (self.0 >> 15usize) & 0x01;
1341 super::vals::Rxwne::from_bits(val as u8)
1342 }
1343 #[doc = "RxFIFO Word Not Empty"]
1344 #[inline(always)]
1345 pub fn set_rxwne(&mut self, val: super::vals::Rxwne) {
1346 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.to_bits() as u32) & 0x01) << 15usize);
1347 }
1348 #[doc = "Number of data frames remaining in current TSIZE session"]
1349 #[inline(always)]
1350 pub const fn ctsize(&self) -> u16 {
1351 let val = (self.0 >> 16usize) & 0xffff;
1352 val as u16
1353 }
1354 #[doc = "Number of data frames remaining in current TSIZE session"]
1355 #[inline(always)]
1356 pub fn set_ctsize(&mut self, val: u16) {
1357 self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize);
1358 }
1359 }
1360 impl Default for Sr {
1361 #[inline(always)]
1362 fn default() -> Sr {
1363 Sr(0)
1364 }
1365 }
1366 impl core::fmt::Debug for Sr {
1367 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1368 f.debug_struct("Sr")
1369 .field("rxp", &self.rxp())
1370 .field("txp", &self.txp())
1371 .field("dxp", &self.dxp())
1372 .field("eot", &self.eot())
1373 .field("txtf", &self.txtf())
1374 .field("udr", &self.udr())
1375 .field("ovr", &self.ovr())
1376 .field("crce", &self.crce())
1377 .field("tifre", &self.tifre())
1378 .field("modf", &self.modf())
1379 .field("susp", &self.susp())
1380 .field("txc", &self.txc())
1381 .field("rxplvl", &self.rxplvl())
1382 .field("rxwne", &self.rxwne())
1383 .field("ctsize", &self.ctsize())
1384 .finish()
1385 }
1386 }
1387 #[cfg(feature = "defmt")]
1388 impl defmt::Format for Sr {
1389 fn format(&self, f: defmt::Formatter) {
1390 #[derive(defmt :: Format)]
1391 struct Sr {
1392 rxp: bool,
1393 txp: bool,
1394 dxp: bool,
1395 eot: bool,
1396 txtf: bool,
1397 udr: bool,
1398 ovr: bool,
1399 crce: bool,
1400 tifre: bool,
1401 modf: bool,
1402 susp: bool,
1403 txc: bool,
1404 rxplvl: super::vals::Rxplvl,
1405 rxwne: super::vals::Rxwne,
1406 ctsize: u16,
1407 }
1408 let proxy = Sr {
1409 rxp: self.rxp(),
1410 txp: self.txp(),
1411 dxp: self.dxp(),
1412 eot: self.eot(),
1413 txtf: self.txtf(),
1414 udr: self.udr(),
1415 ovr: self.ovr(),
1416 crce: self.crce(),
1417 tifre: self.tifre(),
1418 modf: self.modf(),
1419 susp: self.susp(),
1420 txc: self.txc(),
1421 rxplvl: self.rxplvl(),
1422 rxwne: self.rxwne(),
1423 ctsize: self.ctsize(),
1424 };
1425 defmt::write!(f, "{}", proxy)
1426 }
1427 }
1428 #[doc = "Transmitter CRC Register"]
1429 #[repr(transparent)]
1430 #[derive(Copy, Clone, Eq, PartialEq)]
1431 pub struct Txcrc(pub u32);
1432 impl Txcrc {
1433 #[doc = "CRC register for transmitter"]
1434 #[inline(always)]
1435 pub const fn txcrc(&self) -> u32 {
1436 let val = (self.0 >> 0usize) & 0xffff_ffff;
1437 val as u32
1438 }
1439 #[doc = "CRC register for transmitter"]
1440 #[inline(always)]
1441 pub fn set_txcrc(&mut self, val: u32) {
1442 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1443 }
1444 }
1445 impl Default for Txcrc {
1446 #[inline(always)]
1447 fn default() -> Txcrc {
1448 Txcrc(0)
1449 }
1450 }
1451 impl core::fmt::Debug for Txcrc {
1452 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1453 f.debug_struct("Txcrc").field("txcrc", &self.txcrc()).finish()
1454 }
1455 }
1456 #[cfg(feature = "defmt")]
1457 impl defmt::Format for Txcrc {
1458 fn format(&self, f: defmt::Formatter) {
1459 #[derive(defmt :: Format)]
1460 struct Txcrc {
1461 txcrc: u32,
1462 }
1463 let proxy = Txcrc { txcrc: self.txcrc() };
1464 defmt::write!(f, "{}", proxy)
1465 }
1466 }
1467 #[doc = "Underrun Data Register"]
1468 #[repr(transparent)]
1469 #[derive(Copy, Clone, Eq, PartialEq)]
1470 pub struct Udrdr(pub u32);
1471 impl Udrdr {
1472 #[doc = "Data at slave underrun condition"]
1473 #[inline(always)]
1474 pub const fn udrdr(&self) -> u32 {
1475 let val = (self.0 >> 0usize) & 0xffff_ffff;
1476 val as u32
1477 }
1478 #[doc = "Data at slave underrun condition"]
1479 #[inline(always)]
1480 pub fn set_udrdr(&mut self, val: u32) {
1481 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1482 }
1483 }
1484 impl Default for Udrdr {
1485 #[inline(always)]
1486 fn default() -> Udrdr {
1487 Udrdr(0)
1488 }
1489 }
1490 impl core::fmt::Debug for Udrdr {
1491 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1492 f.debug_struct("Udrdr").field("udrdr", &self.udrdr()).finish()
1493 }
1494 }
1495 #[cfg(feature = "defmt")]
1496 impl defmt::Format for Udrdr {
1497 fn format(&self, f: defmt::Formatter) {
1498 #[derive(defmt :: Format)]
1499 struct Udrdr {
1500 udrdr: u32,
1501 }
1502 let proxy = Udrdr { udrdr: self.udrdr() };
1503 defmt::write!(f, "{}", proxy)
1504 }
1505 }
1506}
1507pub mod vals {
1508 #[repr(u8)]
1509 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1510 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1511 pub enum Comm {
1512 #[doc = "Full duplex"]
1513 FULL_DUPLEX = 0x0,
1514 #[doc = "Simplex transmitter only"]
1515 TRANSMITTER = 0x01,
1516 #[doc = "Simplex receiver only"]
1517 RECEIVER = 0x02,
1518 #[doc = "Half duplex"]
1519 HALF_DUPLEX = 0x03,
1520 }
1521 impl Comm {
1522 #[inline(always)]
1523 pub const fn from_bits(val: u8) -> Comm {
1524 unsafe { core::mem::transmute(val & 0x03) }
1525 }
1526 #[inline(always)]
1527 pub const fn to_bits(self) -> u8 {
1528 unsafe { core::mem::transmute(self) }
1529 }
1530 }
1531 impl From<u8> for Comm {
1532 #[inline(always)]
1533 fn from(val: u8) -> Comm {
1534 Comm::from_bits(val)
1535 }
1536 }
1537 impl From<Comm> for u8 {
1538 #[inline(always)]
1539 fn from(val: Comm) -> u8 {
1540 Comm::to_bits(val)
1541 }
1542 }
1543 #[repr(u8)]
1544 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1545 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1546 pub enum Cpha {
1547 #[doc = "The first clock transition is the first data capture edge"]
1548 FIRST_EDGE = 0x0,
1549 #[doc = "The second clock transition is the first data capture edge"]
1550 SECOND_EDGE = 0x01,
1551 }
1552 impl Cpha {
1553 #[inline(always)]
1554 pub const fn from_bits(val: u8) -> Cpha {
1555 unsafe { core::mem::transmute(val & 0x01) }
1556 }
1557 #[inline(always)]
1558 pub const fn to_bits(self) -> u8 {
1559 unsafe { core::mem::transmute(self) }
1560 }
1561 }
1562 impl From<u8> for Cpha {
1563 #[inline(always)]
1564 fn from(val: u8) -> Cpha {
1565 Cpha::from_bits(val)
1566 }
1567 }
1568 impl From<Cpha> for u8 {
1569 #[inline(always)]
1570 fn from(val: Cpha) -> u8 {
1571 Cpha::to_bits(val)
1572 }
1573 }
1574 #[repr(u8)]
1575 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1576 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1577 pub enum Cpol {
1578 #[doc = "CK to 0 when idle"]
1579 IDLE_LOW = 0x0,
1580 #[doc = "CK to 1 when idle"]
1581 IDLE_HIGH = 0x01,
1582 }
1583 impl Cpol {
1584 #[inline(always)]
1585 pub const fn from_bits(val: u8) -> Cpol {
1586 unsafe { core::mem::transmute(val & 0x01) }
1587 }
1588 #[inline(always)]
1589 pub const fn to_bits(self) -> u8 {
1590 unsafe { core::mem::transmute(self) }
1591 }
1592 }
1593 impl From<u8> for Cpol {
1594 #[inline(always)]
1595 fn from(val: u8) -> Cpol {
1596 Cpol::from_bits(val)
1597 }
1598 }
1599 impl From<Cpol> for u8 {
1600 #[inline(always)]
1601 fn from(val: Cpol) -> u8 {
1602 Cpol::to_bits(val)
1603 }
1604 }
1605 #[repr(u8)]
1606 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1607 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1608 pub enum Fthlv {
1609 #[doc = "1 frame"]
1610 ONE_FRAME = 0x0,
1611 #[doc = "2 frames"]
1612 TWO_FRAMES = 0x01,
1613 #[doc = "3 frames"]
1614 THREE_FRAMES = 0x02,
1615 #[doc = "4 frames"]
1616 FOUR_FRAMES = 0x03,
1617 #[doc = "5 frames"]
1618 FIVE_FRAMES = 0x04,
1619 #[doc = "6 frames"]
1620 SIX_FRAMES = 0x05,
1621 #[doc = "7 frames"]
1622 SEVEN_FRAMES = 0x06,
1623 #[doc = "8 frames"]
1624 EIGHT_FRAMES = 0x07,
1625 #[doc = "9 frames"]
1626 NINE_FRAMES = 0x08,
1627 #[doc = "10 frames"]
1628 TEN_FRAMES = 0x09,
1629 #[doc = "11 frames"]
1630 ELEVEN_FRAMES = 0x0a,
1631 #[doc = "12 frames"]
1632 TWELVE_FRAMES = 0x0b,
1633 #[doc = "13 frames"]
1634 THIRTEEN_FRAMES = 0x0c,
1635 #[doc = "14 frames"]
1636 FOURTEEN_FRAMES = 0x0d,
1637 #[doc = "15 frames"]
1638 FIFTEEN_FRAMES = 0x0e,
1639 #[doc = "16 frames"]
1640 SIXTEEN_FRAMES = 0x0f,
1641 }
1642 impl Fthlv {
1643 #[inline(always)]
1644 pub const fn from_bits(val: u8) -> Fthlv {
1645 unsafe { core::mem::transmute(val & 0x0f) }
1646 }
1647 #[inline(always)]
1648 pub const fn to_bits(self) -> u8 {
1649 unsafe { core::mem::transmute(self) }
1650 }
1651 }
1652 impl From<u8> for Fthlv {
1653 #[inline(always)]
1654 fn from(val: u8) -> Fthlv {
1655 Fthlv::from_bits(val)
1656 }
1657 }
1658 impl From<Fthlv> for u8 {
1659 #[inline(always)]
1660 fn from(val: Fthlv) -> u8 {
1661 Fthlv::to_bits(val)
1662 }
1663 }
1664 #[repr(u8)]
1665 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1666 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1667 pub enum Hddir {
1668 #[doc = "Receiver in half duplex mode"]
1669 RECEIVER = 0x0,
1670 #[doc = "Transmitter in half duplex mode"]
1671 TRANSMITTER = 0x01,
1672 }
1673 impl Hddir {
1674 #[inline(always)]
1675 pub const fn from_bits(val: u8) -> Hddir {
1676 unsafe { core::mem::transmute(val & 0x01) }
1677 }
1678 #[inline(always)]
1679 pub const fn to_bits(self) -> u8 {
1680 unsafe { core::mem::transmute(self) }
1681 }
1682 }
1683 impl From<u8> for Hddir {
1684 #[inline(always)]
1685 fn from(val: u8) -> Hddir {
1686 Hddir::from_bits(val)
1687 }
1688 }
1689 impl From<Hddir> for u8 {
1690 #[inline(always)]
1691 fn from(val: Hddir) -> u8 {
1692 Hddir::to_bits(val)
1693 }
1694 }
1695 #[repr(u8)]
1696 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1697 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1698 pub enum Lsbfirst {
1699 #[doc = "Data is transmitted/received with the MSB first"]
1700 MSBFIRST = 0x0,
1701 #[doc = "Data is transmitted/received with the LSB first"]
1702 LSBFIRST = 0x01,
1703 }
1704 impl Lsbfirst {
1705 #[inline(always)]
1706 pub const fn from_bits(val: u8) -> Lsbfirst {
1707 unsafe { core::mem::transmute(val & 0x01) }
1708 }
1709 #[inline(always)]
1710 pub const fn to_bits(self) -> u8 {
1711 unsafe { core::mem::transmute(self) }
1712 }
1713 }
1714 impl From<u8> for Lsbfirst {
1715 #[inline(always)]
1716 fn from(val: u8) -> Lsbfirst {
1717 Lsbfirst::from_bits(val)
1718 }
1719 }
1720 impl From<Lsbfirst> for u8 {
1721 #[inline(always)]
1722 fn from(val: Lsbfirst) -> u8 {
1723 Lsbfirst::to_bits(val)
1724 }
1725 }
1726 #[repr(u8)]
1727 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1728 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1729 pub enum Master {
1730 #[doc = "Slave configuration"]
1731 SLAVE = 0x0,
1732 #[doc = "Master configuration"]
1733 MASTER = 0x01,
1734 }
1735 impl Master {
1736 #[inline(always)]
1737 pub const fn from_bits(val: u8) -> Master {
1738 unsafe { core::mem::transmute(val & 0x01) }
1739 }
1740 #[inline(always)]
1741 pub const fn to_bits(self) -> u8 {
1742 unsafe { core::mem::transmute(self) }
1743 }
1744 }
1745 impl From<u8> for Master {
1746 #[inline(always)]
1747 fn from(val: u8) -> Master {
1748 Master::from_bits(val)
1749 }
1750 }
1751 impl From<Master> for u8 {
1752 #[inline(always)]
1753 fn from(val: Master) -> u8 {
1754 Master::to_bits(val)
1755 }
1756 }
1757 #[repr(u8)]
1758 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1759 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1760 pub enum Mbr {
1761 #[doc = "f_spi_ker_ck / 2"]
1762 DIV2 = 0x0,
1763 #[doc = "f_spi_ker_ck / 4"]
1764 DIV4 = 0x01,
1765 #[doc = "f_spi_ker_ck / 8"]
1766 DIV8 = 0x02,
1767 #[doc = "f_spi_ker_ck / 16"]
1768 DIV16 = 0x03,
1769 #[doc = "f_spi_ker_ck / 32"]
1770 DIV32 = 0x04,
1771 #[doc = "f_spi_ker_ck / 64"]
1772 DIV64 = 0x05,
1773 #[doc = "f_spi_ker_ck / 128"]
1774 DIV128 = 0x06,
1775 #[doc = "f_spi_ker_ck / 256"]
1776 DIV256 = 0x07,
1777 }
1778 impl Mbr {
1779 #[inline(always)]
1780 pub const fn from_bits(val: u8) -> Mbr {
1781 unsafe { core::mem::transmute(val & 0x07) }
1782 }
1783 #[inline(always)]
1784 pub const fn to_bits(self) -> u8 {
1785 unsafe { core::mem::transmute(self) }
1786 }
1787 }
1788 impl From<u8> for Mbr {
1789 #[inline(always)]
1790 fn from(val: u8) -> Mbr {
1791 Mbr::from_bits(val)
1792 }
1793 }
1794 impl From<Mbr> for u8 {
1795 #[inline(always)]
1796 fn from(val: Mbr) -> u8 {
1797 Mbr::to_bits(val)
1798 }
1799 }
1800 #[repr(u8)]
1801 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1802 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1803 pub enum Rcrcini {
1804 #[doc = "All zeros RX CRC initialization pattern"]
1805 ALL_ZEROS = 0x0,
1806 #[doc = "All ones RX CRC initialization pattern"]
1807 ALL_ONES = 0x01,
1808 }
1809 impl Rcrcini {
1810 #[inline(always)]
1811 pub const fn from_bits(val: u8) -> Rcrcini {
1812 unsafe { core::mem::transmute(val & 0x01) }
1813 }
1814 #[inline(always)]
1815 pub const fn to_bits(self) -> u8 {
1816 unsafe { core::mem::transmute(self) }
1817 }
1818 }
1819 impl From<u8> for Rcrcini {
1820 #[inline(always)]
1821 fn from(val: u8) -> Rcrcini {
1822 Rcrcini::from_bits(val)
1823 }
1824 }
1825 impl From<Rcrcini> for u8 {
1826 #[inline(always)]
1827 fn from(val: Rcrcini) -> u8 {
1828 Rcrcini::to_bits(val)
1829 }
1830 }
1831 #[repr(u8)]
1832 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1833 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1834 pub enum Rdiom {
1835 #[doc = "RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect)"]
1836 PERMANENTLY_ACTIVE = 0x0,
1837 #[doc = "RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect)"]
1838 FROM_INPUT = 0x01,
1839 }
1840 impl Rdiom {
1841 #[inline(always)]
1842 pub const fn from_bits(val: u8) -> Rdiom {
1843 unsafe { core::mem::transmute(val & 0x01) }
1844 }
1845 #[inline(always)]
1846 pub const fn to_bits(self) -> u8 {
1847 unsafe { core::mem::transmute(self) }
1848 }
1849 }
1850 impl From<u8> for Rdiom {
1851 #[inline(always)]
1852 fn from(val: u8) -> Rdiom {
1853 Rdiom::from_bits(val)
1854 }
1855 }
1856 impl From<Rdiom> for u8 {
1857 #[inline(always)]
1858 fn from(val: Rdiom) -> u8 {
1859 Rdiom::to_bits(val)
1860 }
1861 }
1862 #[repr(u8)]
1863 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1864 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1865 pub enum Rdiop {
1866 #[doc = "high level of the signal means the slave is ready for communication"]
1867 READY_HIGH = 0x0,
1868 #[doc = "low level of the signal means the slave is ready for communication"]
1869 READY_LOW = 0x01,
1870 }
1871 impl Rdiop {
1872 #[inline(always)]
1873 pub const fn from_bits(val: u8) -> Rdiop {
1874 unsafe { core::mem::transmute(val & 0x01) }
1875 }
1876 #[inline(always)]
1877 pub const fn to_bits(self) -> u8 {
1878 unsafe { core::mem::transmute(self) }
1879 }
1880 }
1881 impl From<u8> for Rdiop {
1882 #[inline(always)]
1883 fn from(val: u8) -> Rdiop {
1884 Rdiop::from_bits(val)
1885 }
1886 }
1887 impl From<Rdiop> for u8 {
1888 #[inline(always)]
1889 fn from(val: Rdiop) -> u8 {
1890 Rdiop::to_bits(val)
1891 }
1892 }
1893 #[repr(u8)]
1894 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1895 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1896 pub enum Rxplvl {
1897 #[doc = "Zero frames beyond packing ratio available"]
1898 ZERO_FRAMES = 0x0,
1899 #[doc = "One frame beyond packing ratio available"]
1900 ONE_FRAME = 0x01,
1901 #[doc = "Two frame beyond packing ratio available"]
1902 TWO_FRAMES = 0x02,
1903 #[doc = "Three frame beyond packing ratio available"]
1904 THREE_FRAMES = 0x03,
1905 }
1906 impl Rxplvl {
1907 #[inline(always)]
1908 pub const fn from_bits(val: u8) -> Rxplvl {
1909 unsafe { core::mem::transmute(val & 0x03) }
1910 }
1911 #[inline(always)]
1912 pub const fn to_bits(self) -> u8 {
1913 unsafe { core::mem::transmute(self) }
1914 }
1915 }
1916 impl From<u8> for Rxplvl {
1917 #[inline(always)]
1918 fn from(val: u8) -> Rxplvl {
1919 Rxplvl::from_bits(val)
1920 }
1921 }
1922 impl From<Rxplvl> for u8 {
1923 #[inline(always)]
1924 fn from(val: Rxplvl) -> u8 {
1925 Rxplvl::to_bits(val)
1926 }
1927 }
1928 #[repr(u8)]
1929 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1930 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1931 pub enum Rxwne {
1932 #[doc = "Less than 32-bit data frame received"]
1933 LESS_THAN32 = 0x0,
1934 #[doc = "At least 32-bit data frame received"]
1935 AT_LEAST32 = 0x01,
1936 }
1937 impl Rxwne {
1938 #[inline(always)]
1939 pub const fn from_bits(val: u8) -> Rxwne {
1940 unsafe { core::mem::transmute(val & 0x01) }
1941 }
1942 #[inline(always)]
1943 pub const fn to_bits(self) -> u8 {
1944 unsafe { core::mem::transmute(self) }
1945 }
1946 }
1947 impl From<u8> for Rxwne {
1948 #[inline(always)]
1949 fn from(val: u8) -> Rxwne {
1950 Rxwne::from_bits(val)
1951 }
1952 }
1953 impl From<Rxwne> for u8 {
1954 #[inline(always)]
1955 fn from(val: Rxwne) -> u8 {
1956 Rxwne::to_bits(val)
1957 }
1958 }
1959 #[repr(u8)]
1960 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1961 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1962 pub enum Sp {
1963 #[doc = "Motorola SPI protocol"]
1964 MOTOROLA = 0x0,
1965 #[doc = "TI SPI protocol"]
1966 TI = 0x01,
1967 _RESERVED_2 = 0x02,
1968 _RESERVED_3 = 0x03,
1969 _RESERVED_4 = 0x04,
1970 _RESERVED_5 = 0x05,
1971 _RESERVED_6 = 0x06,
1972 _RESERVED_7 = 0x07,
1973 }
1974 impl Sp {
1975 #[inline(always)]
1976 pub const fn from_bits(val: u8) -> Sp {
1977 unsafe { core::mem::transmute(val & 0x07) }
1978 }
1979 #[inline(always)]
1980 pub const fn to_bits(self) -> u8 {
1981 unsafe { core::mem::transmute(self) }
1982 }
1983 }
1984 impl From<u8> for Sp {
1985 #[inline(always)]
1986 fn from(val: u8) -> Sp {
1987 Sp::from_bits(val)
1988 }
1989 }
1990 impl From<Sp> for u8 {
1991 #[inline(always)]
1992 fn from(val: Sp) -> u8 {
1993 Sp::to_bits(val)
1994 }
1995 }
1996 #[repr(u8)]
1997 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1998 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1999 pub enum Ssiop {
2000 #[doc = "Low level is active for SS signal"]
2001 ACTIVE_LOW = 0x0,
2002 #[doc = "High level is active for SS signal"]
2003 ACTIVE_HIGH = 0x01,
2004 }
2005 impl Ssiop {
2006 #[inline(always)]
2007 pub const fn from_bits(val: u8) -> Ssiop {
2008 unsafe { core::mem::transmute(val & 0x01) }
2009 }
2010 #[inline(always)]
2011 pub const fn to_bits(self) -> u8 {
2012 unsafe { core::mem::transmute(self) }
2013 }
2014 }
2015 impl From<u8> for Ssiop {
2016 #[inline(always)]
2017 fn from(val: u8) -> Ssiop {
2018 Ssiop::from_bits(val)
2019 }
2020 }
2021 impl From<Ssiop> for u8 {
2022 #[inline(always)]
2023 fn from(val: Ssiop) -> u8 {
2024 Ssiop::to_bits(val)
2025 }
2026 }
2027 #[repr(u8)]
2028 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2029 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2030 pub enum Ssom {
2031 #[doc = "SS is asserted until data transfer complete"]
2032 ASSERTED = 0x0,
2033 #[doc = "Data frames interleaved with SS not asserted during MIDI"]
2034 NOT_ASSERTED = 0x01,
2035 }
2036 impl Ssom {
2037 #[inline(always)]
2038 pub const fn from_bits(val: u8) -> Ssom {
2039 unsafe { core::mem::transmute(val & 0x01) }
2040 }
2041 #[inline(always)]
2042 pub const fn to_bits(self) -> u8 {
2043 unsafe { core::mem::transmute(self) }
2044 }
2045 }
2046 impl From<u8> for Ssom {
2047 #[inline(always)]
2048 fn from(val: u8) -> Ssom {
2049 Ssom::from_bits(val)
2050 }
2051 }
2052 impl From<Ssom> for u8 {
2053 #[inline(always)]
2054 fn from(val: Ssom) -> u8 {
2055 Ssom::to_bits(val)
2056 }
2057 }
2058 #[repr(u8)]
2059 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2060 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2061 pub enum Tcrcini {
2062 #[doc = "All zeros TX CRC initialization pattern"]
2063 ALL_ZEROS = 0x0,
2064 #[doc = "All ones TX CRC initialization pattern"]
2065 ALL_ONES = 0x01,
2066 }
2067 impl Tcrcini {
2068 #[inline(always)]
2069 pub const fn from_bits(val: u8) -> Tcrcini {
2070 unsafe { core::mem::transmute(val & 0x01) }
2071 }
2072 #[inline(always)]
2073 pub const fn to_bits(self) -> u8 {
2074 unsafe { core::mem::transmute(self) }
2075 }
2076 }
2077 impl From<u8> for Tcrcini {
2078 #[inline(always)]
2079 fn from(val: u8) -> Tcrcini {
2080 Tcrcini::from_bits(val)
2081 }
2082 }
2083 impl From<Tcrcini> for u8 {
2084 #[inline(always)]
2085 fn from(val: Tcrcini) -> u8 {
2086 Tcrcini::to_bits(val)
2087 }
2088 }
2089 #[repr(u8)]
2090 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2091 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2092 pub enum Trigpol {
2093 #[doc = "trigger is active on raising edge"]
2094 RISING_EDGE = 0x0,
2095 #[doc = "trigger is active on falling edge"]
2096 FALLING_EDGE = 0x01,
2097 }
2098 impl Trigpol {
2099 #[inline(always)]
2100 pub const fn from_bits(val: u8) -> Trigpol {
2101 unsafe { core::mem::transmute(val & 0x01) }
2102 }
2103 #[inline(always)]
2104 pub const fn to_bits(self) -> u8 {
2105 unsafe { core::mem::transmute(self) }
2106 }
2107 }
2108 impl From<u8> for Trigpol {
2109 #[inline(always)]
2110 fn from(val: u8) -> Trigpol {
2111 Trigpol::from_bits(val)
2112 }
2113 }
2114 impl From<Trigpol> for u8 {
2115 #[inline(always)]
2116 fn from(val: Trigpol) -> u8 {
2117 Trigpol::to_bits(val)
2118 }
2119 }
2120 #[repr(u8)]
2121 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2122 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2123 pub enum Udrcfg {
2124 #[doc = "Slave sends a constant underrun pattern"]
2125 CONSTANT = 0x0,
2126 #[doc = "Slave repeats last received data frame from master"]
2127 REPEAT_RECEIVED = 0x01,
2128 #[doc = "Slave repeats last transmitted data frame"]
2129 REPEAT_TRANSMITTED = 0x02,
2130 _RESERVED_3 = 0x03,
2131 }
2132 impl Udrcfg {
2133 #[inline(always)]
2134 pub const fn from_bits(val: u8) -> Udrcfg {
2135 unsafe { core::mem::transmute(val & 0x03) }
2136 }
2137 #[inline(always)]
2138 pub const fn to_bits(self) -> u8 {
2139 unsafe { core::mem::transmute(self) }
2140 }
2141 }
2142 impl From<u8> for Udrcfg {
2143 #[inline(always)]
2144 fn from(val: u8) -> Udrcfg {
2145 Udrcfg::from_bits(val)
2146 }
2147 }
2148 impl From<Udrcfg> for u8 {
2149 #[inline(always)]
2150 fn from(val: Udrcfg) -> u8 {
2151 Udrcfg::to_bits(val)
2152 }
2153 }
2154}
2155