1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "System configuration controller"]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Syscfg {
9 ptr: *mut u8,
10}
11unsafe impl Send for Syscfg {}
12unsafe impl Sync for Syscfg {}
13impl Syscfg {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "SYSCFG secure configuration register"]
23 #[inline(always)]
24 pub const fn seccfgr(self) -> crate::common::Reg<regs::Seccfgr, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "configuration register 1"]
28 #[inline(always)]
29 pub const fn cfgr1(self) -> crate::common::Reg<regs::Cfgr1, crate::common::RW> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
31 }
32 #[doc = "FPU interrupt mask register"]
33 #[inline(always)]
34 pub const fn fpuimr(self) -> crate::common::Reg<regs::Fpuimr, crate::common::RW> {
35 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
36 }
37 #[doc = "SYSCFG CPU non-secure lock register"]
38 #[inline(always)]
39 pub const fn cnslckr(self) -> crate::common::Reg<regs::Cnslckr, crate::common::RW> {
40 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
41 }
42 #[doc = "SYSCFG CPU secure lock register"]
43 #[inline(always)]
44 pub const fn cslockr(self) -> crate::common::Reg<regs::Cslockr, crate::common::RW> {
45 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
46 }
47 #[doc = "configuration register 2"]
48 #[inline(always)]
49 pub const fn cfgr2(self) -> crate::common::Reg<regs::Cfgr2, crate::common::RW> {
50 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
51 }
52 #[doc = "memory erase status register"]
53 #[inline(always)]
54 pub const fn mesr(self) -> crate::common::Reg<regs::Mesr, crate::common::RW> {
55 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) }
56 }
57 #[doc = "compensation cell control/status register"]
58 #[inline(always)]
59 pub const fn cccsr(self) -> crate::common::Reg<regs::Cccsr, crate::common::RW> {
60 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) }
61 }
62 #[doc = "compensation cell value register"]
63 #[inline(always)]
64 pub const fn ccvr(self) -> crate::common::Reg<regs::Ccvr, crate::common::R> {
65 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
66 }
67 #[doc = "compensation cell code register"]
68 #[inline(always)]
69 pub const fn cccr(self) -> crate::common::Reg<regs::Cccr, crate::common::RW> {
70 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
71 }
72 #[doc = "RSS command register"]
73 #[inline(always)]
74 pub const fn rsscmdr(self) -> crate::common::Reg<regs::Rsscmdr, crate::common::RW> {
75 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
76 }
77 #[doc = "USB Type C and Power Delivery register"]
78 #[inline(always)]
79 pub const fn ucpdr(self) -> crate::common::Reg<regs::Ucpdr, crate::common::RW> {
80 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x70usize) as _) }
81 }
82 #[doc = "OTG_HS PHY register"]
83 #[inline(always)]
84 pub const fn otghsphycr(self) -> crate::common::Reg<regs::Otghsphycr, crate::common::RW> {
85 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x74usize) as _) }
86 }
87 #[doc = "OTG_HS PHY tune register 2"]
88 #[inline(always)]
89 pub const fn otghsphytuner2(self) -> crate::common::Reg<regs::Otghsphytuner2, crate::common::RW> {
90 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x7cusize) as _) }
91 }
92}
93pub mod regs {
94 #[doc = "compensation cell code register"]
95 #[repr(transparent)]
96 #[derive(Copy, Clone, Eq, PartialEq)]
97 pub struct Cccr(pub u32);
98 impl Cccr {
99 #[doc = "NCC1"]
100 #[inline(always)]
101 pub const fn ncc1(&self) -> u8 {
102 let val = (self.0 >> 0usize) & 0x0f;
103 val as u8
104 }
105 #[doc = "NCC1"]
106 #[inline(always)]
107 pub fn set_ncc1(&mut self, val: u8) {
108 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
109 }
110 #[doc = "PCC1"]
111 #[inline(always)]
112 pub const fn pcc1(&self) -> u8 {
113 let val = (self.0 >> 4usize) & 0x0f;
114 val as u8
115 }
116 #[doc = "PCC1"]
117 #[inline(always)]
118 pub fn set_pcc1(&mut self, val: u8) {
119 self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
120 }
121 #[doc = "NCC2"]
122 #[inline(always)]
123 pub const fn ncc2(&self) -> u8 {
124 let val = (self.0 >> 8usize) & 0x0f;
125 val as u8
126 }
127 #[doc = "NCC2"]
128 #[inline(always)]
129 pub fn set_ncc2(&mut self, val: u8) {
130 self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize);
131 }
132 #[doc = "PCC2"]
133 #[inline(always)]
134 pub const fn pcc2(&self) -> u8 {
135 let val = (self.0 >> 12usize) & 0x0f;
136 val as u8
137 }
138 #[doc = "PCC2"]
139 #[inline(always)]
140 pub fn set_pcc2(&mut self, val: u8) {
141 self.0 = (self.0 & !(0x0f << 12usize)) | (((val as u32) & 0x0f) << 12usize);
142 }
143 }
144 impl Default for Cccr {
145 #[inline(always)]
146 fn default() -> Cccr {
147 Cccr(0)
148 }
149 }
150 impl core::fmt::Debug for Cccr {
151 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
152 f.debug_struct("Cccr")
153 .field("ncc1", &self.ncc1())
154 .field("pcc1", &self.pcc1())
155 .field("ncc2", &self.ncc2())
156 .field("pcc2", &self.pcc2())
157 .finish()
158 }
159 }
160 #[cfg(feature = "defmt")]
161 impl defmt::Format for Cccr {
162 fn format(&self, f: defmt::Formatter) {
163 #[derive(defmt :: Format)]
164 struct Cccr {
165 ncc1: u8,
166 pcc1: u8,
167 ncc2: u8,
168 pcc2: u8,
169 }
170 let proxy = Cccr {
171 ncc1: self.ncc1(),
172 pcc1: self.pcc1(),
173 ncc2: self.ncc2(),
174 pcc2: self.pcc2(),
175 };
176 defmt::write!(f, "{}", proxy)
177 }
178 }
179 #[doc = "compensation cell control/status register"]
180 #[repr(transparent)]
181 #[derive(Copy, Clone, Eq, PartialEq)]
182 pub struct Cccsr(pub u32);
183 impl Cccsr {
184 #[doc = "EN1"]
185 #[inline(always)]
186 pub const fn en1(&self) -> bool {
187 let val = (self.0 >> 0usize) & 0x01;
188 val != 0
189 }
190 #[doc = "EN1"]
191 #[inline(always)]
192 pub fn set_en1(&mut self, val: bool) {
193 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
194 }
195 #[doc = "CS1"]
196 #[inline(always)]
197 pub const fn cs1(&self) -> bool {
198 let val = (self.0 >> 1usize) & 0x01;
199 val != 0
200 }
201 #[doc = "CS1"]
202 #[inline(always)]
203 pub fn set_cs1(&mut self, val: bool) {
204 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
205 }
206 #[doc = "EN2"]
207 #[inline(always)]
208 pub const fn en2(&self) -> bool {
209 let val = (self.0 >> 2usize) & 0x01;
210 val != 0
211 }
212 #[doc = "EN2"]
213 #[inline(always)]
214 pub fn set_en2(&mut self, val: bool) {
215 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
216 }
217 #[doc = "CS2"]
218 #[inline(always)]
219 pub const fn cs2(&self) -> bool {
220 let val = (self.0 >> 3usize) & 0x01;
221 val != 0
222 }
223 #[doc = "CS2"]
224 #[inline(always)]
225 pub fn set_cs2(&mut self, val: bool) {
226 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
227 }
228 #[doc = "RDY1"]
229 #[inline(always)]
230 pub const fn rdy1(&self) -> bool {
231 let val = (self.0 >> 8usize) & 0x01;
232 val != 0
233 }
234 #[doc = "RDY1"]
235 #[inline(always)]
236 pub fn set_rdy1(&mut self, val: bool) {
237 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
238 }
239 #[doc = "RDY2"]
240 #[inline(always)]
241 pub const fn rdy2(&self) -> bool {
242 let val = (self.0 >> 9usize) & 0x01;
243 val != 0
244 }
245 #[doc = "RDY2"]
246 #[inline(always)]
247 pub fn set_rdy2(&mut self, val: bool) {
248 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
249 }
250 }
251 impl Default for Cccsr {
252 #[inline(always)]
253 fn default() -> Cccsr {
254 Cccsr(0)
255 }
256 }
257 impl core::fmt::Debug for Cccsr {
258 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
259 f.debug_struct("Cccsr")
260 .field("en1", &self.en1())
261 .field("cs1", &self.cs1())
262 .field("en2", &self.en2())
263 .field("cs2", &self.cs2())
264 .field("rdy1", &self.rdy1())
265 .field("rdy2", &self.rdy2())
266 .finish()
267 }
268 }
269 #[cfg(feature = "defmt")]
270 impl defmt::Format for Cccsr {
271 fn format(&self, f: defmt::Formatter) {
272 #[derive(defmt :: Format)]
273 struct Cccsr {
274 en1: bool,
275 cs1: bool,
276 en2: bool,
277 cs2: bool,
278 rdy1: bool,
279 rdy2: bool,
280 }
281 let proxy = Cccsr {
282 en1: self.en1(),
283 cs1: self.cs1(),
284 en2: self.en2(),
285 cs2: self.cs2(),
286 rdy1: self.rdy1(),
287 rdy2: self.rdy2(),
288 };
289 defmt::write!(f, "{}", proxy)
290 }
291 }
292 #[doc = "compensation cell value register"]
293 #[repr(transparent)]
294 #[derive(Copy, Clone, Eq, PartialEq)]
295 pub struct Ccvr(pub u32);
296 impl Ccvr {
297 #[doc = "NCV1"]
298 #[inline(always)]
299 pub const fn ncv1(&self) -> u8 {
300 let val = (self.0 >> 0usize) & 0x0f;
301 val as u8
302 }
303 #[doc = "NCV1"]
304 #[inline(always)]
305 pub fn set_ncv1(&mut self, val: u8) {
306 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
307 }
308 #[doc = "PCV1"]
309 #[inline(always)]
310 pub const fn pcv1(&self) -> u8 {
311 let val = (self.0 >> 4usize) & 0x0f;
312 val as u8
313 }
314 #[doc = "PCV1"]
315 #[inline(always)]
316 pub fn set_pcv1(&mut self, val: u8) {
317 self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
318 }
319 #[doc = "NCV2"]
320 #[inline(always)]
321 pub const fn ncv2(&self) -> u8 {
322 let val = (self.0 >> 8usize) & 0x0f;
323 val as u8
324 }
325 #[doc = "NCV2"]
326 #[inline(always)]
327 pub fn set_ncv2(&mut self, val: u8) {
328 self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize);
329 }
330 #[doc = "PCV2"]
331 #[inline(always)]
332 pub const fn pcv2(&self) -> u8 {
333 let val = (self.0 >> 12usize) & 0x0f;
334 val as u8
335 }
336 #[doc = "PCV2"]
337 #[inline(always)]
338 pub fn set_pcv2(&mut self, val: u8) {
339 self.0 = (self.0 & !(0x0f << 12usize)) | (((val as u32) & 0x0f) << 12usize);
340 }
341 }
342 impl Default for Ccvr {
343 #[inline(always)]
344 fn default() -> Ccvr {
345 Ccvr(0)
346 }
347 }
348 impl core::fmt::Debug for Ccvr {
349 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
350 f.debug_struct("Ccvr")
351 .field("ncv1", &self.ncv1())
352 .field("pcv1", &self.pcv1())
353 .field("ncv2", &self.ncv2())
354 .field("pcv2", &self.pcv2())
355 .finish()
356 }
357 }
358 #[cfg(feature = "defmt")]
359 impl defmt::Format for Ccvr {
360 fn format(&self, f: defmt::Formatter) {
361 #[derive(defmt :: Format)]
362 struct Ccvr {
363 ncv1: u8,
364 pcv1: u8,
365 ncv2: u8,
366 pcv2: u8,
367 }
368 let proxy = Ccvr {
369 ncv1: self.ncv1(),
370 pcv1: self.pcv1(),
371 ncv2: self.ncv2(),
372 pcv2: self.pcv2(),
373 };
374 defmt::write!(f, "{}", proxy)
375 }
376 }
377 #[doc = "configuration register 1"]
378 #[repr(transparent)]
379 #[derive(Copy, Clone, Eq, PartialEq)]
380 pub struct Cfgr1(pub u32);
381 impl Cfgr1 {
382 #[doc = "I/O analog switch voltage booster enable"]
383 #[inline(always)]
384 pub const fn boosten(&self) -> bool {
385 let val = (self.0 >> 8usize) & 0x01;
386 val != 0
387 }
388 #[doc = "I/O analog switch voltage booster enable"]
389 #[inline(always)]
390 pub fn set_boosten(&mut self, val: bool) {
391 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
392 }
393 #[doc = "GPIO analog switch control voltage selection"]
394 #[inline(always)]
395 pub const fn anaswvdd(&self) -> bool {
396 let val = (self.0 >> 9usize) & 0x01;
397 val != 0
398 }
399 #[doc = "GPIO analog switch control voltage selection"]
400 #[inline(always)]
401 pub fn set_anaswvdd(&mut self, val: bool) {
402 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
403 }
404 #[doc = "PB6_FMP"]
405 #[inline(always)]
406 pub const fn pb6_fmp(&self) -> bool {
407 let val = (self.0 >> 16usize) & 0x01;
408 val != 0
409 }
410 #[doc = "PB6_FMP"]
411 #[inline(always)]
412 pub fn set_pb6_fmp(&mut self, val: bool) {
413 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
414 }
415 #[doc = "PB7_FMP"]
416 #[inline(always)]
417 pub const fn pb7_fmp(&self) -> bool {
418 let val = (self.0 >> 17usize) & 0x01;
419 val != 0
420 }
421 #[doc = "PB7_FMP"]
422 #[inline(always)]
423 pub fn set_pb7_fmp(&mut self, val: bool) {
424 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
425 }
426 #[doc = "PB8_FMP"]
427 #[inline(always)]
428 pub const fn pb8_fmp(&self) -> bool {
429 let val = (self.0 >> 18usize) & 0x01;
430 val != 0
431 }
432 #[doc = "PB8_FMP"]
433 #[inline(always)]
434 pub fn set_pb8_fmp(&mut self, val: bool) {
435 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
436 }
437 #[doc = "PB9_FMP"]
438 #[inline(always)]
439 pub const fn pb9_fmp(&self) -> bool {
440 let val = (self.0 >> 19usize) & 0x01;
441 val != 0
442 }
443 #[doc = "PB9_FMP"]
444 #[inline(always)]
445 pub fn set_pb9_fmp(&mut self, val: bool) {
446 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
447 }
448 }
449 impl Default for Cfgr1 {
450 #[inline(always)]
451 fn default() -> Cfgr1 {
452 Cfgr1(0)
453 }
454 }
455 impl core::fmt::Debug for Cfgr1 {
456 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
457 f.debug_struct("Cfgr1")
458 .field("boosten", &self.boosten())
459 .field("anaswvdd", &self.anaswvdd())
460 .field("pb6_fmp", &self.pb6_fmp())
461 .field("pb7_fmp", &self.pb7_fmp())
462 .field("pb8_fmp", &self.pb8_fmp())
463 .field("pb9_fmp", &self.pb9_fmp())
464 .finish()
465 }
466 }
467 #[cfg(feature = "defmt")]
468 impl defmt::Format for Cfgr1 {
469 fn format(&self, f: defmt::Formatter) {
470 #[derive(defmt :: Format)]
471 struct Cfgr1 {
472 boosten: bool,
473 anaswvdd: bool,
474 pb6_fmp: bool,
475 pb7_fmp: bool,
476 pb8_fmp: bool,
477 pb9_fmp: bool,
478 }
479 let proxy = Cfgr1 {
480 boosten: self.boosten(),
481 anaswvdd: self.anaswvdd(),
482 pb6_fmp: self.pb6_fmp(),
483 pb7_fmp: self.pb7_fmp(),
484 pb8_fmp: self.pb8_fmp(),
485 pb9_fmp: self.pb9_fmp(),
486 };
487 defmt::write!(f, "{}", proxy)
488 }
489 }
490 #[doc = "configuration register 2"]
491 #[repr(transparent)]
492 #[derive(Copy, Clone, Eq, PartialEq)]
493 pub struct Cfgr2(pub u32);
494 impl Cfgr2 {
495 #[doc = "LOCKUP (hardfault) output enable bit"]
496 #[inline(always)]
497 pub const fn cll(&self) -> bool {
498 let val = (self.0 >> 0usize) & 0x01;
499 val != 0
500 }
501 #[doc = "LOCKUP (hardfault) output enable bit"]
502 #[inline(always)]
503 pub fn set_cll(&mut self, val: bool) {
504 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
505 }
506 #[doc = "SRAM ECC lock bit"]
507 #[inline(always)]
508 pub const fn spl(&self) -> bool {
509 let val = (self.0 >> 1usize) & 0x01;
510 val != 0
511 }
512 #[doc = "SRAM ECC lock bit"]
513 #[inline(always)]
514 pub fn set_spl(&mut self, val: bool) {
515 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
516 }
517 #[doc = "PVD lock enable bit"]
518 #[inline(always)]
519 pub const fn pvdl(&self) -> bool {
520 let val = (self.0 >> 2usize) & 0x01;
521 val != 0
522 }
523 #[doc = "PVD lock enable bit"]
524 #[inline(always)]
525 pub fn set_pvdl(&mut self, val: bool) {
526 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
527 }
528 #[doc = "ECC Lock"]
529 #[inline(always)]
530 pub const fn eccl(&self) -> bool {
531 let val = (self.0 >> 3usize) & 0x01;
532 val != 0
533 }
534 #[doc = "ECC Lock"]
535 #[inline(always)]
536 pub fn set_eccl(&mut self, val: bool) {
537 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
538 }
539 }
540 impl Default for Cfgr2 {
541 #[inline(always)]
542 fn default() -> Cfgr2 {
543 Cfgr2(0)
544 }
545 }
546 impl core::fmt::Debug for Cfgr2 {
547 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
548 f.debug_struct("Cfgr2")
549 .field("cll", &self.cll())
550 .field("spl", &self.spl())
551 .field("pvdl", &self.pvdl())
552 .field("eccl", &self.eccl())
553 .finish()
554 }
555 }
556 #[cfg(feature = "defmt")]
557 impl defmt::Format for Cfgr2 {
558 fn format(&self, f: defmt::Formatter) {
559 #[derive(defmt :: Format)]
560 struct Cfgr2 {
561 cll: bool,
562 spl: bool,
563 pvdl: bool,
564 eccl: bool,
565 }
566 let proxy = Cfgr2 {
567 cll: self.cll(),
568 spl: self.spl(),
569 pvdl: self.pvdl(),
570 eccl: self.eccl(),
571 };
572 defmt::write!(f, "{}", proxy)
573 }
574 }
575 #[doc = "SYSCFG CPU non-secure lock register"]
576 #[repr(transparent)]
577 #[derive(Copy, Clone, Eq, PartialEq)]
578 pub struct Cnslckr(pub u32);
579 impl Cnslckr {
580 #[doc = "VTOR_NS register lock"]
581 #[inline(always)]
582 pub const fn locknsvtor(&self) -> bool {
583 let val = (self.0 >> 0usize) & 0x01;
584 val != 0
585 }
586 #[doc = "VTOR_NS register lock"]
587 #[inline(always)]
588 pub fn set_locknsvtor(&mut self, val: bool) {
589 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
590 }
591 #[doc = "Non-secure MPU registers lock"]
592 #[inline(always)]
593 pub const fn locknsmpu(&self) -> bool {
594 let val = (self.0 >> 1usize) & 0x01;
595 val != 0
596 }
597 #[doc = "Non-secure MPU registers lock"]
598 #[inline(always)]
599 pub fn set_locknsmpu(&mut self, val: bool) {
600 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
601 }
602 }
603 impl Default for Cnslckr {
604 #[inline(always)]
605 fn default() -> Cnslckr {
606 Cnslckr(0)
607 }
608 }
609 impl core::fmt::Debug for Cnslckr {
610 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
611 f.debug_struct("Cnslckr")
612 .field("locknsvtor", &self.locknsvtor())
613 .field("locknsmpu", &self.locknsmpu())
614 .finish()
615 }
616 }
617 #[cfg(feature = "defmt")]
618 impl defmt::Format for Cnslckr {
619 fn format(&self, f: defmt::Formatter) {
620 #[derive(defmt :: Format)]
621 struct Cnslckr {
622 locknsvtor: bool,
623 locknsmpu: bool,
624 }
625 let proxy = Cnslckr {
626 locknsvtor: self.locknsvtor(),
627 locknsmpu: self.locknsmpu(),
628 };
629 defmt::write!(f, "{}", proxy)
630 }
631 }
632 #[doc = "SYSCFG CPU secure lock register"]
633 #[repr(transparent)]
634 #[derive(Copy, Clone, Eq, PartialEq)]
635 pub struct Cslockr(pub u32);
636 impl Cslockr {
637 #[doc = "LOCKSVTAIRCR"]
638 #[inline(always)]
639 pub const fn locksvtaircr(&self) -> bool {
640 let val = (self.0 >> 0usize) & 0x01;
641 val != 0
642 }
643 #[doc = "LOCKSVTAIRCR"]
644 #[inline(always)]
645 pub fn set_locksvtaircr(&mut self, val: bool) {
646 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
647 }
648 #[doc = "LOCKSMPU"]
649 #[inline(always)]
650 pub const fn locksmpu(&self) -> bool {
651 let val = (self.0 >> 1usize) & 0x01;
652 val != 0
653 }
654 #[doc = "LOCKSMPU"]
655 #[inline(always)]
656 pub fn set_locksmpu(&mut self, val: bool) {
657 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
658 }
659 #[doc = "LOCKSAU"]
660 #[inline(always)]
661 pub const fn locksau(&self) -> bool {
662 let val = (self.0 >> 2usize) & 0x01;
663 val != 0
664 }
665 #[doc = "LOCKSAU"]
666 #[inline(always)]
667 pub fn set_locksau(&mut self, val: bool) {
668 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
669 }
670 }
671 impl Default for Cslockr {
672 #[inline(always)]
673 fn default() -> Cslockr {
674 Cslockr(0)
675 }
676 }
677 impl core::fmt::Debug for Cslockr {
678 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
679 f.debug_struct("Cslockr")
680 .field("locksvtaircr", &self.locksvtaircr())
681 .field("locksmpu", &self.locksmpu())
682 .field("locksau", &self.locksau())
683 .finish()
684 }
685 }
686 #[cfg(feature = "defmt")]
687 impl defmt::Format for Cslockr {
688 fn format(&self, f: defmt::Formatter) {
689 #[derive(defmt :: Format)]
690 struct Cslockr {
691 locksvtaircr: bool,
692 locksmpu: bool,
693 locksau: bool,
694 }
695 let proxy = Cslockr {
696 locksvtaircr: self.locksvtaircr(),
697 locksmpu: self.locksmpu(),
698 locksau: self.locksau(),
699 };
700 defmt::write!(f, "{}", proxy)
701 }
702 }
703 #[doc = "FPU interrupt mask register"]
704 #[repr(transparent)]
705 #[derive(Copy, Clone, Eq, PartialEq)]
706 pub struct Fpuimr(pub u32);
707 impl Fpuimr {
708 #[doc = "Floating point unit interrupts enable bits"]
709 #[inline(always)]
710 pub const fn fpu_ie(&self) -> u8 {
711 let val = (self.0 >> 0usize) & 0x3f;
712 val as u8
713 }
714 #[doc = "Floating point unit interrupts enable bits"]
715 #[inline(always)]
716 pub fn set_fpu_ie(&mut self, val: u8) {
717 self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
718 }
719 }
720 impl Default for Fpuimr {
721 #[inline(always)]
722 fn default() -> Fpuimr {
723 Fpuimr(0)
724 }
725 }
726 impl core::fmt::Debug for Fpuimr {
727 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
728 f.debug_struct("Fpuimr").field("fpu_ie", &self.fpu_ie()).finish()
729 }
730 }
731 #[cfg(feature = "defmt")]
732 impl defmt::Format for Fpuimr {
733 fn format(&self, f: defmt::Formatter) {
734 #[derive(defmt :: Format)]
735 struct Fpuimr {
736 fpu_ie: u8,
737 }
738 let proxy = Fpuimr { fpu_ie: self.fpu_ie() };
739 defmt::write!(f, "{}", proxy)
740 }
741 }
742 #[doc = "memory erase status register"]
743 #[repr(transparent)]
744 #[derive(Copy, Clone, Eq, PartialEq)]
745 pub struct Mesr(pub u32);
746 impl Mesr {
747 #[doc = "MCLR"]
748 #[inline(always)]
749 pub const fn mclr(&self) -> bool {
750 let val = (self.0 >> 0usize) & 0x01;
751 val != 0
752 }
753 #[doc = "MCLR"]
754 #[inline(always)]
755 pub fn set_mclr(&mut self, val: bool) {
756 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
757 }
758 #[doc = "IPMEE"]
759 #[inline(always)]
760 pub const fn ipmee(&self) -> bool {
761 let val = (self.0 >> 16usize) & 0x01;
762 val != 0
763 }
764 #[doc = "IPMEE"]
765 #[inline(always)]
766 pub fn set_ipmee(&mut self, val: bool) {
767 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
768 }
769 }
770 impl Default for Mesr {
771 #[inline(always)]
772 fn default() -> Mesr {
773 Mesr(0)
774 }
775 }
776 impl core::fmt::Debug for Mesr {
777 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
778 f.debug_struct("Mesr")
779 .field("mclr", &self.mclr())
780 .field("ipmee", &self.ipmee())
781 .finish()
782 }
783 }
784 #[cfg(feature = "defmt")]
785 impl defmt::Format for Mesr {
786 fn format(&self, f: defmt::Formatter) {
787 #[derive(defmt :: Format)]
788 struct Mesr {
789 mclr: bool,
790 ipmee: bool,
791 }
792 let proxy = Mesr {
793 mclr: self.mclr(),
794 ipmee: self.ipmee(),
795 };
796 defmt::write!(f, "{}", proxy)
797 }
798 }
799 #[doc = "OTG_HS PHY register"]
800 #[repr(transparent)]
801 #[derive(Copy, Clone, Eq, PartialEq)]
802 pub struct Otghsphycr(pub u32);
803 impl Otghsphycr {
804 #[doc = "PHY Enable"]
805 #[inline(always)]
806 pub const fn en(&self) -> bool {
807 let val = (self.0 >> 0usize) & 0x01;
808 val != 0
809 }
810 #[doc = "PHY Enable"]
811 #[inline(always)]
812 pub fn set_en(&mut self, val: bool) {
813 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
814 }
815 #[doc = "Common block power-down control"]
816 #[inline(always)]
817 pub const fn pdctrl(&self) -> bool {
818 let val = (self.0 >> 1usize) & 0x01;
819 val != 0
820 }
821 #[doc = "Common block power-down control"]
822 #[inline(always)]
823 pub fn set_pdctrl(&mut self, val: bool) {
824 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
825 }
826 #[doc = "Reference clock frequency selection"]
827 #[inline(always)]
828 pub const fn clksel(&self) -> super::vals::Usbrefcksel {
829 let val = (self.0 >> 2usize) & 0x0f;
830 super::vals::Usbrefcksel::from_bits(val as u8)
831 }
832 #[doc = "Reference clock frequency selection"]
833 #[inline(always)]
834 pub fn set_clksel(&mut self, val: super::vals::Usbrefcksel) {
835 self.0 = (self.0 & !(0x0f << 2usize)) | (((val.to_bits() as u32) & 0x0f) << 2usize);
836 }
837 }
838 impl Default for Otghsphycr {
839 #[inline(always)]
840 fn default() -> Otghsphycr {
841 Otghsphycr(0)
842 }
843 }
844 impl core::fmt::Debug for Otghsphycr {
845 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
846 f.debug_struct("Otghsphycr")
847 .field("en", &self.en())
848 .field("pdctrl", &self.pdctrl())
849 .field("clksel", &self.clksel())
850 .finish()
851 }
852 }
853 #[cfg(feature = "defmt")]
854 impl defmt::Format for Otghsphycr {
855 fn format(&self, f: defmt::Formatter) {
856 #[derive(defmt :: Format)]
857 struct Otghsphycr {
858 en: bool,
859 pdctrl: bool,
860 clksel: super::vals::Usbrefcksel,
861 }
862 let proxy = Otghsphycr {
863 en: self.en(),
864 pdctrl: self.pdctrl(),
865 clksel: self.clksel(),
866 };
867 defmt::write!(f, "{}", proxy)
868 }
869 }
870 #[doc = "OTG_HS tune register 2"]
871 #[repr(transparent)]
872 #[derive(Copy, Clone, Eq, PartialEq)]
873 pub struct Otghsphytuner2(pub u32);
874 impl Otghsphytuner2 {
875 #[doc = "Disconnect threshold adjustment"]
876 #[inline(always)]
877 pub const fn compdistune(&self) -> u8 {
878 let val = (self.0 >> 0usize) & 0x07;
879 val as u8
880 }
881 #[doc = "Disconnect threshold adjustment"]
882 #[inline(always)]
883 pub fn set_compdistune(&mut self, val: u8) {
884 self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
885 }
886 #[doc = "Squelch threshold adjustment"]
887 #[inline(always)]
888 pub const fn sqrxtune(&self) -> u8 {
889 let val = (self.0 >> 4usize) & 0x07;
890 val as u8
891 }
892 #[doc = "Squelch threshold adjustment"]
893 #[inline(always)]
894 pub fn set_sqrxtune(&mut self, val: u8) {
895 self.0 = (self.0 & !(0x07 << 4usize)) | (((val as u32) & 0x07) << 4usize);
896 }
897 #[doc = "HS transmitter preemphasis current control"]
898 #[inline(always)]
899 pub const fn txpreempamptune(&self) -> u8 {
900 let val = (self.0 >> 13usize) & 0x03;
901 val as u8
902 }
903 #[doc = "HS transmitter preemphasis current control"]
904 #[inline(always)]
905 pub fn set_txpreempamptune(&mut self, val: u8) {
906 self.0 = (self.0 & !(0x03 << 13usize)) | (((val as u32) & 0x03) << 13usize);
907 }
908 }
909 impl Default for Otghsphytuner2 {
910 #[inline(always)]
911 fn default() -> Otghsphytuner2 {
912 Otghsphytuner2(0)
913 }
914 }
915 impl core::fmt::Debug for Otghsphytuner2 {
916 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
917 f.debug_struct("Otghsphytuner2")
918 .field("compdistune", &self.compdistune())
919 .field("sqrxtune", &self.sqrxtune())
920 .field("txpreempamptune", &self.txpreempamptune())
921 .finish()
922 }
923 }
924 #[cfg(feature = "defmt")]
925 impl defmt::Format for Otghsphytuner2 {
926 fn format(&self, f: defmt::Formatter) {
927 #[derive(defmt :: Format)]
928 struct Otghsphytuner2 {
929 compdistune: u8,
930 sqrxtune: u8,
931 txpreempamptune: u8,
932 }
933 let proxy = Otghsphytuner2 {
934 compdistune: self.compdistune(),
935 sqrxtune: self.sqrxtune(),
936 txpreempamptune: self.txpreempamptune(),
937 };
938 defmt::write!(f, "{}", proxy)
939 }
940 }
941 #[doc = "RSS command register"]
942 #[repr(transparent)]
943 #[derive(Copy, Clone, Eq, PartialEq)]
944 pub struct Rsscmdr(pub u32);
945 impl Rsscmdr {
946 #[doc = "RSS commands"]
947 #[inline(always)]
948 pub const fn rsscmd(&self) -> u16 {
949 let val = (self.0 >> 0usize) & 0xffff;
950 val as u16
951 }
952 #[doc = "RSS commands"]
953 #[inline(always)]
954 pub fn set_rsscmd(&mut self, val: u16) {
955 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
956 }
957 }
958 impl Default for Rsscmdr {
959 #[inline(always)]
960 fn default() -> Rsscmdr {
961 Rsscmdr(0)
962 }
963 }
964 impl core::fmt::Debug for Rsscmdr {
965 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
966 f.debug_struct("Rsscmdr").field("rsscmd", &self.rsscmd()).finish()
967 }
968 }
969 #[cfg(feature = "defmt")]
970 impl defmt::Format for Rsscmdr {
971 fn format(&self, f: defmt::Formatter) {
972 #[derive(defmt :: Format)]
973 struct Rsscmdr {
974 rsscmd: u16,
975 }
976 let proxy = Rsscmdr { rsscmd: self.rsscmd() };
977 defmt::write!(f, "{}", proxy)
978 }
979 }
980 #[doc = "SYSCFG secure configuration register"]
981 #[repr(transparent)]
982 #[derive(Copy, Clone, Eq, PartialEq)]
983 pub struct Seccfgr(pub u32);
984 impl Seccfgr {
985 #[doc = "SYSCFG clock control security"]
986 #[inline(always)]
987 pub const fn syscfgsec(&self) -> bool {
988 let val = (self.0 >> 0usize) & 0x01;
989 val != 0
990 }
991 #[doc = "SYSCFG clock control security"]
992 #[inline(always)]
993 pub fn set_syscfgsec(&mut self, val: bool) {
994 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
995 }
996 #[doc = "CLASSBSEC"]
997 #[inline(always)]
998 pub const fn classbsec(&self) -> bool {
999 let val = (self.0 >> 1usize) & 0x01;
1000 val != 0
1001 }
1002 #[doc = "CLASSBSEC"]
1003 #[inline(always)]
1004 pub fn set_classbsec(&mut self, val: bool) {
1005 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1006 }
1007 #[doc = "FPUSEC"]
1008 #[inline(always)]
1009 pub const fn fpusec(&self) -> bool {
1010 let val = (self.0 >> 3usize) & 0x01;
1011 val != 0
1012 }
1013 #[doc = "FPUSEC"]
1014 #[inline(always)]
1015 pub fn set_fpusec(&mut self, val: bool) {
1016 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1017 }
1018 }
1019 impl Default for Seccfgr {
1020 #[inline(always)]
1021 fn default() -> Seccfgr {
1022 Seccfgr(0)
1023 }
1024 }
1025 impl core::fmt::Debug for Seccfgr {
1026 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1027 f.debug_struct("Seccfgr")
1028 .field("syscfgsec", &self.syscfgsec())
1029 .field("classbsec", &self.classbsec())
1030 .field("fpusec", &self.fpusec())
1031 .finish()
1032 }
1033 }
1034 #[cfg(feature = "defmt")]
1035 impl defmt::Format for Seccfgr {
1036 fn format(&self, f: defmt::Formatter) {
1037 #[derive(defmt :: Format)]
1038 struct Seccfgr {
1039 syscfgsec: bool,
1040 classbsec: bool,
1041 fpusec: bool,
1042 }
1043 let proxy = Seccfgr {
1044 syscfgsec: self.syscfgsec(),
1045 classbsec: self.classbsec(),
1046 fpusec: self.fpusec(),
1047 };
1048 defmt::write!(f, "{}", proxy)
1049 }
1050 }
1051 #[doc = "USB Type C and Power Delivery register"]
1052 #[repr(transparent)]
1053 #[derive(Copy, Clone, Eq, PartialEq)]
1054 pub struct Ucpdr(pub u32);
1055 impl Ucpdr {
1056 #[doc = "CC1ENRXFILTER"]
1057 #[inline(always)]
1058 pub const fn cc1enrxfilter(&self) -> bool {
1059 let val = (self.0 >> 0usize) & 0x01;
1060 val != 0
1061 }
1062 #[doc = "CC1ENRXFILTER"]
1063 #[inline(always)]
1064 pub fn set_cc1enrxfilter(&mut self, val: bool) {
1065 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1066 }
1067 #[doc = "CC2ENRXFILTER"]
1068 #[inline(always)]
1069 pub const fn cc2enrxfilter(&self) -> bool {
1070 let val = (self.0 >> 1usize) & 0x01;
1071 val != 0
1072 }
1073 #[doc = "CC2ENRXFILTER"]
1074 #[inline(always)]
1075 pub fn set_cc2enrxfilter(&mut self, val: bool) {
1076 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1077 }
1078 }
1079 impl Default for Ucpdr {
1080 #[inline(always)]
1081 fn default() -> Ucpdr {
1082 Ucpdr(0)
1083 }
1084 }
1085 impl core::fmt::Debug for Ucpdr {
1086 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1087 f.debug_struct("Ucpdr")
1088 .field("cc1enrxfilter", &self.cc1enrxfilter())
1089 .field("cc2enrxfilter", &self.cc2enrxfilter())
1090 .finish()
1091 }
1092 }
1093 #[cfg(feature = "defmt")]
1094 impl defmt::Format for Ucpdr {
1095 fn format(&self, f: defmt::Formatter) {
1096 #[derive(defmt :: Format)]
1097 struct Ucpdr {
1098 cc1enrxfilter: bool,
1099 cc2enrxfilter: bool,
1100 }
1101 let proxy = Ucpdr {
1102 cc1enrxfilter: self.cc1enrxfilter(),
1103 cc2enrxfilter: self.cc2enrxfilter(),
1104 };
1105 defmt::write!(f, "{}", proxy)
1106 }
1107 }
1108}
1109pub mod vals {
1110 #[repr(u8)]
1111 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1112 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1113 pub enum Usbrefcksel {
1114 _RESERVED_0 = 0x0,
1115 _RESERVED_1 = 0x01,
1116 _RESERVED_2 = 0x02,
1117 #[doc = "The kernel clock frequency provided to the OTG_HS PHY is 16 MHz."]
1118 MHZ16 = 0x03,
1119 _RESERVED_4 = 0x04,
1120 _RESERVED_5 = 0x05,
1121 _RESERVED_6 = 0x06,
1122 _RESERVED_7 = 0x07,
1123 #[doc = "The kernel clock frequency provided to the OTG_HS PHY is 19.2 MHz."]
1124 MHZ19_2 = 0x08,
1125 #[doc = "The kernel clock frequency provided to the OTG_HS PHY is 20MHz."]
1126 MHZ20 = 0x09,
1127 #[doc = "The kernel clock frequency provided to the OTG_HS PHY is 24 MHz (default after reset)."]
1128 MHZ24 = 0x0a,
1129 #[doc = "The kernel clock frequency provided to the OTG_HS PHY is 32 MHz."]
1130 MHZ32 = 0x0b,
1131 _RESERVED_c = 0x0c,
1132 _RESERVED_d = 0x0d,
1133 #[doc = "The kernel clock frequency provided to the OTG_HS PHY is 26 MHz."]
1134 MHZ26 = 0x0e,
1135 _RESERVED_f = 0x0f,
1136 }
1137 impl Usbrefcksel {
1138 #[inline(always)]
1139 pub const fn from_bits(val: u8) -> Usbrefcksel {
1140 unsafe { core::mem::transmute(val & 0x0f) }
1141 }
1142 #[inline(always)]
1143 pub const fn to_bits(self) -> u8 {
1144 unsafe { core::mem::transmute(self) }
1145 }
1146 }
1147 impl From<u8> for Usbrefcksel {
1148 #[inline(always)]
1149 fn from(val: u8) -> Usbrefcksel {
1150 Usbrefcksel::from_bits(val)
1151 }
1152 }
1153 impl From<Usbrefcksel> for u8 {
1154 #[inline(always)]
1155 fn from(val: Usbrefcksel) -> u8 {
1156 Usbrefcksel::to_bits(val)
1157 }
1158 }
1159}
1160