1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "1-channel timers"]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Tim1ch {
9 ptr: *mut u8,
10}
11unsafe impl Send for Tim1ch {}
12unsafe impl Sync for Tim1ch {}
13impl Tim1ch {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "control register 1"]
23 #[inline(always)]
24 pub const fn cr1(self) -> crate::common::Reg<regs::Cr11ch, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "DMA/Interrupt enable register"]
28 #[inline(always)]
29 pub const fn dier(self) -> crate::common::Reg<regs::Dier1ch, crate::common::RW> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
31 }
32 #[doc = "status register"]
33 #[inline(always)]
34 pub const fn sr(self) -> crate::common::Reg<regs::Sr1ch, crate::common::RW> {
35 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
36 }
37 #[doc = "event generation register"]
38 #[inline(always)]
39 pub const fn egr(self) -> crate::common::Reg<regs::Egr1ch, crate::common::W> {
40 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
41 }
42 #[doc = "capture/compare mode register 1 (input mode)"]
43 #[inline(always)]
44 pub const fn ccmr_input(self, n: usize) -> crate::common::Reg<regs::CcmrInput1ch, crate::common::RW> {
45 assert!(n < 1usize);
46 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize + n * 4usize) as _) }
47 }
48 #[doc = "capture/compare mode register 1 (output mode)"]
49 #[inline(always)]
50 pub const fn ccmr_output(self, n: usize) -> crate::common::Reg<regs::CcmrOutput1ch, crate::common::RW> {
51 assert!(n < 1usize);
52 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize + n * 4usize) as _) }
53 }
54 #[doc = "capture/compare enable register"]
55 #[inline(always)]
56 pub const fn ccer(self) -> crate::common::Reg<regs::Ccer1ch, crate::common::RW> {
57 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
58 }
59 #[doc = "counter"]
60 #[inline(always)]
61 pub const fn cnt(self) -> crate::common::Reg<regs::CntCore, crate::common::RW> {
62 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
63 }
64 #[doc = "prescaler"]
65 #[inline(always)]
66 pub const fn psc(self) -> crate::common::Reg<u16, crate::common::RW> {
67 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
68 }
69 #[doc = "auto-reload register (Dither mode disabled)"]
70 #[inline(always)]
71 pub const fn arr(self) -> crate::common::Reg<regs::ArrCore, crate::common::RW> {
72 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
73 }
74 #[doc = "auto-reload register (Dither mode enabled)"]
75 #[inline(always)]
76 pub const fn arr_dither(self) -> crate::common::Reg<regs::ArrDitherCore, crate::common::RW> {
77 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
78 }
79 #[doc = "capture/compare register x (x=1) (Dither mode disabled)"]
80 #[inline(always)]
81 pub const fn ccr(self, n: usize) -> crate::common::Reg<regs::Ccr1ch, crate::common::RW> {
82 assert!(n < 1usize);
83 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize + n * 4usize) as _) }
84 }
85 #[doc = "capture/compare register x (x=1) (Dither mode enabled)"]
86 #[inline(always)]
87 pub const fn ccr_dither(self, n: usize) -> crate::common::Reg<regs::CcrDither1ch, crate::common::RW> {
88 assert!(n < 1usize);
89 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize + n * 4usize) as _) }
90 }
91 #[doc = "input selection register"]
92 #[inline(always)]
93 pub const fn tisel(self) -> crate::common::Reg<regs::Tisel1ch, crate::common::RW> {
94 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) }
95 }
96 #[doc = "Option register 1 Note: Check Reference Manual to parse this register content"]
97 #[inline(always)]
98 pub const fn or(self) -> crate::common::Reg<u32, crate::common::RW> {
99 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x68usize) as _) }
100 }
101}
102#[doc = "1-channel with one complementary output timers"]
103#[derive(Copy, Clone, Eq, PartialEq)]
104pub struct Tim1chCmp {
105 ptr: *mut u8,
106}
107unsafe impl Send for Tim1chCmp {}
108unsafe impl Sync for Tim1chCmp {}
109impl Tim1chCmp {
110 #[inline(always)]
111 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
112 Self { ptr: ptr as _ }
113 }
114 #[inline(always)]
115 pub const fn as_ptr(&self) -> *mut () {
116 self.ptr as _
117 }
118 #[doc = "control register 1"]
119 #[inline(always)]
120 pub const fn cr1(self) -> crate::common::Reg<regs::Cr11ch, crate::common::RW> {
121 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
122 }
123 #[doc = "control register 2"]
124 #[inline(always)]
125 pub const fn cr2(self) -> crate::common::Reg<regs::Cr21chCmp, crate::common::RW> {
126 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
127 }
128 #[doc = "DMA/Interrupt enable register"]
129 #[inline(always)]
130 pub const fn dier(self) -> crate::common::Reg<regs::Dier1chCmp, crate::common::RW> {
131 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
132 }
133 #[doc = "status register"]
134 #[inline(always)]
135 pub const fn sr(self) -> crate::common::Reg<regs::Sr1chCmp, crate::common::RW> {
136 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
137 }
138 #[doc = "event generation register"]
139 #[inline(always)]
140 pub const fn egr(self) -> crate::common::Reg<regs::Egr1chCmp, crate::common::W> {
141 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
142 }
143 #[doc = "capture/compare mode register 1 (input mode)"]
144 #[inline(always)]
145 pub const fn ccmr_input(self, n: usize) -> crate::common::Reg<regs::CcmrInput1ch, crate::common::RW> {
146 assert!(n < 1usize);
147 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize + n * 4usize) as _) }
148 }
149 #[doc = "capture/compare mode register 1 (output mode)"]
150 #[inline(always)]
151 pub const fn ccmr_output(self, n: usize) -> crate::common::Reg<regs::CcmrOutput1ch, crate::common::RW> {
152 assert!(n < 1usize);
153 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize + n * 4usize) as _) }
154 }
155 #[doc = "capture/compare enable register"]
156 #[inline(always)]
157 pub const fn ccer(self) -> crate::common::Reg<regs::Ccer1chCmp, crate::common::RW> {
158 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
159 }
160 #[doc = "counter"]
161 #[inline(always)]
162 pub const fn cnt(self) -> crate::common::Reg<regs::CntCore, crate::common::RW> {
163 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
164 }
165 #[doc = "prescaler"]
166 #[inline(always)]
167 pub const fn psc(self) -> crate::common::Reg<u16, crate::common::RW> {
168 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
169 }
170 #[doc = "auto-reload register (Dither mode disabled)"]
171 #[inline(always)]
172 pub const fn arr(self) -> crate::common::Reg<regs::ArrCore, crate::common::RW> {
173 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
174 }
175 #[doc = "auto-reload register (Dither mode enabled)"]
176 #[inline(always)]
177 pub const fn arr_dither(self) -> crate::common::Reg<regs::ArrDitherCore, crate::common::RW> {
178 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
179 }
180 #[doc = "repetition counter register"]
181 #[inline(always)]
182 pub const fn rcr(self) -> crate::common::Reg<regs::Rcr1chCmp, crate::common::RW> {
183 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) }
184 }
185 #[doc = "capture/compare register x (x=1) (Dither mode disabled)"]
186 #[inline(always)]
187 pub const fn ccr(self, n: usize) -> crate::common::Reg<regs::Ccr1ch, crate::common::RW> {
188 assert!(n < 1usize);
189 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize + n * 4usize) as _) }
190 }
191 #[doc = "capture/compare register x (x=1) (Dither mode enabled)"]
192 #[inline(always)]
193 pub const fn ccr_dither(self, n: usize) -> crate::common::Reg<regs::CcrDither1ch, crate::common::RW> {
194 assert!(n < 1usize);
195 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize + n * 4usize) as _) }
196 }
197 #[doc = "break and dead-time register"]
198 #[inline(always)]
199 pub const fn bdtr(self) -> crate::common::Reg<regs::Bdtr1chCmp, crate::common::RW> {
200 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) }
201 }
202 #[doc = "break and dead-time register"]
203 #[inline(always)]
204 pub const fn dtr2(self) -> crate::common::Reg<regs::Dtr21chCmp, crate::common::RW> {
205 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x54usize) as _) }
206 }
207 #[doc = "input selection register"]
208 #[inline(always)]
209 pub const fn tisel(self) -> crate::common::Reg<regs::Tisel1ch, crate::common::RW> {
210 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) }
211 }
212 #[doc = "alternate function register 1"]
213 #[inline(always)]
214 pub const fn af1(self) -> crate::common::Reg<regs::Af11chCmp, crate::common::RW> {
215 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize) as _) }
216 }
217 #[doc = "alternate function register 2"]
218 #[inline(always)]
219 pub const fn af2(self) -> crate::common::Reg<regs::Af21chCmp, crate::common::RW> {
220 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x64usize) as _) }
221 }
222 #[doc = "Option register 1 Note: Check Reference Manual to parse this register content"]
223 #[inline(always)]
224 pub const fn or(self) -> crate::common::Reg<u32, crate::common::RW> {
225 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x68usize) as _) }
226 }
227 #[doc = "DMA control register"]
228 #[inline(always)]
229 pub const fn dcr(self) -> crate::common::Reg<regs::Dcr1chCmp, crate::common::RW> {
230 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x03dcusize) as _) }
231 }
232 #[doc = "DMA address for full transfer"]
233 #[inline(always)]
234 pub const fn dmar(self) -> crate::common::Reg<u32, crate::common::RW> {
235 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x03e0usize) as _) }
236 }
237}
238#[doc = "2-channel timers"]
239#[derive(Copy, Clone, Eq, PartialEq)]
240pub struct Tim2ch {
241 ptr: *mut u8,
242}
243unsafe impl Send for Tim2ch {}
244unsafe impl Sync for Tim2ch {}
245impl Tim2ch {
246 #[inline(always)]
247 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
248 Self { ptr: ptr as _ }
249 }
250 #[inline(always)]
251 pub const fn as_ptr(&self) -> *mut () {
252 self.ptr as _
253 }
254 #[doc = "control register 1"]
255 #[inline(always)]
256 pub const fn cr1(self) -> crate::common::Reg<regs::Cr11ch, crate::common::RW> {
257 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
258 }
259 #[doc = "control register 2"]
260 #[inline(always)]
261 pub const fn cr2(self) -> crate::common::Reg<regs::Cr22ch, crate::common::RW> {
262 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
263 }
264 #[doc = "slave mode control register"]
265 #[inline(always)]
266 pub const fn smcr(self) -> crate::common::Reg<regs::Smcr2ch, crate::common::RW> {
267 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
268 }
269 #[doc = "DMA/Interrupt enable register"]
270 #[inline(always)]
271 pub const fn dier(self) -> crate::common::Reg<regs::Dier2ch, crate::common::RW> {
272 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
273 }
274 #[doc = "status register"]
275 #[inline(always)]
276 pub const fn sr(self) -> crate::common::Reg<regs::Sr2ch, crate::common::RW> {
277 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
278 }
279 #[doc = "event generation register"]
280 #[inline(always)]
281 pub const fn egr(self) -> crate::common::Reg<regs::Egr2ch, crate::common::W> {
282 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
283 }
284 #[doc = "capture/compare mode register 1 (input mode)"]
285 #[inline(always)]
286 pub const fn ccmr_input(self, n: usize) -> crate::common::Reg<regs::CcmrInput2ch, crate::common::RW> {
287 assert!(n < 1usize);
288 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize + n * 4usize) as _) }
289 }
290 #[doc = "capture/compare mode register 1 (output mode)"]
291 #[inline(always)]
292 pub const fn ccmr_output(self, n: usize) -> crate::common::Reg<regs::CcmrOutput2ch, crate::common::RW> {
293 assert!(n < 1usize);
294 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize + n * 4usize) as _) }
295 }
296 #[doc = "capture/compare enable register"]
297 #[inline(always)]
298 pub const fn ccer(self) -> crate::common::Reg<regs::Ccer2ch, crate::common::RW> {
299 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
300 }
301 #[doc = "counter"]
302 #[inline(always)]
303 pub const fn cnt(self) -> crate::common::Reg<regs::CntCore, crate::common::RW> {
304 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
305 }
306 #[doc = "prescaler"]
307 #[inline(always)]
308 pub const fn psc(self) -> crate::common::Reg<u16, crate::common::RW> {
309 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
310 }
311 #[doc = "auto-reload register (Dither mode disabled)"]
312 #[inline(always)]
313 pub const fn arr(self) -> crate::common::Reg<regs::ArrCore, crate::common::RW> {
314 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
315 }
316 #[doc = "auto-reload register (Dither mode enabled)"]
317 #[inline(always)]
318 pub const fn arr_dither(self) -> crate::common::Reg<regs::ArrDitherCore, crate::common::RW> {
319 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
320 }
321 #[doc = "capture/compare register x (x=1-2) (Dither mode disabled)"]
322 #[inline(always)]
323 pub const fn ccr(self, n: usize) -> crate::common::Reg<regs::Ccr1ch, crate::common::RW> {
324 assert!(n < 2usize);
325 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize + n * 4usize) as _) }
326 }
327 #[doc = "capture/compare register x (x=1-2) (Dither mode enabled)"]
328 #[inline(always)]
329 pub const fn ccr_dither(self, n: usize) -> crate::common::Reg<regs::CcrDither1ch, crate::common::RW> {
330 assert!(n < 2usize);
331 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize + n * 4usize) as _) }
332 }
333 #[doc = "input selection register"]
334 #[inline(always)]
335 pub const fn tisel(self) -> crate::common::Reg<regs::Tisel2ch, crate::common::RW> {
336 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) }
337 }
338 #[doc = "Option register 1 Note: Check Reference Manual to parse this register content"]
339 #[inline(always)]
340 pub const fn or(self) -> crate::common::Reg<u32, crate::common::RW> {
341 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x68usize) as _) }
342 }
343}
344#[doc = "2-channel with one complementary output timers"]
345#[derive(Copy, Clone, Eq, PartialEq)]
346pub struct Tim2chCmp {
347 ptr: *mut u8,
348}
349unsafe impl Send for Tim2chCmp {}
350unsafe impl Sync for Tim2chCmp {}
351impl Tim2chCmp {
352 #[inline(always)]
353 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
354 Self { ptr: ptr as _ }
355 }
356 #[inline(always)]
357 pub const fn as_ptr(&self) -> *mut () {
358 self.ptr as _
359 }
360 #[doc = "control register 1"]
361 #[inline(always)]
362 pub const fn cr1(self) -> crate::common::Reg<regs::Cr11ch, crate::common::RW> {
363 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
364 }
365 #[doc = "control register 2"]
366 #[inline(always)]
367 pub const fn cr2(self) -> crate::common::Reg<regs::Cr22chCmp, crate::common::RW> {
368 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
369 }
370 #[doc = "slave mode control register"]
371 #[inline(always)]
372 pub const fn smcr(self) -> crate::common::Reg<regs::Smcr2chCmp, crate::common::RW> {
373 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
374 }
375 #[doc = "DMA/Interrupt enable register"]
376 #[inline(always)]
377 pub const fn dier(self) -> crate::common::Reg<regs::Dier2chCmp, crate::common::RW> {
378 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
379 }
380 #[doc = "status register"]
381 #[inline(always)]
382 pub const fn sr(self) -> crate::common::Reg<regs::Sr2chCmp, crate::common::RW> {
383 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
384 }
385 #[doc = "event generation register"]
386 #[inline(always)]
387 pub const fn egr(self) -> crate::common::Reg<regs::Egr2chCmp, crate::common::W> {
388 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
389 }
390 #[doc = "capture/compare mode register 1 (input mode)"]
391 #[inline(always)]
392 pub const fn ccmr_input(self, n: usize) -> crate::common::Reg<regs::CcmrInput1ch, crate::common::RW> {
393 assert!(n < 2usize);
394 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize + n * 4usize) as _) }
395 }
396 #[doc = "capture/compare mode register 1 (output mode)"]
397 #[inline(always)]
398 pub const fn ccmr_output(self, n: usize) -> crate::common::Reg<regs::CcmrOutput1ch, crate::common::RW> {
399 assert!(n < 2usize);
400 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize + n * 4usize) as _) }
401 }
402 #[doc = "capture/compare enable register"]
403 #[inline(always)]
404 pub const fn ccer(self) -> crate::common::Reg<regs::Ccer2chCmp, crate::common::RW> {
405 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
406 }
407 #[doc = "counter"]
408 #[inline(always)]
409 pub const fn cnt(self) -> crate::common::Reg<regs::CntCore, crate::common::RW> {
410 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
411 }
412 #[doc = "prescaler"]
413 #[inline(always)]
414 pub const fn psc(self) -> crate::common::Reg<u16, crate::common::RW> {
415 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
416 }
417 #[doc = "auto-reload register (Dither mode disabled)"]
418 #[inline(always)]
419 pub const fn arr(self) -> crate::common::Reg<regs::ArrCore, crate::common::RW> {
420 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
421 }
422 #[doc = "auto-reload register (Dither mode enabled)"]
423 #[inline(always)]
424 pub const fn arr_dither(self) -> crate::common::Reg<regs::ArrDitherCore, crate::common::RW> {
425 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
426 }
427 #[doc = "repetition counter register"]
428 #[inline(always)]
429 pub const fn rcr(self) -> crate::common::Reg<regs::Rcr1chCmp, crate::common::RW> {
430 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) }
431 }
432 #[doc = "capture/compare register x (x=1-2)"]
433 #[inline(always)]
434 pub const fn ccr(self, n: usize) -> crate::common::Reg<regs::Ccr1ch, crate::common::RW> {
435 assert!(n < 2usize);
436 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize + n * 4usize) as _) }
437 }
438 #[doc = "capture/compare register x (x=1-2) (Dither mode enabled)"]
439 #[inline(always)]
440 pub const fn ccr_dither(self, n: usize) -> crate::common::Reg<regs::CcrDither1ch, crate::common::RW> {
441 assert!(n < 2usize);
442 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize + n * 4usize) as _) }
443 }
444 #[doc = "break and dead-time register"]
445 #[inline(always)]
446 pub const fn bdtr(self) -> crate::common::Reg<regs::Bdtr1chCmp, crate::common::RW> {
447 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) }
448 }
449 #[doc = "break and dead-time register"]
450 #[inline(always)]
451 pub const fn dtr2(self) -> crate::common::Reg<regs::Dtr21chCmp, crate::common::RW> {
452 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x54usize) as _) }
453 }
454 #[doc = "input selection register"]
455 #[inline(always)]
456 pub const fn tisel(self) -> crate::common::Reg<regs::Tisel2ch, crate::common::RW> {
457 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) }
458 }
459 #[doc = "alternate function register 1"]
460 #[inline(always)]
461 pub const fn af1(self) -> crate::common::Reg<regs::Af11chCmp, crate::common::RW> {
462 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize) as _) }
463 }
464 #[doc = "alternate function register 2"]
465 #[inline(always)]
466 pub const fn af2(self) -> crate::common::Reg<regs::Af21chCmp, crate::common::RW> {
467 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x64usize) as _) }
468 }
469 #[doc = "Option register 1 Note: Check Reference Manual to parse this register content"]
470 #[inline(always)]
471 pub const fn or(self) -> crate::common::Reg<u32, crate::common::RW> {
472 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x68usize) as _) }
473 }
474 #[doc = "DMA control register"]
475 #[inline(always)]
476 pub const fn dcr(self) -> crate::common::Reg<regs::Dcr1chCmp, crate::common::RW> {
477 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x03dcusize) as _) }
478 }
479 #[doc = "DMA address for full transfer"]
480 #[inline(always)]
481 pub const fn dmar(self) -> crate::common::Reg<u32, crate::common::RW> {
482 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x03e0usize) as _) }
483 }
484}
485#[doc = "Advanced Control timers"]
486#[derive(Copy, Clone, Eq, PartialEq)]
487pub struct TimAdv {
488 ptr: *mut u8,
489}
490unsafe impl Send for TimAdv {}
491unsafe impl Sync for TimAdv {}
492impl TimAdv {
493 #[inline(always)]
494 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
495 Self { ptr: ptr as _ }
496 }
497 #[inline(always)]
498 pub const fn as_ptr(&self) -> *mut () {
499 self.ptr as _
500 }
501 #[doc = "control register 1"]
502 #[inline(always)]
503 pub const fn cr1(self) -> crate::common::Reg<regs::Cr1Gp16, crate::common::RW> {
504 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
505 }
506 #[doc = "control register 2"]
507 #[inline(always)]
508 pub const fn cr2(self) -> crate::common::Reg<regs::Cr2Adv, crate::common::RW> {
509 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
510 }
511 #[doc = "slave mode control register"]
512 #[inline(always)]
513 pub const fn smcr(self) -> crate::common::Reg<regs::SmcrAdv, crate::common::RW> {
514 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
515 }
516 #[doc = "DMA/Interrupt enable register"]
517 #[inline(always)]
518 pub const fn dier(self) -> crate::common::Reg<regs::DierAdv, crate::common::RW> {
519 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
520 }
521 #[doc = "status register"]
522 #[inline(always)]
523 pub const fn sr(self) -> crate::common::Reg<regs::SrAdv, crate::common::RW> {
524 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
525 }
526 #[doc = "event generation register"]
527 #[inline(always)]
528 pub const fn egr(self) -> crate::common::Reg<regs::EgrAdv, crate::common::W> {
529 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
530 }
531 #[doc = "capture/compare mode register 1-2 (input mode)"]
532 #[inline(always)]
533 pub const fn ccmr_input(self, n: usize) -> crate::common::Reg<regs::CcmrInput2ch, crate::common::RW> {
534 assert!(n < 2usize);
535 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize + n * 4usize) as _) }
536 }
537 #[doc = "capture/compare mode register 1-2 (output mode)"]
538 #[inline(always)]
539 pub const fn ccmr_output(self, n: usize) -> crate::common::Reg<regs::CcmrOutputGp16, crate::common::RW> {
540 assert!(n < 2usize);
541 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize + n * 4usize) as _) }
542 }
543 #[doc = "capture/compare enable register"]
544 #[inline(always)]
545 pub const fn ccer(self) -> crate::common::Reg<regs::CcerAdv, crate::common::RW> {
546 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
547 }
548 #[doc = "counter"]
549 #[inline(always)]
550 pub const fn cnt(self) -> crate::common::Reg<regs::CntCore, crate::common::RW> {
551 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
552 }
553 #[doc = "prescaler"]
554 #[inline(always)]
555 pub const fn psc(self) -> crate::common::Reg<u16, crate::common::RW> {
556 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
557 }
558 #[doc = "auto-reload register (Dither mode disabled)"]
559 #[inline(always)]
560 pub const fn arr(self) -> crate::common::Reg<regs::ArrCore, crate::common::RW> {
561 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
562 }
563 #[doc = "auto-reload register (Dither mode enabled)"]
564 #[inline(always)]
565 pub const fn arr_dither(self) -> crate::common::Reg<regs::ArrDitherCore, crate::common::RW> {
566 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
567 }
568 #[doc = "repetition counter register"]
569 #[inline(always)]
570 pub const fn rcr(self) -> crate::common::Reg<regs::RcrAdv, crate::common::RW> {
571 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) }
572 }
573 #[doc = "capture/compare register x (x=1-4)"]
574 #[inline(always)]
575 pub const fn ccr(self, n: usize) -> crate::common::Reg<regs::Ccr1ch, crate::common::RW> {
576 assert!(n < 4usize);
577 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize + n * 4usize) as _) }
578 }
579 #[doc = "capture/compare register x (x=1-2) (Dither mode enabled)"]
580 #[inline(always)]
581 pub const fn ccr_dither(self, n: usize) -> crate::common::Reg<regs::CcrDither1ch, crate::common::RW> {
582 assert!(n < 2usize);
583 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize + n * 4usize) as _) }
584 }
585 #[doc = "break and dead-time register"]
586 #[inline(always)]
587 pub const fn bdtr(self) -> crate::common::Reg<regs::BdtrAdv, crate::common::RW> {
588 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x44usize) as _) }
589 }
590 #[doc = "capture/compare register 5 (Dither mode disabled)"]
591 #[inline(always)]
592 pub const fn ccr5(self) -> crate::common::Reg<regs::Ccr5Adv, crate::common::RW> {
593 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) }
594 }
595 #[doc = "capture/compare register 5 (Dither mode enabled)"]
596 #[inline(always)]
597 pub const fn ccr5_dither(self) -> crate::common::Reg<regs::Ccr5DitherAdv, crate::common::RW> {
598 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x48usize) as _) }
599 }
600 #[doc = "capture/compare register 6 (Dither mode disabled)"]
601 #[inline(always)]
602 pub const fn ccr6(self) -> crate::common::Reg<regs::Ccr1ch, crate::common::RW> {
603 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x4cusize) as _) }
604 }
605 #[doc = "capture/compare register 6 (Dither mode enabled)"]
606 #[inline(always)]
607 pub const fn ccr6_dither(self) -> crate::common::Reg<regs::CcrDither1ch, crate::common::RW> {
608 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x4cusize) as _) }
609 }
610 #[doc = "capture/compare mode register 3"]
611 #[inline(always)]
612 pub const fn ccmr3(self) -> crate::common::Reg<regs::Ccmr3Adv, crate::common::RW> {
613 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x50usize) as _) }
614 }
615 #[doc = "break and dead-time register"]
616 #[inline(always)]
617 pub const fn dtr2(self) -> crate::common::Reg<regs::Dtr21chCmp, crate::common::RW> {
618 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x54usize) as _) }
619 }
620 #[doc = "encoder control register"]
621 #[inline(always)]
622 pub const fn ecr(self) -> crate::common::Reg<regs::EcrGp16, crate::common::RW> {
623 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x58usize) as _) }
624 }
625 #[doc = "input selection register"]
626 #[inline(always)]
627 pub const fn tisel(self) -> crate::common::Reg<regs::TiselGp16, crate::common::RW> {
628 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) }
629 }
630 #[doc = "alternate function register 1"]
631 #[inline(always)]
632 pub const fn af1(self) -> crate::common::Reg<regs::Af1Adv, crate::common::RW> {
633 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize) as _) }
634 }
635 #[doc = "alternate function register 2"]
636 #[inline(always)]
637 pub const fn af2(self) -> crate::common::Reg<regs::Af2Adv, crate::common::RW> {
638 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x64usize) as _) }
639 }
640 #[doc = "Option register 1 Note: Check Reference Manual to parse this register content"]
641 #[inline(always)]
642 pub const fn or(self) -> crate::common::Reg<u32, crate::common::RW> {
643 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x68usize) as _) }
644 }
645 #[doc = "DMA control register"]
646 #[inline(always)]
647 pub const fn dcr(self) -> crate::common::Reg<regs::Dcr1chCmp, crate::common::RW> {
648 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x03dcusize) as _) }
649 }
650 #[doc = "DMA address for full transfer"]
651 #[inline(always)]
652 pub const fn dmar(self) -> crate::common::Reg<u32, crate::common::RW> {
653 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x03e0usize) as _) }
654 }
655}
656#[doc = "Basic timers"]
657#[derive(Copy, Clone, Eq, PartialEq)]
658pub struct TimBasic {
659 ptr: *mut u8,
660}
661unsafe impl Send for TimBasic {}
662unsafe impl Sync for TimBasic {}
663impl TimBasic {
664 #[inline(always)]
665 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
666 Self { ptr: ptr as _ }
667 }
668 #[inline(always)]
669 pub const fn as_ptr(&self) -> *mut () {
670 self.ptr as _
671 }
672 #[doc = "control register 1"]
673 #[inline(always)]
674 pub const fn cr1(self) -> crate::common::Reg<regs::Cr1Core, crate::common::RW> {
675 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
676 }
677 #[doc = "control register 2"]
678 #[inline(always)]
679 pub const fn cr2(self) -> crate::common::Reg<regs::Cr2Basic, crate::common::RW> {
680 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
681 }
682 #[doc = "DMA/Interrupt enable register"]
683 #[inline(always)]
684 pub const fn dier(self) -> crate::common::Reg<regs::DierBasicNoCr2, crate::common::RW> {
685 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
686 }
687 #[doc = "status register"]
688 #[inline(always)]
689 pub const fn sr(self) -> crate::common::Reg<regs::SrCore, crate::common::RW> {
690 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
691 }
692 #[doc = "event generation register"]
693 #[inline(always)]
694 pub const fn egr(self) -> crate::common::Reg<regs::EgrCore, crate::common::W> {
695 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
696 }
697 #[doc = "counter"]
698 #[inline(always)]
699 pub const fn cnt(self) -> crate::common::Reg<regs::CntCore, crate::common::RW> {
700 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
701 }
702 #[doc = "prescaler"]
703 #[inline(always)]
704 pub const fn psc(self) -> crate::common::Reg<u16, crate::common::RW> {
705 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
706 }
707 #[doc = "auto-reload register (Dither mode disabled)"]
708 #[inline(always)]
709 pub const fn arr(self) -> crate::common::Reg<regs::ArrCore, crate::common::RW> {
710 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
711 }
712 #[doc = "auto-reload register (Dither mode enabled)"]
713 #[inline(always)]
714 pub const fn arr_dither(self) -> crate::common::Reg<regs::ArrDitherCore, crate::common::RW> {
715 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
716 }
717}
718#[doc = "Virtual Basic timers without CR2 register for common part of TIM_BASIC and TIM_1CH_CMP"]
719#[derive(Copy, Clone, Eq, PartialEq)]
720pub struct TimBasicNoCr2 {
721 ptr: *mut u8,
722}
723unsafe impl Send for TimBasicNoCr2 {}
724unsafe impl Sync for TimBasicNoCr2 {}
725impl TimBasicNoCr2 {
726 #[inline(always)]
727 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
728 Self { ptr: ptr as _ }
729 }
730 #[inline(always)]
731 pub const fn as_ptr(&self) -> *mut () {
732 self.ptr as _
733 }
734 #[doc = "control register 1"]
735 #[inline(always)]
736 pub const fn cr1(self) -> crate::common::Reg<regs::Cr1Core, crate::common::RW> {
737 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
738 }
739 #[doc = "DMA/Interrupt enable register"]
740 #[inline(always)]
741 pub const fn dier(self) -> crate::common::Reg<regs::DierBasicNoCr2, crate::common::RW> {
742 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
743 }
744 #[doc = "status register"]
745 #[inline(always)]
746 pub const fn sr(self) -> crate::common::Reg<regs::SrCore, crate::common::RW> {
747 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
748 }
749 #[doc = "event generation register"]
750 #[inline(always)]
751 pub const fn egr(self) -> crate::common::Reg<regs::EgrCore, crate::common::W> {
752 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
753 }
754 #[doc = "counter"]
755 #[inline(always)]
756 pub const fn cnt(self) -> crate::common::Reg<regs::CntCore, crate::common::RW> {
757 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
758 }
759 #[doc = "prescaler"]
760 #[inline(always)]
761 pub const fn psc(self) -> crate::common::Reg<u16, crate::common::RW> {
762 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
763 }
764 #[doc = "auto-reload register (Dither mode disabled)"]
765 #[inline(always)]
766 pub const fn arr(self) -> crate::common::Reg<regs::ArrCore, crate::common::RW> {
767 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
768 }
769 #[doc = "auto-reload register (Dither mode enabled)"]
770 #[inline(always)]
771 pub const fn arr_dither(self) -> crate::common::Reg<regs::ArrDitherCore, crate::common::RW> {
772 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
773 }
774}
775#[doc = "Virtual timer for common part of TIM_BASIC and TIM_1CH"]
776#[derive(Copy, Clone, Eq, PartialEq)]
777pub struct TimCore {
778 ptr: *mut u8,
779}
780unsafe impl Send for TimCore {}
781unsafe impl Sync for TimCore {}
782impl TimCore {
783 #[inline(always)]
784 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
785 Self { ptr: ptr as _ }
786 }
787 #[inline(always)]
788 pub const fn as_ptr(&self) -> *mut () {
789 self.ptr as _
790 }
791 #[doc = "control register 1"]
792 #[inline(always)]
793 pub const fn cr1(self) -> crate::common::Reg<regs::Cr1Core, crate::common::RW> {
794 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
795 }
796 #[doc = "DMA/Interrupt enable register"]
797 #[inline(always)]
798 pub const fn dier(self) -> crate::common::Reg<regs::DierCore, crate::common::RW> {
799 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
800 }
801 #[doc = "status register"]
802 #[inline(always)]
803 pub const fn sr(self) -> crate::common::Reg<regs::SrCore, crate::common::RW> {
804 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
805 }
806 #[doc = "event generation register"]
807 #[inline(always)]
808 pub const fn egr(self) -> crate::common::Reg<regs::EgrCore, crate::common::W> {
809 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
810 }
811 #[doc = "counter"]
812 #[inline(always)]
813 pub const fn cnt(self) -> crate::common::Reg<regs::CntCore, crate::common::RW> {
814 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
815 }
816 #[doc = "prescaler"]
817 #[inline(always)]
818 pub const fn psc(self) -> crate::common::Reg<u16, crate::common::RW> {
819 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
820 }
821 #[doc = "auto-reload register (Dither mode disabled)"]
822 #[inline(always)]
823 pub const fn arr(self) -> crate::common::Reg<regs::ArrCore, crate::common::RW> {
824 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
825 }
826 #[doc = "auto-reload register (Dither mode enabled)"]
827 #[inline(always)]
828 pub const fn arr_dither(self) -> crate::common::Reg<regs::ArrDitherCore, crate::common::RW> {
829 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
830 }
831}
832#[doc = "General purpose 16-bit timers"]
833#[derive(Copy, Clone, Eq, PartialEq)]
834pub struct TimGp16 {
835 ptr: *mut u8,
836}
837unsafe impl Send for TimGp16 {}
838unsafe impl Sync for TimGp16 {}
839impl TimGp16 {
840 #[inline(always)]
841 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
842 Self { ptr: ptr as _ }
843 }
844 #[inline(always)]
845 pub const fn as_ptr(&self) -> *mut () {
846 self.ptr as _
847 }
848 #[doc = "control register 1"]
849 #[inline(always)]
850 pub const fn cr1(self) -> crate::common::Reg<regs::Cr1Gp16, crate::common::RW> {
851 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
852 }
853 #[doc = "control register 2"]
854 #[inline(always)]
855 pub const fn cr2(self) -> crate::common::Reg<regs::Cr2Gp16, crate::common::RW> {
856 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
857 }
858 #[doc = "slave mode control register"]
859 #[inline(always)]
860 pub const fn smcr(self) -> crate::common::Reg<regs::SmcrGp16, crate::common::RW> {
861 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
862 }
863 #[doc = "DMA/Interrupt enable register"]
864 #[inline(always)]
865 pub const fn dier(self) -> crate::common::Reg<regs::DierGp16, crate::common::RW> {
866 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
867 }
868 #[doc = "status register"]
869 #[inline(always)]
870 pub const fn sr(self) -> crate::common::Reg<regs::SrGp16, crate::common::RW> {
871 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
872 }
873 #[doc = "event generation register"]
874 #[inline(always)]
875 pub const fn egr(self) -> crate::common::Reg<regs::EgrGp16, crate::common::W> {
876 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
877 }
878 #[doc = "capture/compare mode register 1-2 (input mode)"]
879 #[inline(always)]
880 pub const fn ccmr_input(self, n: usize) -> crate::common::Reg<regs::CcmrInput2ch, crate::common::RW> {
881 assert!(n < 2usize);
882 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize + n * 4usize) as _) }
883 }
884 #[doc = "capture/compare mode register 1-2 (output mode)"]
885 #[inline(always)]
886 pub const fn ccmr_output(self, n: usize) -> crate::common::Reg<regs::CcmrOutputGp16, crate::common::RW> {
887 assert!(n < 2usize);
888 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize + n * 4usize) as _) }
889 }
890 #[doc = "capture/compare enable register"]
891 #[inline(always)]
892 pub const fn ccer(self) -> crate::common::Reg<regs::CcerGp16, crate::common::RW> {
893 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
894 }
895 #[doc = "counter"]
896 #[inline(always)]
897 pub const fn cnt(self) -> crate::common::Reg<regs::CntCore, crate::common::RW> {
898 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
899 }
900 #[doc = "prescaler"]
901 #[inline(always)]
902 pub const fn psc(self) -> crate::common::Reg<u16, crate::common::RW> {
903 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
904 }
905 #[doc = "auto-reload register (Dither mode disabled)"]
906 #[inline(always)]
907 pub const fn arr(self) -> crate::common::Reg<regs::ArrCore, crate::common::RW> {
908 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
909 }
910 #[doc = "auto-reload register (Dither mode enabled)"]
911 #[inline(always)]
912 pub const fn arr_dither(self) -> crate::common::Reg<regs::ArrDitherCore, crate::common::RW> {
913 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
914 }
915 #[doc = "capture/compare register x (x=1-4) (Dither mode disabled)"]
916 #[inline(always)]
917 pub const fn ccr(self, n: usize) -> crate::common::Reg<regs::Ccr1ch, crate::common::RW> {
918 assert!(n < 4usize);
919 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize + n * 4usize) as _) }
920 }
921 #[doc = "capture/compare register x (x=1-4) (Dither mode enabled)"]
922 #[inline(always)]
923 pub const fn ccr_dither(self, n: usize) -> crate::common::Reg<regs::CcrDither1ch, crate::common::RW> {
924 assert!(n < 4usize);
925 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize + n * 4usize) as _) }
926 }
927 #[doc = "encoder control register"]
928 #[inline(always)]
929 pub const fn ecr(self) -> crate::common::Reg<regs::EcrGp16, crate::common::RW> {
930 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x58usize) as _) }
931 }
932 #[doc = "input selection register"]
933 #[inline(always)]
934 pub const fn tisel(self) -> crate::common::Reg<regs::TiselGp16, crate::common::RW> {
935 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) }
936 }
937 #[doc = "alternate function register 1"]
938 #[inline(always)]
939 pub const fn af1(self) -> crate::common::Reg<regs::Af1Gp16, crate::common::RW> {
940 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize) as _) }
941 }
942 #[doc = "alternate function register 2"]
943 #[inline(always)]
944 pub const fn af2(self) -> crate::common::Reg<regs::Af21chCmp, crate::common::RW> {
945 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x64usize) as _) }
946 }
947 #[doc = "Option register 1 Note: Check Reference Manual to parse this register content"]
948 #[inline(always)]
949 pub const fn or(self) -> crate::common::Reg<u32, crate::common::RW> {
950 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x68usize) as _) }
951 }
952 #[doc = "DMA control register"]
953 #[inline(always)]
954 pub const fn dcr(self) -> crate::common::Reg<regs::Dcr1chCmp, crate::common::RW> {
955 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x03dcusize) as _) }
956 }
957 #[doc = "DMA address for full transfer"]
958 #[inline(always)]
959 pub const fn dmar(self) -> crate::common::Reg<u32, crate::common::RW> {
960 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x03e0usize) as _) }
961 }
962}
963#[doc = "General purpose 32-bit timers"]
964#[derive(Copy, Clone, Eq, PartialEq)]
965pub struct TimGp32 {
966 ptr: *mut u8,
967}
968unsafe impl Send for TimGp32 {}
969unsafe impl Sync for TimGp32 {}
970impl TimGp32 {
971 #[inline(always)]
972 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
973 Self { ptr: ptr as _ }
974 }
975 #[inline(always)]
976 pub const fn as_ptr(&self) -> *mut () {
977 self.ptr as _
978 }
979 #[doc = "control register 1"]
980 #[inline(always)]
981 pub const fn cr1(self) -> crate::common::Reg<regs::Cr1Gp16, crate::common::RW> {
982 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
983 }
984 #[doc = "control register 2"]
985 #[inline(always)]
986 pub const fn cr2(self) -> crate::common::Reg<regs::Cr2Gp16, crate::common::RW> {
987 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
988 }
989 #[doc = "slave mode control register"]
990 #[inline(always)]
991 pub const fn smcr(self) -> crate::common::Reg<regs::SmcrGp16, crate::common::RW> {
992 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
993 }
994 #[doc = "DMA/Interrupt enable register"]
995 #[inline(always)]
996 pub const fn dier(self) -> crate::common::Reg<regs::DierGp16, crate::common::RW> {
997 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
998 }
999 #[doc = "status register"]
1000 #[inline(always)]
1001 pub const fn sr(self) -> crate::common::Reg<regs::SrGp16, crate::common::RW> {
1002 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
1003 }
1004 #[doc = "event generation register"]
1005 #[inline(always)]
1006 pub const fn egr(self) -> crate::common::Reg<regs::EgrGp16, crate::common::W> {
1007 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
1008 }
1009 #[doc = "capture/compare mode register 1-2 (input mode)"]
1010 #[inline(always)]
1011 pub const fn ccmr_input(self, n: usize) -> crate::common::Reg<regs::CcmrInput2ch, crate::common::RW> {
1012 assert!(n < 2usize);
1013 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize + n * 4usize) as _) }
1014 }
1015 #[doc = "capture/compare mode register 1-2 (output mode)"]
1016 #[inline(always)]
1017 pub const fn ccmr_output(self, n: usize) -> crate::common::Reg<regs::CcmrOutputGp16, crate::common::RW> {
1018 assert!(n < 2usize);
1019 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize + n * 4usize) as _) }
1020 }
1021 #[doc = "capture/compare enable register"]
1022 #[inline(always)]
1023 pub const fn ccer(self) -> crate::common::Reg<regs::CcerGp16, crate::common::RW> {
1024 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
1025 }
1026 #[doc = "counter (Dither mode disabled)"]
1027 #[inline(always)]
1028 pub const fn cnt(self) -> crate::common::Reg<u32, crate::common::RW> {
1029 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
1030 }
1031 #[doc = "counter (Dither mode enbled)"]
1032 #[inline(always)]
1033 pub const fn cnt_dither(self) -> crate::common::Reg<regs::CntDitherGp32, crate::common::RW> {
1034 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
1035 }
1036 #[doc = "prescaler"]
1037 #[inline(always)]
1038 pub const fn psc(self) -> crate::common::Reg<u16, crate::common::RW> {
1039 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
1040 }
1041 #[doc = "auto-reload register (Dither mode disabled)"]
1042 #[inline(always)]
1043 pub const fn arr(self) -> crate::common::Reg<u32, crate::common::RW> {
1044 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
1045 }
1046 #[doc = "auto-reload register (Dither mode enabled)"]
1047 #[inline(always)]
1048 pub const fn arr_dither(self) -> crate::common::Reg<regs::ArrDitherGp32, crate::common::RW> {
1049 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
1050 }
1051 #[doc = "capture/compare register x (x=1-4) (Dither mode disabled)"]
1052 #[inline(always)]
1053 pub const fn ccr(self, n: usize) -> crate::common::Reg<u32, crate::common::RW> {
1054 assert!(n < 4usize);
1055 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize + n * 4usize) as _) }
1056 }
1057 #[doc = "capture/compare register x (x=1-4) (Dither mode enabled)"]
1058 #[inline(always)]
1059 pub const fn ccr_dither(self, n: usize) -> crate::common::Reg<regs::CcrDitherGp32, crate::common::RW> {
1060 assert!(n < 4usize);
1061 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize + n * 4usize) as _) }
1062 }
1063 #[doc = "encoder control register"]
1064 #[inline(always)]
1065 pub const fn ecr(self) -> crate::common::Reg<regs::EcrGp16, crate::common::RW> {
1066 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x58usize) as _) }
1067 }
1068 #[doc = "input selection register"]
1069 #[inline(always)]
1070 pub const fn tisel(self) -> crate::common::Reg<regs::TiselGp16, crate::common::RW> {
1071 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x5cusize) as _) }
1072 }
1073 #[doc = "alternate function register 1"]
1074 #[inline(always)]
1075 pub const fn af1(self) -> crate::common::Reg<regs::Af1Gp16, crate::common::RW> {
1076 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x60usize) as _) }
1077 }
1078 #[doc = "alternate function register 2"]
1079 #[inline(always)]
1080 pub const fn af2(self) -> crate::common::Reg<regs::Af21chCmp, crate::common::RW> {
1081 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x64usize) as _) }
1082 }
1083 #[doc = "Option register 1 Note: Check Reference Manual to parse this register content"]
1084 #[inline(always)]
1085 pub const fn or(self) -> crate::common::Reg<u32, crate::common::RW> {
1086 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x68usize) as _) }
1087 }
1088 #[doc = "DMA control register"]
1089 #[inline(always)]
1090 pub const fn dcr(self) -> crate::common::Reg<regs::Dcr1chCmp, crate::common::RW> {
1091 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x03dcusize) as _) }
1092 }
1093 #[doc = "DMA address for full transfer"]
1094 #[inline(always)]
1095 pub const fn dmar(self) -> crate::common::Reg<u32, crate::common::RW> {
1096 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x03e0usize) as _) }
1097 }
1098}
1099pub mod regs {
1100 #[doc = "alternate function register 1"]
1101 #[repr(transparent)]
1102 #[derive(Copy, Clone, Eq, PartialEq)]
1103 pub struct Af11chCmp(pub u32);
1104 impl Af11chCmp {
1105 #[doc = "TIMx_BKIN input enable"]
1106 #[inline(always)]
1107 pub const fn bkine(&self) -> bool {
1108 let val = (self.0 >> 0usize) & 0x01;
1109 val != 0
1110 }
1111 #[doc = "TIMx_BKIN input enable"]
1112 #[inline(always)]
1113 pub fn set_bkine(&mut self, val: bool) {
1114 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1115 }
1116 #[doc = "TIM_BRK_CMPx (x=1-8) enable"]
1117 #[inline(always)]
1118 pub const fn bkcmpe(&self, n: usize) -> bool {
1119 assert!(n < 8usize);
1120 let offs = 1usize + n * 1usize;
1121 let val = (self.0 >> offs) & 0x01;
1122 val != 0
1123 }
1124 #[doc = "TIM_BRK_CMPx (x=1-8) enable"]
1125 #[inline(always)]
1126 pub fn set_bkcmpe(&mut self, n: usize, val: bool) {
1127 assert!(n < 8usize);
1128 let offs = 1usize + n * 1usize;
1129 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1130 }
1131 #[doc = "TIMx_BKIN input polarity"]
1132 #[inline(always)]
1133 pub const fn bkinp(&self) -> super::vals::Bkinp {
1134 let val = (self.0 >> 9usize) & 0x01;
1135 super::vals::Bkinp::from_bits(val as u8)
1136 }
1137 #[doc = "TIMx_BKIN input polarity"]
1138 #[inline(always)]
1139 pub fn set_bkinp(&mut self, val: super::vals::Bkinp) {
1140 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.to_bits() as u32) & 0x01) << 9usize);
1141 }
1142 #[doc = "TIM_BRK_CMPx (x=1-4) input polarity"]
1143 #[inline(always)]
1144 pub const fn bkcmpp(&self, n: usize) -> super::vals::Bkinp {
1145 assert!(n < 4usize);
1146 let offs = 10usize + n * 1usize;
1147 let val = (self.0 >> offs) & 0x01;
1148 super::vals::Bkinp::from_bits(val as u8)
1149 }
1150 #[doc = "TIM_BRK_CMPx (x=1-4) input polarity"]
1151 #[inline(always)]
1152 pub fn set_bkcmpp(&mut self, n: usize, val: super::vals::Bkinp) {
1153 assert!(n < 4usize);
1154 let offs = 10usize + n * 1usize;
1155 self.0 = (self.0 & !(0x01 << offs)) | (((val.to_bits() as u32) & 0x01) << offs);
1156 }
1157 }
1158 impl Default for Af11chCmp {
1159 #[inline(always)]
1160 fn default() -> Af11chCmp {
1161 Af11chCmp(0)
1162 }
1163 }
1164 impl core::fmt::Debug for Af11chCmp {
1165 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1166 f.debug_struct("Af11chCmp")
1167 .field("bkine", &self.bkine())
1168 .field(
1169 "bkcmpe",
1170 &[
1171 self.bkcmpe(0usize),
1172 self.bkcmpe(1usize),
1173 self.bkcmpe(2usize),
1174 self.bkcmpe(3usize),
1175 self.bkcmpe(4usize),
1176 self.bkcmpe(5usize),
1177 self.bkcmpe(6usize),
1178 self.bkcmpe(7usize),
1179 ],
1180 )
1181 .field("bkinp", &self.bkinp())
1182 .field(
1183 "bkcmpp",
1184 &[
1185 self.bkcmpp(0usize),
1186 self.bkcmpp(1usize),
1187 self.bkcmpp(2usize),
1188 self.bkcmpp(3usize),
1189 ],
1190 )
1191 .finish()
1192 }
1193 }
1194 #[cfg(feature = "defmt")]
1195 impl defmt::Format for Af11chCmp {
1196 fn format(&self, f: defmt::Formatter) {
1197 #[derive(defmt :: Format)]
1198 struct Af11chCmp {
1199 bkine: bool,
1200 bkcmpe: [bool; 8usize],
1201 bkinp: super::vals::Bkinp,
1202 bkcmpp: [super::vals::Bkinp; 4usize],
1203 }
1204 let proxy = Af11chCmp {
1205 bkine: self.bkine(),
1206 bkcmpe: [
1207 self.bkcmpe(0usize),
1208 self.bkcmpe(1usize),
1209 self.bkcmpe(2usize),
1210 self.bkcmpe(3usize),
1211 self.bkcmpe(4usize),
1212 self.bkcmpe(5usize),
1213 self.bkcmpe(6usize),
1214 self.bkcmpe(7usize),
1215 ],
1216 bkinp: self.bkinp(),
1217 bkcmpp: [
1218 self.bkcmpp(0usize),
1219 self.bkcmpp(1usize),
1220 self.bkcmpp(2usize),
1221 self.bkcmpp(3usize),
1222 ],
1223 };
1224 defmt::write!(f, "{}", proxy)
1225 }
1226 }
1227 #[doc = "alternate function register 1"]
1228 #[repr(transparent)]
1229 #[derive(Copy, Clone, Eq, PartialEq)]
1230 pub struct Af1Adv(pub u32);
1231 impl Af1Adv {
1232 #[doc = "TIMx_BKIN input enable"]
1233 #[inline(always)]
1234 pub const fn bkine(&self) -> bool {
1235 let val = (self.0 >> 0usize) & 0x01;
1236 val != 0
1237 }
1238 #[doc = "TIMx_BKIN input enable"]
1239 #[inline(always)]
1240 pub fn set_bkine(&mut self, val: bool) {
1241 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1242 }
1243 #[doc = "TIM_BRK_CMPx (x=1-8) enable"]
1244 #[inline(always)]
1245 pub const fn bkcmpe(&self, n: usize) -> bool {
1246 assert!(n < 8usize);
1247 let offs = 1usize + n * 1usize;
1248 let val = (self.0 >> offs) & 0x01;
1249 val != 0
1250 }
1251 #[doc = "TIM_BRK_CMPx (x=1-8) enable"]
1252 #[inline(always)]
1253 pub fn set_bkcmpe(&mut self, n: usize, val: bool) {
1254 assert!(n < 8usize);
1255 let offs = 1usize + n * 1usize;
1256 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1257 }
1258 #[doc = "TIMx_BKIN input polarity"]
1259 #[inline(always)]
1260 pub const fn bkinp(&self) -> super::vals::Bkinp {
1261 let val = (self.0 >> 9usize) & 0x01;
1262 super::vals::Bkinp::from_bits(val as u8)
1263 }
1264 #[doc = "TIMx_BKIN input polarity"]
1265 #[inline(always)]
1266 pub fn set_bkinp(&mut self, val: super::vals::Bkinp) {
1267 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.to_bits() as u32) & 0x01) << 9usize);
1268 }
1269 #[doc = "TIM_BRK_CMPx (x=1-4) input polarity"]
1270 #[inline(always)]
1271 pub const fn bkcmpp(&self, n: usize) -> super::vals::Bkinp {
1272 assert!(n < 4usize);
1273 let offs = 10usize + n * 1usize;
1274 let val = (self.0 >> offs) & 0x01;
1275 super::vals::Bkinp::from_bits(val as u8)
1276 }
1277 #[doc = "TIM_BRK_CMPx (x=1-4) input polarity"]
1278 #[inline(always)]
1279 pub fn set_bkcmpp(&mut self, n: usize, val: super::vals::Bkinp) {
1280 assert!(n < 4usize);
1281 let offs = 10usize + n * 1usize;
1282 self.0 = (self.0 & !(0x01 << offs)) | (((val.to_bits() as u32) & 0x01) << offs);
1283 }
1284 #[doc = "etr_in source selection"]
1285 #[inline(always)]
1286 pub const fn etrsel(&self) -> u8 {
1287 let val = (self.0 >> 14usize) & 0x0f;
1288 val as u8
1289 }
1290 #[doc = "etr_in source selection"]
1291 #[inline(always)]
1292 pub fn set_etrsel(&mut self, val: u8) {
1293 self.0 = (self.0 & !(0x0f << 14usize)) | (((val as u32) & 0x0f) << 14usize);
1294 }
1295 }
1296 impl Default for Af1Adv {
1297 #[inline(always)]
1298 fn default() -> Af1Adv {
1299 Af1Adv(0)
1300 }
1301 }
1302 impl core::fmt::Debug for Af1Adv {
1303 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1304 f.debug_struct("Af1Adv")
1305 .field("bkine", &self.bkine())
1306 .field(
1307 "bkcmpe",
1308 &[
1309 self.bkcmpe(0usize),
1310 self.bkcmpe(1usize),
1311 self.bkcmpe(2usize),
1312 self.bkcmpe(3usize),
1313 self.bkcmpe(4usize),
1314 self.bkcmpe(5usize),
1315 self.bkcmpe(6usize),
1316 self.bkcmpe(7usize),
1317 ],
1318 )
1319 .field("bkinp", &self.bkinp())
1320 .field(
1321 "bkcmpp",
1322 &[
1323 self.bkcmpp(0usize),
1324 self.bkcmpp(1usize),
1325 self.bkcmpp(2usize),
1326 self.bkcmpp(3usize),
1327 ],
1328 )
1329 .field("etrsel", &self.etrsel())
1330 .finish()
1331 }
1332 }
1333 #[cfg(feature = "defmt")]
1334 impl defmt::Format for Af1Adv {
1335 fn format(&self, f: defmt::Formatter) {
1336 #[derive(defmt :: Format)]
1337 struct Af1Adv {
1338 bkine: bool,
1339 bkcmpe: [bool; 8usize],
1340 bkinp: super::vals::Bkinp,
1341 bkcmpp: [super::vals::Bkinp; 4usize],
1342 etrsel: u8,
1343 }
1344 let proxy = Af1Adv {
1345 bkine: self.bkine(),
1346 bkcmpe: [
1347 self.bkcmpe(0usize),
1348 self.bkcmpe(1usize),
1349 self.bkcmpe(2usize),
1350 self.bkcmpe(3usize),
1351 self.bkcmpe(4usize),
1352 self.bkcmpe(5usize),
1353 self.bkcmpe(6usize),
1354 self.bkcmpe(7usize),
1355 ],
1356 bkinp: self.bkinp(),
1357 bkcmpp: [
1358 self.bkcmpp(0usize),
1359 self.bkcmpp(1usize),
1360 self.bkcmpp(2usize),
1361 self.bkcmpp(3usize),
1362 ],
1363 etrsel: self.etrsel(),
1364 };
1365 defmt::write!(f, "{}", proxy)
1366 }
1367 }
1368 #[doc = "alternate function register 1"]
1369 #[repr(transparent)]
1370 #[derive(Copy, Clone, Eq, PartialEq)]
1371 pub struct Af1Gp16(pub u32);
1372 impl Af1Gp16 {
1373 #[doc = "etr_in source selection"]
1374 #[inline(always)]
1375 pub const fn etrsel(&self) -> u8 {
1376 let val = (self.0 >> 14usize) & 0x0f;
1377 val as u8
1378 }
1379 #[doc = "etr_in source selection"]
1380 #[inline(always)]
1381 pub fn set_etrsel(&mut self, val: u8) {
1382 self.0 = (self.0 & !(0x0f << 14usize)) | (((val as u32) & 0x0f) << 14usize);
1383 }
1384 }
1385 impl Default for Af1Gp16 {
1386 #[inline(always)]
1387 fn default() -> Af1Gp16 {
1388 Af1Gp16(0)
1389 }
1390 }
1391 impl core::fmt::Debug for Af1Gp16 {
1392 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1393 f.debug_struct("Af1Gp16").field("etrsel", &self.etrsel()).finish()
1394 }
1395 }
1396 #[cfg(feature = "defmt")]
1397 impl defmt::Format for Af1Gp16 {
1398 fn format(&self, f: defmt::Formatter) {
1399 #[derive(defmt :: Format)]
1400 struct Af1Gp16 {
1401 etrsel: u8,
1402 }
1403 let proxy = Af1Gp16 { etrsel: self.etrsel() };
1404 defmt::write!(f, "{}", proxy)
1405 }
1406 }
1407 #[doc = "alternate function register 2"]
1408 #[repr(transparent)]
1409 #[derive(Copy, Clone, Eq, PartialEq)]
1410 pub struct Af21chCmp(pub u32);
1411 impl Af21chCmp {
1412 #[doc = "ocref_clr source selection"]
1413 #[inline(always)]
1414 pub const fn ocrsel(&self) -> u8 {
1415 let val = (self.0 >> 16usize) & 0x07;
1416 val as u8
1417 }
1418 #[doc = "ocref_clr source selection"]
1419 #[inline(always)]
1420 pub fn set_ocrsel(&mut self, val: u8) {
1421 self.0 = (self.0 & !(0x07 << 16usize)) | (((val as u32) & 0x07) << 16usize);
1422 }
1423 }
1424 impl Default for Af21chCmp {
1425 #[inline(always)]
1426 fn default() -> Af21chCmp {
1427 Af21chCmp(0)
1428 }
1429 }
1430 impl core::fmt::Debug for Af21chCmp {
1431 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1432 f.debug_struct("Af21chCmp").field("ocrsel", &self.ocrsel()).finish()
1433 }
1434 }
1435 #[cfg(feature = "defmt")]
1436 impl defmt::Format for Af21chCmp {
1437 fn format(&self, f: defmt::Formatter) {
1438 #[derive(defmt :: Format)]
1439 struct Af21chCmp {
1440 ocrsel: u8,
1441 }
1442 let proxy = Af21chCmp { ocrsel: self.ocrsel() };
1443 defmt::write!(f, "{}", proxy)
1444 }
1445 }
1446 #[doc = "alternate function register 2"]
1447 #[repr(transparent)]
1448 #[derive(Copy, Clone, Eq, PartialEq)]
1449 pub struct Af2Adv(pub u32);
1450 impl Af2Adv {
1451 #[doc = "TIMx_BKIN2 input enable"]
1452 #[inline(always)]
1453 pub const fn bk2ine(&self) -> bool {
1454 let val = (self.0 >> 0usize) & 0x01;
1455 val != 0
1456 }
1457 #[doc = "TIMx_BKIN2 input enable"]
1458 #[inline(always)]
1459 pub fn set_bk2ine(&mut self, val: bool) {
1460 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1461 }
1462 #[doc = "TIM_BRK2_CMPx (x=1-8) enable"]
1463 #[inline(always)]
1464 pub const fn bk2cmpe(&self, n: usize) -> bool {
1465 assert!(n < 8usize);
1466 let offs = 1usize + n * 1usize;
1467 let val = (self.0 >> offs) & 0x01;
1468 val != 0
1469 }
1470 #[doc = "TIM_BRK2_CMPx (x=1-8) enable"]
1471 #[inline(always)]
1472 pub fn set_bk2cmpe(&mut self, n: usize, val: bool) {
1473 assert!(n < 8usize);
1474 let offs = 1usize + n * 1usize;
1475 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1476 }
1477 #[doc = "TIMx_BK2IN input polarity"]
1478 #[inline(always)]
1479 pub const fn bk2inp(&self) -> super::vals::Bkinp {
1480 let val = (self.0 >> 9usize) & 0x01;
1481 super::vals::Bkinp::from_bits(val as u8)
1482 }
1483 #[doc = "TIMx_BK2IN input polarity"]
1484 #[inline(always)]
1485 pub fn set_bk2inp(&mut self, val: super::vals::Bkinp) {
1486 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.to_bits() as u32) & 0x01) << 9usize);
1487 }
1488 #[doc = "TIM_BRK2_CMPx (x=1-4) input polarity"]
1489 #[inline(always)]
1490 pub const fn bk2cmpp(&self, n: usize) -> super::vals::Bkinp {
1491 assert!(n < 4usize);
1492 let offs = 10usize + n * 1usize;
1493 let val = (self.0 >> offs) & 0x01;
1494 super::vals::Bkinp::from_bits(val as u8)
1495 }
1496 #[doc = "TIM_BRK2_CMPx (x=1-4) input polarity"]
1497 #[inline(always)]
1498 pub fn set_bk2cmpp(&mut self, n: usize, val: super::vals::Bkinp) {
1499 assert!(n < 4usize);
1500 let offs = 10usize + n * 1usize;
1501 self.0 = (self.0 & !(0x01 << offs)) | (((val.to_bits() as u32) & 0x01) << offs);
1502 }
1503 #[doc = "ocref_clr source selection"]
1504 #[inline(always)]
1505 pub const fn ocrsel(&self) -> u8 {
1506 let val = (self.0 >> 16usize) & 0x07;
1507 val as u8
1508 }
1509 #[doc = "ocref_clr source selection"]
1510 #[inline(always)]
1511 pub fn set_ocrsel(&mut self, val: u8) {
1512 self.0 = (self.0 & !(0x07 << 16usize)) | (((val as u32) & 0x07) << 16usize);
1513 }
1514 }
1515 impl Default for Af2Adv {
1516 #[inline(always)]
1517 fn default() -> Af2Adv {
1518 Af2Adv(0)
1519 }
1520 }
1521 impl core::fmt::Debug for Af2Adv {
1522 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1523 f.debug_struct("Af2Adv")
1524 .field("bk2ine", &self.bk2ine())
1525 .field(
1526 "bk2cmpe",
1527 &[
1528 self.bk2cmpe(0usize),
1529 self.bk2cmpe(1usize),
1530 self.bk2cmpe(2usize),
1531 self.bk2cmpe(3usize),
1532 self.bk2cmpe(4usize),
1533 self.bk2cmpe(5usize),
1534 self.bk2cmpe(6usize),
1535 self.bk2cmpe(7usize),
1536 ],
1537 )
1538 .field("bk2inp", &self.bk2inp())
1539 .field(
1540 "bk2cmpp",
1541 &[
1542 self.bk2cmpp(0usize),
1543 self.bk2cmpp(1usize),
1544 self.bk2cmpp(2usize),
1545 self.bk2cmpp(3usize),
1546 ],
1547 )
1548 .field("ocrsel", &self.ocrsel())
1549 .finish()
1550 }
1551 }
1552 #[cfg(feature = "defmt")]
1553 impl defmt::Format for Af2Adv {
1554 fn format(&self, f: defmt::Formatter) {
1555 #[derive(defmt :: Format)]
1556 struct Af2Adv {
1557 bk2ine: bool,
1558 bk2cmpe: [bool; 8usize],
1559 bk2inp: super::vals::Bkinp,
1560 bk2cmpp: [super::vals::Bkinp; 4usize],
1561 ocrsel: u8,
1562 }
1563 let proxy = Af2Adv {
1564 bk2ine: self.bk2ine(),
1565 bk2cmpe: [
1566 self.bk2cmpe(0usize),
1567 self.bk2cmpe(1usize),
1568 self.bk2cmpe(2usize),
1569 self.bk2cmpe(3usize),
1570 self.bk2cmpe(4usize),
1571 self.bk2cmpe(5usize),
1572 self.bk2cmpe(6usize),
1573 self.bk2cmpe(7usize),
1574 ],
1575 bk2inp: self.bk2inp(),
1576 bk2cmpp: [
1577 self.bk2cmpp(0usize),
1578 self.bk2cmpp(1usize),
1579 self.bk2cmpp(2usize),
1580 self.bk2cmpp(3usize),
1581 ],
1582 ocrsel: self.ocrsel(),
1583 };
1584 defmt::write!(f, "{}", proxy)
1585 }
1586 }
1587 #[doc = "auto-reload register (Dither mode disabled)"]
1588 #[repr(transparent)]
1589 #[derive(Copy, Clone, Eq, PartialEq)]
1590 pub struct ArrCore(pub u32);
1591 impl ArrCore {
1592 #[doc = "Auto-reload value"]
1593 #[inline(always)]
1594 pub const fn arr(&self) -> u16 {
1595 let val = (self.0 >> 0usize) & 0xffff;
1596 val as u16
1597 }
1598 #[doc = "Auto-reload value"]
1599 #[inline(always)]
1600 pub fn set_arr(&mut self, val: u16) {
1601 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
1602 }
1603 }
1604 impl Default for ArrCore {
1605 #[inline(always)]
1606 fn default() -> ArrCore {
1607 ArrCore(0)
1608 }
1609 }
1610 impl core::fmt::Debug for ArrCore {
1611 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1612 f.debug_struct("ArrCore").field("arr", &self.arr()).finish()
1613 }
1614 }
1615 #[cfg(feature = "defmt")]
1616 impl defmt::Format for ArrCore {
1617 fn format(&self, f: defmt::Formatter) {
1618 #[derive(defmt :: Format)]
1619 struct ArrCore {
1620 arr: u16,
1621 }
1622 let proxy = ArrCore { arr: self.arr() };
1623 defmt::write!(f, "{}", proxy)
1624 }
1625 }
1626 #[doc = "auto-reload register (Dither mode enabled)"]
1627 #[repr(transparent)]
1628 #[derive(Copy, Clone, Eq, PartialEq)]
1629 pub struct ArrDitherCore(pub u32);
1630 impl ArrDitherCore {
1631 #[doc = "Dither value"]
1632 #[inline(always)]
1633 pub const fn dither(&self) -> u8 {
1634 let val = (self.0 >> 0usize) & 0x0f;
1635 val as u8
1636 }
1637 #[doc = "Dither value"]
1638 #[inline(always)]
1639 pub fn set_dither(&mut self, val: u8) {
1640 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
1641 }
1642 #[doc = "Auto-reload value"]
1643 #[inline(always)]
1644 pub const fn arr(&self) -> u16 {
1645 let val = (self.0 >> 4usize) & 0xffff;
1646 val as u16
1647 }
1648 #[doc = "Auto-reload value"]
1649 #[inline(always)]
1650 pub fn set_arr(&mut self, val: u16) {
1651 self.0 = (self.0 & !(0xffff << 4usize)) | (((val as u32) & 0xffff) << 4usize);
1652 }
1653 }
1654 impl Default for ArrDitherCore {
1655 #[inline(always)]
1656 fn default() -> ArrDitherCore {
1657 ArrDitherCore(0)
1658 }
1659 }
1660 impl core::fmt::Debug for ArrDitherCore {
1661 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1662 f.debug_struct("ArrDitherCore")
1663 .field("dither", &self.dither())
1664 .field("arr", &self.arr())
1665 .finish()
1666 }
1667 }
1668 #[cfg(feature = "defmt")]
1669 impl defmt::Format for ArrDitherCore {
1670 fn format(&self, f: defmt::Formatter) {
1671 #[derive(defmt :: Format)]
1672 struct ArrDitherCore {
1673 dither: u8,
1674 arr: u16,
1675 }
1676 let proxy = ArrDitherCore {
1677 dither: self.dither(),
1678 arr: self.arr(),
1679 };
1680 defmt::write!(f, "{}", proxy)
1681 }
1682 }
1683 #[doc = "auto-reload register (Dither mode enabled)"]
1684 #[repr(transparent)]
1685 #[derive(Copy, Clone, Eq, PartialEq)]
1686 pub struct ArrDitherGp32(pub u32);
1687 impl ArrDitherGp32 {
1688 #[doc = "Dither value"]
1689 #[inline(always)]
1690 pub const fn dither(&self) -> u8 {
1691 let val = (self.0 >> 0usize) & 0x0f;
1692 val as u8
1693 }
1694 #[doc = "Dither value"]
1695 #[inline(always)]
1696 pub fn set_dither(&mut self, val: u8) {
1697 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
1698 }
1699 #[doc = "Auto-reload value"]
1700 #[inline(always)]
1701 pub const fn arr(&self) -> u32 {
1702 let val = (self.0 >> 4usize) & 0x0fff_ffff;
1703 val as u32
1704 }
1705 #[doc = "Auto-reload value"]
1706 #[inline(always)]
1707 pub fn set_arr(&mut self, val: u32) {
1708 self.0 = (self.0 & !(0x0fff_ffff << 4usize)) | (((val as u32) & 0x0fff_ffff) << 4usize);
1709 }
1710 }
1711 impl Default for ArrDitherGp32 {
1712 #[inline(always)]
1713 fn default() -> ArrDitherGp32 {
1714 ArrDitherGp32(0)
1715 }
1716 }
1717 impl core::fmt::Debug for ArrDitherGp32 {
1718 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1719 f.debug_struct("ArrDitherGp32")
1720 .field("dither", &self.dither())
1721 .field("arr", &self.arr())
1722 .finish()
1723 }
1724 }
1725 #[cfg(feature = "defmt")]
1726 impl defmt::Format for ArrDitherGp32 {
1727 fn format(&self, f: defmt::Formatter) {
1728 #[derive(defmt :: Format)]
1729 struct ArrDitherGp32 {
1730 dither: u8,
1731 arr: u32,
1732 }
1733 let proxy = ArrDitherGp32 {
1734 dither: self.dither(),
1735 arr: self.arr(),
1736 };
1737 defmt::write!(f, "{}", proxy)
1738 }
1739 }
1740 #[doc = "break and dead-time register"]
1741 #[repr(transparent)]
1742 #[derive(Copy, Clone, Eq, PartialEq)]
1743 pub struct Bdtr1chCmp(pub u32);
1744 impl Bdtr1chCmp {
1745 #[doc = "Dead-time generator setup"]
1746 #[inline(always)]
1747 pub const fn dtg(&self) -> u8 {
1748 let val = (self.0 >> 0usize) & 0xff;
1749 val as u8
1750 }
1751 #[doc = "Dead-time generator setup"]
1752 #[inline(always)]
1753 pub fn set_dtg(&mut self, val: u8) {
1754 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
1755 }
1756 #[doc = "Lock configuration"]
1757 #[inline(always)]
1758 pub const fn lock(&self) -> super::vals::Lock {
1759 let val = (self.0 >> 8usize) & 0x03;
1760 super::vals::Lock::from_bits(val as u8)
1761 }
1762 #[doc = "Lock configuration"]
1763 #[inline(always)]
1764 pub fn set_lock(&mut self, val: super::vals::Lock) {
1765 self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize);
1766 }
1767 #[doc = "Off-state selection for Idle mode"]
1768 #[inline(always)]
1769 pub const fn ossi(&self) -> super::vals::Ossi {
1770 let val = (self.0 >> 10usize) & 0x01;
1771 super::vals::Ossi::from_bits(val as u8)
1772 }
1773 #[doc = "Off-state selection for Idle mode"]
1774 #[inline(always)]
1775 pub fn set_ossi(&mut self, val: super::vals::Ossi) {
1776 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.to_bits() as u32) & 0x01) << 10usize);
1777 }
1778 #[doc = "Off-state selection for Run mode"]
1779 #[inline(always)]
1780 pub const fn ossr(&self) -> super::vals::Ossr {
1781 let val = (self.0 >> 11usize) & 0x01;
1782 super::vals::Ossr::from_bits(val as u8)
1783 }
1784 #[doc = "Off-state selection for Run mode"]
1785 #[inline(always)]
1786 pub fn set_ossr(&mut self, val: super::vals::Ossr) {
1787 self.0 = (self.0 & !(0x01 << 11usize)) | (((val.to_bits() as u32) & 0x01) << 11usize);
1788 }
1789 #[doc = "Break x (x=1) enable"]
1790 #[inline(always)]
1791 pub const fn bke(&self, n: usize) -> bool {
1792 assert!(n < 1usize);
1793 let offs = 12usize + n * 12usize;
1794 let val = (self.0 >> offs) & 0x01;
1795 val != 0
1796 }
1797 #[doc = "Break x (x=1) enable"]
1798 #[inline(always)]
1799 pub fn set_bke(&mut self, n: usize, val: bool) {
1800 assert!(n < 1usize);
1801 let offs = 12usize + n * 12usize;
1802 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
1803 }
1804 #[doc = "Break x (x=1) polarity"]
1805 #[inline(always)]
1806 pub const fn bkp(&self, n: usize) -> super::vals::Bkp {
1807 assert!(n < 1usize);
1808 let offs = 13usize + n * 12usize;
1809 let val = (self.0 >> offs) & 0x01;
1810 super::vals::Bkp::from_bits(val as u8)
1811 }
1812 #[doc = "Break x (x=1) polarity"]
1813 #[inline(always)]
1814 pub fn set_bkp(&mut self, n: usize, val: super::vals::Bkp) {
1815 assert!(n < 1usize);
1816 let offs = 13usize + n * 12usize;
1817 self.0 = (self.0 & !(0x01 << offs)) | (((val.to_bits() as u32) & 0x01) << offs);
1818 }
1819 #[doc = "Automatic output enable"]
1820 #[inline(always)]
1821 pub const fn aoe(&self) -> bool {
1822 let val = (self.0 >> 14usize) & 0x01;
1823 val != 0
1824 }
1825 #[doc = "Automatic output enable"]
1826 #[inline(always)]
1827 pub fn set_aoe(&mut self, val: bool) {
1828 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
1829 }
1830 #[doc = "Main output enable"]
1831 #[inline(always)]
1832 pub const fn moe(&self) -> bool {
1833 let val = (self.0 >> 15usize) & 0x01;
1834 val != 0
1835 }
1836 #[doc = "Main output enable"]
1837 #[inline(always)]
1838 pub fn set_moe(&mut self, val: bool) {
1839 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
1840 }
1841 #[doc = "Break x (x=1) filter"]
1842 #[inline(always)]
1843 pub const fn bkf(&self, n: usize) -> super::vals::FilterValue {
1844 assert!(n < 1usize);
1845 let offs = 16usize + n * 4usize;
1846 let val = (self.0 >> offs) & 0x0f;
1847 super::vals::FilterValue::from_bits(val as u8)
1848 }
1849 #[doc = "Break x (x=1) filter"]
1850 #[inline(always)]
1851 pub fn set_bkf(&mut self, n: usize, val: super::vals::FilterValue) {
1852 assert!(n < 1usize);
1853 let offs = 16usize + n * 4usize;
1854 self.0 = (self.0 & !(0x0f << offs)) | (((val.to_bits() as u32) & 0x0f) << offs);
1855 }
1856 #[doc = "Break x (x=1) Disarm"]
1857 #[inline(always)]
1858 pub const fn bkdsrm(&self, n: usize) -> super::vals::Bkdsrm {
1859 assert!(n < 1usize);
1860 let offs = 26usize + n * 1usize;
1861 let val = (self.0 >> offs) & 0x01;
1862 super::vals::Bkdsrm::from_bits(val as u8)
1863 }
1864 #[doc = "Break x (x=1) Disarm"]
1865 #[inline(always)]
1866 pub fn set_bkdsrm(&mut self, n: usize, val: super::vals::Bkdsrm) {
1867 assert!(n < 1usize);
1868 let offs = 26usize + n * 1usize;
1869 self.0 = (self.0 & !(0x01 << offs)) | (((val.to_bits() as u32) & 0x01) << offs);
1870 }
1871 #[doc = "Break x (x=1) bidirectional"]
1872 #[inline(always)]
1873 pub const fn bkbid(&self, n: usize) -> super::vals::Bkbid {
1874 assert!(n < 1usize);
1875 let offs = 28usize + n * 1usize;
1876 let val = (self.0 >> offs) & 0x01;
1877 super::vals::Bkbid::from_bits(val as u8)
1878 }
1879 #[doc = "Break x (x=1) bidirectional"]
1880 #[inline(always)]
1881 pub fn set_bkbid(&mut self, n: usize, val: super::vals::Bkbid) {
1882 assert!(n < 1usize);
1883 let offs = 28usize + n * 1usize;
1884 self.0 = (self.0 & !(0x01 << offs)) | (((val.to_bits() as u32) & 0x01) << offs);
1885 }
1886 }
1887 impl Default for Bdtr1chCmp {
1888 #[inline(always)]
1889 fn default() -> Bdtr1chCmp {
1890 Bdtr1chCmp(0)
1891 }
1892 }
1893 impl core::fmt::Debug for Bdtr1chCmp {
1894 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1895 f.debug_struct("Bdtr1chCmp")
1896 .field("dtg", &self.dtg())
1897 .field("lock", &self.lock())
1898 .field("ossi", &self.ossi())
1899 .field("ossr", &self.ossr())
1900 .field("bke", &[self.bke(0usize)])
1901 .field("bkp", &[self.bkp(0usize)])
1902 .field("aoe", &self.aoe())
1903 .field("moe", &self.moe())
1904 .field("bkf", &[self.bkf(0usize)])
1905 .field("bkdsrm", &[self.bkdsrm(0usize)])
1906 .field("bkbid", &[self.bkbid(0usize)])
1907 .finish()
1908 }
1909 }
1910 #[cfg(feature = "defmt")]
1911 impl defmt::Format for Bdtr1chCmp {
1912 fn format(&self, f: defmt::Formatter) {
1913 #[derive(defmt :: Format)]
1914 struct Bdtr1chCmp {
1915 dtg: u8,
1916 lock: super::vals::Lock,
1917 ossi: super::vals::Ossi,
1918 ossr: super::vals::Ossr,
1919 bke: [bool; 1usize],
1920 bkp: [super::vals::Bkp; 1usize],
1921 aoe: bool,
1922 moe: bool,
1923 bkf: [super::vals::FilterValue; 1usize],
1924 bkdsrm: [super::vals::Bkdsrm; 1usize],
1925 bkbid: [super::vals::Bkbid; 1usize],
1926 }
1927 let proxy = Bdtr1chCmp {
1928 dtg: self.dtg(),
1929 lock: self.lock(),
1930 ossi: self.ossi(),
1931 ossr: self.ossr(),
1932 bke: [self.bke(0usize)],
1933 bkp: [self.bkp(0usize)],
1934 aoe: self.aoe(),
1935 moe: self.moe(),
1936 bkf: [self.bkf(0usize)],
1937 bkdsrm: [self.bkdsrm(0usize)],
1938 bkbid: [self.bkbid(0usize)],
1939 };
1940 defmt::write!(f, "{}", proxy)
1941 }
1942 }
1943 #[doc = "break and dead-time register"]
1944 #[repr(transparent)]
1945 #[derive(Copy, Clone, Eq, PartialEq)]
1946 pub struct BdtrAdv(pub u32);
1947 impl BdtrAdv {
1948 #[doc = "Dead-time generator setup"]
1949 #[inline(always)]
1950 pub const fn dtg(&self) -> u8 {
1951 let val = (self.0 >> 0usize) & 0xff;
1952 val as u8
1953 }
1954 #[doc = "Dead-time generator setup"]
1955 #[inline(always)]
1956 pub fn set_dtg(&mut self, val: u8) {
1957 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
1958 }
1959 #[doc = "Lock configuration"]
1960 #[inline(always)]
1961 pub const fn lock(&self) -> super::vals::Lock {
1962 let val = (self.0 >> 8usize) & 0x03;
1963 super::vals::Lock::from_bits(val as u8)
1964 }
1965 #[doc = "Lock configuration"]
1966 #[inline(always)]
1967 pub fn set_lock(&mut self, val: super::vals::Lock) {
1968 self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize);
1969 }
1970 #[doc = "Off-state selection for Idle mode"]
1971 #[inline(always)]
1972 pub const fn ossi(&self) -> super::vals::Ossi {
1973 let val = (self.0 >> 10usize) & 0x01;
1974 super::vals::Ossi::from_bits(val as u8)
1975 }
1976 #[doc = "Off-state selection for Idle mode"]
1977 #[inline(always)]
1978 pub fn set_ossi(&mut self, val: super::vals::Ossi) {
1979 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.to_bits() as u32) & 0x01) << 10usize);
1980 }
1981 #[doc = "Off-state selection for Run mode"]
1982 #[inline(always)]
1983 pub const fn ossr(&self) -> super::vals::Ossr {
1984 let val = (self.0 >> 11usize) & 0x01;
1985 super::vals::Ossr::from_bits(val as u8)
1986 }
1987 #[doc = "Off-state selection for Run mode"]
1988 #[inline(always)]
1989 pub fn set_ossr(&mut self, val: super::vals::Ossr) {
1990 self.0 = (self.0 & !(0x01 << 11usize)) | (((val.to_bits() as u32) & 0x01) << 11usize);
1991 }
1992 #[doc = "Break x (x=1,2) enable"]
1993 #[inline(always)]
1994 pub const fn bke(&self, n: usize) -> bool {
1995 assert!(n < 2usize);
1996 let offs = 12usize + n * 12usize;
1997 let val = (self.0 >> offs) & 0x01;
1998 val != 0
1999 }
2000 #[doc = "Break x (x=1,2) enable"]
2001 #[inline(always)]
2002 pub fn set_bke(&mut self, n: usize, val: bool) {
2003 assert!(n < 2usize);
2004 let offs = 12usize + n * 12usize;
2005 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2006 }
2007 #[doc = "Break x (x=1,2) polarity"]
2008 #[inline(always)]
2009 pub const fn bkp(&self, n: usize) -> super::vals::Bkp {
2010 assert!(n < 2usize);
2011 let offs = 13usize + n * 12usize;
2012 let val = (self.0 >> offs) & 0x01;
2013 super::vals::Bkp::from_bits(val as u8)
2014 }
2015 #[doc = "Break x (x=1,2) polarity"]
2016 #[inline(always)]
2017 pub fn set_bkp(&mut self, n: usize, val: super::vals::Bkp) {
2018 assert!(n < 2usize);
2019 let offs = 13usize + n * 12usize;
2020 self.0 = (self.0 & !(0x01 << offs)) | (((val.to_bits() as u32) & 0x01) << offs);
2021 }
2022 #[doc = "Automatic output enable"]
2023 #[inline(always)]
2024 pub const fn aoe(&self) -> bool {
2025 let val = (self.0 >> 14usize) & 0x01;
2026 val != 0
2027 }
2028 #[doc = "Automatic output enable"]
2029 #[inline(always)]
2030 pub fn set_aoe(&mut self, val: bool) {
2031 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
2032 }
2033 #[doc = "Main output enable"]
2034 #[inline(always)]
2035 pub const fn moe(&self) -> bool {
2036 let val = (self.0 >> 15usize) & 0x01;
2037 val != 0
2038 }
2039 #[doc = "Main output enable"]
2040 #[inline(always)]
2041 pub fn set_moe(&mut self, val: bool) {
2042 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
2043 }
2044 #[doc = "Break x (x=1,2) filter"]
2045 #[inline(always)]
2046 pub const fn bkf(&self, n: usize) -> super::vals::FilterValue {
2047 assert!(n < 2usize);
2048 let offs = 16usize + n * 4usize;
2049 let val = (self.0 >> offs) & 0x0f;
2050 super::vals::FilterValue::from_bits(val as u8)
2051 }
2052 #[doc = "Break x (x=1,2) filter"]
2053 #[inline(always)]
2054 pub fn set_bkf(&mut self, n: usize, val: super::vals::FilterValue) {
2055 assert!(n < 2usize);
2056 let offs = 16usize + n * 4usize;
2057 self.0 = (self.0 & !(0x0f << offs)) | (((val.to_bits() as u32) & 0x0f) << offs);
2058 }
2059 #[doc = "Break x (x=1,2) Disarm"]
2060 #[inline(always)]
2061 pub const fn bkdsrm(&self, n: usize) -> super::vals::Bkdsrm {
2062 assert!(n < 2usize);
2063 let offs = 26usize + n * 1usize;
2064 let val = (self.0 >> offs) & 0x01;
2065 super::vals::Bkdsrm::from_bits(val as u8)
2066 }
2067 #[doc = "Break x (x=1,2) Disarm"]
2068 #[inline(always)]
2069 pub fn set_bkdsrm(&mut self, n: usize, val: super::vals::Bkdsrm) {
2070 assert!(n < 2usize);
2071 let offs = 26usize + n * 1usize;
2072 self.0 = (self.0 & !(0x01 << offs)) | (((val.to_bits() as u32) & 0x01) << offs);
2073 }
2074 #[doc = "Break x (x=1,2) bidirectional"]
2075 #[inline(always)]
2076 pub const fn bkbid(&self, n: usize) -> super::vals::Bkbid {
2077 assert!(n < 2usize);
2078 let offs = 28usize + n * 1usize;
2079 let val = (self.0 >> offs) & 0x01;
2080 super::vals::Bkbid::from_bits(val as u8)
2081 }
2082 #[doc = "Break x (x=1,2) bidirectional"]
2083 #[inline(always)]
2084 pub fn set_bkbid(&mut self, n: usize, val: super::vals::Bkbid) {
2085 assert!(n < 2usize);
2086 let offs = 28usize + n * 1usize;
2087 self.0 = (self.0 & !(0x01 << offs)) | (((val.to_bits() as u32) & 0x01) << offs);
2088 }
2089 }
2090 impl Default for BdtrAdv {
2091 #[inline(always)]
2092 fn default() -> BdtrAdv {
2093 BdtrAdv(0)
2094 }
2095 }
2096 impl core::fmt::Debug for BdtrAdv {
2097 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2098 f.debug_struct("BdtrAdv")
2099 .field("dtg", &self.dtg())
2100 .field("lock", &self.lock())
2101 .field("ossi", &self.ossi())
2102 .field("ossr", &self.ossr())
2103 .field("bke", &[self.bke(0usize), self.bke(1usize)])
2104 .field("bkp", &[self.bkp(0usize), self.bkp(1usize)])
2105 .field("aoe", &self.aoe())
2106 .field("moe", &self.moe())
2107 .field("bkf", &[self.bkf(0usize), self.bkf(1usize)])
2108 .field("bkdsrm", &[self.bkdsrm(0usize), self.bkdsrm(1usize)])
2109 .field("bkbid", &[self.bkbid(0usize), self.bkbid(1usize)])
2110 .finish()
2111 }
2112 }
2113 #[cfg(feature = "defmt")]
2114 impl defmt::Format for BdtrAdv {
2115 fn format(&self, f: defmt::Formatter) {
2116 #[derive(defmt :: Format)]
2117 struct BdtrAdv {
2118 dtg: u8,
2119 lock: super::vals::Lock,
2120 ossi: super::vals::Ossi,
2121 ossr: super::vals::Ossr,
2122 bke: [bool; 2usize],
2123 bkp: [super::vals::Bkp; 2usize],
2124 aoe: bool,
2125 moe: bool,
2126 bkf: [super::vals::FilterValue; 2usize],
2127 bkdsrm: [super::vals::Bkdsrm; 2usize],
2128 bkbid: [super::vals::Bkbid; 2usize],
2129 }
2130 let proxy = BdtrAdv {
2131 dtg: self.dtg(),
2132 lock: self.lock(),
2133 ossi: self.ossi(),
2134 ossr: self.ossr(),
2135 bke: [self.bke(0usize), self.bke(1usize)],
2136 bkp: [self.bkp(0usize), self.bkp(1usize)],
2137 aoe: self.aoe(),
2138 moe: self.moe(),
2139 bkf: [self.bkf(0usize), self.bkf(1usize)],
2140 bkdsrm: [self.bkdsrm(0usize), self.bkdsrm(1usize)],
2141 bkbid: [self.bkbid(0usize), self.bkbid(1usize)],
2142 };
2143 defmt::write!(f, "{}", proxy)
2144 }
2145 }
2146 #[doc = "capture/compare enable register"]
2147 #[repr(transparent)]
2148 #[derive(Copy, Clone, Eq, PartialEq)]
2149 pub struct Ccer1ch(pub u32);
2150 impl Ccer1ch {
2151 #[doc = "Capture/Compare x (x=1) output enable"]
2152 #[inline(always)]
2153 pub const fn cce(&self, n: usize) -> bool {
2154 assert!(n < 1usize);
2155 let offs = 0usize + n * 4usize;
2156 let val = (self.0 >> offs) & 0x01;
2157 val != 0
2158 }
2159 #[doc = "Capture/Compare x (x=1) output enable"]
2160 #[inline(always)]
2161 pub fn set_cce(&mut self, n: usize, val: bool) {
2162 assert!(n < 1usize);
2163 let offs = 0usize + n * 4usize;
2164 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2165 }
2166 #[doc = "Capture/Compare x (x=1) output Polarity"]
2167 #[inline(always)]
2168 pub const fn ccp(&self, n: usize) -> bool {
2169 assert!(n < 1usize);
2170 let offs = 1usize + n * 4usize;
2171 let val = (self.0 >> offs) & 0x01;
2172 val != 0
2173 }
2174 #[doc = "Capture/Compare x (x=1) output Polarity"]
2175 #[inline(always)]
2176 pub fn set_ccp(&mut self, n: usize, val: bool) {
2177 assert!(n < 1usize);
2178 let offs = 1usize + n * 4usize;
2179 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2180 }
2181 #[doc = "Capture/Compare x (x=1) output Polarity"]
2182 #[inline(always)]
2183 pub const fn ccnp(&self, n: usize) -> bool {
2184 assert!(n < 1usize);
2185 let offs = 3usize + n * 4usize;
2186 let val = (self.0 >> offs) & 0x01;
2187 val != 0
2188 }
2189 #[doc = "Capture/Compare x (x=1) output Polarity"]
2190 #[inline(always)]
2191 pub fn set_ccnp(&mut self, n: usize, val: bool) {
2192 assert!(n < 1usize);
2193 let offs = 3usize + n * 4usize;
2194 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2195 }
2196 }
2197 impl Default for Ccer1ch {
2198 #[inline(always)]
2199 fn default() -> Ccer1ch {
2200 Ccer1ch(0)
2201 }
2202 }
2203 impl core::fmt::Debug for Ccer1ch {
2204 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2205 f.debug_struct("Ccer1ch")
2206 .field("cce", &[self.cce(0usize)])
2207 .field("ccp", &[self.ccp(0usize)])
2208 .field("ccnp", &[self.ccnp(0usize)])
2209 .finish()
2210 }
2211 }
2212 #[cfg(feature = "defmt")]
2213 impl defmt::Format for Ccer1ch {
2214 fn format(&self, f: defmt::Formatter) {
2215 #[derive(defmt :: Format)]
2216 struct Ccer1ch {
2217 cce: [bool; 1usize],
2218 ccp: [bool; 1usize],
2219 ccnp: [bool; 1usize],
2220 }
2221 let proxy = Ccer1ch {
2222 cce: [self.cce(0usize)],
2223 ccp: [self.ccp(0usize)],
2224 ccnp: [self.ccnp(0usize)],
2225 };
2226 defmt::write!(f, "{}", proxy)
2227 }
2228 }
2229 #[doc = "capture/compare enable register"]
2230 #[repr(transparent)]
2231 #[derive(Copy, Clone, Eq, PartialEq)]
2232 pub struct Ccer1chCmp(pub u32);
2233 impl Ccer1chCmp {
2234 #[doc = "Capture/Compare x (x=1) output enable"]
2235 #[inline(always)]
2236 pub const fn cce(&self, n: usize) -> bool {
2237 assert!(n < 1usize);
2238 let offs = 0usize + n * 4usize;
2239 let val = (self.0 >> offs) & 0x01;
2240 val != 0
2241 }
2242 #[doc = "Capture/Compare x (x=1) output enable"]
2243 #[inline(always)]
2244 pub fn set_cce(&mut self, n: usize, val: bool) {
2245 assert!(n < 1usize);
2246 let offs = 0usize + n * 4usize;
2247 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2248 }
2249 #[doc = "Capture/Compare x (x=1) output Polarity"]
2250 #[inline(always)]
2251 pub const fn ccp(&self, n: usize) -> bool {
2252 assert!(n < 1usize);
2253 let offs = 1usize + n * 4usize;
2254 let val = (self.0 >> offs) & 0x01;
2255 val != 0
2256 }
2257 #[doc = "Capture/Compare x (x=1) output Polarity"]
2258 #[inline(always)]
2259 pub fn set_ccp(&mut self, n: usize, val: bool) {
2260 assert!(n < 1usize);
2261 let offs = 1usize + n * 4usize;
2262 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2263 }
2264 #[doc = "Capture/Compare x (x=1) complementary output enable"]
2265 #[inline(always)]
2266 pub const fn ccne(&self, n: usize) -> bool {
2267 assert!(n < 1usize);
2268 let offs = 2usize + n * 4usize;
2269 let val = (self.0 >> offs) & 0x01;
2270 val != 0
2271 }
2272 #[doc = "Capture/Compare x (x=1) complementary output enable"]
2273 #[inline(always)]
2274 pub fn set_ccne(&mut self, n: usize, val: bool) {
2275 assert!(n < 1usize);
2276 let offs = 2usize + n * 4usize;
2277 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2278 }
2279 #[doc = "Capture/Compare x (x=1) output Polarity"]
2280 #[inline(always)]
2281 pub const fn ccnp(&self, n: usize) -> bool {
2282 assert!(n < 1usize);
2283 let offs = 3usize + n * 4usize;
2284 let val = (self.0 >> offs) & 0x01;
2285 val != 0
2286 }
2287 #[doc = "Capture/Compare x (x=1) output Polarity"]
2288 #[inline(always)]
2289 pub fn set_ccnp(&mut self, n: usize, val: bool) {
2290 assert!(n < 1usize);
2291 let offs = 3usize + n * 4usize;
2292 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2293 }
2294 }
2295 impl Default for Ccer1chCmp {
2296 #[inline(always)]
2297 fn default() -> Ccer1chCmp {
2298 Ccer1chCmp(0)
2299 }
2300 }
2301 impl core::fmt::Debug for Ccer1chCmp {
2302 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2303 f.debug_struct("Ccer1chCmp")
2304 .field("cce", &[self.cce(0usize)])
2305 .field("ccp", &[self.ccp(0usize)])
2306 .field("ccne", &[self.ccne(0usize)])
2307 .field("ccnp", &[self.ccnp(0usize)])
2308 .finish()
2309 }
2310 }
2311 #[cfg(feature = "defmt")]
2312 impl defmt::Format for Ccer1chCmp {
2313 fn format(&self, f: defmt::Formatter) {
2314 #[derive(defmt :: Format)]
2315 struct Ccer1chCmp {
2316 cce: [bool; 1usize],
2317 ccp: [bool; 1usize],
2318 ccne: [bool; 1usize],
2319 ccnp: [bool; 1usize],
2320 }
2321 let proxy = Ccer1chCmp {
2322 cce: [self.cce(0usize)],
2323 ccp: [self.ccp(0usize)],
2324 ccne: [self.ccne(0usize)],
2325 ccnp: [self.ccnp(0usize)],
2326 };
2327 defmt::write!(f, "{}", proxy)
2328 }
2329 }
2330 #[doc = "capture/compare enable register"]
2331 #[repr(transparent)]
2332 #[derive(Copy, Clone, Eq, PartialEq)]
2333 pub struct Ccer2ch(pub u32);
2334 impl Ccer2ch {
2335 #[doc = "Capture/Compare x (x=1-2) output enable"]
2336 #[inline(always)]
2337 pub const fn cce(&self, n: usize) -> bool {
2338 assert!(n < 2usize);
2339 let offs = 0usize + n * 4usize;
2340 let val = (self.0 >> offs) & 0x01;
2341 val != 0
2342 }
2343 #[doc = "Capture/Compare x (x=1-2) output enable"]
2344 #[inline(always)]
2345 pub fn set_cce(&mut self, n: usize, val: bool) {
2346 assert!(n < 2usize);
2347 let offs = 0usize + n * 4usize;
2348 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2349 }
2350 #[doc = "Capture/Compare x (x=1-2) output Polarity"]
2351 #[inline(always)]
2352 pub const fn ccp(&self, n: usize) -> bool {
2353 assert!(n < 2usize);
2354 let offs = 1usize + n * 4usize;
2355 let val = (self.0 >> offs) & 0x01;
2356 val != 0
2357 }
2358 #[doc = "Capture/Compare x (x=1-2) output Polarity"]
2359 #[inline(always)]
2360 pub fn set_ccp(&mut self, n: usize, val: bool) {
2361 assert!(n < 2usize);
2362 let offs = 1usize + n * 4usize;
2363 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2364 }
2365 #[doc = "Capture/Compare x (x=1-2) output Polarity"]
2366 #[inline(always)]
2367 pub const fn ccnp(&self, n: usize) -> bool {
2368 assert!(n < 2usize);
2369 let offs = 3usize + n * 4usize;
2370 let val = (self.0 >> offs) & 0x01;
2371 val != 0
2372 }
2373 #[doc = "Capture/Compare x (x=1-2) output Polarity"]
2374 #[inline(always)]
2375 pub fn set_ccnp(&mut self, n: usize, val: bool) {
2376 assert!(n < 2usize);
2377 let offs = 3usize + n * 4usize;
2378 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2379 }
2380 }
2381 impl Default for Ccer2ch {
2382 #[inline(always)]
2383 fn default() -> Ccer2ch {
2384 Ccer2ch(0)
2385 }
2386 }
2387 impl core::fmt::Debug for Ccer2ch {
2388 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2389 f.debug_struct("Ccer2ch")
2390 .field("cce", &[self.cce(0usize), self.cce(1usize)])
2391 .field("ccp", &[self.ccp(0usize), self.ccp(1usize)])
2392 .field("ccnp", &[self.ccnp(0usize), self.ccnp(1usize)])
2393 .finish()
2394 }
2395 }
2396 #[cfg(feature = "defmt")]
2397 impl defmt::Format for Ccer2ch {
2398 fn format(&self, f: defmt::Formatter) {
2399 #[derive(defmt :: Format)]
2400 struct Ccer2ch {
2401 cce: [bool; 2usize],
2402 ccp: [bool; 2usize],
2403 ccnp: [bool; 2usize],
2404 }
2405 let proxy = Ccer2ch {
2406 cce: [self.cce(0usize), self.cce(1usize)],
2407 ccp: [self.ccp(0usize), self.ccp(1usize)],
2408 ccnp: [self.ccnp(0usize), self.ccnp(1usize)],
2409 };
2410 defmt::write!(f, "{}", proxy)
2411 }
2412 }
2413 #[doc = "capture/compare enable register"]
2414 #[repr(transparent)]
2415 #[derive(Copy, Clone, Eq, PartialEq)]
2416 pub struct Ccer2chCmp(pub u32);
2417 impl Ccer2chCmp {
2418 #[doc = "Capture/Compare x (x=1-2) output enable"]
2419 #[inline(always)]
2420 pub const fn cce(&self, n: usize) -> bool {
2421 assert!(n < 2usize);
2422 let offs = 0usize + n * 4usize;
2423 let val = (self.0 >> offs) & 0x01;
2424 val != 0
2425 }
2426 #[doc = "Capture/Compare x (x=1-2) output enable"]
2427 #[inline(always)]
2428 pub fn set_cce(&mut self, n: usize, val: bool) {
2429 assert!(n < 2usize);
2430 let offs = 0usize + n * 4usize;
2431 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2432 }
2433 #[doc = "Capture/Compare x (x=1-2) output Polarity"]
2434 #[inline(always)]
2435 pub const fn ccp(&self, n: usize) -> bool {
2436 assert!(n < 2usize);
2437 let offs = 1usize + n * 4usize;
2438 let val = (self.0 >> offs) & 0x01;
2439 val != 0
2440 }
2441 #[doc = "Capture/Compare x (x=1-2) output Polarity"]
2442 #[inline(always)]
2443 pub fn set_ccp(&mut self, n: usize, val: bool) {
2444 assert!(n < 2usize);
2445 let offs = 1usize + n * 4usize;
2446 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2447 }
2448 #[doc = "Capture/Compare x (x=1) complementary output enable"]
2449 #[inline(always)]
2450 pub const fn ccne(&self, n: usize) -> bool {
2451 assert!(n < 1usize);
2452 let offs = 2usize + n * 4usize;
2453 let val = (self.0 >> offs) & 0x01;
2454 val != 0
2455 }
2456 #[doc = "Capture/Compare x (x=1) complementary output enable"]
2457 #[inline(always)]
2458 pub fn set_ccne(&mut self, n: usize, val: bool) {
2459 assert!(n < 1usize);
2460 let offs = 2usize + n * 4usize;
2461 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2462 }
2463 #[doc = "Capture/Compare x (x=1-2) output Polarity"]
2464 #[inline(always)]
2465 pub const fn ccnp(&self, n: usize) -> bool {
2466 assert!(n < 2usize);
2467 let offs = 3usize + n * 4usize;
2468 let val = (self.0 >> offs) & 0x01;
2469 val != 0
2470 }
2471 #[doc = "Capture/Compare x (x=1-2) output Polarity"]
2472 #[inline(always)]
2473 pub fn set_ccnp(&mut self, n: usize, val: bool) {
2474 assert!(n < 2usize);
2475 let offs = 3usize + n * 4usize;
2476 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2477 }
2478 }
2479 impl Default for Ccer2chCmp {
2480 #[inline(always)]
2481 fn default() -> Ccer2chCmp {
2482 Ccer2chCmp(0)
2483 }
2484 }
2485 impl core::fmt::Debug for Ccer2chCmp {
2486 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2487 f.debug_struct("Ccer2chCmp")
2488 .field("cce", &[self.cce(0usize), self.cce(1usize)])
2489 .field("ccp", &[self.ccp(0usize), self.ccp(1usize)])
2490 .field("ccne", &[self.ccne(0usize)])
2491 .field("ccnp", &[self.ccnp(0usize), self.ccnp(1usize)])
2492 .finish()
2493 }
2494 }
2495 #[cfg(feature = "defmt")]
2496 impl defmt::Format for Ccer2chCmp {
2497 fn format(&self, f: defmt::Formatter) {
2498 #[derive(defmt :: Format)]
2499 struct Ccer2chCmp {
2500 cce: [bool; 2usize],
2501 ccp: [bool; 2usize],
2502 ccne: [bool; 1usize],
2503 ccnp: [bool; 2usize],
2504 }
2505 let proxy = Ccer2chCmp {
2506 cce: [self.cce(0usize), self.cce(1usize)],
2507 ccp: [self.ccp(0usize), self.ccp(1usize)],
2508 ccne: [self.ccne(0usize)],
2509 ccnp: [self.ccnp(0usize), self.ccnp(1usize)],
2510 };
2511 defmt::write!(f, "{}", proxy)
2512 }
2513 }
2514 #[doc = "capture/compare enable register"]
2515 #[repr(transparent)]
2516 #[derive(Copy, Clone, Eq, PartialEq)]
2517 pub struct CcerAdv(pub u32);
2518 impl CcerAdv {
2519 #[doc = "Capture/Compare x (x=1-6) output enable"]
2520 #[inline(always)]
2521 pub const fn cce(&self, n: usize) -> bool {
2522 assert!(n < 6usize);
2523 let offs = 0usize + n * 4usize;
2524 let val = (self.0 >> offs) & 0x01;
2525 val != 0
2526 }
2527 #[doc = "Capture/Compare x (x=1-6) output enable"]
2528 #[inline(always)]
2529 pub fn set_cce(&mut self, n: usize, val: bool) {
2530 assert!(n < 6usize);
2531 let offs = 0usize + n * 4usize;
2532 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2533 }
2534 #[doc = "Capture/Compare x (x=1-6) output Polarity"]
2535 #[inline(always)]
2536 pub const fn ccp(&self, n: usize) -> bool {
2537 assert!(n < 6usize);
2538 let offs = 1usize + n * 4usize;
2539 let val = (self.0 >> offs) & 0x01;
2540 val != 0
2541 }
2542 #[doc = "Capture/Compare x (x=1-6) output Polarity"]
2543 #[inline(always)]
2544 pub fn set_ccp(&mut self, n: usize, val: bool) {
2545 assert!(n < 6usize);
2546 let offs = 1usize + n * 4usize;
2547 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2548 }
2549 #[doc = "Capture/Compare x (x=1-4) complementary output enable"]
2550 #[inline(always)]
2551 pub const fn ccne(&self, n: usize) -> bool {
2552 assert!(n < 4usize);
2553 let offs = 2usize + n * 4usize;
2554 let val = (self.0 >> offs) & 0x01;
2555 val != 0
2556 }
2557 #[doc = "Capture/Compare x (x=1-4) complementary output enable"]
2558 #[inline(always)]
2559 pub fn set_ccne(&mut self, n: usize, val: bool) {
2560 assert!(n < 4usize);
2561 let offs = 2usize + n * 4usize;
2562 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2563 }
2564 #[doc = "Capture/Compare x (x=1-4) output Polarity"]
2565 #[inline(always)]
2566 pub const fn ccnp(&self, n: usize) -> bool {
2567 assert!(n < 4usize);
2568 let offs = 3usize + n * 4usize;
2569 let val = (self.0 >> offs) & 0x01;
2570 val != 0
2571 }
2572 #[doc = "Capture/Compare x (x=1-4) output Polarity"]
2573 #[inline(always)]
2574 pub fn set_ccnp(&mut self, n: usize, val: bool) {
2575 assert!(n < 4usize);
2576 let offs = 3usize + n * 4usize;
2577 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2578 }
2579 }
2580 impl Default for CcerAdv {
2581 #[inline(always)]
2582 fn default() -> CcerAdv {
2583 CcerAdv(0)
2584 }
2585 }
2586 impl core::fmt::Debug for CcerAdv {
2587 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2588 f.debug_struct("CcerAdv")
2589 .field(
2590 "cce",
2591 &[
2592 self.cce(0usize),
2593 self.cce(1usize),
2594 self.cce(2usize),
2595 self.cce(3usize),
2596 self.cce(4usize),
2597 self.cce(5usize),
2598 ],
2599 )
2600 .field(
2601 "ccp",
2602 &[
2603 self.ccp(0usize),
2604 self.ccp(1usize),
2605 self.ccp(2usize),
2606 self.ccp(3usize),
2607 self.ccp(4usize),
2608 self.ccp(5usize),
2609 ],
2610 )
2611 .field(
2612 "ccne",
2613 &[
2614 self.ccne(0usize),
2615 self.ccne(1usize),
2616 self.ccne(2usize),
2617 self.ccne(3usize),
2618 ],
2619 )
2620 .field(
2621 "ccnp",
2622 &[
2623 self.ccnp(0usize),
2624 self.ccnp(1usize),
2625 self.ccnp(2usize),
2626 self.ccnp(3usize),
2627 ],
2628 )
2629 .finish()
2630 }
2631 }
2632 #[cfg(feature = "defmt")]
2633 impl defmt::Format for CcerAdv {
2634 fn format(&self, f: defmt::Formatter) {
2635 #[derive(defmt :: Format)]
2636 struct CcerAdv {
2637 cce: [bool; 6usize],
2638 ccp: [bool; 6usize],
2639 ccne: [bool; 4usize],
2640 ccnp: [bool; 4usize],
2641 }
2642 let proxy = CcerAdv {
2643 cce: [
2644 self.cce(0usize),
2645 self.cce(1usize),
2646 self.cce(2usize),
2647 self.cce(3usize),
2648 self.cce(4usize),
2649 self.cce(5usize),
2650 ],
2651 ccp: [
2652 self.ccp(0usize),
2653 self.ccp(1usize),
2654 self.ccp(2usize),
2655 self.ccp(3usize),
2656 self.ccp(4usize),
2657 self.ccp(5usize),
2658 ],
2659 ccne: [
2660 self.ccne(0usize),
2661 self.ccne(1usize),
2662 self.ccne(2usize),
2663 self.ccne(3usize),
2664 ],
2665 ccnp: [
2666 self.ccnp(0usize),
2667 self.ccnp(1usize),
2668 self.ccnp(2usize),
2669 self.ccnp(3usize),
2670 ],
2671 };
2672 defmt::write!(f, "{}", proxy)
2673 }
2674 }
2675 #[doc = "capture/compare enable register"]
2676 #[repr(transparent)]
2677 #[derive(Copy, Clone, Eq, PartialEq)]
2678 pub struct CcerGp16(pub u32);
2679 impl CcerGp16 {
2680 #[doc = "Capture/Compare x (x=1-4) output enable"]
2681 #[inline(always)]
2682 pub const fn cce(&self, n: usize) -> bool {
2683 assert!(n < 4usize);
2684 let offs = 0usize + n * 4usize;
2685 let val = (self.0 >> offs) & 0x01;
2686 val != 0
2687 }
2688 #[doc = "Capture/Compare x (x=1-4) output enable"]
2689 #[inline(always)]
2690 pub fn set_cce(&mut self, n: usize, val: bool) {
2691 assert!(n < 4usize);
2692 let offs = 0usize + n * 4usize;
2693 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2694 }
2695 #[doc = "Capture/Compare x (x=1-4) output Polarity"]
2696 #[inline(always)]
2697 pub const fn ccp(&self, n: usize) -> bool {
2698 assert!(n < 4usize);
2699 let offs = 1usize + n * 4usize;
2700 let val = (self.0 >> offs) & 0x01;
2701 val != 0
2702 }
2703 #[doc = "Capture/Compare x (x=1-4) output Polarity"]
2704 #[inline(always)]
2705 pub fn set_ccp(&mut self, n: usize, val: bool) {
2706 assert!(n < 4usize);
2707 let offs = 1usize + n * 4usize;
2708 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2709 }
2710 #[doc = "Capture/Compare x (x=1-4) output Polarity"]
2711 #[inline(always)]
2712 pub const fn ccnp(&self, n: usize) -> bool {
2713 assert!(n < 4usize);
2714 let offs = 3usize + n * 4usize;
2715 let val = (self.0 >> offs) & 0x01;
2716 val != 0
2717 }
2718 #[doc = "Capture/Compare x (x=1-4) output Polarity"]
2719 #[inline(always)]
2720 pub fn set_ccnp(&mut self, n: usize, val: bool) {
2721 assert!(n < 4usize);
2722 let offs = 3usize + n * 4usize;
2723 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2724 }
2725 }
2726 impl Default for CcerGp16 {
2727 #[inline(always)]
2728 fn default() -> CcerGp16 {
2729 CcerGp16(0)
2730 }
2731 }
2732 impl core::fmt::Debug for CcerGp16 {
2733 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2734 f.debug_struct("CcerGp16")
2735 .field(
2736 "cce",
2737 &[self.cce(0usize), self.cce(1usize), self.cce(2usize), self.cce(3usize)],
2738 )
2739 .field(
2740 "ccp",
2741 &[self.ccp(0usize), self.ccp(1usize), self.ccp(2usize), self.ccp(3usize)],
2742 )
2743 .field(
2744 "ccnp",
2745 &[
2746 self.ccnp(0usize),
2747 self.ccnp(1usize),
2748 self.ccnp(2usize),
2749 self.ccnp(3usize),
2750 ],
2751 )
2752 .finish()
2753 }
2754 }
2755 #[cfg(feature = "defmt")]
2756 impl defmt::Format for CcerGp16 {
2757 fn format(&self, f: defmt::Formatter) {
2758 #[derive(defmt :: Format)]
2759 struct CcerGp16 {
2760 cce: [bool; 4usize],
2761 ccp: [bool; 4usize],
2762 ccnp: [bool; 4usize],
2763 }
2764 let proxy = CcerGp16 {
2765 cce: [self.cce(0usize), self.cce(1usize), self.cce(2usize), self.cce(3usize)],
2766 ccp: [self.ccp(0usize), self.ccp(1usize), self.ccp(2usize), self.ccp(3usize)],
2767 ccnp: [
2768 self.ccnp(0usize),
2769 self.ccnp(1usize),
2770 self.ccnp(2usize),
2771 self.ccnp(3usize),
2772 ],
2773 };
2774 defmt::write!(f, "{}", proxy)
2775 }
2776 }
2777 #[doc = "capture/compare mode register 3"]
2778 #[repr(transparent)]
2779 #[derive(Copy, Clone, Eq, PartialEq)]
2780 pub struct Ccmr3Adv(pub u32);
2781 impl Ccmr3Adv {
2782 #[doc = "Output compare x (x=5,6) fast enable"]
2783 #[inline(always)]
2784 pub const fn ocfe(&self, n: usize) -> bool {
2785 assert!(n < 2usize);
2786 let offs = 2usize + n * 8usize;
2787 let val = (self.0 >> offs) & 0x01;
2788 val != 0
2789 }
2790 #[doc = "Output compare x (x=5,6) fast enable"]
2791 #[inline(always)]
2792 pub fn set_ocfe(&mut self, n: usize, val: bool) {
2793 assert!(n < 2usize);
2794 let offs = 2usize + n * 8usize;
2795 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2796 }
2797 #[doc = "Output compare x (x=5,6) preload enable"]
2798 #[inline(always)]
2799 pub const fn ocpe(&self, n: usize) -> bool {
2800 assert!(n < 2usize);
2801 let offs = 3usize + n * 8usize;
2802 let val = (self.0 >> offs) & 0x01;
2803 val != 0
2804 }
2805 #[doc = "Output compare x (x=5,6) preload enable"]
2806 #[inline(always)]
2807 pub fn set_ocpe(&mut self, n: usize, val: bool) {
2808 assert!(n < 2usize);
2809 let offs = 3usize + n * 8usize;
2810 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2811 }
2812 #[doc = "Output compare x (x=5,6) mode"]
2813 #[inline(always)]
2814 pub const fn ocm(&self, n: usize) -> super::vals::Ocm {
2815 assert!(n < 2usize);
2816 let mut val = 0;
2817 let offs = 4usize + n * 8usize;
2818 val += (((self.0 >> offs) & 0x07) << 0usize);
2819 let offs = 16usize + n * 8usize;
2820 val += (((self.0 >> offs) & 0x01) << 3usize);
2821 super::vals::Ocm::from_bits(val as u8)
2822 }
2823 #[doc = "Output compare x (x=5,6) mode"]
2824 #[inline(always)]
2825 pub fn set_ocm(&mut self, n: usize, val: super::vals::Ocm) {
2826 assert!(n < 2usize);
2827 let offs = 4usize + n * 8usize;
2828 self.0 = (self.0 & !(0x07 << offs)) | (((val.to_bits() as u32 >> 0usize) & 0x07) << offs);
2829 let offs = 16usize + n * 8usize;
2830 self.0 = (self.0 & !(0x01 << offs)) | (((val.to_bits() as u32 >> 3usize) & 0x01) << offs);
2831 }
2832 #[doc = "Output compare x (x=5,6) clear enable"]
2833 #[inline(always)]
2834 pub const fn occe(&self, n: usize) -> bool {
2835 assert!(n < 2usize);
2836 let offs = 7usize + n * 8usize;
2837 let val = (self.0 >> offs) & 0x01;
2838 val != 0
2839 }
2840 #[doc = "Output compare x (x=5,6) clear enable"]
2841 #[inline(always)]
2842 pub fn set_occe(&mut self, n: usize, val: bool) {
2843 assert!(n < 2usize);
2844 let offs = 7usize + n * 8usize;
2845 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
2846 }
2847 }
2848 impl Default for Ccmr3Adv {
2849 #[inline(always)]
2850 fn default() -> Ccmr3Adv {
2851 Ccmr3Adv(0)
2852 }
2853 }
2854 impl core::fmt::Debug for Ccmr3Adv {
2855 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2856 f.debug_struct("Ccmr3Adv")
2857 .field("ocfe", &[self.ocfe(0usize), self.ocfe(1usize)])
2858 .field("ocpe", &[self.ocpe(0usize), self.ocpe(1usize)])
2859 .field("ocm", &[self.ocm(0usize), self.ocm(1usize)])
2860 .field("occe", &[self.occe(0usize), self.occe(1usize)])
2861 .finish()
2862 }
2863 }
2864 #[cfg(feature = "defmt")]
2865 impl defmt::Format for Ccmr3Adv {
2866 fn format(&self, f: defmt::Formatter) {
2867 #[derive(defmt :: Format)]
2868 struct Ccmr3Adv {
2869 ocfe: [bool; 2usize],
2870 ocpe: [bool; 2usize],
2871 ocm: [super::vals::Ocm; 2usize],
2872 occe: [bool; 2usize],
2873 }
2874 let proxy = Ccmr3Adv {
2875 ocfe: [self.ocfe(0usize), self.ocfe(1usize)],
2876 ocpe: [self.ocpe(0usize), self.ocpe(1usize)],
2877 ocm: [self.ocm(0usize), self.ocm(1usize)],
2878 occe: [self.occe(0usize), self.occe(1usize)],
2879 };
2880 defmt::write!(f, "{}", proxy)
2881 }
2882 }
2883 #[doc = "capture/compare mode register x (x=1) (input mode)"]
2884 #[repr(transparent)]
2885 #[derive(Copy, Clone, Eq, PartialEq)]
2886 pub struct CcmrInput1ch(pub u32);
2887 impl CcmrInput1ch {
2888 #[doc = "Capture/Compare y selection"]
2889 #[inline(always)]
2890 pub const fn ccs(&self, n: usize) -> super::vals::CcmrInputCcs {
2891 assert!(n < 1usize);
2892 let offs = 0usize + n * 8usize;
2893 let val = (self.0 >> offs) & 0x03;
2894 super::vals::CcmrInputCcs::from_bits(val as u8)
2895 }
2896 #[doc = "Capture/Compare y selection"]
2897 #[inline(always)]
2898 pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrInputCcs) {
2899 assert!(n < 1usize);
2900 let offs = 0usize + n * 8usize;
2901 self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs);
2902 }
2903 #[doc = "Input capture y prescaler"]
2904 #[inline(always)]
2905 pub const fn icpsc(&self, n: usize) -> u8 {
2906 assert!(n < 1usize);
2907 let offs = 2usize + n * 8usize;
2908 let val = (self.0 >> offs) & 0x03;
2909 val as u8
2910 }
2911 #[doc = "Input capture y prescaler"]
2912 #[inline(always)]
2913 pub fn set_icpsc(&mut self, n: usize, val: u8) {
2914 assert!(n < 1usize);
2915 let offs = 2usize + n * 8usize;
2916 self.0 = (self.0 & !(0x03 << offs)) | (((val as u32) & 0x03) << offs);
2917 }
2918 #[doc = "Input capture y filter"]
2919 #[inline(always)]
2920 pub const fn icf(&self, n: usize) -> super::vals::FilterValue {
2921 assert!(n < 1usize);
2922 let offs = 4usize + n * 8usize;
2923 let val = (self.0 >> offs) & 0x0f;
2924 super::vals::FilterValue::from_bits(val as u8)
2925 }
2926 #[doc = "Input capture y filter"]
2927 #[inline(always)]
2928 pub fn set_icf(&mut self, n: usize, val: super::vals::FilterValue) {
2929 assert!(n < 1usize);
2930 let offs = 4usize + n * 8usize;
2931 self.0 = (self.0 & !(0x0f << offs)) | (((val.to_bits() as u32) & 0x0f) << offs);
2932 }
2933 }
2934 impl Default for CcmrInput1ch {
2935 #[inline(always)]
2936 fn default() -> CcmrInput1ch {
2937 CcmrInput1ch(0)
2938 }
2939 }
2940 impl core::fmt::Debug for CcmrInput1ch {
2941 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2942 f.debug_struct("CcmrInput1ch")
2943 .field("ccs", &[self.ccs(0usize)])
2944 .field("icpsc", &[self.icpsc(0usize)])
2945 .field("icf", &[self.icf(0usize)])
2946 .finish()
2947 }
2948 }
2949 #[cfg(feature = "defmt")]
2950 impl defmt::Format for CcmrInput1ch {
2951 fn format(&self, f: defmt::Formatter) {
2952 #[derive(defmt :: Format)]
2953 struct CcmrInput1ch {
2954 ccs: [super::vals::CcmrInputCcs; 1usize],
2955 icpsc: [u8; 1usize],
2956 icf: [super::vals::FilterValue; 1usize],
2957 }
2958 let proxy = CcmrInput1ch {
2959 ccs: [self.ccs(0usize)],
2960 icpsc: [self.icpsc(0usize)],
2961 icf: [self.icf(0usize)],
2962 };
2963 defmt::write!(f, "{}", proxy)
2964 }
2965 }
2966 #[doc = "capture/compare mode register x (x=1) (input mode)"]
2967 #[repr(transparent)]
2968 #[derive(Copy, Clone, Eq, PartialEq)]
2969 pub struct CcmrInput2ch(pub u32);
2970 impl CcmrInput2ch {
2971 #[doc = "Capture/Compare y selection"]
2972 #[inline(always)]
2973 pub const fn ccs(&self, n: usize) -> super::vals::CcmrInputCcs {
2974 assert!(n < 2usize);
2975 let offs = 0usize + n * 8usize;
2976 let val = (self.0 >> offs) & 0x03;
2977 super::vals::CcmrInputCcs::from_bits(val as u8)
2978 }
2979 #[doc = "Capture/Compare y selection"]
2980 #[inline(always)]
2981 pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrInputCcs) {
2982 assert!(n < 2usize);
2983 let offs = 0usize + n * 8usize;
2984 self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs);
2985 }
2986 #[doc = "Input capture y prescaler"]
2987 #[inline(always)]
2988 pub const fn icpsc(&self, n: usize) -> u8 {
2989 assert!(n < 2usize);
2990 let offs = 2usize + n * 8usize;
2991 let val = (self.0 >> offs) & 0x03;
2992 val as u8
2993 }
2994 #[doc = "Input capture y prescaler"]
2995 #[inline(always)]
2996 pub fn set_icpsc(&mut self, n: usize, val: u8) {
2997 assert!(n < 2usize);
2998 let offs = 2usize + n * 8usize;
2999 self.0 = (self.0 & !(0x03 << offs)) | (((val as u32) & 0x03) << offs);
3000 }
3001 #[doc = "Input capture y filter"]
3002 #[inline(always)]
3003 pub const fn icf(&self, n: usize) -> super::vals::FilterValue {
3004 assert!(n < 2usize);
3005 let offs = 4usize + n * 8usize;
3006 let val = (self.0 >> offs) & 0x0f;
3007 super::vals::FilterValue::from_bits(val as u8)
3008 }
3009 #[doc = "Input capture y filter"]
3010 #[inline(always)]
3011 pub fn set_icf(&mut self, n: usize, val: super::vals::FilterValue) {
3012 assert!(n < 2usize);
3013 let offs = 4usize + n * 8usize;
3014 self.0 = (self.0 & !(0x0f << offs)) | (((val.to_bits() as u32) & 0x0f) << offs);
3015 }
3016 }
3017 impl Default for CcmrInput2ch {
3018 #[inline(always)]
3019 fn default() -> CcmrInput2ch {
3020 CcmrInput2ch(0)
3021 }
3022 }
3023 impl core::fmt::Debug for CcmrInput2ch {
3024 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3025 f.debug_struct("CcmrInput2ch")
3026 .field("ccs", &[self.ccs(0usize), self.ccs(1usize)])
3027 .field("icpsc", &[self.icpsc(0usize), self.icpsc(1usize)])
3028 .field("icf", &[self.icf(0usize), self.icf(1usize)])
3029 .finish()
3030 }
3031 }
3032 #[cfg(feature = "defmt")]
3033 impl defmt::Format for CcmrInput2ch {
3034 fn format(&self, f: defmt::Formatter) {
3035 #[derive(defmt :: Format)]
3036 struct CcmrInput2ch {
3037 ccs: [super::vals::CcmrInputCcs; 2usize],
3038 icpsc: [u8; 2usize],
3039 icf: [super::vals::FilterValue; 2usize],
3040 }
3041 let proxy = CcmrInput2ch {
3042 ccs: [self.ccs(0usize), self.ccs(1usize)],
3043 icpsc: [self.icpsc(0usize), self.icpsc(1usize)],
3044 icf: [self.icf(0usize), self.icf(1usize)],
3045 };
3046 defmt::write!(f, "{}", proxy)
3047 }
3048 }
3049 #[doc = "capture/compare mode register x (x=1) (output mode)"]
3050 #[repr(transparent)]
3051 #[derive(Copy, Clone, Eq, PartialEq)]
3052 pub struct CcmrOutput1ch(pub u32);
3053 impl CcmrOutput1ch {
3054 #[doc = "Capture/Compare y selection"]
3055 #[inline(always)]
3056 pub const fn ccs(&self, n: usize) -> super::vals::CcmrOutputCcs {
3057 assert!(n < 1usize);
3058 let offs = 0usize + n * 8usize;
3059 let val = (self.0 >> offs) & 0x03;
3060 super::vals::CcmrOutputCcs::from_bits(val as u8)
3061 }
3062 #[doc = "Capture/Compare y selection"]
3063 #[inline(always)]
3064 pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrOutputCcs) {
3065 assert!(n < 1usize);
3066 let offs = 0usize + n * 8usize;
3067 self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs);
3068 }
3069 #[doc = "Output compare y fast enable"]
3070 #[inline(always)]
3071 pub const fn ocfe(&self, n: usize) -> bool {
3072 assert!(n < 1usize);
3073 let offs = 2usize + n * 8usize;
3074 let val = (self.0 >> offs) & 0x01;
3075 val != 0
3076 }
3077 #[doc = "Output compare y fast enable"]
3078 #[inline(always)]
3079 pub fn set_ocfe(&mut self, n: usize, val: bool) {
3080 assert!(n < 1usize);
3081 let offs = 2usize + n * 8usize;
3082 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3083 }
3084 #[doc = "Output compare y preload enable"]
3085 #[inline(always)]
3086 pub const fn ocpe(&self, n: usize) -> bool {
3087 assert!(n < 1usize);
3088 let offs = 3usize + n * 8usize;
3089 let val = (self.0 >> offs) & 0x01;
3090 val != 0
3091 }
3092 #[doc = "Output compare y preload enable"]
3093 #[inline(always)]
3094 pub fn set_ocpe(&mut self, n: usize, val: bool) {
3095 assert!(n < 1usize);
3096 let offs = 3usize + n * 8usize;
3097 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3098 }
3099 #[doc = "Output compare y mode"]
3100 #[inline(always)]
3101 pub const fn ocm(&self, n: usize) -> super::vals::Ocm {
3102 assert!(n < 1usize);
3103 let mut val = 0;
3104 let offs = 4usize + n * 8usize;
3105 val += (((self.0 >> offs) & 0x07) << 0usize);
3106 let offs = 16usize + n * 8usize;
3107 val += (((self.0 >> offs) & 0x01) << 3usize);
3108 super::vals::Ocm::from_bits(val as u8)
3109 }
3110 #[doc = "Output compare y mode"]
3111 #[inline(always)]
3112 pub fn set_ocm(&mut self, n: usize, val: super::vals::Ocm) {
3113 assert!(n < 1usize);
3114 let offs = 4usize + n * 8usize;
3115 self.0 = (self.0 & !(0x07 << offs)) | (((val.to_bits() as u32 >> 0usize) & 0x07) << offs);
3116 let offs = 16usize + n * 8usize;
3117 self.0 = (self.0 & !(0x01 << offs)) | (((val.to_bits() as u32 >> 3usize) & 0x01) << offs);
3118 }
3119 }
3120 impl Default for CcmrOutput1ch {
3121 #[inline(always)]
3122 fn default() -> CcmrOutput1ch {
3123 CcmrOutput1ch(0)
3124 }
3125 }
3126 impl core::fmt::Debug for CcmrOutput1ch {
3127 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3128 f.debug_struct("CcmrOutput1ch")
3129 .field("ccs", &[self.ccs(0usize)])
3130 .field("ocfe", &[self.ocfe(0usize)])
3131 .field("ocpe", &[self.ocpe(0usize)])
3132 .field("ocm", &[self.ocm(0usize)])
3133 .finish()
3134 }
3135 }
3136 #[cfg(feature = "defmt")]
3137 impl defmt::Format for CcmrOutput1ch {
3138 fn format(&self, f: defmt::Formatter) {
3139 #[derive(defmt :: Format)]
3140 struct CcmrOutput1ch {
3141 ccs: [super::vals::CcmrOutputCcs; 1usize],
3142 ocfe: [bool; 1usize],
3143 ocpe: [bool; 1usize],
3144 ocm: [super::vals::Ocm; 1usize],
3145 }
3146 let proxy = CcmrOutput1ch {
3147 ccs: [self.ccs(0usize)],
3148 ocfe: [self.ocfe(0usize)],
3149 ocpe: [self.ocpe(0usize)],
3150 ocm: [self.ocm(0usize)],
3151 };
3152 defmt::write!(f, "{}", proxy)
3153 }
3154 }
3155 #[doc = "capture/compare mode register x (x=1) (output mode)"]
3156 #[repr(transparent)]
3157 #[derive(Copy, Clone, Eq, PartialEq)]
3158 pub struct CcmrOutput2ch(pub u32);
3159 impl CcmrOutput2ch {
3160 #[doc = "Capture/Compare y selection"]
3161 #[inline(always)]
3162 pub const fn ccs(&self, n: usize) -> super::vals::CcmrOutputCcs {
3163 assert!(n < 2usize);
3164 let offs = 0usize + n * 8usize;
3165 let val = (self.0 >> offs) & 0x03;
3166 super::vals::CcmrOutputCcs::from_bits(val as u8)
3167 }
3168 #[doc = "Capture/Compare y selection"]
3169 #[inline(always)]
3170 pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrOutputCcs) {
3171 assert!(n < 2usize);
3172 let offs = 0usize + n * 8usize;
3173 self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs);
3174 }
3175 #[doc = "Output compare y fast enable"]
3176 #[inline(always)]
3177 pub const fn ocfe(&self, n: usize) -> bool {
3178 assert!(n < 2usize);
3179 let offs = 2usize + n * 8usize;
3180 let val = (self.0 >> offs) & 0x01;
3181 val != 0
3182 }
3183 #[doc = "Output compare y fast enable"]
3184 #[inline(always)]
3185 pub fn set_ocfe(&mut self, n: usize, val: bool) {
3186 assert!(n < 2usize);
3187 let offs = 2usize + n * 8usize;
3188 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3189 }
3190 #[doc = "Output compare y preload enable"]
3191 #[inline(always)]
3192 pub const fn ocpe(&self, n: usize) -> bool {
3193 assert!(n < 2usize);
3194 let offs = 3usize + n * 8usize;
3195 let val = (self.0 >> offs) & 0x01;
3196 val != 0
3197 }
3198 #[doc = "Output compare y preload enable"]
3199 #[inline(always)]
3200 pub fn set_ocpe(&mut self, n: usize, val: bool) {
3201 assert!(n < 2usize);
3202 let offs = 3usize + n * 8usize;
3203 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3204 }
3205 #[doc = "Output compare y mode"]
3206 #[inline(always)]
3207 pub const fn ocm(&self, n: usize) -> super::vals::Ocm {
3208 assert!(n < 2usize);
3209 let mut val = 0;
3210 let offs = 4usize + n * 8usize;
3211 val += (((self.0 >> offs) & 0x07) << 0usize);
3212 let offs = 16usize + n * 8usize;
3213 val += (((self.0 >> offs) & 0x01) << 3usize);
3214 super::vals::Ocm::from_bits(val as u8)
3215 }
3216 #[doc = "Output compare y mode"]
3217 #[inline(always)]
3218 pub fn set_ocm(&mut self, n: usize, val: super::vals::Ocm) {
3219 assert!(n < 2usize);
3220 let offs = 4usize + n * 8usize;
3221 self.0 = (self.0 & !(0x07 << offs)) | (((val.to_bits() as u32 >> 0usize) & 0x07) << offs);
3222 let offs = 16usize + n * 8usize;
3223 self.0 = (self.0 & !(0x01 << offs)) | (((val.to_bits() as u32 >> 3usize) & 0x01) << offs);
3224 }
3225 }
3226 impl Default for CcmrOutput2ch {
3227 #[inline(always)]
3228 fn default() -> CcmrOutput2ch {
3229 CcmrOutput2ch(0)
3230 }
3231 }
3232 impl core::fmt::Debug for CcmrOutput2ch {
3233 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3234 f.debug_struct("CcmrOutput2ch")
3235 .field("ccs", &[self.ccs(0usize), self.ccs(1usize)])
3236 .field("ocfe", &[self.ocfe(0usize), self.ocfe(1usize)])
3237 .field("ocpe", &[self.ocpe(0usize), self.ocpe(1usize)])
3238 .field("ocm", &[self.ocm(0usize), self.ocm(1usize)])
3239 .finish()
3240 }
3241 }
3242 #[cfg(feature = "defmt")]
3243 impl defmt::Format for CcmrOutput2ch {
3244 fn format(&self, f: defmt::Formatter) {
3245 #[derive(defmt :: Format)]
3246 struct CcmrOutput2ch {
3247 ccs: [super::vals::CcmrOutputCcs; 2usize],
3248 ocfe: [bool; 2usize],
3249 ocpe: [bool; 2usize],
3250 ocm: [super::vals::Ocm; 2usize],
3251 }
3252 let proxy = CcmrOutput2ch {
3253 ccs: [self.ccs(0usize), self.ccs(1usize)],
3254 ocfe: [self.ocfe(0usize), self.ocfe(1usize)],
3255 ocpe: [self.ocpe(0usize), self.ocpe(1usize)],
3256 ocm: [self.ocm(0usize), self.ocm(1usize)],
3257 };
3258 defmt::write!(f, "{}", proxy)
3259 }
3260 }
3261 #[doc = "capture/compare mode register x (x=1-2) (output mode)"]
3262 #[repr(transparent)]
3263 #[derive(Copy, Clone, Eq, PartialEq)]
3264 pub struct CcmrOutputGp16(pub u32);
3265 impl CcmrOutputGp16 {
3266 #[doc = "Capture/Compare y selection"]
3267 #[inline(always)]
3268 pub const fn ccs(&self, n: usize) -> super::vals::CcmrOutputCcs {
3269 assert!(n < 2usize);
3270 let offs = 0usize + n * 8usize;
3271 let val = (self.0 >> offs) & 0x03;
3272 super::vals::CcmrOutputCcs::from_bits(val as u8)
3273 }
3274 #[doc = "Capture/Compare y selection"]
3275 #[inline(always)]
3276 pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrOutputCcs) {
3277 assert!(n < 2usize);
3278 let offs = 0usize + n * 8usize;
3279 self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs);
3280 }
3281 #[doc = "Output compare y fast enable"]
3282 #[inline(always)]
3283 pub const fn ocfe(&self, n: usize) -> bool {
3284 assert!(n < 2usize);
3285 let offs = 2usize + n * 8usize;
3286 let val = (self.0 >> offs) & 0x01;
3287 val != 0
3288 }
3289 #[doc = "Output compare y fast enable"]
3290 #[inline(always)]
3291 pub fn set_ocfe(&mut self, n: usize, val: bool) {
3292 assert!(n < 2usize);
3293 let offs = 2usize + n * 8usize;
3294 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3295 }
3296 #[doc = "Output compare y preload enable"]
3297 #[inline(always)]
3298 pub const fn ocpe(&self, n: usize) -> bool {
3299 assert!(n < 2usize);
3300 let offs = 3usize + n * 8usize;
3301 let val = (self.0 >> offs) & 0x01;
3302 val != 0
3303 }
3304 #[doc = "Output compare y preload enable"]
3305 #[inline(always)]
3306 pub fn set_ocpe(&mut self, n: usize, val: bool) {
3307 assert!(n < 2usize);
3308 let offs = 3usize + n * 8usize;
3309 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3310 }
3311 #[doc = "Output compare y mode"]
3312 #[inline(always)]
3313 pub const fn ocm(&self, n: usize) -> super::vals::Ocm {
3314 assert!(n < 2usize);
3315 let mut val = 0;
3316 let offs = 4usize + n * 8usize;
3317 val += (((self.0 >> offs) & 0x07) << 0usize);
3318 let offs = 16usize + n * 8usize;
3319 val += (((self.0 >> offs) & 0x01) << 3usize);
3320 super::vals::Ocm::from_bits(val as u8)
3321 }
3322 #[doc = "Output compare y mode"]
3323 #[inline(always)]
3324 pub fn set_ocm(&mut self, n: usize, val: super::vals::Ocm) {
3325 assert!(n < 2usize);
3326 let offs = 4usize + n * 8usize;
3327 self.0 = (self.0 & !(0x07 << offs)) | (((val.to_bits() as u32 >> 0usize) & 0x07) << offs);
3328 let offs = 16usize + n * 8usize;
3329 self.0 = (self.0 & !(0x01 << offs)) | (((val.to_bits() as u32 >> 3usize) & 0x01) << offs);
3330 }
3331 #[doc = "Output compare y clear enable"]
3332 #[inline(always)]
3333 pub const fn occe(&self, n: usize) -> bool {
3334 assert!(n < 2usize);
3335 let offs = 7usize + n * 8usize;
3336 let val = (self.0 >> offs) & 0x01;
3337 val != 0
3338 }
3339 #[doc = "Output compare y clear enable"]
3340 #[inline(always)]
3341 pub fn set_occe(&mut self, n: usize, val: bool) {
3342 assert!(n < 2usize);
3343 let offs = 7usize + n * 8usize;
3344 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
3345 }
3346 }
3347 impl Default for CcmrOutputGp16 {
3348 #[inline(always)]
3349 fn default() -> CcmrOutputGp16 {
3350 CcmrOutputGp16(0)
3351 }
3352 }
3353 impl core::fmt::Debug for CcmrOutputGp16 {
3354 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3355 f.debug_struct("CcmrOutputGp16")
3356 .field("ccs", &[self.ccs(0usize), self.ccs(1usize)])
3357 .field("ocfe", &[self.ocfe(0usize), self.ocfe(1usize)])
3358 .field("ocpe", &[self.ocpe(0usize), self.ocpe(1usize)])
3359 .field("ocm", &[self.ocm(0usize), self.ocm(1usize)])
3360 .field("occe", &[self.occe(0usize), self.occe(1usize)])
3361 .finish()
3362 }
3363 }
3364 #[cfg(feature = "defmt")]
3365 impl defmt::Format for CcmrOutputGp16 {
3366 fn format(&self, f: defmt::Formatter) {
3367 #[derive(defmt :: Format)]
3368 struct CcmrOutputGp16 {
3369 ccs: [super::vals::CcmrOutputCcs; 2usize],
3370 ocfe: [bool; 2usize],
3371 ocpe: [bool; 2usize],
3372 ocm: [super::vals::Ocm; 2usize],
3373 occe: [bool; 2usize],
3374 }
3375 let proxy = CcmrOutputGp16 {
3376 ccs: [self.ccs(0usize), self.ccs(1usize)],
3377 ocfe: [self.ocfe(0usize), self.ocfe(1usize)],
3378 ocpe: [self.ocpe(0usize), self.ocpe(1usize)],
3379 ocm: [self.ocm(0usize), self.ocm(1usize)],
3380 occe: [self.occe(0usize), self.occe(1usize)],
3381 };
3382 defmt::write!(f, "{}", proxy)
3383 }
3384 }
3385 #[doc = "capture/compare register x (x=1-4,6) (Dither mode disabled)"]
3386 #[repr(transparent)]
3387 #[derive(Copy, Clone, Eq, PartialEq)]
3388 pub struct Ccr1ch(pub u32);
3389 impl Ccr1ch {
3390 #[doc = "capture/compare x (x=1-4,6) value"]
3391 #[inline(always)]
3392 pub const fn ccr(&self) -> u16 {
3393 let val = (self.0 >> 0usize) & 0xffff;
3394 val as u16
3395 }
3396 #[doc = "capture/compare x (x=1-4,6) value"]
3397 #[inline(always)]
3398 pub fn set_ccr(&mut self, val: u16) {
3399 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
3400 }
3401 }
3402 impl Default for Ccr1ch {
3403 #[inline(always)]
3404 fn default() -> Ccr1ch {
3405 Ccr1ch(0)
3406 }
3407 }
3408 impl core::fmt::Debug for Ccr1ch {
3409 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3410 f.debug_struct("Ccr1ch").field("ccr", &self.ccr()).finish()
3411 }
3412 }
3413 #[cfg(feature = "defmt")]
3414 impl defmt::Format for Ccr1ch {
3415 fn format(&self, f: defmt::Formatter) {
3416 #[derive(defmt :: Format)]
3417 struct Ccr1ch {
3418 ccr: u16,
3419 }
3420 let proxy = Ccr1ch { ccr: self.ccr() };
3421 defmt::write!(f, "{}", proxy)
3422 }
3423 }
3424 #[doc = "capture/compare register 5 (Dither mode disabled)"]
3425 #[repr(transparent)]
3426 #[derive(Copy, Clone, Eq, PartialEq)]
3427 pub struct Ccr5Adv(pub u32);
3428 impl Ccr5Adv {
3429 #[doc = "capture/compare x (x=1-4,6) value"]
3430 #[inline(always)]
3431 pub const fn ccr(&self) -> u16 {
3432 let val = (self.0 >> 0usize) & 0xffff;
3433 val as u16
3434 }
3435 #[doc = "capture/compare x (x=1-4,6) value"]
3436 #[inline(always)]
3437 pub fn set_ccr(&mut self, val: u16) {
3438 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
3439 }
3440 #[doc = "Group channel 5 and channel x (x=1-3)"]
3441 #[inline(always)]
3442 pub const fn gc5c(&self, n: usize) -> super::vals::Gc5c {
3443 assert!(n < 3usize);
3444 let offs = 29usize + n * 1usize;
3445 let val = (self.0 >> offs) & 0x01;
3446 super::vals::Gc5c::from_bits(val as u8)
3447 }
3448 #[doc = "Group channel 5 and channel x (x=1-3)"]
3449 #[inline(always)]
3450 pub fn set_gc5c(&mut self, n: usize, val: super::vals::Gc5c) {
3451 assert!(n < 3usize);
3452 let offs = 29usize + n * 1usize;
3453 self.0 = (self.0 & !(0x01 << offs)) | (((val.to_bits() as u32) & 0x01) << offs);
3454 }
3455 }
3456 impl Default for Ccr5Adv {
3457 #[inline(always)]
3458 fn default() -> Ccr5Adv {
3459 Ccr5Adv(0)
3460 }
3461 }
3462 impl core::fmt::Debug for Ccr5Adv {
3463 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3464 f.debug_struct("Ccr5Adv")
3465 .field("ccr", &self.ccr())
3466 .field("gc5c", &[self.gc5c(0usize), self.gc5c(1usize), self.gc5c(2usize)])
3467 .finish()
3468 }
3469 }
3470 #[cfg(feature = "defmt")]
3471 impl defmt::Format for Ccr5Adv {
3472 fn format(&self, f: defmt::Formatter) {
3473 #[derive(defmt :: Format)]
3474 struct Ccr5Adv {
3475 ccr: u16,
3476 gc5c: [super::vals::Gc5c; 3usize],
3477 }
3478 let proxy = Ccr5Adv {
3479 ccr: self.ccr(),
3480 gc5c: [self.gc5c(0usize), self.gc5c(1usize), self.gc5c(2usize)],
3481 };
3482 defmt::write!(f, "{}", proxy)
3483 }
3484 }
3485 #[doc = "capture/compare register 5 (Dither mode enabled)"]
3486 #[repr(transparent)]
3487 #[derive(Copy, Clone, Eq, PartialEq)]
3488 pub struct Ccr5DitherAdv(pub u32);
3489 impl Ccr5DitherAdv {
3490 #[doc = "capture/compare x (x=1-4,6) value"]
3491 #[inline(always)]
3492 pub const fn dither(&self) -> u8 {
3493 let val = (self.0 >> 0usize) & 0x0f;
3494 val as u8
3495 }
3496 #[doc = "capture/compare x (x=1-4,6) value"]
3497 #[inline(always)]
3498 pub fn set_dither(&mut self, val: u8) {
3499 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
3500 }
3501 #[doc = "capture/compare x (x=1-4,6) value"]
3502 #[inline(always)]
3503 pub const fn ccr(&self) -> u16 {
3504 let val = (self.0 >> 4usize) & 0xffff;
3505 val as u16
3506 }
3507 #[doc = "capture/compare x (x=1-4,6) value"]
3508 #[inline(always)]
3509 pub fn set_ccr(&mut self, val: u16) {
3510 self.0 = (self.0 & !(0xffff << 4usize)) | (((val as u32) & 0xffff) << 4usize);
3511 }
3512 #[doc = "Group channel 5 and channel x (x=1-3)"]
3513 #[inline(always)]
3514 pub const fn gc5c(&self, n: usize) -> super::vals::Gc5c {
3515 assert!(n < 3usize);
3516 let offs = 29usize + n * 1usize;
3517 let val = (self.0 >> offs) & 0x01;
3518 super::vals::Gc5c::from_bits(val as u8)
3519 }
3520 #[doc = "Group channel 5 and channel x (x=1-3)"]
3521 #[inline(always)]
3522 pub fn set_gc5c(&mut self, n: usize, val: super::vals::Gc5c) {
3523 assert!(n < 3usize);
3524 let offs = 29usize + n * 1usize;
3525 self.0 = (self.0 & !(0x01 << offs)) | (((val.to_bits() as u32) & 0x01) << offs);
3526 }
3527 }
3528 impl Default for Ccr5DitherAdv {
3529 #[inline(always)]
3530 fn default() -> Ccr5DitherAdv {
3531 Ccr5DitherAdv(0)
3532 }
3533 }
3534 impl core::fmt::Debug for Ccr5DitherAdv {
3535 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3536 f.debug_struct("Ccr5DitherAdv")
3537 .field("dither", &self.dither())
3538 .field("ccr", &self.ccr())
3539 .field("gc5c", &[self.gc5c(0usize), self.gc5c(1usize), self.gc5c(2usize)])
3540 .finish()
3541 }
3542 }
3543 #[cfg(feature = "defmt")]
3544 impl defmt::Format for Ccr5DitherAdv {
3545 fn format(&self, f: defmt::Formatter) {
3546 #[derive(defmt :: Format)]
3547 struct Ccr5DitherAdv {
3548 dither: u8,
3549 ccr: u16,
3550 gc5c: [super::vals::Gc5c; 3usize],
3551 }
3552 let proxy = Ccr5DitherAdv {
3553 dither: self.dither(),
3554 ccr: self.ccr(),
3555 gc5c: [self.gc5c(0usize), self.gc5c(1usize), self.gc5c(2usize)],
3556 };
3557 defmt::write!(f, "{}", proxy)
3558 }
3559 }
3560 #[doc = "capture/compare register x (x=1-4,6) (Dither mode enabled)"]
3561 #[repr(transparent)]
3562 #[derive(Copy, Clone, Eq, PartialEq)]
3563 pub struct CcrDither1ch(pub u32);
3564 impl CcrDither1ch {
3565 #[doc = "capture/compare x (x=1-4,6) value"]
3566 #[inline(always)]
3567 pub const fn dither(&self) -> u8 {
3568 let val = (self.0 >> 0usize) & 0x0f;
3569 val as u8
3570 }
3571 #[doc = "capture/compare x (x=1-4,6) value"]
3572 #[inline(always)]
3573 pub fn set_dither(&mut self, val: u8) {
3574 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
3575 }
3576 #[doc = "capture/compare x (x=1-4,6) value"]
3577 #[inline(always)]
3578 pub const fn ccr(&self) -> u16 {
3579 let val = (self.0 >> 4usize) & 0xffff;
3580 val as u16
3581 }
3582 #[doc = "capture/compare x (x=1-4,6) value"]
3583 #[inline(always)]
3584 pub fn set_ccr(&mut self, val: u16) {
3585 self.0 = (self.0 & !(0xffff << 4usize)) | (((val as u32) & 0xffff) << 4usize);
3586 }
3587 }
3588 impl Default for CcrDither1ch {
3589 #[inline(always)]
3590 fn default() -> CcrDither1ch {
3591 CcrDither1ch(0)
3592 }
3593 }
3594 impl core::fmt::Debug for CcrDither1ch {
3595 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3596 f.debug_struct("CcrDither1ch")
3597 .field("dither", &self.dither())
3598 .field("ccr", &self.ccr())
3599 .finish()
3600 }
3601 }
3602 #[cfg(feature = "defmt")]
3603 impl defmt::Format for CcrDither1ch {
3604 fn format(&self, f: defmt::Formatter) {
3605 #[derive(defmt :: Format)]
3606 struct CcrDither1ch {
3607 dither: u8,
3608 ccr: u16,
3609 }
3610 let proxy = CcrDither1ch {
3611 dither: self.dither(),
3612 ccr: self.ccr(),
3613 };
3614 defmt::write!(f, "{}", proxy)
3615 }
3616 }
3617 #[doc = "capture/compare register x (x=1-4,6) (Dither mode enabled)"]
3618 #[repr(transparent)]
3619 #[derive(Copy, Clone, Eq, PartialEq)]
3620 pub struct CcrDitherGp32(pub u32);
3621 impl CcrDitherGp32 {
3622 #[doc = "Dither value"]
3623 #[inline(always)]
3624 pub const fn dither(&self) -> u8 {
3625 let val = (self.0 >> 0usize) & 0x0f;
3626 val as u8
3627 }
3628 #[doc = "Dither value"]
3629 #[inline(always)]
3630 pub fn set_dither(&mut self, val: u8) {
3631 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
3632 }
3633 #[doc = "capture/compare x (x=1-4,6) value"]
3634 #[inline(always)]
3635 pub const fn ccr(&self) -> u32 {
3636 let val = (self.0 >> 4usize) & 0x0fff_ffff;
3637 val as u32
3638 }
3639 #[doc = "capture/compare x (x=1-4,6) value"]
3640 #[inline(always)]
3641 pub fn set_ccr(&mut self, val: u32) {
3642 self.0 = (self.0 & !(0x0fff_ffff << 4usize)) | (((val as u32) & 0x0fff_ffff) << 4usize);
3643 }
3644 }
3645 impl Default for CcrDitherGp32 {
3646 #[inline(always)]
3647 fn default() -> CcrDitherGp32 {
3648 CcrDitherGp32(0)
3649 }
3650 }
3651 impl core::fmt::Debug for CcrDitherGp32 {
3652 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3653 f.debug_struct("CcrDitherGp32")
3654 .field("dither", &self.dither())
3655 .field("ccr", &self.ccr())
3656 .finish()
3657 }
3658 }
3659 #[cfg(feature = "defmt")]
3660 impl defmt::Format for CcrDitherGp32 {
3661 fn format(&self, f: defmt::Formatter) {
3662 #[derive(defmt :: Format)]
3663 struct CcrDitherGp32 {
3664 dither: u8,
3665 ccr: u32,
3666 }
3667 let proxy = CcrDitherGp32 {
3668 dither: self.dither(),
3669 ccr: self.ccr(),
3670 };
3671 defmt::write!(f, "{}", proxy)
3672 }
3673 }
3674 #[doc = "counter"]
3675 #[repr(transparent)]
3676 #[derive(Copy, Clone, Eq, PartialEq)]
3677 pub struct CntCore(pub u32);
3678 impl CntCore {
3679 #[doc = "counter value"]
3680 #[inline(always)]
3681 pub const fn cnt(&self) -> u16 {
3682 let val = (self.0 >> 0usize) & 0xffff;
3683 val as u16
3684 }
3685 #[doc = "counter value"]
3686 #[inline(always)]
3687 pub fn set_cnt(&mut self, val: u16) {
3688 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
3689 }
3690 #[doc = "UIF copy"]
3691 #[inline(always)]
3692 pub const fn uifcpy(&self) -> bool {
3693 let val = (self.0 >> 31usize) & 0x01;
3694 val != 0
3695 }
3696 #[doc = "UIF copy"]
3697 #[inline(always)]
3698 pub fn set_uifcpy(&mut self, val: bool) {
3699 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
3700 }
3701 }
3702 impl Default for CntCore {
3703 #[inline(always)]
3704 fn default() -> CntCore {
3705 CntCore(0)
3706 }
3707 }
3708 impl core::fmt::Debug for CntCore {
3709 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3710 f.debug_struct("CntCore")
3711 .field("cnt", &self.cnt())
3712 .field("uifcpy", &self.uifcpy())
3713 .finish()
3714 }
3715 }
3716 #[cfg(feature = "defmt")]
3717 impl defmt::Format for CntCore {
3718 fn format(&self, f: defmt::Formatter) {
3719 #[derive(defmt :: Format)]
3720 struct CntCore {
3721 cnt: u16,
3722 uifcpy: bool,
3723 }
3724 let proxy = CntCore {
3725 cnt: self.cnt(),
3726 uifcpy: self.uifcpy(),
3727 };
3728 defmt::write!(f, "{}", proxy)
3729 }
3730 }
3731 #[doc = "counter (Dither mode enabled)"]
3732 #[repr(transparent)]
3733 #[derive(Copy, Clone, Eq, PartialEq)]
3734 pub struct CntDitherGp32(pub u32);
3735 impl CntDitherGp32 {
3736 #[doc = "counter value"]
3737 #[inline(always)]
3738 pub const fn cnt(&self) -> u32 {
3739 let val = (self.0 >> 0usize) & 0x7fff_ffff;
3740 val as u32
3741 }
3742 #[doc = "counter value"]
3743 #[inline(always)]
3744 pub fn set_cnt(&mut self, val: u32) {
3745 self.0 = (self.0 & !(0x7fff_ffff << 0usize)) | (((val as u32) & 0x7fff_ffff) << 0usize);
3746 }
3747 #[doc = "UIF copy"]
3748 #[inline(always)]
3749 pub const fn uifcpy(&self) -> bool {
3750 let val = (self.0 >> 31usize) & 0x01;
3751 val != 0
3752 }
3753 #[doc = "UIF copy"]
3754 #[inline(always)]
3755 pub fn set_uifcpy(&mut self, val: bool) {
3756 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
3757 }
3758 }
3759 impl Default for CntDitherGp32 {
3760 #[inline(always)]
3761 fn default() -> CntDitherGp32 {
3762 CntDitherGp32(0)
3763 }
3764 }
3765 impl core::fmt::Debug for CntDitherGp32 {
3766 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3767 f.debug_struct("CntDitherGp32")
3768 .field("cnt", &self.cnt())
3769 .field("uifcpy", &self.uifcpy())
3770 .finish()
3771 }
3772 }
3773 #[cfg(feature = "defmt")]
3774 impl defmt::Format for CntDitherGp32 {
3775 fn format(&self, f: defmt::Formatter) {
3776 #[derive(defmt :: Format)]
3777 struct CntDitherGp32 {
3778 cnt: u32,
3779 uifcpy: bool,
3780 }
3781 let proxy = CntDitherGp32 {
3782 cnt: self.cnt(),
3783 uifcpy: self.uifcpy(),
3784 };
3785 defmt::write!(f, "{}", proxy)
3786 }
3787 }
3788 #[doc = "control register 1"]
3789 #[repr(transparent)]
3790 #[derive(Copy, Clone, Eq, PartialEq)]
3791 pub struct Cr11ch(pub u32);
3792 impl Cr11ch {
3793 #[doc = "Counter enable"]
3794 #[inline(always)]
3795 pub const fn cen(&self) -> bool {
3796 let val = (self.0 >> 0usize) & 0x01;
3797 val != 0
3798 }
3799 #[doc = "Counter enable"]
3800 #[inline(always)]
3801 pub fn set_cen(&mut self, val: bool) {
3802 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
3803 }
3804 #[doc = "Update disable"]
3805 #[inline(always)]
3806 pub const fn udis(&self) -> bool {
3807 let val = (self.0 >> 1usize) & 0x01;
3808 val != 0
3809 }
3810 #[doc = "Update disable"]
3811 #[inline(always)]
3812 pub fn set_udis(&mut self, val: bool) {
3813 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
3814 }
3815 #[doc = "Update request source"]
3816 #[inline(always)]
3817 pub const fn urs(&self) -> super::vals::Urs {
3818 let val = (self.0 >> 2usize) & 0x01;
3819 super::vals::Urs::from_bits(val as u8)
3820 }
3821 #[doc = "Update request source"]
3822 #[inline(always)]
3823 pub fn set_urs(&mut self, val: super::vals::Urs) {
3824 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize);
3825 }
3826 #[doc = "One-pulse mode enbaled"]
3827 #[inline(always)]
3828 pub const fn opm(&self) -> bool {
3829 let val = (self.0 >> 3usize) & 0x01;
3830 val != 0
3831 }
3832 #[doc = "One-pulse mode enbaled"]
3833 #[inline(always)]
3834 pub fn set_opm(&mut self, val: bool) {
3835 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
3836 }
3837 #[doc = "Auto-reload preload enable"]
3838 #[inline(always)]
3839 pub const fn arpe(&self) -> bool {
3840 let val = (self.0 >> 7usize) & 0x01;
3841 val != 0
3842 }
3843 #[doc = "Auto-reload preload enable"]
3844 #[inline(always)]
3845 pub fn set_arpe(&mut self, val: bool) {
3846 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
3847 }
3848 #[doc = "Clock division"]
3849 #[inline(always)]
3850 pub const fn ckd(&self) -> super::vals::Ckd {
3851 let val = (self.0 >> 8usize) & 0x03;
3852 super::vals::Ckd::from_bits(val as u8)
3853 }
3854 #[doc = "Clock division"]
3855 #[inline(always)]
3856 pub fn set_ckd(&mut self, val: super::vals::Ckd) {
3857 self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize);
3858 }
3859 #[doc = "UIF status bit remapping enable"]
3860 #[inline(always)]
3861 pub const fn uifremap(&self) -> bool {
3862 let val = (self.0 >> 11usize) & 0x01;
3863 val != 0
3864 }
3865 #[doc = "UIF status bit remapping enable"]
3866 #[inline(always)]
3867 pub fn set_uifremap(&mut self, val: bool) {
3868 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
3869 }
3870 #[doc = "Dithering enable"]
3871 #[inline(always)]
3872 pub const fn dithen(&self) -> bool {
3873 let val = (self.0 >> 12usize) & 0x01;
3874 val != 0
3875 }
3876 #[doc = "Dithering enable"]
3877 #[inline(always)]
3878 pub fn set_dithen(&mut self, val: bool) {
3879 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
3880 }
3881 }
3882 impl Default for Cr11ch {
3883 #[inline(always)]
3884 fn default() -> Cr11ch {
3885 Cr11ch(0)
3886 }
3887 }
3888 impl core::fmt::Debug for Cr11ch {
3889 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3890 f.debug_struct("Cr11ch")
3891 .field("cen", &self.cen())
3892 .field("udis", &self.udis())
3893 .field("urs", &self.urs())
3894 .field("opm", &self.opm())
3895 .field("arpe", &self.arpe())
3896 .field("ckd", &self.ckd())
3897 .field("uifremap", &self.uifremap())
3898 .field("dithen", &self.dithen())
3899 .finish()
3900 }
3901 }
3902 #[cfg(feature = "defmt")]
3903 impl defmt::Format for Cr11ch {
3904 fn format(&self, f: defmt::Formatter) {
3905 #[derive(defmt :: Format)]
3906 struct Cr11ch {
3907 cen: bool,
3908 udis: bool,
3909 urs: super::vals::Urs,
3910 opm: bool,
3911 arpe: bool,
3912 ckd: super::vals::Ckd,
3913 uifremap: bool,
3914 dithen: bool,
3915 }
3916 let proxy = Cr11ch {
3917 cen: self.cen(),
3918 udis: self.udis(),
3919 urs: self.urs(),
3920 opm: self.opm(),
3921 arpe: self.arpe(),
3922 ckd: self.ckd(),
3923 uifremap: self.uifremap(),
3924 dithen: self.dithen(),
3925 };
3926 defmt::write!(f, "{}", proxy)
3927 }
3928 }
3929 #[doc = "control register 1"]
3930 #[repr(transparent)]
3931 #[derive(Copy, Clone, Eq, PartialEq)]
3932 pub struct Cr1Core(pub u32);
3933 impl Cr1Core {
3934 #[doc = "Counter enable"]
3935 #[inline(always)]
3936 pub const fn cen(&self) -> bool {
3937 let val = (self.0 >> 0usize) & 0x01;
3938 val != 0
3939 }
3940 #[doc = "Counter enable"]
3941 #[inline(always)]
3942 pub fn set_cen(&mut self, val: bool) {
3943 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
3944 }
3945 #[doc = "Update disable"]
3946 #[inline(always)]
3947 pub const fn udis(&self) -> bool {
3948 let val = (self.0 >> 1usize) & 0x01;
3949 val != 0
3950 }
3951 #[doc = "Update disable"]
3952 #[inline(always)]
3953 pub fn set_udis(&mut self, val: bool) {
3954 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
3955 }
3956 #[doc = "Update request source"]
3957 #[inline(always)]
3958 pub const fn urs(&self) -> super::vals::Urs {
3959 let val = (self.0 >> 2usize) & 0x01;
3960 super::vals::Urs::from_bits(val as u8)
3961 }
3962 #[doc = "Update request source"]
3963 #[inline(always)]
3964 pub fn set_urs(&mut self, val: super::vals::Urs) {
3965 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize);
3966 }
3967 #[doc = "One-pulse mode enbaled"]
3968 #[inline(always)]
3969 pub const fn opm(&self) -> bool {
3970 let val = (self.0 >> 3usize) & 0x01;
3971 val != 0
3972 }
3973 #[doc = "One-pulse mode enbaled"]
3974 #[inline(always)]
3975 pub fn set_opm(&mut self, val: bool) {
3976 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
3977 }
3978 #[doc = "Auto-reload preload enable"]
3979 #[inline(always)]
3980 pub const fn arpe(&self) -> bool {
3981 let val = (self.0 >> 7usize) & 0x01;
3982 val != 0
3983 }
3984 #[doc = "Auto-reload preload enable"]
3985 #[inline(always)]
3986 pub fn set_arpe(&mut self, val: bool) {
3987 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
3988 }
3989 #[doc = "UIF status bit remapping enable"]
3990 #[inline(always)]
3991 pub const fn uifremap(&self) -> bool {
3992 let val = (self.0 >> 11usize) & 0x01;
3993 val != 0
3994 }
3995 #[doc = "UIF status bit remapping enable"]
3996 #[inline(always)]
3997 pub fn set_uifremap(&mut self, val: bool) {
3998 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
3999 }
4000 #[doc = "Dithering enable"]
4001 #[inline(always)]
4002 pub const fn dithen(&self) -> bool {
4003 let val = (self.0 >> 12usize) & 0x01;
4004 val != 0
4005 }
4006 #[doc = "Dithering enable"]
4007 #[inline(always)]
4008 pub fn set_dithen(&mut self, val: bool) {
4009 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
4010 }
4011 }
4012 impl Default for Cr1Core {
4013 #[inline(always)]
4014 fn default() -> Cr1Core {
4015 Cr1Core(0)
4016 }
4017 }
4018 impl core::fmt::Debug for Cr1Core {
4019 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4020 f.debug_struct("Cr1Core")
4021 .field("cen", &self.cen())
4022 .field("udis", &self.udis())
4023 .field("urs", &self.urs())
4024 .field("opm", &self.opm())
4025 .field("arpe", &self.arpe())
4026 .field("uifremap", &self.uifremap())
4027 .field("dithen", &self.dithen())
4028 .finish()
4029 }
4030 }
4031 #[cfg(feature = "defmt")]
4032 impl defmt::Format for Cr1Core {
4033 fn format(&self, f: defmt::Formatter) {
4034 #[derive(defmt :: Format)]
4035 struct Cr1Core {
4036 cen: bool,
4037 udis: bool,
4038 urs: super::vals::Urs,
4039 opm: bool,
4040 arpe: bool,
4041 uifremap: bool,
4042 dithen: bool,
4043 }
4044 let proxy = Cr1Core {
4045 cen: self.cen(),
4046 udis: self.udis(),
4047 urs: self.urs(),
4048 opm: self.opm(),
4049 arpe: self.arpe(),
4050 uifremap: self.uifremap(),
4051 dithen: self.dithen(),
4052 };
4053 defmt::write!(f, "{}", proxy)
4054 }
4055 }
4056 #[doc = "control register 1"]
4057 #[repr(transparent)]
4058 #[derive(Copy, Clone, Eq, PartialEq)]
4059 pub struct Cr1Gp16(pub u32);
4060 impl Cr1Gp16 {
4061 #[doc = "Counter enable"]
4062 #[inline(always)]
4063 pub const fn cen(&self) -> bool {
4064 let val = (self.0 >> 0usize) & 0x01;
4065 val != 0
4066 }
4067 #[doc = "Counter enable"]
4068 #[inline(always)]
4069 pub fn set_cen(&mut self, val: bool) {
4070 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
4071 }
4072 #[doc = "Update disable"]
4073 #[inline(always)]
4074 pub const fn udis(&self) -> bool {
4075 let val = (self.0 >> 1usize) & 0x01;
4076 val != 0
4077 }
4078 #[doc = "Update disable"]
4079 #[inline(always)]
4080 pub fn set_udis(&mut self, val: bool) {
4081 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
4082 }
4083 #[doc = "Update request source"]
4084 #[inline(always)]
4085 pub const fn urs(&self) -> super::vals::Urs {
4086 let val = (self.0 >> 2usize) & 0x01;
4087 super::vals::Urs::from_bits(val as u8)
4088 }
4089 #[doc = "Update request source"]
4090 #[inline(always)]
4091 pub fn set_urs(&mut self, val: super::vals::Urs) {
4092 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize);
4093 }
4094 #[doc = "One-pulse mode enbaled"]
4095 #[inline(always)]
4096 pub const fn opm(&self) -> bool {
4097 let val = (self.0 >> 3usize) & 0x01;
4098 val != 0
4099 }
4100 #[doc = "One-pulse mode enbaled"]
4101 #[inline(always)]
4102 pub fn set_opm(&mut self, val: bool) {
4103 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
4104 }
4105 #[doc = "Direction"]
4106 #[inline(always)]
4107 pub const fn dir(&self) -> super::vals::Dir {
4108 let val = (self.0 >> 4usize) & 0x01;
4109 super::vals::Dir::from_bits(val as u8)
4110 }
4111 #[doc = "Direction"]
4112 #[inline(always)]
4113 pub fn set_dir(&mut self, val: super::vals::Dir) {
4114 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize);
4115 }
4116 #[doc = "Center-aligned mode selection"]
4117 #[inline(always)]
4118 pub const fn cms(&self) -> super::vals::Cms {
4119 let val = (self.0 >> 5usize) & 0x03;
4120 super::vals::Cms::from_bits(val as u8)
4121 }
4122 #[doc = "Center-aligned mode selection"]
4123 #[inline(always)]
4124 pub fn set_cms(&mut self, val: super::vals::Cms) {
4125 self.0 = (self.0 & !(0x03 << 5usize)) | (((val.to_bits() as u32) & 0x03) << 5usize);
4126 }
4127 #[doc = "Auto-reload preload enable"]
4128 #[inline(always)]
4129 pub const fn arpe(&self) -> bool {
4130 let val = (self.0 >> 7usize) & 0x01;
4131 val != 0
4132 }
4133 #[doc = "Auto-reload preload enable"]
4134 #[inline(always)]
4135 pub fn set_arpe(&mut self, val: bool) {
4136 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
4137 }
4138 #[doc = "Clock division"]
4139 #[inline(always)]
4140 pub const fn ckd(&self) -> super::vals::Ckd {
4141 let val = (self.0 >> 8usize) & 0x03;
4142 super::vals::Ckd::from_bits(val as u8)
4143 }
4144 #[doc = "Clock division"]
4145 #[inline(always)]
4146 pub fn set_ckd(&mut self, val: super::vals::Ckd) {
4147 self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize);
4148 }
4149 #[doc = "UIF status bit remapping enable"]
4150 #[inline(always)]
4151 pub const fn uifremap(&self) -> bool {
4152 let val = (self.0 >> 11usize) & 0x01;
4153 val != 0
4154 }
4155 #[doc = "UIF status bit remapping enable"]
4156 #[inline(always)]
4157 pub fn set_uifremap(&mut self, val: bool) {
4158 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
4159 }
4160 #[doc = "Dithering enable"]
4161 #[inline(always)]
4162 pub const fn dithen(&self) -> bool {
4163 let val = (self.0 >> 12usize) & 0x01;
4164 val != 0
4165 }
4166 #[doc = "Dithering enable"]
4167 #[inline(always)]
4168 pub fn set_dithen(&mut self, val: bool) {
4169 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
4170 }
4171 }
4172 impl Default for Cr1Gp16 {
4173 #[inline(always)]
4174 fn default() -> Cr1Gp16 {
4175 Cr1Gp16(0)
4176 }
4177 }
4178 impl core::fmt::Debug for Cr1Gp16 {
4179 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4180 f.debug_struct("Cr1Gp16")
4181 .field("cen", &self.cen())
4182 .field("udis", &self.udis())
4183 .field("urs", &self.urs())
4184 .field("opm", &self.opm())
4185 .field("dir", &self.dir())
4186 .field("cms", &self.cms())
4187 .field("arpe", &self.arpe())
4188 .field("ckd", &self.ckd())
4189 .field("uifremap", &self.uifremap())
4190 .field("dithen", &self.dithen())
4191 .finish()
4192 }
4193 }
4194 #[cfg(feature = "defmt")]
4195 impl defmt::Format for Cr1Gp16 {
4196 fn format(&self, f: defmt::Formatter) {
4197 #[derive(defmt :: Format)]
4198 struct Cr1Gp16 {
4199 cen: bool,
4200 udis: bool,
4201 urs: super::vals::Urs,
4202 opm: bool,
4203 dir: super::vals::Dir,
4204 cms: super::vals::Cms,
4205 arpe: bool,
4206 ckd: super::vals::Ckd,
4207 uifremap: bool,
4208 dithen: bool,
4209 }
4210 let proxy = Cr1Gp16 {
4211 cen: self.cen(),
4212 udis: self.udis(),
4213 urs: self.urs(),
4214 opm: self.opm(),
4215 dir: self.dir(),
4216 cms: self.cms(),
4217 arpe: self.arpe(),
4218 ckd: self.ckd(),
4219 uifremap: self.uifremap(),
4220 dithen: self.dithen(),
4221 };
4222 defmt::write!(f, "{}", proxy)
4223 }
4224 }
4225 #[doc = "control register 2"]
4226 #[repr(transparent)]
4227 #[derive(Copy, Clone, Eq, PartialEq)]
4228 pub struct Cr21chCmp(pub u32);
4229 impl Cr21chCmp {
4230 #[doc = "Capture/compare preloaded control"]
4231 #[inline(always)]
4232 pub const fn ccpc(&self) -> bool {
4233 let val = (self.0 >> 0usize) & 0x01;
4234 val != 0
4235 }
4236 #[doc = "Capture/compare preloaded control"]
4237 #[inline(always)]
4238 pub fn set_ccpc(&mut self, val: bool) {
4239 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
4240 }
4241 #[doc = "Capture/compare control update selection"]
4242 #[inline(always)]
4243 pub const fn ccus(&self) -> bool {
4244 let val = (self.0 >> 2usize) & 0x01;
4245 val != 0
4246 }
4247 #[doc = "Capture/compare control update selection"]
4248 #[inline(always)]
4249 pub fn set_ccus(&mut self, val: bool) {
4250 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
4251 }
4252 #[doc = "Capture/compare DMA selection"]
4253 #[inline(always)]
4254 pub const fn ccds(&self) -> super::vals::Ccds {
4255 let val = (self.0 >> 3usize) & 0x01;
4256 super::vals::Ccds::from_bits(val as u8)
4257 }
4258 #[doc = "Capture/compare DMA selection"]
4259 #[inline(always)]
4260 pub fn set_ccds(&mut self, val: super::vals::Ccds) {
4261 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize);
4262 }
4263 #[doc = "Output Idle state x (x=1)"]
4264 #[inline(always)]
4265 pub const fn ois(&self, n: usize) -> bool {
4266 assert!(n < 1usize);
4267 let offs = 8usize + n * 2usize;
4268 let val = (self.0 >> offs) & 0x01;
4269 val != 0
4270 }
4271 #[doc = "Output Idle state x (x=1)"]
4272 #[inline(always)]
4273 pub fn set_ois(&mut self, n: usize, val: bool) {
4274 assert!(n < 1usize);
4275 let offs = 8usize + n * 2usize;
4276 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
4277 }
4278 #[doc = "Output Idle state x (x=1)"]
4279 #[inline(always)]
4280 pub const fn oisn(&self, n: usize) -> bool {
4281 assert!(n < 1usize);
4282 let offs = 9usize + n * 2usize;
4283 let val = (self.0 >> offs) & 0x01;
4284 val != 0
4285 }
4286 #[doc = "Output Idle state x (x=1)"]
4287 #[inline(always)]
4288 pub fn set_oisn(&mut self, n: usize, val: bool) {
4289 assert!(n < 1usize);
4290 let offs = 9usize + n * 2usize;
4291 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
4292 }
4293 }
4294 impl Default for Cr21chCmp {
4295 #[inline(always)]
4296 fn default() -> Cr21chCmp {
4297 Cr21chCmp(0)
4298 }
4299 }
4300 impl core::fmt::Debug for Cr21chCmp {
4301 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4302 f.debug_struct("Cr21chCmp")
4303 .field("ccpc", &self.ccpc())
4304 .field("ccus", &self.ccus())
4305 .field("ccds", &self.ccds())
4306 .field("ois", &[self.ois(0usize)])
4307 .field("oisn", &[self.oisn(0usize)])
4308 .finish()
4309 }
4310 }
4311 #[cfg(feature = "defmt")]
4312 impl defmt::Format for Cr21chCmp {
4313 fn format(&self, f: defmt::Formatter) {
4314 #[derive(defmt :: Format)]
4315 struct Cr21chCmp {
4316 ccpc: bool,
4317 ccus: bool,
4318 ccds: super::vals::Ccds,
4319 ois: [bool; 1usize],
4320 oisn: [bool; 1usize],
4321 }
4322 let proxy = Cr21chCmp {
4323 ccpc: self.ccpc(),
4324 ccus: self.ccus(),
4325 ccds: self.ccds(),
4326 ois: [self.ois(0usize)],
4327 oisn: [self.oisn(0usize)],
4328 };
4329 defmt::write!(f, "{}", proxy)
4330 }
4331 }
4332 #[doc = "control register 2"]
4333 #[repr(transparent)]
4334 #[derive(Copy, Clone, Eq, PartialEq)]
4335 pub struct Cr22ch(pub u32);
4336 impl Cr22ch {
4337 #[doc = "Master mode selection"]
4338 #[inline(always)]
4339 pub const fn mms(&self) -> super::vals::Mms {
4340 let mut val = 0;
4341 val += (((self.0 >> 4usize) & 0x07) << 0usize);
4342 val += (((self.0 >> 25usize) & 0x01) << 3usize);
4343 super::vals::Mms::from_bits(val as u8)
4344 }
4345 #[doc = "Master mode selection"]
4346 #[inline(always)]
4347 pub fn set_mms(&mut self, val: super::vals::Mms) {
4348 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32 >> 0usize) & 0x07) << 4usize);
4349 self.0 = (self.0 & !(0x01 << 25usize)) | (((val.to_bits() as u32 >> 3usize) & 0x01) << 25usize);
4350 }
4351 #[doc = "TI1 selection"]
4352 #[inline(always)]
4353 pub const fn ti1s(&self) -> super::vals::Ti1s {
4354 let val = (self.0 >> 7usize) & 0x01;
4355 super::vals::Ti1s::from_bits(val as u8)
4356 }
4357 #[doc = "TI1 selection"]
4358 #[inline(always)]
4359 pub fn set_ti1s(&mut self, val: super::vals::Ti1s) {
4360 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize);
4361 }
4362 }
4363 impl Default for Cr22ch {
4364 #[inline(always)]
4365 fn default() -> Cr22ch {
4366 Cr22ch(0)
4367 }
4368 }
4369 impl core::fmt::Debug for Cr22ch {
4370 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4371 f.debug_struct("Cr22ch")
4372 .field("mms", &self.mms())
4373 .field("ti1s", &self.ti1s())
4374 .finish()
4375 }
4376 }
4377 #[cfg(feature = "defmt")]
4378 impl defmt::Format for Cr22ch {
4379 fn format(&self, f: defmt::Formatter) {
4380 #[derive(defmt :: Format)]
4381 struct Cr22ch {
4382 mms: super::vals::Mms,
4383 ti1s: super::vals::Ti1s,
4384 }
4385 let proxy = Cr22ch {
4386 mms: self.mms(),
4387 ti1s: self.ti1s(),
4388 };
4389 defmt::write!(f, "{}", proxy)
4390 }
4391 }
4392 #[doc = "control register 2"]
4393 #[repr(transparent)]
4394 #[derive(Copy, Clone, Eq, PartialEq)]
4395 pub struct Cr22chCmp(pub u32);
4396 impl Cr22chCmp {
4397 #[doc = "Capture/compare preloaded control"]
4398 #[inline(always)]
4399 pub const fn ccpc(&self) -> bool {
4400 let val = (self.0 >> 0usize) & 0x01;
4401 val != 0
4402 }
4403 #[doc = "Capture/compare preloaded control"]
4404 #[inline(always)]
4405 pub fn set_ccpc(&mut self, val: bool) {
4406 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
4407 }
4408 #[doc = "Capture/compare control update selection"]
4409 #[inline(always)]
4410 pub const fn ccus(&self) -> bool {
4411 let val = (self.0 >> 2usize) & 0x01;
4412 val != 0
4413 }
4414 #[doc = "Capture/compare control update selection"]
4415 #[inline(always)]
4416 pub fn set_ccus(&mut self, val: bool) {
4417 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
4418 }
4419 #[doc = "Capture/compare DMA selection"]
4420 #[inline(always)]
4421 pub const fn ccds(&self) -> super::vals::Ccds {
4422 let val = (self.0 >> 3usize) & 0x01;
4423 super::vals::Ccds::from_bits(val as u8)
4424 }
4425 #[doc = "Capture/compare DMA selection"]
4426 #[inline(always)]
4427 pub fn set_ccds(&mut self, val: super::vals::Ccds) {
4428 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize);
4429 }
4430 #[doc = "Master mode selection"]
4431 #[inline(always)]
4432 pub const fn mms(&self) -> super::vals::Mms {
4433 let mut val = 0;
4434 val += (((self.0 >> 4usize) & 0x07) << 0usize);
4435 val += (((self.0 >> 25usize) & 0x01) << 3usize);
4436 super::vals::Mms::from_bits(val as u8)
4437 }
4438 #[doc = "Master mode selection"]
4439 #[inline(always)]
4440 pub fn set_mms(&mut self, val: super::vals::Mms) {
4441 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32 >> 0usize) & 0x07) << 4usize);
4442 self.0 = (self.0 & !(0x01 << 25usize)) | (((val.to_bits() as u32 >> 3usize) & 0x01) << 25usize);
4443 }
4444 #[doc = "TI1 selection"]
4445 #[inline(always)]
4446 pub const fn ti1s(&self) -> super::vals::Ti1s {
4447 let val = (self.0 >> 7usize) & 0x01;
4448 super::vals::Ti1s::from_bits(val as u8)
4449 }
4450 #[doc = "TI1 selection"]
4451 #[inline(always)]
4452 pub fn set_ti1s(&mut self, val: super::vals::Ti1s) {
4453 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize);
4454 }
4455 #[doc = "Output Idle state x (x=1,2)"]
4456 #[inline(always)]
4457 pub const fn ois(&self, n: usize) -> bool {
4458 assert!(n < 2usize);
4459 let offs = 8usize + n * 2usize;
4460 let val = (self.0 >> offs) & 0x01;
4461 val != 0
4462 }
4463 #[doc = "Output Idle state x (x=1,2)"]
4464 #[inline(always)]
4465 pub fn set_ois(&mut self, n: usize, val: bool) {
4466 assert!(n < 2usize);
4467 let offs = 8usize + n * 2usize;
4468 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
4469 }
4470 #[doc = "Output Idle state x (x=1)"]
4471 #[inline(always)]
4472 pub const fn oisn(&self, n: usize) -> bool {
4473 assert!(n < 1usize);
4474 let offs = 9usize + n * 2usize;
4475 let val = (self.0 >> offs) & 0x01;
4476 val != 0
4477 }
4478 #[doc = "Output Idle state x (x=1)"]
4479 #[inline(always)]
4480 pub fn set_oisn(&mut self, n: usize, val: bool) {
4481 assert!(n < 1usize);
4482 let offs = 9usize + n * 2usize;
4483 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
4484 }
4485 }
4486 impl Default for Cr22chCmp {
4487 #[inline(always)]
4488 fn default() -> Cr22chCmp {
4489 Cr22chCmp(0)
4490 }
4491 }
4492 impl core::fmt::Debug for Cr22chCmp {
4493 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4494 f.debug_struct("Cr22chCmp")
4495 .field("ccpc", &self.ccpc())
4496 .field("ccus", &self.ccus())
4497 .field("ccds", &self.ccds())
4498 .field("mms", &self.mms())
4499 .field("ti1s", &self.ti1s())
4500 .field("ois", &[self.ois(0usize), self.ois(1usize)])
4501 .field("oisn", &[self.oisn(0usize)])
4502 .finish()
4503 }
4504 }
4505 #[cfg(feature = "defmt")]
4506 impl defmt::Format for Cr22chCmp {
4507 fn format(&self, f: defmt::Formatter) {
4508 #[derive(defmt :: Format)]
4509 struct Cr22chCmp {
4510 ccpc: bool,
4511 ccus: bool,
4512 ccds: super::vals::Ccds,
4513 mms: super::vals::Mms,
4514 ti1s: super::vals::Ti1s,
4515 ois: [bool; 2usize],
4516 oisn: [bool; 1usize],
4517 }
4518 let proxy = Cr22chCmp {
4519 ccpc: self.ccpc(),
4520 ccus: self.ccus(),
4521 ccds: self.ccds(),
4522 mms: self.mms(),
4523 ti1s: self.ti1s(),
4524 ois: [self.ois(0usize), self.ois(1usize)],
4525 oisn: [self.oisn(0usize)],
4526 };
4527 defmt::write!(f, "{}", proxy)
4528 }
4529 }
4530 #[doc = "control register 2"]
4531 #[repr(transparent)]
4532 #[derive(Copy, Clone, Eq, PartialEq)]
4533 pub struct Cr2Adv(pub u32);
4534 impl Cr2Adv {
4535 #[doc = "Capture/compare preloaded control"]
4536 #[inline(always)]
4537 pub const fn ccpc(&self) -> bool {
4538 let val = (self.0 >> 0usize) & 0x01;
4539 val != 0
4540 }
4541 #[doc = "Capture/compare preloaded control"]
4542 #[inline(always)]
4543 pub fn set_ccpc(&mut self, val: bool) {
4544 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
4545 }
4546 #[doc = "Capture/compare control update selection"]
4547 #[inline(always)]
4548 pub const fn ccus(&self) -> bool {
4549 let val = (self.0 >> 2usize) & 0x01;
4550 val != 0
4551 }
4552 #[doc = "Capture/compare control update selection"]
4553 #[inline(always)]
4554 pub fn set_ccus(&mut self, val: bool) {
4555 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
4556 }
4557 #[doc = "Capture/compare DMA selection"]
4558 #[inline(always)]
4559 pub const fn ccds(&self) -> super::vals::Ccds {
4560 let val = (self.0 >> 3usize) & 0x01;
4561 super::vals::Ccds::from_bits(val as u8)
4562 }
4563 #[doc = "Capture/compare DMA selection"]
4564 #[inline(always)]
4565 pub fn set_ccds(&mut self, val: super::vals::Ccds) {
4566 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize);
4567 }
4568 #[doc = "Master mode selection"]
4569 #[inline(always)]
4570 pub const fn mms(&self) -> super::vals::Mms {
4571 let mut val = 0;
4572 val += (((self.0 >> 4usize) & 0x07) << 0usize);
4573 val += (((self.0 >> 25usize) & 0x01) << 3usize);
4574 super::vals::Mms::from_bits(val as u8)
4575 }
4576 #[doc = "Master mode selection"]
4577 #[inline(always)]
4578 pub fn set_mms(&mut self, val: super::vals::Mms) {
4579 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32 >> 0usize) & 0x07) << 4usize);
4580 self.0 = (self.0 & !(0x01 << 25usize)) | (((val.to_bits() as u32 >> 3usize) & 0x01) << 25usize);
4581 }
4582 #[doc = "TI1 selection"]
4583 #[inline(always)]
4584 pub const fn ti1s(&self) -> super::vals::Ti1s {
4585 let val = (self.0 >> 7usize) & 0x01;
4586 super::vals::Ti1s::from_bits(val as u8)
4587 }
4588 #[doc = "TI1 selection"]
4589 #[inline(always)]
4590 pub fn set_ti1s(&mut self, val: super::vals::Ti1s) {
4591 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize);
4592 }
4593 #[doc = "Output Idle state x (x=1-6)"]
4594 #[inline(always)]
4595 pub const fn ois(&self, n: usize) -> bool {
4596 assert!(n < 6usize);
4597 let offs = 8usize + n * 2usize;
4598 let val = (self.0 >> offs) & 0x01;
4599 val != 0
4600 }
4601 #[doc = "Output Idle state x (x=1-6)"]
4602 #[inline(always)]
4603 pub fn set_ois(&mut self, n: usize, val: bool) {
4604 assert!(n < 6usize);
4605 let offs = 8usize + n * 2usize;
4606 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
4607 }
4608 #[doc = "Output Idle state x N x (x=1-4)"]
4609 #[inline(always)]
4610 pub const fn oisn(&self, n: usize) -> bool {
4611 assert!(n < 4usize);
4612 let offs = 9usize + n * 2usize;
4613 let val = (self.0 >> offs) & 0x01;
4614 val != 0
4615 }
4616 #[doc = "Output Idle state x N x (x=1-4)"]
4617 #[inline(always)]
4618 pub fn set_oisn(&mut self, n: usize, val: bool) {
4619 assert!(n < 4usize);
4620 let offs = 9usize + n * 2usize;
4621 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
4622 }
4623 #[doc = "Master mode selection 2"]
4624 #[inline(always)]
4625 pub const fn mms2(&self) -> super::vals::Mms2 {
4626 let val = (self.0 >> 20usize) & 0x0f;
4627 super::vals::Mms2::from_bits(val as u8)
4628 }
4629 #[doc = "Master mode selection 2"]
4630 #[inline(always)]
4631 pub fn set_mms2(&mut self, val: super::vals::Mms2) {
4632 self.0 = (self.0 & !(0x0f << 20usize)) | (((val.to_bits() as u32) & 0x0f) << 20usize);
4633 }
4634 }
4635 impl Default for Cr2Adv {
4636 #[inline(always)]
4637 fn default() -> Cr2Adv {
4638 Cr2Adv(0)
4639 }
4640 }
4641 impl core::fmt::Debug for Cr2Adv {
4642 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4643 f.debug_struct("Cr2Adv")
4644 .field("ccpc", &self.ccpc())
4645 .field("ccus", &self.ccus())
4646 .field("ccds", &self.ccds())
4647 .field("mms", &self.mms())
4648 .field("ti1s", &self.ti1s())
4649 .field(
4650 "ois",
4651 &[
4652 self.ois(0usize),
4653 self.ois(1usize),
4654 self.ois(2usize),
4655 self.ois(3usize),
4656 self.ois(4usize),
4657 self.ois(5usize),
4658 ],
4659 )
4660 .field(
4661 "oisn",
4662 &[
4663 self.oisn(0usize),
4664 self.oisn(1usize),
4665 self.oisn(2usize),
4666 self.oisn(3usize),
4667 ],
4668 )
4669 .field("mms2", &self.mms2())
4670 .finish()
4671 }
4672 }
4673 #[cfg(feature = "defmt")]
4674 impl defmt::Format for Cr2Adv {
4675 fn format(&self, f: defmt::Formatter) {
4676 #[derive(defmt :: Format)]
4677 struct Cr2Adv {
4678 ccpc: bool,
4679 ccus: bool,
4680 ccds: super::vals::Ccds,
4681 mms: super::vals::Mms,
4682 ti1s: super::vals::Ti1s,
4683 ois: [bool; 6usize],
4684 oisn: [bool; 4usize],
4685 mms2: super::vals::Mms2,
4686 }
4687 let proxy = Cr2Adv {
4688 ccpc: self.ccpc(),
4689 ccus: self.ccus(),
4690 ccds: self.ccds(),
4691 mms: self.mms(),
4692 ti1s: self.ti1s(),
4693 ois: [
4694 self.ois(0usize),
4695 self.ois(1usize),
4696 self.ois(2usize),
4697 self.ois(3usize),
4698 self.ois(4usize),
4699 self.ois(5usize),
4700 ],
4701 oisn: [
4702 self.oisn(0usize),
4703 self.oisn(1usize),
4704 self.oisn(2usize),
4705 self.oisn(3usize),
4706 ],
4707 mms2: self.mms2(),
4708 };
4709 defmt::write!(f, "{}", proxy)
4710 }
4711 }
4712 #[doc = "control register 2"]
4713 #[repr(transparent)]
4714 #[derive(Copy, Clone, Eq, PartialEq)]
4715 pub struct Cr2Basic(pub u32);
4716 impl Cr2Basic {
4717 #[doc = "Master mode selection"]
4718 #[inline(always)]
4719 pub const fn mms(&self) -> super::vals::Mms {
4720 let mut val = 0;
4721 val += (((self.0 >> 4usize) & 0x07) << 0usize);
4722 val += (((self.0 >> 25usize) & 0x01) << 3usize);
4723 super::vals::Mms::from_bits(val as u8)
4724 }
4725 #[doc = "Master mode selection"]
4726 #[inline(always)]
4727 pub fn set_mms(&mut self, val: super::vals::Mms) {
4728 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32 >> 0usize) & 0x07) << 4usize);
4729 self.0 = (self.0 & !(0x01 << 25usize)) | (((val.to_bits() as u32 >> 3usize) & 0x01) << 25usize);
4730 }
4731 }
4732 impl Default for Cr2Basic {
4733 #[inline(always)]
4734 fn default() -> Cr2Basic {
4735 Cr2Basic(0)
4736 }
4737 }
4738 impl core::fmt::Debug for Cr2Basic {
4739 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4740 f.debug_struct("Cr2Basic").field("mms", &self.mms()).finish()
4741 }
4742 }
4743 #[cfg(feature = "defmt")]
4744 impl defmt::Format for Cr2Basic {
4745 fn format(&self, f: defmt::Formatter) {
4746 #[derive(defmt :: Format)]
4747 struct Cr2Basic {
4748 mms: super::vals::Mms,
4749 }
4750 let proxy = Cr2Basic { mms: self.mms() };
4751 defmt::write!(f, "{}", proxy)
4752 }
4753 }
4754 #[doc = "control register 2"]
4755 #[repr(transparent)]
4756 #[derive(Copy, Clone, Eq, PartialEq)]
4757 pub struct Cr2Gp16(pub u32);
4758 impl Cr2Gp16 {
4759 #[doc = "Capture/compare DMA selection"]
4760 #[inline(always)]
4761 pub const fn ccds(&self) -> super::vals::Ccds {
4762 let val = (self.0 >> 3usize) & 0x01;
4763 super::vals::Ccds::from_bits(val as u8)
4764 }
4765 #[doc = "Capture/compare DMA selection"]
4766 #[inline(always)]
4767 pub fn set_ccds(&mut self, val: super::vals::Ccds) {
4768 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize);
4769 }
4770 #[doc = "Master mode selection"]
4771 #[inline(always)]
4772 pub const fn mms(&self) -> super::vals::Mms {
4773 let mut val = 0;
4774 val += (((self.0 >> 4usize) & 0x07) << 0usize);
4775 val += (((self.0 >> 25usize) & 0x01) << 3usize);
4776 super::vals::Mms::from_bits(val as u8)
4777 }
4778 #[doc = "Master mode selection"]
4779 #[inline(always)]
4780 pub fn set_mms(&mut self, val: super::vals::Mms) {
4781 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32 >> 0usize) & 0x07) << 4usize);
4782 self.0 = (self.0 & !(0x01 << 25usize)) | (((val.to_bits() as u32 >> 3usize) & 0x01) << 25usize);
4783 }
4784 #[doc = "TI1 selection"]
4785 #[inline(always)]
4786 pub const fn ti1s(&self) -> super::vals::Ti1s {
4787 let val = (self.0 >> 7usize) & 0x01;
4788 super::vals::Ti1s::from_bits(val as u8)
4789 }
4790 #[doc = "TI1 selection"]
4791 #[inline(always)]
4792 pub fn set_ti1s(&mut self, val: super::vals::Ti1s) {
4793 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize);
4794 }
4795 }
4796 impl Default for Cr2Gp16 {
4797 #[inline(always)]
4798 fn default() -> Cr2Gp16 {
4799 Cr2Gp16(0)
4800 }
4801 }
4802 impl core::fmt::Debug for Cr2Gp16 {
4803 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4804 f.debug_struct("Cr2Gp16")
4805 .field("ccds", &self.ccds())
4806 .field("mms", &self.mms())
4807 .field("ti1s", &self.ti1s())
4808 .finish()
4809 }
4810 }
4811 #[cfg(feature = "defmt")]
4812 impl defmt::Format for Cr2Gp16 {
4813 fn format(&self, f: defmt::Formatter) {
4814 #[derive(defmt :: Format)]
4815 struct Cr2Gp16 {
4816 ccds: super::vals::Ccds,
4817 mms: super::vals::Mms,
4818 ti1s: super::vals::Ti1s,
4819 }
4820 let proxy = Cr2Gp16 {
4821 ccds: self.ccds(),
4822 mms: self.mms(),
4823 ti1s: self.ti1s(),
4824 };
4825 defmt::write!(f, "{}", proxy)
4826 }
4827 }
4828 #[doc = "DMA control register"]
4829 #[repr(transparent)]
4830 #[derive(Copy, Clone, Eq, PartialEq)]
4831 pub struct Dcr1chCmp(pub u32);
4832 impl Dcr1chCmp {
4833 #[doc = "DMA base address"]
4834 #[inline(always)]
4835 pub const fn dba(&self) -> u8 {
4836 let val = (self.0 >> 0usize) & 0x1f;
4837 val as u8
4838 }
4839 #[doc = "DMA base address"]
4840 #[inline(always)]
4841 pub fn set_dba(&mut self, val: u8) {
4842 self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
4843 }
4844 #[doc = "DMA burst length"]
4845 #[inline(always)]
4846 pub const fn dbl(&self) -> u8 {
4847 let val = (self.0 >> 8usize) & 0x1f;
4848 val as u8
4849 }
4850 #[doc = "DMA burst length"]
4851 #[inline(always)]
4852 pub fn set_dbl(&mut self, val: u8) {
4853 self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize);
4854 }
4855 #[doc = "DMA burst source selection"]
4856 #[inline(always)]
4857 pub const fn dbss(&self) -> super::vals::Dbss {
4858 let val = (self.0 >> 16usize) & 0x0f;
4859 super::vals::Dbss::from_bits(val as u8)
4860 }
4861 #[doc = "DMA burst source selection"]
4862 #[inline(always)]
4863 pub fn set_dbss(&mut self, val: super::vals::Dbss) {
4864 self.0 = (self.0 & !(0x0f << 16usize)) | (((val.to_bits() as u32) & 0x0f) << 16usize);
4865 }
4866 }
4867 impl Default for Dcr1chCmp {
4868 #[inline(always)]
4869 fn default() -> Dcr1chCmp {
4870 Dcr1chCmp(0)
4871 }
4872 }
4873 impl core::fmt::Debug for Dcr1chCmp {
4874 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4875 f.debug_struct("Dcr1chCmp")
4876 .field("dba", &self.dba())
4877 .field("dbl", &self.dbl())
4878 .field("dbss", &self.dbss())
4879 .finish()
4880 }
4881 }
4882 #[cfg(feature = "defmt")]
4883 impl defmt::Format for Dcr1chCmp {
4884 fn format(&self, f: defmt::Formatter) {
4885 #[derive(defmt :: Format)]
4886 struct Dcr1chCmp {
4887 dba: u8,
4888 dbl: u8,
4889 dbss: super::vals::Dbss,
4890 }
4891 let proxy = Dcr1chCmp {
4892 dba: self.dba(),
4893 dbl: self.dbl(),
4894 dbss: self.dbss(),
4895 };
4896 defmt::write!(f, "{}", proxy)
4897 }
4898 }
4899 #[doc = "DMA/Interrupt enable register"]
4900 #[repr(transparent)]
4901 #[derive(Copy, Clone, Eq, PartialEq)]
4902 pub struct Dier1ch(pub u32);
4903 impl Dier1ch {
4904 #[doc = "Update interrupt enable"]
4905 #[inline(always)]
4906 pub const fn uie(&self) -> bool {
4907 let val = (self.0 >> 0usize) & 0x01;
4908 val != 0
4909 }
4910 #[doc = "Update interrupt enable"]
4911 #[inline(always)]
4912 pub fn set_uie(&mut self, val: bool) {
4913 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
4914 }
4915 #[doc = "Capture/Compare x (x=1) interrupt enable"]
4916 #[inline(always)]
4917 pub const fn ccie(&self, n: usize) -> bool {
4918 assert!(n < 1usize);
4919 let offs = 1usize + n * 1usize;
4920 let val = (self.0 >> offs) & 0x01;
4921 val != 0
4922 }
4923 #[doc = "Capture/Compare x (x=1) interrupt enable"]
4924 #[inline(always)]
4925 pub fn set_ccie(&mut self, n: usize, val: bool) {
4926 assert!(n < 1usize);
4927 let offs = 1usize + n * 1usize;
4928 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
4929 }
4930 }
4931 impl Default for Dier1ch {
4932 #[inline(always)]
4933 fn default() -> Dier1ch {
4934 Dier1ch(0)
4935 }
4936 }
4937 impl core::fmt::Debug for Dier1ch {
4938 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4939 f.debug_struct("Dier1ch")
4940 .field("uie", &self.uie())
4941 .field("ccie", &[self.ccie(0usize)])
4942 .finish()
4943 }
4944 }
4945 #[cfg(feature = "defmt")]
4946 impl defmt::Format for Dier1ch {
4947 fn format(&self, f: defmt::Formatter) {
4948 #[derive(defmt :: Format)]
4949 struct Dier1ch {
4950 uie: bool,
4951 ccie: [bool; 1usize],
4952 }
4953 let proxy = Dier1ch {
4954 uie: self.uie(),
4955 ccie: [self.ccie(0usize)],
4956 };
4957 defmt::write!(f, "{}", proxy)
4958 }
4959 }
4960 #[doc = "DMA/Interrupt enable register"]
4961 #[repr(transparent)]
4962 #[derive(Copy, Clone, Eq, PartialEq)]
4963 pub struct Dier1chCmp(pub u32);
4964 impl Dier1chCmp {
4965 #[doc = "Update interrupt enable"]
4966 #[inline(always)]
4967 pub const fn uie(&self) -> bool {
4968 let val = (self.0 >> 0usize) & 0x01;
4969 val != 0
4970 }
4971 #[doc = "Update interrupt enable"]
4972 #[inline(always)]
4973 pub fn set_uie(&mut self, val: bool) {
4974 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
4975 }
4976 #[doc = "Capture/Compare x (x=1) interrupt enable"]
4977 #[inline(always)]
4978 pub const fn ccie(&self, n: usize) -> bool {
4979 assert!(n < 1usize);
4980 let offs = 1usize + n * 1usize;
4981 let val = (self.0 >> offs) & 0x01;
4982 val != 0
4983 }
4984 #[doc = "Capture/Compare x (x=1) interrupt enable"]
4985 #[inline(always)]
4986 pub fn set_ccie(&mut self, n: usize, val: bool) {
4987 assert!(n < 1usize);
4988 let offs = 1usize + n * 1usize;
4989 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
4990 }
4991 #[doc = "COM interrupt enable"]
4992 #[inline(always)]
4993 pub const fn comie(&self) -> bool {
4994 let val = (self.0 >> 5usize) & 0x01;
4995 val != 0
4996 }
4997 #[doc = "COM interrupt enable"]
4998 #[inline(always)]
4999 pub fn set_comie(&mut self, val: bool) {
5000 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
5001 }
5002 #[doc = "Break interrupt enable"]
5003 #[inline(always)]
5004 pub const fn bie(&self) -> bool {
5005 let val = (self.0 >> 7usize) & 0x01;
5006 val != 0
5007 }
5008 #[doc = "Break interrupt enable"]
5009 #[inline(always)]
5010 pub fn set_bie(&mut self, val: bool) {
5011 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
5012 }
5013 #[doc = "Update DMA request enable"]
5014 #[inline(always)]
5015 pub const fn ude(&self) -> bool {
5016 let val = (self.0 >> 8usize) & 0x01;
5017 val != 0
5018 }
5019 #[doc = "Update DMA request enable"]
5020 #[inline(always)]
5021 pub fn set_ude(&mut self, val: bool) {
5022 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
5023 }
5024 #[doc = "Capture/Compare x (x=1) DMA request enable"]
5025 #[inline(always)]
5026 pub const fn ccde(&self, n: usize) -> bool {
5027 assert!(n < 1usize);
5028 let offs = 9usize + n * 1usize;
5029 let val = (self.0 >> offs) & 0x01;
5030 val != 0
5031 }
5032 #[doc = "Capture/Compare x (x=1) DMA request enable"]
5033 #[inline(always)]
5034 pub fn set_ccde(&mut self, n: usize, val: bool) {
5035 assert!(n < 1usize);
5036 let offs = 9usize + n * 1usize;
5037 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
5038 }
5039 }
5040 impl Default for Dier1chCmp {
5041 #[inline(always)]
5042 fn default() -> Dier1chCmp {
5043 Dier1chCmp(0)
5044 }
5045 }
5046 impl core::fmt::Debug for Dier1chCmp {
5047 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5048 f.debug_struct("Dier1chCmp")
5049 .field("uie", &self.uie())
5050 .field("ccie", &[self.ccie(0usize)])
5051 .field("comie", &self.comie())
5052 .field("bie", &self.bie())
5053 .field("ude", &self.ude())
5054 .field("ccde", &[self.ccde(0usize)])
5055 .finish()
5056 }
5057 }
5058 #[cfg(feature = "defmt")]
5059 impl defmt::Format for Dier1chCmp {
5060 fn format(&self, f: defmt::Formatter) {
5061 #[derive(defmt :: Format)]
5062 struct Dier1chCmp {
5063 uie: bool,
5064 ccie: [bool; 1usize],
5065 comie: bool,
5066 bie: bool,
5067 ude: bool,
5068 ccde: [bool; 1usize],
5069 }
5070 let proxy = Dier1chCmp {
5071 uie: self.uie(),
5072 ccie: [self.ccie(0usize)],
5073 comie: self.comie(),
5074 bie: self.bie(),
5075 ude: self.ude(),
5076 ccde: [self.ccde(0usize)],
5077 };
5078 defmt::write!(f, "{}", proxy)
5079 }
5080 }
5081 #[doc = "DMA/Interrupt enable register"]
5082 #[repr(transparent)]
5083 #[derive(Copy, Clone, Eq, PartialEq)]
5084 pub struct Dier2ch(pub u32);
5085 impl Dier2ch {
5086 #[doc = "Update interrupt enable"]
5087 #[inline(always)]
5088 pub const fn uie(&self) -> bool {
5089 let val = (self.0 >> 0usize) & 0x01;
5090 val != 0
5091 }
5092 #[doc = "Update interrupt enable"]
5093 #[inline(always)]
5094 pub fn set_uie(&mut self, val: bool) {
5095 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
5096 }
5097 #[doc = "Capture/Compare x (x=1-2) interrupt enable"]
5098 #[inline(always)]
5099 pub const fn ccie(&self, n: usize) -> bool {
5100 assert!(n < 2usize);
5101 let offs = 1usize + n * 1usize;
5102 let val = (self.0 >> offs) & 0x01;
5103 val != 0
5104 }
5105 #[doc = "Capture/Compare x (x=1-2) interrupt enable"]
5106 #[inline(always)]
5107 pub fn set_ccie(&mut self, n: usize, val: bool) {
5108 assert!(n < 2usize);
5109 let offs = 1usize + n * 1usize;
5110 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
5111 }
5112 #[doc = "Trigger interrupt enable"]
5113 #[inline(always)]
5114 pub const fn tie(&self) -> bool {
5115 let val = (self.0 >> 6usize) & 0x01;
5116 val != 0
5117 }
5118 #[doc = "Trigger interrupt enable"]
5119 #[inline(always)]
5120 pub fn set_tie(&mut self, val: bool) {
5121 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
5122 }
5123 }
5124 impl Default for Dier2ch {
5125 #[inline(always)]
5126 fn default() -> Dier2ch {
5127 Dier2ch(0)
5128 }
5129 }
5130 impl core::fmt::Debug for Dier2ch {
5131 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5132 f.debug_struct("Dier2ch")
5133 .field("uie", &self.uie())
5134 .field("ccie", &[self.ccie(0usize), self.ccie(1usize)])
5135 .field("tie", &self.tie())
5136 .finish()
5137 }
5138 }
5139 #[cfg(feature = "defmt")]
5140 impl defmt::Format for Dier2ch {
5141 fn format(&self, f: defmt::Formatter) {
5142 #[derive(defmt :: Format)]
5143 struct Dier2ch {
5144 uie: bool,
5145 ccie: [bool; 2usize],
5146 tie: bool,
5147 }
5148 let proxy = Dier2ch {
5149 uie: self.uie(),
5150 ccie: [self.ccie(0usize), self.ccie(1usize)],
5151 tie: self.tie(),
5152 };
5153 defmt::write!(f, "{}", proxy)
5154 }
5155 }
5156 #[doc = "DMA/Interrupt enable register"]
5157 #[repr(transparent)]
5158 #[derive(Copy, Clone, Eq, PartialEq)]
5159 pub struct Dier2chCmp(pub u32);
5160 impl Dier2chCmp {
5161 #[doc = "Update interrupt enable"]
5162 #[inline(always)]
5163 pub const fn uie(&self) -> bool {
5164 let val = (self.0 >> 0usize) & 0x01;
5165 val != 0
5166 }
5167 #[doc = "Update interrupt enable"]
5168 #[inline(always)]
5169 pub fn set_uie(&mut self, val: bool) {
5170 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
5171 }
5172 #[doc = "Capture/Compare x (x=1) interrupt enable"]
5173 #[inline(always)]
5174 pub const fn ccie(&self, n: usize) -> bool {
5175 assert!(n < 1usize);
5176 let offs = 1usize + n * 1usize;
5177 let val = (self.0 >> offs) & 0x01;
5178 val != 0
5179 }
5180 #[doc = "Capture/Compare x (x=1) interrupt enable"]
5181 #[inline(always)]
5182 pub fn set_ccie(&mut self, n: usize, val: bool) {
5183 assert!(n < 1usize);
5184 let offs = 1usize + n * 1usize;
5185 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
5186 }
5187 #[doc = "COM interrupt enable"]
5188 #[inline(always)]
5189 pub const fn comie(&self) -> bool {
5190 let val = (self.0 >> 5usize) & 0x01;
5191 val != 0
5192 }
5193 #[doc = "COM interrupt enable"]
5194 #[inline(always)]
5195 pub fn set_comie(&mut self, val: bool) {
5196 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
5197 }
5198 #[doc = "Trigger interrupt enable"]
5199 #[inline(always)]
5200 pub const fn tie(&self) -> bool {
5201 let val = (self.0 >> 6usize) & 0x01;
5202 val != 0
5203 }
5204 #[doc = "Trigger interrupt enable"]
5205 #[inline(always)]
5206 pub fn set_tie(&mut self, val: bool) {
5207 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
5208 }
5209 #[doc = "Break interrupt enable"]
5210 #[inline(always)]
5211 pub const fn bie(&self) -> bool {
5212 let val = (self.0 >> 7usize) & 0x01;
5213 val != 0
5214 }
5215 #[doc = "Break interrupt enable"]
5216 #[inline(always)]
5217 pub fn set_bie(&mut self, val: bool) {
5218 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
5219 }
5220 #[doc = "Update DMA request enable"]
5221 #[inline(always)]
5222 pub const fn ude(&self) -> bool {
5223 let val = (self.0 >> 8usize) & 0x01;
5224 val != 0
5225 }
5226 #[doc = "Update DMA request enable"]
5227 #[inline(always)]
5228 pub fn set_ude(&mut self, val: bool) {
5229 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
5230 }
5231 #[doc = "Capture/Compare x (x=1) DMA request enable"]
5232 #[inline(always)]
5233 pub const fn ccde(&self, n: usize) -> bool {
5234 assert!(n < 1usize);
5235 let offs = 9usize + n * 1usize;
5236 let val = (self.0 >> offs) & 0x01;
5237 val != 0
5238 }
5239 #[doc = "Capture/Compare x (x=1) DMA request enable"]
5240 #[inline(always)]
5241 pub fn set_ccde(&mut self, n: usize, val: bool) {
5242 assert!(n < 1usize);
5243 let offs = 9usize + n * 1usize;
5244 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
5245 }
5246 #[doc = "COM DMA request enable"]
5247 #[inline(always)]
5248 pub const fn comde(&self) -> bool {
5249 let val = (self.0 >> 13usize) & 0x01;
5250 val != 0
5251 }
5252 #[doc = "COM DMA request enable"]
5253 #[inline(always)]
5254 pub fn set_comde(&mut self, val: bool) {
5255 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
5256 }
5257 #[doc = "Trigger DMA request enable"]
5258 #[inline(always)]
5259 pub const fn tde(&self) -> bool {
5260 let val = (self.0 >> 14usize) & 0x01;
5261 val != 0
5262 }
5263 #[doc = "Trigger DMA request enable"]
5264 #[inline(always)]
5265 pub fn set_tde(&mut self, val: bool) {
5266 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
5267 }
5268 }
5269 impl Default for Dier2chCmp {
5270 #[inline(always)]
5271 fn default() -> Dier2chCmp {
5272 Dier2chCmp(0)
5273 }
5274 }
5275 impl core::fmt::Debug for Dier2chCmp {
5276 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5277 f.debug_struct("Dier2chCmp")
5278 .field("uie", &self.uie())
5279 .field("ccie", &[self.ccie(0usize)])
5280 .field("comie", &self.comie())
5281 .field("tie", &self.tie())
5282 .field("bie", &self.bie())
5283 .field("ude", &self.ude())
5284 .field("ccde", &[self.ccde(0usize)])
5285 .field("comde", &self.comde())
5286 .field("tde", &self.tde())
5287 .finish()
5288 }
5289 }
5290 #[cfg(feature = "defmt")]
5291 impl defmt::Format for Dier2chCmp {
5292 fn format(&self, f: defmt::Formatter) {
5293 #[derive(defmt :: Format)]
5294 struct Dier2chCmp {
5295 uie: bool,
5296 ccie: [bool; 1usize],
5297 comie: bool,
5298 tie: bool,
5299 bie: bool,
5300 ude: bool,
5301 ccde: [bool; 1usize],
5302 comde: bool,
5303 tde: bool,
5304 }
5305 let proxy = Dier2chCmp {
5306 uie: self.uie(),
5307 ccie: [self.ccie(0usize)],
5308 comie: self.comie(),
5309 tie: self.tie(),
5310 bie: self.bie(),
5311 ude: self.ude(),
5312 ccde: [self.ccde(0usize)],
5313 comde: self.comde(),
5314 tde: self.tde(),
5315 };
5316 defmt::write!(f, "{}", proxy)
5317 }
5318 }
5319 #[doc = "DMA/Interrupt enable register"]
5320 #[repr(transparent)]
5321 #[derive(Copy, Clone, Eq, PartialEq)]
5322 pub struct DierAdv(pub u32);
5323 impl DierAdv {
5324 #[doc = "Update interrupt enable"]
5325 #[inline(always)]
5326 pub const fn uie(&self) -> bool {
5327 let val = (self.0 >> 0usize) & 0x01;
5328 val != 0
5329 }
5330 #[doc = "Update interrupt enable"]
5331 #[inline(always)]
5332 pub fn set_uie(&mut self, val: bool) {
5333 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
5334 }
5335 #[doc = "Capture/Compare x (x=1-4) interrupt enable"]
5336 #[inline(always)]
5337 pub const fn ccie(&self, n: usize) -> bool {
5338 assert!(n < 4usize);
5339 let offs = 1usize + n * 1usize;
5340 let val = (self.0 >> offs) & 0x01;
5341 val != 0
5342 }
5343 #[doc = "Capture/Compare x (x=1-4) interrupt enable"]
5344 #[inline(always)]
5345 pub fn set_ccie(&mut self, n: usize, val: bool) {
5346 assert!(n < 4usize);
5347 let offs = 1usize + n * 1usize;
5348 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
5349 }
5350 #[doc = "COM interrupt enable"]
5351 #[inline(always)]
5352 pub const fn comie(&self) -> bool {
5353 let val = (self.0 >> 5usize) & 0x01;
5354 val != 0
5355 }
5356 #[doc = "COM interrupt enable"]
5357 #[inline(always)]
5358 pub fn set_comie(&mut self, val: bool) {
5359 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
5360 }
5361 #[doc = "Trigger interrupt enable"]
5362 #[inline(always)]
5363 pub const fn tie(&self) -> bool {
5364 let val = (self.0 >> 6usize) & 0x01;
5365 val != 0
5366 }
5367 #[doc = "Trigger interrupt enable"]
5368 #[inline(always)]
5369 pub fn set_tie(&mut self, val: bool) {
5370 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
5371 }
5372 #[doc = "Break interrupt enable"]
5373 #[inline(always)]
5374 pub const fn bie(&self) -> bool {
5375 let val = (self.0 >> 7usize) & 0x01;
5376 val != 0
5377 }
5378 #[doc = "Break interrupt enable"]
5379 #[inline(always)]
5380 pub fn set_bie(&mut self, val: bool) {
5381 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
5382 }
5383 #[doc = "Update DMA request enable"]
5384 #[inline(always)]
5385 pub const fn ude(&self) -> bool {
5386 let val = (self.0 >> 8usize) & 0x01;
5387 val != 0
5388 }
5389 #[doc = "Update DMA request enable"]
5390 #[inline(always)]
5391 pub fn set_ude(&mut self, val: bool) {
5392 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
5393 }
5394 #[doc = "Capture/Compare x (x=1) DMA request enable"]
5395 #[inline(always)]
5396 pub const fn ccde(&self, n: usize) -> bool {
5397 assert!(n < 4usize);
5398 let offs = 9usize + n * 1usize;
5399 let val = (self.0 >> offs) & 0x01;
5400 val != 0
5401 }
5402 #[doc = "Capture/Compare x (x=1) DMA request enable"]
5403 #[inline(always)]
5404 pub fn set_ccde(&mut self, n: usize, val: bool) {
5405 assert!(n < 4usize);
5406 let offs = 9usize + n * 1usize;
5407 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
5408 }
5409 #[doc = "COM DMA request enable"]
5410 #[inline(always)]
5411 pub const fn comde(&self) -> bool {
5412 let val = (self.0 >> 13usize) & 0x01;
5413 val != 0
5414 }
5415 #[doc = "COM DMA request enable"]
5416 #[inline(always)]
5417 pub fn set_comde(&mut self, val: bool) {
5418 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
5419 }
5420 #[doc = "Trigger DMA request enable"]
5421 #[inline(always)]
5422 pub const fn tde(&self) -> bool {
5423 let val = (self.0 >> 14usize) & 0x01;
5424 val != 0
5425 }
5426 #[doc = "Trigger DMA request enable"]
5427 #[inline(always)]
5428 pub fn set_tde(&mut self, val: bool) {
5429 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
5430 }
5431 #[doc = "Index interrupt enable"]
5432 #[inline(always)]
5433 pub const fn idxie(&self) -> bool {
5434 let val = (self.0 >> 20usize) & 0x01;
5435 val != 0
5436 }
5437 #[doc = "Index interrupt enable"]
5438 #[inline(always)]
5439 pub fn set_idxie(&mut self, val: bool) {
5440 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
5441 }
5442 #[doc = "Direction change interrupt enable"]
5443 #[inline(always)]
5444 pub const fn dirie(&self) -> bool {
5445 let val = (self.0 >> 21usize) & 0x01;
5446 val != 0
5447 }
5448 #[doc = "Direction change interrupt enable"]
5449 #[inline(always)]
5450 pub fn set_dirie(&mut self, val: bool) {
5451 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
5452 }
5453 #[doc = "Index error interrupt enable"]
5454 #[inline(always)]
5455 pub const fn ierrie(&self) -> bool {
5456 let val = (self.0 >> 22usize) & 0x01;
5457 val != 0
5458 }
5459 #[doc = "Index error interrupt enable"]
5460 #[inline(always)]
5461 pub fn set_ierrie(&mut self, val: bool) {
5462 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
5463 }
5464 #[doc = "Transition error interrupt enable"]
5465 #[inline(always)]
5466 pub const fn terrie(&self) -> bool {
5467 let val = (self.0 >> 23usize) & 0x01;
5468 val != 0
5469 }
5470 #[doc = "Transition error interrupt enable"]
5471 #[inline(always)]
5472 pub fn set_terrie(&mut self, val: bool) {
5473 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
5474 }
5475 }
5476 impl Default for DierAdv {
5477 #[inline(always)]
5478 fn default() -> DierAdv {
5479 DierAdv(0)
5480 }
5481 }
5482 impl core::fmt::Debug for DierAdv {
5483 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5484 f.debug_struct("DierAdv")
5485 .field("uie", &self.uie())
5486 .field(
5487 "ccie",
5488 &[
5489 self.ccie(0usize),
5490 self.ccie(1usize),
5491 self.ccie(2usize),
5492 self.ccie(3usize),
5493 ],
5494 )
5495 .field("comie", &self.comie())
5496 .field("tie", &self.tie())
5497 .field("bie", &self.bie())
5498 .field("ude", &self.ude())
5499 .field(
5500 "ccde",
5501 &[
5502 self.ccde(0usize),
5503 self.ccde(1usize),
5504 self.ccde(2usize),
5505 self.ccde(3usize),
5506 ],
5507 )
5508 .field("comde", &self.comde())
5509 .field("tde", &self.tde())
5510 .field("idxie", &self.idxie())
5511 .field("dirie", &self.dirie())
5512 .field("ierrie", &self.ierrie())
5513 .field("terrie", &self.terrie())
5514 .finish()
5515 }
5516 }
5517 #[cfg(feature = "defmt")]
5518 impl defmt::Format for DierAdv {
5519 fn format(&self, f: defmt::Formatter) {
5520 #[derive(defmt :: Format)]
5521 struct DierAdv {
5522 uie: bool,
5523 ccie: [bool; 4usize],
5524 comie: bool,
5525 tie: bool,
5526 bie: bool,
5527 ude: bool,
5528 ccde: [bool; 4usize],
5529 comde: bool,
5530 tde: bool,
5531 idxie: bool,
5532 dirie: bool,
5533 ierrie: bool,
5534 terrie: bool,
5535 }
5536 let proxy = DierAdv {
5537 uie: self.uie(),
5538 ccie: [
5539 self.ccie(0usize),
5540 self.ccie(1usize),
5541 self.ccie(2usize),
5542 self.ccie(3usize),
5543 ],
5544 comie: self.comie(),
5545 tie: self.tie(),
5546 bie: self.bie(),
5547 ude: self.ude(),
5548 ccde: [
5549 self.ccde(0usize),
5550 self.ccde(1usize),
5551 self.ccde(2usize),
5552 self.ccde(3usize),
5553 ],
5554 comde: self.comde(),
5555 tde: self.tde(),
5556 idxie: self.idxie(),
5557 dirie: self.dirie(),
5558 ierrie: self.ierrie(),
5559 terrie: self.terrie(),
5560 };
5561 defmt::write!(f, "{}", proxy)
5562 }
5563 }
5564 #[doc = "DMA/Interrupt enable register"]
5565 #[repr(transparent)]
5566 #[derive(Copy, Clone, Eq, PartialEq)]
5567 pub struct DierBasicNoCr2(pub u32);
5568 impl DierBasicNoCr2 {
5569 #[doc = "Update interrupt enable"]
5570 #[inline(always)]
5571 pub const fn uie(&self) -> bool {
5572 let val = (self.0 >> 0usize) & 0x01;
5573 val != 0
5574 }
5575 #[doc = "Update interrupt enable"]
5576 #[inline(always)]
5577 pub fn set_uie(&mut self, val: bool) {
5578 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
5579 }
5580 #[doc = "Update DMA request enable"]
5581 #[inline(always)]
5582 pub const fn ude(&self) -> bool {
5583 let val = (self.0 >> 8usize) & 0x01;
5584 val != 0
5585 }
5586 #[doc = "Update DMA request enable"]
5587 #[inline(always)]
5588 pub fn set_ude(&mut self, val: bool) {
5589 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
5590 }
5591 }
5592 impl Default for DierBasicNoCr2 {
5593 #[inline(always)]
5594 fn default() -> DierBasicNoCr2 {
5595 DierBasicNoCr2(0)
5596 }
5597 }
5598 impl core::fmt::Debug for DierBasicNoCr2 {
5599 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5600 f.debug_struct("DierBasicNoCr2")
5601 .field("uie", &self.uie())
5602 .field("ude", &self.ude())
5603 .finish()
5604 }
5605 }
5606 #[cfg(feature = "defmt")]
5607 impl defmt::Format for DierBasicNoCr2 {
5608 fn format(&self, f: defmt::Formatter) {
5609 #[derive(defmt :: Format)]
5610 struct DierBasicNoCr2 {
5611 uie: bool,
5612 ude: bool,
5613 }
5614 let proxy = DierBasicNoCr2 {
5615 uie: self.uie(),
5616 ude: self.ude(),
5617 };
5618 defmt::write!(f, "{}", proxy)
5619 }
5620 }
5621 #[doc = "DMA/Interrupt enable register"]
5622 #[repr(transparent)]
5623 #[derive(Copy, Clone, Eq, PartialEq)]
5624 pub struct DierCore(pub u32);
5625 impl DierCore {
5626 #[doc = "Update interrupt enable"]
5627 #[inline(always)]
5628 pub const fn uie(&self) -> bool {
5629 let val = (self.0 >> 0usize) & 0x01;
5630 val != 0
5631 }
5632 #[doc = "Update interrupt enable"]
5633 #[inline(always)]
5634 pub fn set_uie(&mut self, val: bool) {
5635 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
5636 }
5637 }
5638 impl Default for DierCore {
5639 #[inline(always)]
5640 fn default() -> DierCore {
5641 DierCore(0)
5642 }
5643 }
5644 impl core::fmt::Debug for DierCore {
5645 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5646 f.debug_struct("DierCore").field("uie", &self.uie()).finish()
5647 }
5648 }
5649 #[cfg(feature = "defmt")]
5650 impl defmt::Format for DierCore {
5651 fn format(&self, f: defmt::Formatter) {
5652 #[derive(defmt :: Format)]
5653 struct DierCore {
5654 uie: bool,
5655 }
5656 let proxy = DierCore { uie: self.uie() };
5657 defmt::write!(f, "{}", proxy)
5658 }
5659 }
5660 #[doc = "DMA/Interrupt enable register"]
5661 #[repr(transparent)]
5662 #[derive(Copy, Clone, Eq, PartialEq)]
5663 pub struct DierGp16(pub u32);
5664 impl DierGp16 {
5665 #[doc = "Update interrupt enable"]
5666 #[inline(always)]
5667 pub const fn uie(&self) -> bool {
5668 let val = (self.0 >> 0usize) & 0x01;
5669 val != 0
5670 }
5671 #[doc = "Update interrupt enable"]
5672 #[inline(always)]
5673 pub fn set_uie(&mut self, val: bool) {
5674 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
5675 }
5676 #[doc = "Capture/Compare x (x=1-4) interrupt enable"]
5677 #[inline(always)]
5678 pub const fn ccie(&self, n: usize) -> bool {
5679 assert!(n < 4usize);
5680 let offs = 1usize + n * 1usize;
5681 let val = (self.0 >> offs) & 0x01;
5682 val != 0
5683 }
5684 #[doc = "Capture/Compare x (x=1-4) interrupt enable"]
5685 #[inline(always)]
5686 pub fn set_ccie(&mut self, n: usize, val: bool) {
5687 assert!(n < 4usize);
5688 let offs = 1usize + n * 1usize;
5689 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
5690 }
5691 #[doc = "Trigger interrupt enable"]
5692 #[inline(always)]
5693 pub const fn tie(&self) -> bool {
5694 let val = (self.0 >> 6usize) & 0x01;
5695 val != 0
5696 }
5697 #[doc = "Trigger interrupt enable"]
5698 #[inline(always)]
5699 pub fn set_tie(&mut self, val: bool) {
5700 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
5701 }
5702 #[doc = "Update DMA request enable"]
5703 #[inline(always)]
5704 pub const fn ude(&self) -> bool {
5705 let val = (self.0 >> 8usize) & 0x01;
5706 val != 0
5707 }
5708 #[doc = "Update DMA request enable"]
5709 #[inline(always)]
5710 pub fn set_ude(&mut self, val: bool) {
5711 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
5712 }
5713 #[doc = "Capture/Compare x (x=1-4) DMA request enable"]
5714 #[inline(always)]
5715 pub const fn ccde(&self, n: usize) -> bool {
5716 assert!(n < 4usize);
5717 let offs = 9usize + n * 1usize;
5718 let val = (self.0 >> offs) & 0x01;
5719 val != 0
5720 }
5721 #[doc = "Capture/Compare x (x=1-4) DMA request enable"]
5722 #[inline(always)]
5723 pub fn set_ccde(&mut self, n: usize, val: bool) {
5724 assert!(n < 4usize);
5725 let offs = 9usize + n * 1usize;
5726 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
5727 }
5728 #[doc = "Trigger DMA request enable"]
5729 #[inline(always)]
5730 pub const fn tde(&self) -> bool {
5731 let val = (self.0 >> 14usize) & 0x01;
5732 val != 0
5733 }
5734 #[doc = "Trigger DMA request enable"]
5735 #[inline(always)]
5736 pub fn set_tde(&mut self, val: bool) {
5737 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
5738 }
5739 #[doc = "Index interrupt enable"]
5740 #[inline(always)]
5741 pub const fn idxie(&self) -> bool {
5742 let val = (self.0 >> 20usize) & 0x01;
5743 val != 0
5744 }
5745 #[doc = "Index interrupt enable"]
5746 #[inline(always)]
5747 pub fn set_idxie(&mut self, val: bool) {
5748 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
5749 }
5750 #[doc = "Direction change interrupt enable"]
5751 #[inline(always)]
5752 pub const fn dirie(&self) -> bool {
5753 let val = (self.0 >> 21usize) & 0x01;
5754 val != 0
5755 }
5756 #[doc = "Direction change interrupt enable"]
5757 #[inline(always)]
5758 pub fn set_dirie(&mut self, val: bool) {
5759 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
5760 }
5761 #[doc = "Index error interrupt enable"]
5762 #[inline(always)]
5763 pub const fn ierrie(&self) -> bool {
5764 let val = (self.0 >> 22usize) & 0x01;
5765 val != 0
5766 }
5767 #[doc = "Index error interrupt enable"]
5768 #[inline(always)]
5769 pub fn set_ierrie(&mut self, val: bool) {
5770 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
5771 }
5772 #[doc = "Transition error interrupt enable"]
5773 #[inline(always)]
5774 pub const fn terrie(&self) -> bool {
5775 let val = (self.0 >> 23usize) & 0x01;
5776 val != 0
5777 }
5778 #[doc = "Transition error interrupt enable"]
5779 #[inline(always)]
5780 pub fn set_terrie(&mut self, val: bool) {
5781 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
5782 }
5783 }
5784 impl Default for DierGp16 {
5785 #[inline(always)]
5786 fn default() -> DierGp16 {
5787 DierGp16(0)
5788 }
5789 }
5790 impl core::fmt::Debug for DierGp16 {
5791 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5792 f.debug_struct("DierGp16")
5793 .field("uie", &self.uie())
5794 .field(
5795 "ccie",
5796 &[
5797 self.ccie(0usize),
5798 self.ccie(1usize),
5799 self.ccie(2usize),
5800 self.ccie(3usize),
5801 ],
5802 )
5803 .field("tie", &self.tie())
5804 .field("ude", &self.ude())
5805 .field(
5806 "ccde",
5807 &[
5808 self.ccde(0usize),
5809 self.ccde(1usize),
5810 self.ccde(2usize),
5811 self.ccde(3usize),
5812 ],
5813 )
5814 .field("tde", &self.tde())
5815 .field("idxie", &self.idxie())
5816 .field("dirie", &self.dirie())
5817 .field("ierrie", &self.ierrie())
5818 .field("terrie", &self.terrie())
5819 .finish()
5820 }
5821 }
5822 #[cfg(feature = "defmt")]
5823 impl defmt::Format for DierGp16 {
5824 fn format(&self, f: defmt::Formatter) {
5825 #[derive(defmt :: Format)]
5826 struct DierGp16 {
5827 uie: bool,
5828 ccie: [bool; 4usize],
5829 tie: bool,
5830 ude: bool,
5831 ccde: [bool; 4usize],
5832 tde: bool,
5833 idxie: bool,
5834 dirie: bool,
5835 ierrie: bool,
5836 terrie: bool,
5837 }
5838 let proxy = DierGp16 {
5839 uie: self.uie(),
5840 ccie: [
5841 self.ccie(0usize),
5842 self.ccie(1usize),
5843 self.ccie(2usize),
5844 self.ccie(3usize),
5845 ],
5846 tie: self.tie(),
5847 ude: self.ude(),
5848 ccde: [
5849 self.ccde(0usize),
5850 self.ccde(1usize),
5851 self.ccde(2usize),
5852 self.ccde(3usize),
5853 ],
5854 tde: self.tde(),
5855 idxie: self.idxie(),
5856 dirie: self.dirie(),
5857 ierrie: self.ierrie(),
5858 terrie: self.terrie(),
5859 };
5860 defmt::write!(f, "{}", proxy)
5861 }
5862 }
5863 #[doc = "deadtime register 2"]
5864 #[repr(transparent)]
5865 #[derive(Copy, Clone, Eq, PartialEq)]
5866 pub struct Dtr21chCmp(pub u32);
5867 impl Dtr21chCmp {
5868 #[doc = "Dead-time falling edge generator setup"]
5869 #[inline(always)]
5870 pub const fn dtgf(&self) -> u8 {
5871 let val = (self.0 >> 0usize) & 0xff;
5872 val as u8
5873 }
5874 #[doc = "Dead-time falling edge generator setup"]
5875 #[inline(always)]
5876 pub fn set_dtgf(&mut self, val: u8) {
5877 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
5878 }
5879 #[doc = "Deadtime asymmetric enable"]
5880 #[inline(always)]
5881 pub const fn dtae(&self) -> super::vals::Dtae {
5882 let val = (self.0 >> 16usize) & 0x01;
5883 super::vals::Dtae::from_bits(val as u8)
5884 }
5885 #[doc = "Deadtime asymmetric enable"]
5886 #[inline(always)]
5887 pub fn set_dtae(&mut self, val: super::vals::Dtae) {
5888 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.to_bits() as u32) & 0x01) << 16usize);
5889 }
5890 #[doc = "Deadtime preload enable"]
5891 #[inline(always)]
5892 pub const fn dtpe(&self) -> bool {
5893 let val = (self.0 >> 17usize) & 0x01;
5894 val != 0
5895 }
5896 #[doc = "Deadtime preload enable"]
5897 #[inline(always)]
5898 pub fn set_dtpe(&mut self, val: bool) {
5899 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
5900 }
5901 }
5902 impl Default for Dtr21chCmp {
5903 #[inline(always)]
5904 fn default() -> Dtr21chCmp {
5905 Dtr21chCmp(0)
5906 }
5907 }
5908 impl core::fmt::Debug for Dtr21chCmp {
5909 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5910 f.debug_struct("Dtr21chCmp")
5911 .field("dtgf", &self.dtgf())
5912 .field("dtae", &self.dtae())
5913 .field("dtpe", &self.dtpe())
5914 .finish()
5915 }
5916 }
5917 #[cfg(feature = "defmt")]
5918 impl defmt::Format for Dtr21chCmp {
5919 fn format(&self, f: defmt::Formatter) {
5920 #[derive(defmt :: Format)]
5921 struct Dtr21chCmp {
5922 dtgf: u8,
5923 dtae: super::vals::Dtae,
5924 dtpe: bool,
5925 }
5926 let proxy = Dtr21chCmp {
5927 dtgf: self.dtgf(),
5928 dtae: self.dtae(),
5929 dtpe: self.dtpe(),
5930 };
5931 defmt::write!(f, "{}", proxy)
5932 }
5933 }
5934 #[doc = "encoder control register"]
5935 #[repr(transparent)]
5936 #[derive(Copy, Clone, Eq, PartialEq)]
5937 pub struct EcrGp16(pub u32);
5938 impl EcrGp16 {
5939 #[doc = "Index enable"]
5940 #[inline(always)]
5941 pub const fn ie(&self) -> bool {
5942 let val = (self.0 >> 0usize) & 0x01;
5943 val != 0
5944 }
5945 #[doc = "Index enable"]
5946 #[inline(always)]
5947 pub fn set_ie(&mut self, val: bool) {
5948 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
5949 }
5950 #[doc = "Index direction"]
5951 #[inline(always)]
5952 pub const fn idir(&self) -> super::vals::Idir {
5953 let val = (self.0 >> 1usize) & 0x03;
5954 super::vals::Idir::from_bits(val as u8)
5955 }
5956 #[doc = "Index direction"]
5957 #[inline(always)]
5958 pub fn set_idir(&mut self, val: super::vals::Idir) {
5959 self.0 = (self.0 & !(0x03 << 1usize)) | (((val.to_bits() as u32) & 0x03) << 1usize);
5960 }
5961 #[doc = "Index blanking"]
5962 #[inline(always)]
5963 pub const fn iblk(&self) -> super::vals::Iblk {
5964 let val = (self.0 >> 3usize) & 0x03;
5965 super::vals::Iblk::from_bits(val as u8)
5966 }
5967 #[doc = "Index blanking"]
5968 #[inline(always)]
5969 pub fn set_iblk(&mut self, val: super::vals::Iblk) {
5970 self.0 = (self.0 & !(0x03 << 3usize)) | (((val.to_bits() as u32) & 0x03) << 3usize);
5971 }
5972 #[doc = "First index"]
5973 #[inline(always)]
5974 pub const fn fidx(&self) -> super::vals::Fidx {
5975 let val = (self.0 >> 5usize) & 0x01;
5976 super::vals::Fidx::from_bits(val as u8)
5977 }
5978 #[doc = "First index"]
5979 #[inline(always)]
5980 pub fn set_fidx(&mut self, val: super::vals::Fidx) {
5981 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.to_bits() as u32) & 0x01) << 5usize);
5982 }
5983 #[doc = "Index positioning"]
5984 #[inline(always)]
5985 pub const fn ipos(&self) -> u8 {
5986 let val = (self.0 >> 6usize) & 0x03;
5987 val as u8
5988 }
5989 #[doc = "Index positioning"]
5990 #[inline(always)]
5991 pub fn set_ipos(&mut self, val: u8) {
5992 self.0 = (self.0 & !(0x03 << 6usize)) | (((val as u32) & 0x03) << 6usize);
5993 }
5994 #[doc = "Pulse width"]
5995 #[inline(always)]
5996 pub const fn pw(&self) -> u8 {
5997 let val = (self.0 >> 16usize) & 0xff;
5998 val as u8
5999 }
6000 #[doc = "Pulse width"]
6001 #[inline(always)]
6002 pub fn set_pw(&mut self, val: u8) {
6003 self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
6004 }
6005 #[doc = "Pulse width prescaler"]
6006 #[inline(always)]
6007 pub const fn pwprsc(&self) -> u8 {
6008 let val = (self.0 >> 24usize) & 0x03;
6009 val as u8
6010 }
6011 #[doc = "Pulse width prescaler"]
6012 #[inline(always)]
6013 pub fn set_pwprsc(&mut self, val: u8) {
6014 self.0 = (self.0 & !(0x03 << 24usize)) | (((val as u32) & 0x03) << 24usize);
6015 }
6016 }
6017 impl Default for EcrGp16 {
6018 #[inline(always)]
6019 fn default() -> EcrGp16 {
6020 EcrGp16(0)
6021 }
6022 }
6023 impl core::fmt::Debug for EcrGp16 {
6024 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6025 f.debug_struct("EcrGp16")
6026 .field("ie", &self.ie())
6027 .field("idir", &self.idir())
6028 .field("iblk", &self.iblk())
6029 .field("fidx", &self.fidx())
6030 .field("ipos", &self.ipos())
6031 .field("pw", &self.pw())
6032 .field("pwprsc", &self.pwprsc())
6033 .finish()
6034 }
6035 }
6036 #[cfg(feature = "defmt")]
6037 impl defmt::Format for EcrGp16 {
6038 fn format(&self, f: defmt::Formatter) {
6039 #[derive(defmt :: Format)]
6040 struct EcrGp16 {
6041 ie: bool,
6042 idir: super::vals::Idir,
6043 iblk: super::vals::Iblk,
6044 fidx: super::vals::Fidx,
6045 ipos: u8,
6046 pw: u8,
6047 pwprsc: u8,
6048 }
6049 let proxy = EcrGp16 {
6050 ie: self.ie(),
6051 idir: self.idir(),
6052 iblk: self.iblk(),
6053 fidx: self.fidx(),
6054 ipos: self.ipos(),
6055 pw: self.pw(),
6056 pwprsc: self.pwprsc(),
6057 };
6058 defmt::write!(f, "{}", proxy)
6059 }
6060 }
6061 #[doc = "event generation register"]
6062 #[repr(transparent)]
6063 #[derive(Copy, Clone, Eq, PartialEq)]
6064 pub struct Egr1ch(pub u32);
6065 impl Egr1ch {
6066 #[doc = "Update generation"]
6067 #[inline(always)]
6068 pub const fn ug(&self) -> bool {
6069 let val = (self.0 >> 0usize) & 0x01;
6070 val != 0
6071 }
6072 #[doc = "Update generation"]
6073 #[inline(always)]
6074 pub fn set_ug(&mut self, val: bool) {
6075 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
6076 }
6077 #[doc = "Capture/compare x (x=1) generation"]
6078 #[inline(always)]
6079 pub const fn ccg(&self, n: usize) -> bool {
6080 assert!(n < 1usize);
6081 let offs = 1usize + n * 1usize;
6082 let val = (self.0 >> offs) & 0x01;
6083 val != 0
6084 }
6085 #[doc = "Capture/compare x (x=1) generation"]
6086 #[inline(always)]
6087 pub fn set_ccg(&mut self, n: usize, val: bool) {
6088 assert!(n < 1usize);
6089 let offs = 1usize + n * 1usize;
6090 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
6091 }
6092 }
6093 impl Default for Egr1ch {
6094 #[inline(always)]
6095 fn default() -> Egr1ch {
6096 Egr1ch(0)
6097 }
6098 }
6099 impl core::fmt::Debug for Egr1ch {
6100 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6101 f.debug_struct("Egr1ch")
6102 .field("ug", &self.ug())
6103 .field("ccg", &[self.ccg(0usize)])
6104 .finish()
6105 }
6106 }
6107 #[cfg(feature = "defmt")]
6108 impl defmt::Format for Egr1ch {
6109 fn format(&self, f: defmt::Formatter) {
6110 #[derive(defmt :: Format)]
6111 struct Egr1ch {
6112 ug: bool,
6113 ccg: [bool; 1usize],
6114 }
6115 let proxy = Egr1ch {
6116 ug: self.ug(),
6117 ccg: [self.ccg(0usize)],
6118 };
6119 defmt::write!(f, "{}", proxy)
6120 }
6121 }
6122 #[doc = "event generation register"]
6123 #[repr(transparent)]
6124 #[derive(Copy, Clone, Eq, PartialEq)]
6125 pub struct Egr1chCmp(pub u32);
6126 impl Egr1chCmp {
6127 #[doc = "Update generation"]
6128 #[inline(always)]
6129 pub const fn ug(&self) -> bool {
6130 let val = (self.0 >> 0usize) & 0x01;
6131 val != 0
6132 }
6133 #[doc = "Update generation"]
6134 #[inline(always)]
6135 pub fn set_ug(&mut self, val: bool) {
6136 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
6137 }
6138 #[doc = "Capture/compare x (x=1) generation"]
6139 #[inline(always)]
6140 pub const fn ccg(&self, n: usize) -> bool {
6141 assert!(n < 1usize);
6142 let offs = 1usize + n * 1usize;
6143 let val = (self.0 >> offs) & 0x01;
6144 val != 0
6145 }
6146 #[doc = "Capture/compare x (x=1) generation"]
6147 #[inline(always)]
6148 pub fn set_ccg(&mut self, n: usize, val: bool) {
6149 assert!(n < 1usize);
6150 let offs = 1usize + n * 1usize;
6151 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
6152 }
6153 #[doc = "Capture/Compare control update generation"]
6154 #[inline(always)]
6155 pub const fn comg(&self) -> bool {
6156 let val = (self.0 >> 5usize) & 0x01;
6157 val != 0
6158 }
6159 #[doc = "Capture/Compare control update generation"]
6160 #[inline(always)]
6161 pub fn set_comg(&mut self, val: bool) {
6162 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
6163 }
6164 #[doc = "Break x (x=1) generation"]
6165 #[inline(always)]
6166 pub const fn bg(&self, n: usize) -> bool {
6167 assert!(n < 1usize);
6168 let offs = 7usize + n * 1usize;
6169 let val = (self.0 >> offs) & 0x01;
6170 val != 0
6171 }
6172 #[doc = "Break x (x=1) generation"]
6173 #[inline(always)]
6174 pub fn set_bg(&mut self, n: usize, val: bool) {
6175 assert!(n < 1usize);
6176 let offs = 7usize + n * 1usize;
6177 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
6178 }
6179 }
6180 impl Default for Egr1chCmp {
6181 #[inline(always)]
6182 fn default() -> Egr1chCmp {
6183 Egr1chCmp(0)
6184 }
6185 }
6186 impl core::fmt::Debug for Egr1chCmp {
6187 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6188 f.debug_struct("Egr1chCmp")
6189 .field("ug", &self.ug())
6190 .field("ccg", &[self.ccg(0usize)])
6191 .field("comg", &self.comg())
6192 .field("bg", &[self.bg(0usize)])
6193 .finish()
6194 }
6195 }
6196 #[cfg(feature = "defmt")]
6197 impl defmt::Format for Egr1chCmp {
6198 fn format(&self, f: defmt::Formatter) {
6199 #[derive(defmt :: Format)]
6200 struct Egr1chCmp {
6201 ug: bool,
6202 ccg: [bool; 1usize],
6203 comg: bool,
6204 bg: [bool; 1usize],
6205 }
6206 let proxy = Egr1chCmp {
6207 ug: self.ug(),
6208 ccg: [self.ccg(0usize)],
6209 comg: self.comg(),
6210 bg: [self.bg(0usize)],
6211 };
6212 defmt::write!(f, "{}", proxy)
6213 }
6214 }
6215 #[doc = "event generation register"]
6216 #[repr(transparent)]
6217 #[derive(Copy, Clone, Eq, PartialEq)]
6218 pub struct Egr2ch(pub u32);
6219 impl Egr2ch {
6220 #[doc = "Update generation"]
6221 #[inline(always)]
6222 pub const fn ug(&self) -> bool {
6223 let val = (self.0 >> 0usize) & 0x01;
6224 val != 0
6225 }
6226 #[doc = "Update generation"]
6227 #[inline(always)]
6228 pub fn set_ug(&mut self, val: bool) {
6229 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
6230 }
6231 #[doc = "Capture/compare x (x=1-2) generation"]
6232 #[inline(always)]
6233 pub const fn ccg(&self, n: usize) -> bool {
6234 assert!(n < 2usize);
6235 let offs = 1usize + n * 1usize;
6236 let val = (self.0 >> offs) & 0x01;
6237 val != 0
6238 }
6239 #[doc = "Capture/compare x (x=1-2) generation"]
6240 #[inline(always)]
6241 pub fn set_ccg(&mut self, n: usize, val: bool) {
6242 assert!(n < 2usize);
6243 let offs = 1usize + n * 1usize;
6244 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
6245 }
6246 #[doc = "Trigger generation"]
6247 #[inline(always)]
6248 pub const fn tg(&self) -> bool {
6249 let val = (self.0 >> 6usize) & 0x01;
6250 val != 0
6251 }
6252 #[doc = "Trigger generation"]
6253 #[inline(always)]
6254 pub fn set_tg(&mut self, val: bool) {
6255 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
6256 }
6257 }
6258 impl Default for Egr2ch {
6259 #[inline(always)]
6260 fn default() -> Egr2ch {
6261 Egr2ch(0)
6262 }
6263 }
6264 impl core::fmt::Debug for Egr2ch {
6265 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6266 f.debug_struct("Egr2ch")
6267 .field("ug", &self.ug())
6268 .field("ccg", &[self.ccg(0usize), self.ccg(1usize)])
6269 .field("tg", &self.tg())
6270 .finish()
6271 }
6272 }
6273 #[cfg(feature = "defmt")]
6274 impl defmt::Format for Egr2ch {
6275 fn format(&self, f: defmt::Formatter) {
6276 #[derive(defmt :: Format)]
6277 struct Egr2ch {
6278 ug: bool,
6279 ccg: [bool; 2usize],
6280 tg: bool,
6281 }
6282 let proxy = Egr2ch {
6283 ug: self.ug(),
6284 ccg: [self.ccg(0usize), self.ccg(1usize)],
6285 tg: self.tg(),
6286 };
6287 defmt::write!(f, "{}", proxy)
6288 }
6289 }
6290 #[doc = "event generation register"]
6291 #[repr(transparent)]
6292 #[derive(Copy, Clone, Eq, PartialEq)]
6293 pub struct Egr2chCmp(pub u32);
6294 impl Egr2chCmp {
6295 #[doc = "Update generation"]
6296 #[inline(always)]
6297 pub const fn ug(&self) -> bool {
6298 let val = (self.0 >> 0usize) & 0x01;
6299 val != 0
6300 }
6301 #[doc = "Update generation"]
6302 #[inline(always)]
6303 pub fn set_ug(&mut self, val: bool) {
6304 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
6305 }
6306 #[doc = "Capture/compare x (x=1,2) generation"]
6307 #[inline(always)]
6308 pub const fn ccg(&self, n: usize) -> bool {
6309 assert!(n < 2usize);
6310 let offs = 1usize + n * 1usize;
6311 let val = (self.0 >> offs) & 0x01;
6312 val != 0
6313 }
6314 #[doc = "Capture/compare x (x=1,2) generation"]
6315 #[inline(always)]
6316 pub fn set_ccg(&mut self, n: usize, val: bool) {
6317 assert!(n < 2usize);
6318 let offs = 1usize + n * 1usize;
6319 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
6320 }
6321 #[doc = "Capture/Compare control update generation"]
6322 #[inline(always)]
6323 pub const fn comg(&self) -> bool {
6324 let val = (self.0 >> 5usize) & 0x01;
6325 val != 0
6326 }
6327 #[doc = "Capture/Compare control update generation"]
6328 #[inline(always)]
6329 pub fn set_comg(&mut self, val: bool) {
6330 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
6331 }
6332 #[doc = "Trigger generation"]
6333 #[inline(always)]
6334 pub const fn tg(&self) -> bool {
6335 let val = (self.0 >> 6usize) & 0x01;
6336 val != 0
6337 }
6338 #[doc = "Trigger generation"]
6339 #[inline(always)]
6340 pub fn set_tg(&mut self, val: bool) {
6341 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
6342 }
6343 #[doc = "Break x (x=1) generation"]
6344 #[inline(always)]
6345 pub const fn bg(&self, n: usize) -> bool {
6346 assert!(n < 1usize);
6347 let offs = 7usize + n * 1usize;
6348 let val = (self.0 >> offs) & 0x01;
6349 val != 0
6350 }
6351 #[doc = "Break x (x=1) generation"]
6352 #[inline(always)]
6353 pub fn set_bg(&mut self, n: usize, val: bool) {
6354 assert!(n < 1usize);
6355 let offs = 7usize + n * 1usize;
6356 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
6357 }
6358 }
6359 impl Default for Egr2chCmp {
6360 #[inline(always)]
6361 fn default() -> Egr2chCmp {
6362 Egr2chCmp(0)
6363 }
6364 }
6365 impl core::fmt::Debug for Egr2chCmp {
6366 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6367 f.debug_struct("Egr2chCmp")
6368 .field("ug", &self.ug())
6369 .field("ccg", &[self.ccg(0usize), self.ccg(1usize)])
6370 .field("comg", &self.comg())
6371 .field("tg", &self.tg())
6372 .field("bg", &[self.bg(0usize)])
6373 .finish()
6374 }
6375 }
6376 #[cfg(feature = "defmt")]
6377 impl defmt::Format for Egr2chCmp {
6378 fn format(&self, f: defmt::Formatter) {
6379 #[derive(defmt :: Format)]
6380 struct Egr2chCmp {
6381 ug: bool,
6382 ccg: [bool; 2usize],
6383 comg: bool,
6384 tg: bool,
6385 bg: [bool; 1usize],
6386 }
6387 let proxy = Egr2chCmp {
6388 ug: self.ug(),
6389 ccg: [self.ccg(0usize), self.ccg(1usize)],
6390 comg: self.comg(),
6391 tg: self.tg(),
6392 bg: [self.bg(0usize)],
6393 };
6394 defmt::write!(f, "{}", proxy)
6395 }
6396 }
6397 #[doc = "event generation register"]
6398 #[repr(transparent)]
6399 #[derive(Copy, Clone, Eq, PartialEq)]
6400 pub struct EgrAdv(pub u32);
6401 impl EgrAdv {
6402 #[doc = "Update generation"]
6403 #[inline(always)]
6404 pub const fn ug(&self) -> bool {
6405 let val = (self.0 >> 0usize) & 0x01;
6406 val != 0
6407 }
6408 #[doc = "Update generation"]
6409 #[inline(always)]
6410 pub fn set_ug(&mut self, val: bool) {
6411 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
6412 }
6413 #[doc = "Capture/compare x (x=1-4) generation"]
6414 #[inline(always)]
6415 pub const fn ccg(&self, n: usize) -> bool {
6416 assert!(n < 4usize);
6417 let offs = 1usize + n * 1usize;
6418 let val = (self.0 >> offs) & 0x01;
6419 val != 0
6420 }
6421 #[doc = "Capture/compare x (x=1-4) generation"]
6422 #[inline(always)]
6423 pub fn set_ccg(&mut self, n: usize, val: bool) {
6424 assert!(n < 4usize);
6425 let offs = 1usize + n * 1usize;
6426 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
6427 }
6428 #[doc = "Capture/Compare control update generation"]
6429 #[inline(always)]
6430 pub const fn comg(&self) -> bool {
6431 let val = (self.0 >> 5usize) & 0x01;
6432 val != 0
6433 }
6434 #[doc = "Capture/Compare control update generation"]
6435 #[inline(always)]
6436 pub fn set_comg(&mut self, val: bool) {
6437 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
6438 }
6439 #[doc = "Trigger generation"]
6440 #[inline(always)]
6441 pub const fn tg(&self) -> bool {
6442 let val = (self.0 >> 6usize) & 0x01;
6443 val != 0
6444 }
6445 #[doc = "Trigger generation"]
6446 #[inline(always)]
6447 pub fn set_tg(&mut self, val: bool) {
6448 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
6449 }
6450 #[doc = "Break x (x=1-2) generation"]
6451 #[inline(always)]
6452 pub const fn bg(&self, n: usize) -> bool {
6453 assert!(n < 2usize);
6454 let offs = 7usize + n * 1usize;
6455 let val = (self.0 >> offs) & 0x01;
6456 val != 0
6457 }
6458 #[doc = "Break x (x=1-2) generation"]
6459 #[inline(always)]
6460 pub fn set_bg(&mut self, n: usize, val: bool) {
6461 assert!(n < 2usize);
6462 let offs = 7usize + n * 1usize;
6463 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
6464 }
6465 }
6466 impl Default for EgrAdv {
6467 #[inline(always)]
6468 fn default() -> EgrAdv {
6469 EgrAdv(0)
6470 }
6471 }
6472 impl core::fmt::Debug for EgrAdv {
6473 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6474 f.debug_struct("EgrAdv")
6475 .field("ug", &self.ug())
6476 .field(
6477 "ccg",
6478 &[self.ccg(0usize), self.ccg(1usize), self.ccg(2usize), self.ccg(3usize)],
6479 )
6480 .field("comg", &self.comg())
6481 .field("tg", &self.tg())
6482 .field("bg", &[self.bg(0usize), self.bg(1usize)])
6483 .finish()
6484 }
6485 }
6486 #[cfg(feature = "defmt")]
6487 impl defmt::Format for EgrAdv {
6488 fn format(&self, f: defmt::Formatter) {
6489 #[derive(defmt :: Format)]
6490 struct EgrAdv {
6491 ug: bool,
6492 ccg: [bool; 4usize],
6493 comg: bool,
6494 tg: bool,
6495 bg: [bool; 2usize],
6496 }
6497 let proxy = EgrAdv {
6498 ug: self.ug(),
6499 ccg: [self.ccg(0usize), self.ccg(1usize), self.ccg(2usize), self.ccg(3usize)],
6500 comg: self.comg(),
6501 tg: self.tg(),
6502 bg: [self.bg(0usize), self.bg(1usize)],
6503 };
6504 defmt::write!(f, "{}", proxy)
6505 }
6506 }
6507 #[doc = "event generation register"]
6508 #[repr(transparent)]
6509 #[derive(Copy, Clone, Eq, PartialEq)]
6510 pub struct EgrCore(pub u32);
6511 impl EgrCore {
6512 #[doc = "Update generation"]
6513 #[inline(always)]
6514 pub const fn ug(&self) -> bool {
6515 let val = (self.0 >> 0usize) & 0x01;
6516 val != 0
6517 }
6518 #[doc = "Update generation"]
6519 #[inline(always)]
6520 pub fn set_ug(&mut self, val: bool) {
6521 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
6522 }
6523 }
6524 impl Default for EgrCore {
6525 #[inline(always)]
6526 fn default() -> EgrCore {
6527 EgrCore(0)
6528 }
6529 }
6530 impl core::fmt::Debug for EgrCore {
6531 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6532 f.debug_struct("EgrCore").field("ug", &self.ug()).finish()
6533 }
6534 }
6535 #[cfg(feature = "defmt")]
6536 impl defmt::Format for EgrCore {
6537 fn format(&self, f: defmt::Formatter) {
6538 #[derive(defmt :: Format)]
6539 struct EgrCore {
6540 ug: bool,
6541 }
6542 let proxy = EgrCore { ug: self.ug() };
6543 defmt::write!(f, "{}", proxy)
6544 }
6545 }
6546 #[doc = "event generation register"]
6547 #[repr(transparent)]
6548 #[derive(Copy, Clone, Eq, PartialEq)]
6549 pub struct EgrGp16(pub u32);
6550 impl EgrGp16 {
6551 #[doc = "Update generation"]
6552 #[inline(always)]
6553 pub const fn ug(&self) -> bool {
6554 let val = (self.0 >> 0usize) & 0x01;
6555 val != 0
6556 }
6557 #[doc = "Update generation"]
6558 #[inline(always)]
6559 pub fn set_ug(&mut self, val: bool) {
6560 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
6561 }
6562 #[doc = "Capture/compare x (x=1-4) generation"]
6563 #[inline(always)]
6564 pub const fn ccg(&self, n: usize) -> bool {
6565 assert!(n < 4usize);
6566 let offs = 1usize + n * 1usize;
6567 let val = (self.0 >> offs) & 0x01;
6568 val != 0
6569 }
6570 #[doc = "Capture/compare x (x=1-4) generation"]
6571 #[inline(always)]
6572 pub fn set_ccg(&mut self, n: usize, val: bool) {
6573 assert!(n < 4usize);
6574 let offs = 1usize + n * 1usize;
6575 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
6576 }
6577 #[doc = "Trigger generation"]
6578 #[inline(always)]
6579 pub const fn tg(&self) -> bool {
6580 let val = (self.0 >> 6usize) & 0x01;
6581 val != 0
6582 }
6583 #[doc = "Trigger generation"]
6584 #[inline(always)]
6585 pub fn set_tg(&mut self, val: bool) {
6586 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
6587 }
6588 }
6589 impl Default for EgrGp16 {
6590 #[inline(always)]
6591 fn default() -> EgrGp16 {
6592 EgrGp16(0)
6593 }
6594 }
6595 impl core::fmt::Debug for EgrGp16 {
6596 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6597 f.debug_struct("EgrGp16")
6598 .field("ug", &self.ug())
6599 .field(
6600 "ccg",
6601 &[self.ccg(0usize), self.ccg(1usize), self.ccg(2usize), self.ccg(3usize)],
6602 )
6603 .field("tg", &self.tg())
6604 .finish()
6605 }
6606 }
6607 #[cfg(feature = "defmt")]
6608 impl defmt::Format for EgrGp16 {
6609 fn format(&self, f: defmt::Formatter) {
6610 #[derive(defmt :: Format)]
6611 struct EgrGp16 {
6612 ug: bool,
6613 ccg: [bool; 4usize],
6614 tg: bool,
6615 }
6616 let proxy = EgrGp16 {
6617 ug: self.ug(),
6618 ccg: [self.ccg(0usize), self.ccg(1usize), self.ccg(2usize), self.ccg(3usize)],
6619 tg: self.tg(),
6620 };
6621 defmt::write!(f, "{}", proxy)
6622 }
6623 }
6624 #[doc = "repetition counter register"]
6625 #[repr(transparent)]
6626 #[derive(Copy, Clone, Eq, PartialEq)]
6627 pub struct Rcr1chCmp(pub u32);
6628 impl Rcr1chCmp {
6629 #[doc = "Repetition counter value"]
6630 #[inline(always)]
6631 pub const fn rep(&self) -> u8 {
6632 let val = (self.0 >> 0usize) & 0xff;
6633 val as u8
6634 }
6635 #[doc = "Repetition counter value"]
6636 #[inline(always)]
6637 pub fn set_rep(&mut self, val: u8) {
6638 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
6639 }
6640 }
6641 impl Default for Rcr1chCmp {
6642 #[inline(always)]
6643 fn default() -> Rcr1chCmp {
6644 Rcr1chCmp(0)
6645 }
6646 }
6647 impl core::fmt::Debug for Rcr1chCmp {
6648 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6649 f.debug_struct("Rcr1chCmp").field("rep", &self.rep()).finish()
6650 }
6651 }
6652 #[cfg(feature = "defmt")]
6653 impl defmt::Format for Rcr1chCmp {
6654 fn format(&self, f: defmt::Formatter) {
6655 #[derive(defmt :: Format)]
6656 struct Rcr1chCmp {
6657 rep: u8,
6658 }
6659 let proxy = Rcr1chCmp { rep: self.rep() };
6660 defmt::write!(f, "{}", proxy)
6661 }
6662 }
6663 #[doc = "repetition counter register"]
6664 #[repr(transparent)]
6665 #[derive(Copy, Clone, Eq, PartialEq)]
6666 pub struct RcrAdv(pub u32);
6667 impl RcrAdv {
6668 #[doc = "Repetition counter value"]
6669 #[inline(always)]
6670 pub const fn rep(&self) -> u16 {
6671 let val = (self.0 >> 0usize) & 0xffff;
6672 val as u16
6673 }
6674 #[doc = "Repetition counter value"]
6675 #[inline(always)]
6676 pub fn set_rep(&mut self, val: u16) {
6677 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
6678 }
6679 }
6680 impl Default for RcrAdv {
6681 #[inline(always)]
6682 fn default() -> RcrAdv {
6683 RcrAdv(0)
6684 }
6685 }
6686 impl core::fmt::Debug for RcrAdv {
6687 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6688 f.debug_struct("RcrAdv").field("rep", &self.rep()).finish()
6689 }
6690 }
6691 #[cfg(feature = "defmt")]
6692 impl defmt::Format for RcrAdv {
6693 fn format(&self, f: defmt::Formatter) {
6694 #[derive(defmt :: Format)]
6695 struct RcrAdv {
6696 rep: u16,
6697 }
6698 let proxy = RcrAdv { rep: self.rep() };
6699 defmt::write!(f, "{}", proxy)
6700 }
6701 }
6702 #[doc = "slave mode control register"]
6703 #[repr(transparent)]
6704 #[derive(Copy, Clone, Eq, PartialEq)]
6705 pub struct Smcr2ch(pub u32);
6706 impl Smcr2ch {
6707 #[doc = "Slave mode selection"]
6708 #[inline(always)]
6709 pub const fn sms(&self) -> super::vals::Sms {
6710 let mut val = 0;
6711 val += (((self.0 >> 0usize) & 0x07) << 0usize);
6712 val += (((self.0 >> 16usize) & 0x01) << 3usize);
6713 super::vals::Sms::from_bits(val as u8)
6714 }
6715 #[doc = "Slave mode selection"]
6716 #[inline(always)]
6717 pub fn set_sms(&mut self, val: super::vals::Sms) {
6718 self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32 >> 0usize) & 0x07) << 0usize);
6719 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.to_bits() as u32 >> 3usize) & 0x01) << 16usize);
6720 }
6721 #[doc = "Trigger selection"]
6722 #[inline(always)]
6723 pub const fn ts(&self) -> super::vals::Ts {
6724 let mut val = 0;
6725 val += (((self.0 >> 4usize) & 0x07) << 0usize);
6726 val += (((self.0 >> 20usize) & 0x03) << 3usize);
6727 super::vals::Ts::from_bits(val as u8)
6728 }
6729 #[doc = "Trigger selection"]
6730 #[inline(always)]
6731 pub fn set_ts(&mut self, val: super::vals::Ts) {
6732 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32 >> 0usize) & 0x07) << 4usize);
6733 self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32 >> 3usize) & 0x03) << 20usize);
6734 }
6735 #[doc = "Master/Slave mode"]
6736 #[inline(always)]
6737 pub const fn msm(&self) -> super::vals::Msm {
6738 let val = (self.0 >> 7usize) & 0x01;
6739 super::vals::Msm::from_bits(val as u8)
6740 }
6741 #[doc = "Master/Slave mode"]
6742 #[inline(always)]
6743 pub fn set_msm(&mut self, val: super::vals::Msm) {
6744 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize);
6745 }
6746 }
6747 impl Default for Smcr2ch {
6748 #[inline(always)]
6749 fn default() -> Smcr2ch {
6750 Smcr2ch(0)
6751 }
6752 }
6753 impl core::fmt::Debug for Smcr2ch {
6754 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6755 f.debug_struct("Smcr2ch")
6756 .field("sms", &self.sms())
6757 .field("ts", &self.ts())
6758 .field("msm", &self.msm())
6759 .finish()
6760 }
6761 }
6762 #[cfg(feature = "defmt")]
6763 impl defmt::Format for Smcr2ch {
6764 fn format(&self, f: defmt::Formatter) {
6765 #[derive(defmt :: Format)]
6766 struct Smcr2ch {
6767 sms: super::vals::Sms,
6768 ts: super::vals::Ts,
6769 msm: super::vals::Msm,
6770 }
6771 let proxy = Smcr2ch {
6772 sms: self.sms(),
6773 ts: self.ts(),
6774 msm: self.msm(),
6775 };
6776 defmt::write!(f, "{}", proxy)
6777 }
6778 }
6779 #[doc = "slave mode control register"]
6780 #[repr(transparent)]
6781 #[derive(Copy, Clone, Eq, PartialEq)]
6782 pub struct Smcr2chCmp(pub u32);
6783 impl Smcr2chCmp {
6784 #[doc = "Slave mode selection"]
6785 #[inline(always)]
6786 pub const fn sms(&self) -> super::vals::Sms {
6787 let mut val = 0;
6788 val += (((self.0 >> 0usize) & 0x07) << 0usize);
6789 val += (((self.0 >> 16usize) & 0x01) << 3usize);
6790 super::vals::Sms::from_bits(val as u8)
6791 }
6792 #[doc = "Slave mode selection"]
6793 #[inline(always)]
6794 pub fn set_sms(&mut self, val: super::vals::Sms) {
6795 self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32 >> 0usize) & 0x07) << 0usize);
6796 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.to_bits() as u32 >> 3usize) & 0x01) << 16usize);
6797 }
6798 #[doc = "Trigger selection"]
6799 #[inline(always)]
6800 pub const fn ts(&self) -> super::vals::Ts {
6801 let mut val = 0;
6802 val += (((self.0 >> 4usize) & 0x07) << 0usize);
6803 val += (((self.0 >> 20usize) & 0x03) << 3usize);
6804 super::vals::Ts::from_bits(val as u8)
6805 }
6806 #[doc = "Trigger selection"]
6807 #[inline(always)]
6808 pub fn set_ts(&mut self, val: super::vals::Ts) {
6809 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32 >> 0usize) & 0x07) << 4usize);
6810 self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32 >> 3usize) & 0x03) << 20usize);
6811 }
6812 #[doc = "Master/Slave mode"]
6813 #[inline(always)]
6814 pub const fn msm(&self) -> super::vals::Msm {
6815 let val = (self.0 >> 7usize) & 0x01;
6816 super::vals::Msm::from_bits(val as u8)
6817 }
6818 #[doc = "Master/Slave mode"]
6819 #[inline(always)]
6820 pub fn set_msm(&mut self, val: super::vals::Msm) {
6821 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize);
6822 }
6823 #[doc = "SMS preload enable"]
6824 #[inline(always)]
6825 pub const fn smspe(&self) -> bool {
6826 let val = (self.0 >> 24usize) & 0x01;
6827 val != 0
6828 }
6829 #[doc = "SMS preload enable"]
6830 #[inline(always)]
6831 pub fn set_smspe(&mut self, val: bool) {
6832 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
6833 }
6834 }
6835 impl Default for Smcr2chCmp {
6836 #[inline(always)]
6837 fn default() -> Smcr2chCmp {
6838 Smcr2chCmp(0)
6839 }
6840 }
6841 impl core::fmt::Debug for Smcr2chCmp {
6842 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
6843 f.debug_struct("Smcr2chCmp")
6844 .field("sms", &self.sms())
6845 .field("ts", &self.ts())
6846 .field("msm", &self.msm())
6847 .field("smspe", &self.smspe())
6848 .finish()
6849 }
6850 }
6851 #[cfg(feature = "defmt")]
6852 impl defmt::Format for Smcr2chCmp {
6853 fn format(&self, f: defmt::Formatter) {
6854 #[derive(defmt :: Format)]
6855 struct Smcr2chCmp {
6856 sms: super::vals::Sms,
6857 ts: super::vals::Ts,
6858 msm: super::vals::Msm,
6859 smspe: bool,
6860 }
6861 let proxy = Smcr2chCmp {
6862 sms: self.sms(),
6863 ts: self.ts(),
6864 msm: self.msm(),
6865 smspe: self.smspe(),
6866 };
6867 defmt::write!(f, "{}", proxy)
6868 }
6869 }
6870 #[doc = "slave mode control register"]
6871 #[repr(transparent)]
6872 #[derive(Copy, Clone, Eq, PartialEq)]
6873 pub struct SmcrAdv(pub u32);
6874 impl SmcrAdv {
6875 #[doc = "Slave mode selection"]
6876 #[inline(always)]
6877 pub const fn sms(&self) -> super::vals::Sms {
6878 let mut val = 0;
6879 val += (((self.0 >> 0usize) & 0x07) << 0usize);
6880 val += (((self.0 >> 16usize) & 0x01) << 3usize);
6881 super::vals::Sms::from_bits(val as u8)
6882 }
6883 #[doc = "Slave mode selection"]
6884 #[inline(always)]
6885 pub fn set_sms(&mut self, val: super::vals::Sms) {
6886 self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32 >> 0usize) & 0x07) << 0usize);
6887 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.to_bits() as u32 >> 3usize) & 0x01) << 16usize);
6888 }
6889 #[doc = "OCREF clear selection"]
6890 #[inline(always)]
6891 pub const fn occs(&self) -> super::vals::Occs {
6892 let val = (self.0 >> 3usize) & 0x01;
6893 super::vals::Occs::from_bits(val as u8)
6894 }
6895 #[doc = "OCREF clear selection"]
6896 #[inline(always)]
6897 pub fn set_occs(&mut self, val: super::vals::Occs) {
6898 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize);
6899 }
6900 #[doc = "Trigger selection"]
6901 #[inline(always)]
6902 pub const fn ts(&self) -> super::vals::Ts {
6903 let mut val = 0;
6904 val += (((self.0 >> 4usize) & 0x07) << 0usize);
6905 val += (((self.0 >> 20usize) & 0x03) << 3usize);
6906 super::vals::Ts::from_bits(val as u8)
6907 }
6908 #[doc = "Trigger selection"]
6909 #[inline(always)]
6910 pub fn set_ts(&mut self, val: super::vals::Ts) {
6911 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32 >> 0usize) & 0x07) << 4usize);
6912 self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32 >> 3usize) & 0x03) << 20usize);
6913 }
6914 #[doc = "Master/Slave mode"]
6915 #[inline(always)]
6916 pub const fn msm(&self) -> super::vals::Msm {
6917 let val = (self.0 >> 7usize) & 0x01;
6918 super::vals::Msm::from_bits(val as u8)
6919 }
6920 #[doc = "Master/Slave mode"]
6921 #[inline(always)]
6922 pub fn set_msm(&mut self, val: super::vals::Msm) {
6923 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize);
6924 }
6925 #[doc = "External trigger filter"]
6926 #[inline(always)]
6927 pub const fn etf(&self) -> super::vals::FilterValue {
6928 let val = (self.0 >> 8usize) & 0x0f;
6929 super::vals::FilterValue::from_bits(val as u8)
6930 }
6931 #[doc = "External trigger filter"]
6932 #[inline(always)]
6933 pub fn set_etf(&mut self, val: super::vals::FilterValue) {
6934 self.0 = (self.0 & !(0x0f << 8usize)) | (((val.to_bits() as u32) & 0x0f) << 8usize);
6935 }
6936 #[doc = "External trigger prescaler"]
6937 #[inline(always)]
6938 pub const fn etps(&self) -> super::vals::Etps {
6939 let val = (self.0 >> 12usize) & 0x03;
6940 super::vals::Etps::from_bits(val as u8)
6941 }
6942 #[doc = "External trigger prescaler"]
6943 #[inline(always)]
6944 pub fn set_etps(&mut self, val: super::vals::Etps) {
6945 self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize);
6946 }
6947 #[doc = "External clock mode 2 enable"]
6948 #[inline(always)]
6949 pub const fn ece(&self) -> bool {
6950 let val = (self.0 >> 14usize) & 0x01;
6951 val != 0
6952 }
6953 #[doc = "External clock mode 2 enable"]
6954 #[inline(always)]
6955 pub fn set_ece(&mut self, val: bool) {
6956 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
6957 }
6958 #[doc = "External trigger polarity"]
6959 #[inline(always)]
6960 pub const fn etp(&self) -> super::vals::Etp {
6961 let val = (self.0 >> 15usize) & 0x01;
6962 super::vals::Etp::from_bits(val as u8)
6963 }
6964 #[doc = "External trigger polarity"]
6965 #[inline(always)]
6966 pub fn set_etp(&mut self, val: super::vals::Etp) {
6967 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.to_bits() as u32) & 0x01) << 15usize);
6968 }
6969 #[doc = "SMS preload enable"]
6970 #[inline(always)]
6971 pub const fn smspe(&self) -> bool {
6972 let val = (self.0 >> 24usize) & 0x01;
6973 val != 0
6974 }
6975 #[doc = "SMS preload enable"]
6976 #[inline(always)]
6977 pub fn set_smspe(&mut self, val: bool) {
6978 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
6979 }
6980 #[doc = "SMS preload source"]
6981 #[inline(always)]
6982 pub const fn smsps(&self) -> super::vals::Smsps {
6983 let val = (self.0 >> 25usize) & 0x01;
6984 super::vals::Smsps::from_bits(val as u8)
6985 }
6986 #[doc = "SMS preload source"]
6987 #[inline(always)]
6988 pub fn set_smsps(&mut self, val: super::vals::Smsps) {
6989 self.0 = (self.0 & !(0x01 << 25usize)) | (((val.to_bits() as u32) & 0x01) << 25usize);
6990 }
6991 }
6992 impl Default for SmcrAdv {
6993 #[inline(always)]
6994 fn default() -> SmcrAdv {
6995 SmcrAdv(0)
6996 }
6997 }
6998 impl core::fmt::Debug for SmcrAdv {
6999 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7000 f.debug_struct("SmcrAdv")
7001 .field("sms", &self.sms())
7002 .field("occs", &self.occs())
7003 .field("ts", &self.ts())
7004 .field("msm", &self.msm())
7005 .field("etf", &self.etf())
7006 .field("etps", &self.etps())
7007 .field("ece", &self.ece())
7008 .field("etp", &self.etp())
7009 .field("smspe", &self.smspe())
7010 .field("smsps", &self.smsps())
7011 .finish()
7012 }
7013 }
7014 #[cfg(feature = "defmt")]
7015 impl defmt::Format for SmcrAdv {
7016 fn format(&self, f: defmt::Formatter) {
7017 #[derive(defmt :: Format)]
7018 struct SmcrAdv {
7019 sms: super::vals::Sms,
7020 occs: super::vals::Occs,
7021 ts: super::vals::Ts,
7022 msm: super::vals::Msm,
7023 etf: super::vals::FilterValue,
7024 etps: super::vals::Etps,
7025 ece: bool,
7026 etp: super::vals::Etp,
7027 smspe: bool,
7028 smsps: super::vals::Smsps,
7029 }
7030 let proxy = SmcrAdv {
7031 sms: self.sms(),
7032 occs: self.occs(),
7033 ts: self.ts(),
7034 msm: self.msm(),
7035 etf: self.etf(),
7036 etps: self.etps(),
7037 ece: self.ece(),
7038 etp: self.etp(),
7039 smspe: self.smspe(),
7040 smsps: self.smsps(),
7041 };
7042 defmt::write!(f, "{}", proxy)
7043 }
7044 }
7045 #[doc = "slave mode control register"]
7046 #[repr(transparent)]
7047 #[derive(Copy, Clone, Eq, PartialEq)]
7048 pub struct SmcrGp16(pub u32);
7049 impl SmcrGp16 {
7050 #[doc = "Slave mode selection"]
7051 #[inline(always)]
7052 pub const fn sms(&self) -> super::vals::Sms {
7053 let mut val = 0;
7054 val += (((self.0 >> 0usize) & 0x07) << 0usize);
7055 val += (((self.0 >> 16usize) & 0x01) << 3usize);
7056 super::vals::Sms::from_bits(val as u8)
7057 }
7058 #[doc = "Slave mode selection"]
7059 #[inline(always)]
7060 pub fn set_sms(&mut self, val: super::vals::Sms) {
7061 self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32 >> 0usize) & 0x07) << 0usize);
7062 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.to_bits() as u32 >> 3usize) & 0x01) << 16usize);
7063 }
7064 #[doc = "Trigger selection"]
7065 #[inline(always)]
7066 pub const fn ts(&self) -> super::vals::Ts {
7067 let mut val = 0;
7068 val += (((self.0 >> 4usize) & 0x07) << 0usize);
7069 val += (((self.0 >> 20usize) & 0x03) << 3usize);
7070 super::vals::Ts::from_bits(val as u8)
7071 }
7072 #[doc = "Trigger selection"]
7073 #[inline(always)]
7074 pub fn set_ts(&mut self, val: super::vals::Ts) {
7075 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32 >> 0usize) & 0x07) << 4usize);
7076 self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32 >> 3usize) & 0x03) << 20usize);
7077 }
7078 #[doc = "Master/Slave mode"]
7079 #[inline(always)]
7080 pub const fn msm(&self) -> super::vals::Msm {
7081 let val = (self.0 >> 7usize) & 0x01;
7082 super::vals::Msm::from_bits(val as u8)
7083 }
7084 #[doc = "Master/Slave mode"]
7085 #[inline(always)]
7086 pub fn set_msm(&mut self, val: super::vals::Msm) {
7087 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize);
7088 }
7089 #[doc = "External trigger filter"]
7090 #[inline(always)]
7091 pub const fn etf(&self) -> super::vals::FilterValue {
7092 let val = (self.0 >> 8usize) & 0x0f;
7093 super::vals::FilterValue::from_bits(val as u8)
7094 }
7095 #[doc = "External trigger filter"]
7096 #[inline(always)]
7097 pub fn set_etf(&mut self, val: super::vals::FilterValue) {
7098 self.0 = (self.0 & !(0x0f << 8usize)) | (((val.to_bits() as u32) & 0x0f) << 8usize);
7099 }
7100 #[doc = "External trigger prescaler"]
7101 #[inline(always)]
7102 pub const fn etps(&self) -> super::vals::Etps {
7103 let val = (self.0 >> 12usize) & 0x03;
7104 super::vals::Etps::from_bits(val as u8)
7105 }
7106 #[doc = "External trigger prescaler"]
7107 #[inline(always)]
7108 pub fn set_etps(&mut self, val: super::vals::Etps) {
7109 self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize);
7110 }
7111 #[doc = "External clock mode 2 enable"]
7112 #[inline(always)]
7113 pub const fn ece(&self) -> bool {
7114 let val = (self.0 >> 14usize) & 0x01;
7115 val != 0
7116 }
7117 #[doc = "External clock mode 2 enable"]
7118 #[inline(always)]
7119 pub fn set_ece(&mut self, val: bool) {
7120 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
7121 }
7122 #[doc = "External trigger polarity"]
7123 #[inline(always)]
7124 pub const fn etp(&self) -> super::vals::Etp {
7125 let val = (self.0 >> 15usize) & 0x01;
7126 super::vals::Etp::from_bits(val as u8)
7127 }
7128 #[doc = "External trigger polarity"]
7129 #[inline(always)]
7130 pub fn set_etp(&mut self, val: super::vals::Etp) {
7131 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.to_bits() as u32) & 0x01) << 15usize);
7132 }
7133 #[doc = "SMS preload enable"]
7134 #[inline(always)]
7135 pub const fn smspe(&self) -> bool {
7136 let val = (self.0 >> 24usize) & 0x01;
7137 val != 0
7138 }
7139 #[doc = "SMS preload enable"]
7140 #[inline(always)]
7141 pub fn set_smspe(&mut self, val: bool) {
7142 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
7143 }
7144 #[doc = "SMS preload source"]
7145 #[inline(always)]
7146 pub const fn smsps(&self) -> super::vals::Smsps {
7147 let val = (self.0 >> 25usize) & 0x01;
7148 super::vals::Smsps::from_bits(val as u8)
7149 }
7150 #[doc = "SMS preload source"]
7151 #[inline(always)]
7152 pub fn set_smsps(&mut self, val: super::vals::Smsps) {
7153 self.0 = (self.0 & !(0x01 << 25usize)) | (((val.to_bits() as u32) & 0x01) << 25usize);
7154 }
7155 }
7156 impl Default for SmcrGp16 {
7157 #[inline(always)]
7158 fn default() -> SmcrGp16 {
7159 SmcrGp16(0)
7160 }
7161 }
7162 impl core::fmt::Debug for SmcrGp16 {
7163 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7164 f.debug_struct("SmcrGp16")
7165 .field("sms", &self.sms())
7166 .field("ts", &self.ts())
7167 .field("msm", &self.msm())
7168 .field("etf", &self.etf())
7169 .field("etps", &self.etps())
7170 .field("ece", &self.ece())
7171 .field("etp", &self.etp())
7172 .field("smspe", &self.smspe())
7173 .field("smsps", &self.smsps())
7174 .finish()
7175 }
7176 }
7177 #[cfg(feature = "defmt")]
7178 impl defmt::Format for SmcrGp16 {
7179 fn format(&self, f: defmt::Formatter) {
7180 #[derive(defmt :: Format)]
7181 struct SmcrGp16 {
7182 sms: super::vals::Sms,
7183 ts: super::vals::Ts,
7184 msm: super::vals::Msm,
7185 etf: super::vals::FilterValue,
7186 etps: super::vals::Etps,
7187 ece: bool,
7188 etp: super::vals::Etp,
7189 smspe: bool,
7190 smsps: super::vals::Smsps,
7191 }
7192 let proxy = SmcrGp16 {
7193 sms: self.sms(),
7194 ts: self.ts(),
7195 msm: self.msm(),
7196 etf: self.etf(),
7197 etps: self.etps(),
7198 ece: self.ece(),
7199 etp: self.etp(),
7200 smspe: self.smspe(),
7201 smsps: self.smsps(),
7202 };
7203 defmt::write!(f, "{}", proxy)
7204 }
7205 }
7206 #[doc = "status register"]
7207 #[repr(transparent)]
7208 #[derive(Copy, Clone, Eq, PartialEq)]
7209 pub struct Sr1ch(pub u32);
7210 impl Sr1ch {
7211 #[doc = "Update interrupt flag"]
7212 #[inline(always)]
7213 pub const fn uif(&self) -> bool {
7214 let val = (self.0 >> 0usize) & 0x01;
7215 val != 0
7216 }
7217 #[doc = "Update interrupt flag"]
7218 #[inline(always)]
7219 pub fn set_uif(&mut self, val: bool) {
7220 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
7221 }
7222 #[doc = "Capture/compare x (x=1) interrupt flag"]
7223 #[inline(always)]
7224 pub const fn ccif(&self, n: usize) -> bool {
7225 assert!(n < 1usize);
7226 let offs = 1usize + n * 1usize;
7227 let val = (self.0 >> offs) & 0x01;
7228 val != 0
7229 }
7230 #[doc = "Capture/compare x (x=1) interrupt flag"]
7231 #[inline(always)]
7232 pub fn set_ccif(&mut self, n: usize, val: bool) {
7233 assert!(n < 1usize);
7234 let offs = 1usize + n * 1usize;
7235 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
7236 }
7237 #[doc = "Capture/Compare x (x=1) overcapture flag"]
7238 #[inline(always)]
7239 pub const fn ccof(&self, n: usize) -> bool {
7240 assert!(n < 1usize);
7241 let offs = 9usize + n * 1usize;
7242 let val = (self.0 >> offs) & 0x01;
7243 val != 0
7244 }
7245 #[doc = "Capture/Compare x (x=1) overcapture flag"]
7246 #[inline(always)]
7247 pub fn set_ccof(&mut self, n: usize, val: bool) {
7248 assert!(n < 1usize);
7249 let offs = 9usize + n * 1usize;
7250 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
7251 }
7252 }
7253 impl Default for Sr1ch {
7254 #[inline(always)]
7255 fn default() -> Sr1ch {
7256 Sr1ch(0)
7257 }
7258 }
7259 impl core::fmt::Debug for Sr1ch {
7260 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7261 f.debug_struct("Sr1ch")
7262 .field("uif", &self.uif())
7263 .field("ccif", &[self.ccif(0usize)])
7264 .field("ccof", &[self.ccof(0usize)])
7265 .finish()
7266 }
7267 }
7268 #[cfg(feature = "defmt")]
7269 impl defmt::Format for Sr1ch {
7270 fn format(&self, f: defmt::Formatter) {
7271 #[derive(defmt :: Format)]
7272 struct Sr1ch {
7273 uif: bool,
7274 ccif: [bool; 1usize],
7275 ccof: [bool; 1usize],
7276 }
7277 let proxy = Sr1ch {
7278 uif: self.uif(),
7279 ccif: [self.ccif(0usize)],
7280 ccof: [self.ccof(0usize)],
7281 };
7282 defmt::write!(f, "{}", proxy)
7283 }
7284 }
7285 #[doc = "status register"]
7286 #[repr(transparent)]
7287 #[derive(Copy, Clone, Eq, PartialEq)]
7288 pub struct Sr1chCmp(pub u32);
7289 impl Sr1chCmp {
7290 #[doc = "Update interrupt flag"]
7291 #[inline(always)]
7292 pub const fn uif(&self) -> bool {
7293 let val = (self.0 >> 0usize) & 0x01;
7294 val != 0
7295 }
7296 #[doc = "Update interrupt flag"]
7297 #[inline(always)]
7298 pub fn set_uif(&mut self, val: bool) {
7299 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
7300 }
7301 #[doc = "Capture/compare x (x=1) interrupt flag"]
7302 #[inline(always)]
7303 pub const fn ccif(&self, n: usize) -> bool {
7304 assert!(n < 1usize);
7305 let offs = 1usize + n * 1usize;
7306 let val = (self.0 >> offs) & 0x01;
7307 val != 0
7308 }
7309 #[doc = "Capture/compare x (x=1) interrupt flag"]
7310 #[inline(always)]
7311 pub fn set_ccif(&mut self, n: usize, val: bool) {
7312 assert!(n < 1usize);
7313 let offs = 1usize + n * 1usize;
7314 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
7315 }
7316 #[doc = "COM interrupt flag"]
7317 #[inline(always)]
7318 pub const fn comif(&self) -> bool {
7319 let val = (self.0 >> 5usize) & 0x01;
7320 val != 0
7321 }
7322 #[doc = "COM interrupt flag"]
7323 #[inline(always)]
7324 pub fn set_comif(&mut self, val: bool) {
7325 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
7326 }
7327 #[doc = "Break x (x=1) interrupt flag"]
7328 #[inline(always)]
7329 pub const fn bif(&self, n: usize) -> bool {
7330 assert!(n < 1usize);
7331 let offs = 7usize + n * 1usize;
7332 let val = (self.0 >> offs) & 0x01;
7333 val != 0
7334 }
7335 #[doc = "Break x (x=1) interrupt flag"]
7336 #[inline(always)]
7337 pub fn set_bif(&mut self, n: usize, val: bool) {
7338 assert!(n < 1usize);
7339 let offs = 7usize + n * 1usize;
7340 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
7341 }
7342 #[doc = "Capture/Compare x (x=1) overcapture flag"]
7343 #[inline(always)]
7344 pub const fn ccof(&self, n: usize) -> bool {
7345 assert!(n < 1usize);
7346 let offs = 9usize + n * 1usize;
7347 let val = (self.0 >> offs) & 0x01;
7348 val != 0
7349 }
7350 #[doc = "Capture/Compare x (x=1) overcapture flag"]
7351 #[inline(always)]
7352 pub fn set_ccof(&mut self, n: usize, val: bool) {
7353 assert!(n < 1usize);
7354 let offs = 9usize + n * 1usize;
7355 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
7356 }
7357 }
7358 impl Default for Sr1chCmp {
7359 #[inline(always)]
7360 fn default() -> Sr1chCmp {
7361 Sr1chCmp(0)
7362 }
7363 }
7364 impl core::fmt::Debug for Sr1chCmp {
7365 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7366 f.debug_struct("Sr1chCmp")
7367 .field("uif", &self.uif())
7368 .field("ccif", &[self.ccif(0usize)])
7369 .field("comif", &self.comif())
7370 .field("bif", &[self.bif(0usize)])
7371 .field("ccof", &[self.ccof(0usize)])
7372 .finish()
7373 }
7374 }
7375 #[cfg(feature = "defmt")]
7376 impl defmt::Format for Sr1chCmp {
7377 fn format(&self, f: defmt::Formatter) {
7378 #[derive(defmt :: Format)]
7379 struct Sr1chCmp {
7380 uif: bool,
7381 ccif: [bool; 1usize],
7382 comif: bool,
7383 bif: [bool; 1usize],
7384 ccof: [bool; 1usize],
7385 }
7386 let proxy = Sr1chCmp {
7387 uif: self.uif(),
7388 ccif: [self.ccif(0usize)],
7389 comif: self.comif(),
7390 bif: [self.bif(0usize)],
7391 ccof: [self.ccof(0usize)],
7392 };
7393 defmt::write!(f, "{}", proxy)
7394 }
7395 }
7396 #[doc = "status register"]
7397 #[repr(transparent)]
7398 #[derive(Copy, Clone, Eq, PartialEq)]
7399 pub struct Sr2ch(pub u32);
7400 impl Sr2ch {
7401 #[doc = "Update interrupt flag"]
7402 #[inline(always)]
7403 pub const fn uif(&self) -> bool {
7404 let val = (self.0 >> 0usize) & 0x01;
7405 val != 0
7406 }
7407 #[doc = "Update interrupt flag"]
7408 #[inline(always)]
7409 pub fn set_uif(&mut self, val: bool) {
7410 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
7411 }
7412 #[doc = "Capture/compare x (x=1-2) interrupt flag"]
7413 #[inline(always)]
7414 pub const fn ccif(&self, n: usize) -> bool {
7415 assert!(n < 2usize);
7416 let offs = 1usize + n * 1usize;
7417 let val = (self.0 >> offs) & 0x01;
7418 val != 0
7419 }
7420 #[doc = "Capture/compare x (x=1-2) interrupt flag"]
7421 #[inline(always)]
7422 pub fn set_ccif(&mut self, n: usize, val: bool) {
7423 assert!(n < 2usize);
7424 let offs = 1usize + n * 1usize;
7425 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
7426 }
7427 #[doc = "Trigger interrupt flag"]
7428 #[inline(always)]
7429 pub const fn tif(&self) -> bool {
7430 let val = (self.0 >> 6usize) & 0x01;
7431 val != 0
7432 }
7433 #[doc = "Trigger interrupt flag"]
7434 #[inline(always)]
7435 pub fn set_tif(&mut self, val: bool) {
7436 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
7437 }
7438 #[doc = "Capture/Compare x (x=1-2) overcapture flag"]
7439 #[inline(always)]
7440 pub const fn ccof(&self, n: usize) -> bool {
7441 assert!(n < 2usize);
7442 let offs = 9usize + n * 1usize;
7443 let val = (self.0 >> offs) & 0x01;
7444 val != 0
7445 }
7446 #[doc = "Capture/Compare x (x=1-2) overcapture flag"]
7447 #[inline(always)]
7448 pub fn set_ccof(&mut self, n: usize, val: bool) {
7449 assert!(n < 2usize);
7450 let offs = 9usize + n * 1usize;
7451 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
7452 }
7453 }
7454 impl Default for Sr2ch {
7455 #[inline(always)]
7456 fn default() -> Sr2ch {
7457 Sr2ch(0)
7458 }
7459 }
7460 impl core::fmt::Debug for Sr2ch {
7461 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7462 f.debug_struct("Sr2ch")
7463 .field("uif", &self.uif())
7464 .field("ccif", &[self.ccif(0usize), self.ccif(1usize)])
7465 .field("tif", &self.tif())
7466 .field("ccof", &[self.ccof(0usize), self.ccof(1usize)])
7467 .finish()
7468 }
7469 }
7470 #[cfg(feature = "defmt")]
7471 impl defmt::Format for Sr2ch {
7472 fn format(&self, f: defmt::Formatter) {
7473 #[derive(defmt :: Format)]
7474 struct Sr2ch {
7475 uif: bool,
7476 ccif: [bool; 2usize],
7477 tif: bool,
7478 ccof: [bool; 2usize],
7479 }
7480 let proxy = Sr2ch {
7481 uif: self.uif(),
7482 ccif: [self.ccif(0usize), self.ccif(1usize)],
7483 tif: self.tif(),
7484 ccof: [self.ccof(0usize), self.ccof(1usize)],
7485 };
7486 defmt::write!(f, "{}", proxy)
7487 }
7488 }
7489 #[doc = "status register"]
7490 #[repr(transparent)]
7491 #[derive(Copy, Clone, Eq, PartialEq)]
7492 pub struct Sr2chCmp(pub u32);
7493 impl Sr2chCmp {
7494 #[doc = "Update interrupt flag"]
7495 #[inline(always)]
7496 pub const fn uif(&self) -> bool {
7497 let val = (self.0 >> 0usize) & 0x01;
7498 val != 0
7499 }
7500 #[doc = "Update interrupt flag"]
7501 #[inline(always)]
7502 pub fn set_uif(&mut self, val: bool) {
7503 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
7504 }
7505 #[doc = "Capture/compare x (x=1,2) interrupt flag"]
7506 #[inline(always)]
7507 pub const fn ccif(&self, n: usize) -> bool {
7508 assert!(n < 2usize);
7509 let offs = 1usize + n * 1usize;
7510 let val = (self.0 >> offs) & 0x01;
7511 val != 0
7512 }
7513 #[doc = "Capture/compare x (x=1,2) interrupt flag"]
7514 #[inline(always)]
7515 pub fn set_ccif(&mut self, n: usize, val: bool) {
7516 assert!(n < 2usize);
7517 let offs = 1usize + n * 1usize;
7518 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
7519 }
7520 #[doc = "COM interrupt flag"]
7521 #[inline(always)]
7522 pub const fn comif(&self) -> bool {
7523 let val = (self.0 >> 5usize) & 0x01;
7524 val != 0
7525 }
7526 #[doc = "COM interrupt flag"]
7527 #[inline(always)]
7528 pub fn set_comif(&mut self, val: bool) {
7529 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
7530 }
7531 #[doc = "Trigger interrupt flag"]
7532 #[inline(always)]
7533 pub const fn tif(&self) -> bool {
7534 let val = (self.0 >> 6usize) & 0x01;
7535 val != 0
7536 }
7537 #[doc = "Trigger interrupt flag"]
7538 #[inline(always)]
7539 pub fn set_tif(&mut self, val: bool) {
7540 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
7541 }
7542 #[doc = "Break x (x=1) interrupt flag"]
7543 #[inline(always)]
7544 pub const fn bif(&self, n: usize) -> bool {
7545 assert!(n < 1usize);
7546 let offs = 7usize + n * 1usize;
7547 let val = (self.0 >> offs) & 0x01;
7548 val != 0
7549 }
7550 #[doc = "Break x (x=1) interrupt flag"]
7551 #[inline(always)]
7552 pub fn set_bif(&mut self, n: usize, val: bool) {
7553 assert!(n < 1usize);
7554 let offs = 7usize + n * 1usize;
7555 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
7556 }
7557 #[doc = "Capture/Compare x (x=1,2) overcapture flag"]
7558 #[inline(always)]
7559 pub const fn ccof(&self, n: usize) -> bool {
7560 assert!(n < 2usize);
7561 let offs = 9usize + n * 1usize;
7562 let val = (self.0 >> offs) & 0x01;
7563 val != 0
7564 }
7565 #[doc = "Capture/Compare x (x=1,2) overcapture flag"]
7566 #[inline(always)]
7567 pub fn set_ccof(&mut self, n: usize, val: bool) {
7568 assert!(n < 2usize);
7569 let offs = 9usize + n * 1usize;
7570 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
7571 }
7572 }
7573 impl Default for Sr2chCmp {
7574 #[inline(always)]
7575 fn default() -> Sr2chCmp {
7576 Sr2chCmp(0)
7577 }
7578 }
7579 impl core::fmt::Debug for Sr2chCmp {
7580 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7581 f.debug_struct("Sr2chCmp")
7582 .field("uif", &self.uif())
7583 .field("ccif", &[self.ccif(0usize), self.ccif(1usize)])
7584 .field("comif", &self.comif())
7585 .field("tif", &self.tif())
7586 .field("bif", &[self.bif(0usize)])
7587 .field("ccof", &[self.ccof(0usize), self.ccof(1usize)])
7588 .finish()
7589 }
7590 }
7591 #[cfg(feature = "defmt")]
7592 impl defmt::Format for Sr2chCmp {
7593 fn format(&self, f: defmt::Formatter) {
7594 #[derive(defmt :: Format)]
7595 struct Sr2chCmp {
7596 uif: bool,
7597 ccif: [bool; 2usize],
7598 comif: bool,
7599 tif: bool,
7600 bif: [bool; 1usize],
7601 ccof: [bool; 2usize],
7602 }
7603 let proxy = Sr2chCmp {
7604 uif: self.uif(),
7605 ccif: [self.ccif(0usize), self.ccif(1usize)],
7606 comif: self.comif(),
7607 tif: self.tif(),
7608 bif: [self.bif(0usize)],
7609 ccof: [self.ccof(0usize), self.ccof(1usize)],
7610 };
7611 defmt::write!(f, "{}", proxy)
7612 }
7613 }
7614 #[doc = "status register"]
7615 #[repr(transparent)]
7616 #[derive(Copy, Clone, Eq, PartialEq)]
7617 pub struct SrAdv(pub u32);
7618 impl SrAdv {
7619 #[doc = "Update interrupt flag"]
7620 #[inline(always)]
7621 pub const fn uif(&self) -> bool {
7622 let val = (self.0 >> 0usize) & 0x01;
7623 val != 0
7624 }
7625 #[doc = "Update interrupt flag"]
7626 #[inline(always)]
7627 pub fn set_uif(&mut self, val: bool) {
7628 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
7629 }
7630 #[doc = "Capture/compare x (x=1-4) interrupt flag"]
7631 #[inline(always)]
7632 pub const fn ccif(&self, n: usize) -> bool {
7633 assert!(n < 4usize);
7634 let offs = 1usize + n * 1usize;
7635 let val = (self.0 >> offs) & 0x01;
7636 val != 0
7637 }
7638 #[doc = "Capture/compare x (x=1-4) interrupt flag"]
7639 #[inline(always)]
7640 pub fn set_ccif(&mut self, n: usize, val: bool) {
7641 assert!(n < 4usize);
7642 let offs = 1usize + n * 1usize;
7643 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
7644 }
7645 #[doc = "COM interrupt flag"]
7646 #[inline(always)]
7647 pub const fn comif(&self) -> bool {
7648 let val = (self.0 >> 5usize) & 0x01;
7649 val != 0
7650 }
7651 #[doc = "COM interrupt flag"]
7652 #[inline(always)]
7653 pub fn set_comif(&mut self, val: bool) {
7654 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
7655 }
7656 #[doc = "Trigger interrupt flag"]
7657 #[inline(always)]
7658 pub const fn tif(&self) -> bool {
7659 let val = (self.0 >> 6usize) & 0x01;
7660 val != 0
7661 }
7662 #[doc = "Trigger interrupt flag"]
7663 #[inline(always)]
7664 pub fn set_tif(&mut self, val: bool) {
7665 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
7666 }
7667 #[doc = "Break x (x=1,2) interrupt flag"]
7668 #[inline(always)]
7669 pub const fn bif(&self, n: usize) -> bool {
7670 assert!(n < 2usize);
7671 let offs = 7usize + n * 1usize;
7672 let val = (self.0 >> offs) & 0x01;
7673 val != 0
7674 }
7675 #[doc = "Break x (x=1,2) interrupt flag"]
7676 #[inline(always)]
7677 pub fn set_bif(&mut self, n: usize, val: bool) {
7678 assert!(n < 2usize);
7679 let offs = 7usize + n * 1usize;
7680 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
7681 }
7682 #[doc = "Capture/Compare x (x=1-4) overcapture flag"]
7683 #[inline(always)]
7684 pub const fn ccof(&self, n: usize) -> bool {
7685 assert!(n < 4usize);
7686 let offs = 9usize + n * 1usize;
7687 let val = (self.0 >> offs) & 0x01;
7688 val != 0
7689 }
7690 #[doc = "Capture/Compare x (x=1-4) overcapture flag"]
7691 #[inline(always)]
7692 pub fn set_ccof(&mut self, n: usize, val: bool) {
7693 assert!(n < 4usize);
7694 let offs = 9usize + n * 1usize;
7695 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
7696 }
7697 #[doc = "System break interrupt flag"]
7698 #[inline(always)]
7699 pub const fn sbif(&self) -> bool {
7700 let val = (self.0 >> 13usize) & 0x01;
7701 val != 0
7702 }
7703 #[doc = "System break interrupt flag"]
7704 #[inline(always)]
7705 pub fn set_sbif(&mut self, val: bool) {
7706 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
7707 }
7708 #[doc = "Capture/compare 5 interrupt flag"]
7709 #[inline(always)]
7710 pub const fn ccif5(&self) -> bool {
7711 let val = (self.0 >> 16usize) & 0x01;
7712 val != 0
7713 }
7714 #[doc = "Capture/compare 5 interrupt flag"]
7715 #[inline(always)]
7716 pub fn set_ccif5(&mut self, val: bool) {
7717 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
7718 }
7719 #[doc = "Capture/compare 6 interrupt flag"]
7720 #[inline(always)]
7721 pub const fn ccif6(&self) -> bool {
7722 let val = (self.0 >> 17usize) & 0x01;
7723 val != 0
7724 }
7725 #[doc = "Capture/compare 6 interrupt flag"]
7726 #[inline(always)]
7727 pub fn set_ccif6(&mut self, val: bool) {
7728 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
7729 }
7730 #[doc = "Index interrupt flag"]
7731 #[inline(always)]
7732 pub const fn idxif(&self) -> bool {
7733 let val = (self.0 >> 20usize) & 0x01;
7734 val != 0
7735 }
7736 #[doc = "Index interrupt flag"]
7737 #[inline(always)]
7738 pub fn set_idxif(&mut self, val: bool) {
7739 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
7740 }
7741 #[doc = "Direction change interrupt flag"]
7742 #[inline(always)]
7743 pub const fn dirif(&self) -> bool {
7744 let val = (self.0 >> 21usize) & 0x01;
7745 val != 0
7746 }
7747 #[doc = "Direction change interrupt flag"]
7748 #[inline(always)]
7749 pub fn set_dirif(&mut self, val: bool) {
7750 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
7751 }
7752 #[doc = "Index error interrupt flag"]
7753 #[inline(always)]
7754 pub const fn ierrif(&self) -> bool {
7755 let val = (self.0 >> 22usize) & 0x01;
7756 val != 0
7757 }
7758 #[doc = "Index error interrupt flag"]
7759 #[inline(always)]
7760 pub fn set_ierrif(&mut self, val: bool) {
7761 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
7762 }
7763 #[doc = "Transition error interrupt flag"]
7764 #[inline(always)]
7765 pub const fn terrif(&self) -> bool {
7766 let val = (self.0 >> 23usize) & 0x01;
7767 val != 0
7768 }
7769 #[doc = "Transition error interrupt flag"]
7770 #[inline(always)]
7771 pub fn set_terrif(&mut self, val: bool) {
7772 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
7773 }
7774 }
7775 impl Default for SrAdv {
7776 #[inline(always)]
7777 fn default() -> SrAdv {
7778 SrAdv(0)
7779 }
7780 }
7781 impl core::fmt::Debug for SrAdv {
7782 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7783 f.debug_struct("SrAdv")
7784 .field("uif", &self.uif())
7785 .field(
7786 "ccif",
7787 &[
7788 self.ccif(0usize),
7789 self.ccif(1usize),
7790 self.ccif(2usize),
7791 self.ccif(3usize),
7792 ],
7793 )
7794 .field("comif", &self.comif())
7795 .field("tif", &self.tif())
7796 .field("bif", &[self.bif(0usize), self.bif(1usize)])
7797 .field(
7798 "ccof",
7799 &[
7800 self.ccof(0usize),
7801 self.ccof(1usize),
7802 self.ccof(2usize),
7803 self.ccof(3usize),
7804 ],
7805 )
7806 .field("sbif", &self.sbif())
7807 .field("ccif5", &self.ccif5())
7808 .field("ccif6", &self.ccif6())
7809 .field("idxif", &self.idxif())
7810 .field("dirif", &self.dirif())
7811 .field("ierrif", &self.ierrif())
7812 .field("terrif", &self.terrif())
7813 .finish()
7814 }
7815 }
7816 #[cfg(feature = "defmt")]
7817 impl defmt::Format for SrAdv {
7818 fn format(&self, f: defmt::Formatter) {
7819 #[derive(defmt :: Format)]
7820 struct SrAdv {
7821 uif: bool,
7822 ccif: [bool; 4usize],
7823 comif: bool,
7824 tif: bool,
7825 bif: [bool; 2usize],
7826 ccof: [bool; 4usize],
7827 sbif: bool,
7828 ccif5: bool,
7829 ccif6: bool,
7830 idxif: bool,
7831 dirif: bool,
7832 ierrif: bool,
7833 terrif: bool,
7834 }
7835 let proxy = SrAdv {
7836 uif: self.uif(),
7837 ccif: [
7838 self.ccif(0usize),
7839 self.ccif(1usize),
7840 self.ccif(2usize),
7841 self.ccif(3usize),
7842 ],
7843 comif: self.comif(),
7844 tif: self.tif(),
7845 bif: [self.bif(0usize), self.bif(1usize)],
7846 ccof: [
7847 self.ccof(0usize),
7848 self.ccof(1usize),
7849 self.ccof(2usize),
7850 self.ccof(3usize),
7851 ],
7852 sbif: self.sbif(),
7853 ccif5: self.ccif5(),
7854 ccif6: self.ccif6(),
7855 idxif: self.idxif(),
7856 dirif: self.dirif(),
7857 ierrif: self.ierrif(),
7858 terrif: self.terrif(),
7859 };
7860 defmt::write!(f, "{}", proxy)
7861 }
7862 }
7863 #[doc = "status register"]
7864 #[repr(transparent)]
7865 #[derive(Copy, Clone, Eq, PartialEq)]
7866 pub struct SrCore(pub u32);
7867 impl SrCore {
7868 #[doc = "Update interrupt flag"]
7869 #[inline(always)]
7870 pub const fn uif(&self) -> bool {
7871 let val = (self.0 >> 0usize) & 0x01;
7872 val != 0
7873 }
7874 #[doc = "Update interrupt flag"]
7875 #[inline(always)]
7876 pub fn set_uif(&mut self, val: bool) {
7877 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
7878 }
7879 }
7880 impl Default for SrCore {
7881 #[inline(always)]
7882 fn default() -> SrCore {
7883 SrCore(0)
7884 }
7885 }
7886 impl core::fmt::Debug for SrCore {
7887 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7888 f.debug_struct("SrCore").field("uif", &self.uif()).finish()
7889 }
7890 }
7891 #[cfg(feature = "defmt")]
7892 impl defmt::Format for SrCore {
7893 fn format(&self, f: defmt::Formatter) {
7894 #[derive(defmt :: Format)]
7895 struct SrCore {
7896 uif: bool,
7897 }
7898 let proxy = SrCore { uif: self.uif() };
7899 defmt::write!(f, "{}", proxy)
7900 }
7901 }
7902 #[doc = "status register"]
7903 #[repr(transparent)]
7904 #[derive(Copy, Clone, Eq, PartialEq)]
7905 pub struct SrGp16(pub u32);
7906 impl SrGp16 {
7907 #[doc = "Update interrupt flag"]
7908 #[inline(always)]
7909 pub const fn uif(&self) -> bool {
7910 let val = (self.0 >> 0usize) & 0x01;
7911 val != 0
7912 }
7913 #[doc = "Update interrupt flag"]
7914 #[inline(always)]
7915 pub fn set_uif(&mut self, val: bool) {
7916 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
7917 }
7918 #[doc = "Capture/compare x (x=1-4) interrupt flag"]
7919 #[inline(always)]
7920 pub const fn ccif(&self, n: usize) -> bool {
7921 assert!(n < 4usize);
7922 let offs = 1usize + n * 1usize;
7923 let val = (self.0 >> offs) & 0x01;
7924 val != 0
7925 }
7926 #[doc = "Capture/compare x (x=1-4) interrupt flag"]
7927 #[inline(always)]
7928 pub fn set_ccif(&mut self, n: usize, val: bool) {
7929 assert!(n < 4usize);
7930 let offs = 1usize + n * 1usize;
7931 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
7932 }
7933 #[doc = "Trigger interrupt flag"]
7934 #[inline(always)]
7935 pub const fn tif(&self) -> bool {
7936 let val = (self.0 >> 6usize) & 0x01;
7937 val != 0
7938 }
7939 #[doc = "Trigger interrupt flag"]
7940 #[inline(always)]
7941 pub fn set_tif(&mut self, val: bool) {
7942 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
7943 }
7944 #[doc = "Capture/Compare x (x=1-4) overcapture flag"]
7945 #[inline(always)]
7946 pub const fn ccof(&self, n: usize) -> bool {
7947 assert!(n < 4usize);
7948 let offs = 9usize + n * 1usize;
7949 let val = (self.0 >> offs) & 0x01;
7950 val != 0
7951 }
7952 #[doc = "Capture/Compare x (x=1-4) overcapture flag"]
7953 #[inline(always)]
7954 pub fn set_ccof(&mut self, n: usize, val: bool) {
7955 assert!(n < 4usize);
7956 let offs = 9usize + n * 1usize;
7957 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
7958 }
7959 #[doc = "Index interrupt flag"]
7960 #[inline(always)]
7961 pub const fn idxif(&self) -> bool {
7962 let val = (self.0 >> 20usize) & 0x01;
7963 val != 0
7964 }
7965 #[doc = "Index interrupt flag"]
7966 #[inline(always)]
7967 pub fn set_idxif(&mut self, val: bool) {
7968 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
7969 }
7970 #[doc = "Direction change interrupt flag"]
7971 #[inline(always)]
7972 pub const fn dirif(&self) -> bool {
7973 let val = (self.0 >> 21usize) & 0x01;
7974 val != 0
7975 }
7976 #[doc = "Direction change interrupt flag"]
7977 #[inline(always)]
7978 pub fn set_dirif(&mut self, val: bool) {
7979 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
7980 }
7981 #[doc = "Index error interrupt flag"]
7982 #[inline(always)]
7983 pub const fn ierrif(&self) -> bool {
7984 let val = (self.0 >> 22usize) & 0x01;
7985 val != 0
7986 }
7987 #[doc = "Index error interrupt flag"]
7988 #[inline(always)]
7989 pub fn set_ierrif(&mut self, val: bool) {
7990 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
7991 }
7992 #[doc = "Transition error interrupt flag"]
7993 #[inline(always)]
7994 pub const fn terrif(&self) -> bool {
7995 let val = (self.0 >> 23usize) & 0x01;
7996 val != 0
7997 }
7998 #[doc = "Transition error interrupt flag"]
7999 #[inline(always)]
8000 pub fn set_terrif(&mut self, val: bool) {
8001 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
8002 }
8003 }
8004 impl Default for SrGp16 {
8005 #[inline(always)]
8006 fn default() -> SrGp16 {
8007 SrGp16(0)
8008 }
8009 }
8010 impl core::fmt::Debug for SrGp16 {
8011 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
8012 f.debug_struct("SrGp16")
8013 .field("uif", &self.uif())
8014 .field(
8015 "ccif",
8016 &[
8017 self.ccif(0usize),
8018 self.ccif(1usize),
8019 self.ccif(2usize),
8020 self.ccif(3usize),
8021 ],
8022 )
8023 .field("tif", &self.tif())
8024 .field(
8025 "ccof",
8026 &[
8027 self.ccof(0usize),
8028 self.ccof(1usize),
8029 self.ccof(2usize),
8030 self.ccof(3usize),
8031 ],
8032 )
8033 .field("idxif", &self.idxif())
8034 .field("dirif", &self.dirif())
8035 .field("ierrif", &self.ierrif())
8036 .field("terrif", &self.terrif())
8037 .finish()
8038 }
8039 }
8040 #[cfg(feature = "defmt")]
8041 impl defmt::Format for SrGp16 {
8042 fn format(&self, f: defmt::Formatter) {
8043 #[derive(defmt :: Format)]
8044 struct SrGp16 {
8045 uif: bool,
8046 ccif: [bool; 4usize],
8047 tif: bool,
8048 ccof: [bool; 4usize],
8049 idxif: bool,
8050 dirif: bool,
8051 ierrif: bool,
8052 terrif: bool,
8053 }
8054 let proxy = SrGp16 {
8055 uif: self.uif(),
8056 ccif: [
8057 self.ccif(0usize),
8058 self.ccif(1usize),
8059 self.ccif(2usize),
8060 self.ccif(3usize),
8061 ],
8062 tif: self.tif(),
8063 ccof: [
8064 self.ccof(0usize),
8065 self.ccof(1usize),
8066 self.ccof(2usize),
8067 self.ccof(3usize),
8068 ],
8069 idxif: self.idxif(),
8070 dirif: self.dirif(),
8071 ierrif: self.ierrif(),
8072 terrif: self.terrif(),
8073 };
8074 defmt::write!(f, "{}", proxy)
8075 }
8076 }
8077 #[doc = "input selection register"]
8078 #[repr(transparent)]
8079 #[derive(Copy, Clone, Eq, PartialEq)]
8080 pub struct Tisel1ch(pub u32);
8081 impl Tisel1ch {
8082 #[doc = "Selects TIM_TIx (x=1) input"]
8083 #[inline(always)]
8084 pub const fn tisel(&self, n: usize) -> u8 {
8085 assert!(n < 1usize);
8086 let offs = 0usize + n * 8usize;
8087 let val = (self.0 >> offs) & 0x0f;
8088 val as u8
8089 }
8090 #[doc = "Selects TIM_TIx (x=1) input"]
8091 #[inline(always)]
8092 pub fn set_tisel(&mut self, n: usize, val: u8) {
8093 assert!(n < 1usize);
8094 let offs = 0usize + n * 8usize;
8095 self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs);
8096 }
8097 }
8098 impl Default for Tisel1ch {
8099 #[inline(always)]
8100 fn default() -> Tisel1ch {
8101 Tisel1ch(0)
8102 }
8103 }
8104 impl core::fmt::Debug for Tisel1ch {
8105 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
8106 f.debug_struct("Tisel1ch")
8107 .field("tisel", &[self.tisel(0usize)])
8108 .finish()
8109 }
8110 }
8111 #[cfg(feature = "defmt")]
8112 impl defmt::Format for Tisel1ch {
8113 fn format(&self, f: defmt::Formatter) {
8114 #[derive(defmt :: Format)]
8115 struct Tisel1ch {
8116 tisel: [u8; 1usize],
8117 }
8118 let proxy = Tisel1ch {
8119 tisel: [self.tisel(0usize)],
8120 };
8121 defmt::write!(f, "{}", proxy)
8122 }
8123 }
8124 #[doc = "input selection register"]
8125 #[repr(transparent)]
8126 #[derive(Copy, Clone, Eq, PartialEq)]
8127 pub struct Tisel2ch(pub u32);
8128 impl Tisel2ch {
8129 #[doc = "Selects TIM_TIx (x=1-2) input"]
8130 #[inline(always)]
8131 pub const fn tisel(&self, n: usize) -> u8 {
8132 assert!(n < 2usize);
8133 let offs = 0usize + n * 8usize;
8134 let val = (self.0 >> offs) & 0x0f;
8135 val as u8
8136 }
8137 #[doc = "Selects TIM_TIx (x=1-2) input"]
8138 #[inline(always)]
8139 pub fn set_tisel(&mut self, n: usize, val: u8) {
8140 assert!(n < 2usize);
8141 let offs = 0usize + n * 8usize;
8142 self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs);
8143 }
8144 }
8145 impl Default for Tisel2ch {
8146 #[inline(always)]
8147 fn default() -> Tisel2ch {
8148 Tisel2ch(0)
8149 }
8150 }
8151 impl core::fmt::Debug for Tisel2ch {
8152 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
8153 f.debug_struct("Tisel2ch")
8154 .field("tisel", &[self.tisel(0usize), self.tisel(1usize)])
8155 .finish()
8156 }
8157 }
8158 #[cfg(feature = "defmt")]
8159 impl defmt::Format for Tisel2ch {
8160 fn format(&self, f: defmt::Formatter) {
8161 #[derive(defmt :: Format)]
8162 struct Tisel2ch {
8163 tisel: [u8; 2usize],
8164 }
8165 let proxy = Tisel2ch {
8166 tisel: [self.tisel(0usize), self.tisel(1usize)],
8167 };
8168 defmt::write!(f, "{}", proxy)
8169 }
8170 }
8171 #[doc = "input selection register"]
8172 #[repr(transparent)]
8173 #[derive(Copy, Clone, Eq, PartialEq)]
8174 pub struct TiselGp16(pub u32);
8175 impl TiselGp16 {
8176 #[doc = "Selects TIM_TIx (x=1-4) input"]
8177 #[inline(always)]
8178 pub const fn tisel(&self, n: usize) -> u8 {
8179 assert!(n < 4usize);
8180 let offs = 0usize + n * 8usize;
8181 let val = (self.0 >> offs) & 0x0f;
8182 val as u8
8183 }
8184 #[doc = "Selects TIM_TIx (x=1-4) input"]
8185 #[inline(always)]
8186 pub fn set_tisel(&mut self, n: usize, val: u8) {
8187 assert!(n < 4usize);
8188 let offs = 0usize + n * 8usize;
8189 self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs);
8190 }
8191 }
8192 impl Default for TiselGp16 {
8193 #[inline(always)]
8194 fn default() -> TiselGp16 {
8195 TiselGp16(0)
8196 }
8197 }
8198 impl core::fmt::Debug for TiselGp16 {
8199 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
8200 f.debug_struct("TiselGp16")
8201 .field(
8202 "tisel",
8203 &[
8204 self.tisel(0usize),
8205 self.tisel(1usize),
8206 self.tisel(2usize),
8207 self.tisel(3usize),
8208 ],
8209 )
8210 .finish()
8211 }
8212 }
8213 #[cfg(feature = "defmt")]
8214 impl defmt::Format for TiselGp16 {
8215 fn format(&self, f: defmt::Formatter) {
8216 #[derive(defmt :: Format)]
8217 struct TiselGp16 {
8218 tisel: [u8; 4usize],
8219 }
8220 let proxy = TiselGp16 {
8221 tisel: [
8222 self.tisel(0usize),
8223 self.tisel(1usize),
8224 self.tisel(2usize),
8225 self.tisel(3usize),
8226 ],
8227 };
8228 defmt::write!(f, "{}", proxy)
8229 }
8230 }
8231}
8232pub mod vals {
8233 #[repr(u8)]
8234 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8235 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8236 pub enum Bkbid {
8237 #[doc = "Break input tim_brk in input mode"]
8238 INPUT = 0x0,
8239 #[doc = "Break input tim_brk in bidirectional mode"]
8240 BIDIRECTIONAL = 0x01,
8241 }
8242 impl Bkbid {
8243 #[inline(always)]
8244 pub const fn from_bits(val: u8) -> Bkbid {
8245 unsafe { core::mem::transmute(val & 0x01) }
8246 }
8247 #[inline(always)]
8248 pub const fn to_bits(self) -> u8 {
8249 unsafe { core::mem::transmute(self) }
8250 }
8251 }
8252 impl From<u8> for Bkbid {
8253 #[inline(always)]
8254 fn from(val: u8) -> Bkbid {
8255 Bkbid::from_bits(val)
8256 }
8257 }
8258 impl From<Bkbid> for u8 {
8259 #[inline(always)]
8260 fn from(val: Bkbid) -> u8 {
8261 Bkbid::to_bits(val)
8262 }
8263 }
8264 #[repr(u8)]
8265 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8266 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8267 pub enum Bkdsrm {
8268 #[doc = "Break input tim_brk is armed"]
8269 ARMED = 0x0,
8270 #[doc = "Break input tim_brk is disarmed"]
8271 DISARMED = 0x01,
8272 }
8273 impl Bkdsrm {
8274 #[inline(always)]
8275 pub const fn from_bits(val: u8) -> Bkdsrm {
8276 unsafe { core::mem::transmute(val & 0x01) }
8277 }
8278 #[inline(always)]
8279 pub const fn to_bits(self) -> u8 {
8280 unsafe { core::mem::transmute(self) }
8281 }
8282 }
8283 impl From<u8> for Bkdsrm {
8284 #[inline(always)]
8285 fn from(val: u8) -> Bkdsrm {
8286 Bkdsrm::from_bits(val)
8287 }
8288 }
8289 impl From<Bkdsrm> for u8 {
8290 #[inline(always)]
8291 fn from(val: Bkdsrm) -> u8 {
8292 Bkdsrm::to_bits(val)
8293 }
8294 }
8295 #[repr(u8)]
8296 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8297 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8298 pub enum Bkinp {
8299 #[doc = "input polarity is not inverted (active low if BKxP = 0, active high if BKxP = 1)"]
8300 NOT_INVERTED = 0x0,
8301 #[doc = "input polarity is inverted (active high if BKxP = 0, active low if BKxP = 1)"]
8302 INVERTED = 0x01,
8303 }
8304 impl Bkinp {
8305 #[inline(always)]
8306 pub const fn from_bits(val: u8) -> Bkinp {
8307 unsafe { core::mem::transmute(val & 0x01) }
8308 }
8309 #[inline(always)]
8310 pub const fn to_bits(self) -> u8 {
8311 unsafe { core::mem::transmute(self) }
8312 }
8313 }
8314 impl From<u8> for Bkinp {
8315 #[inline(always)]
8316 fn from(val: u8) -> Bkinp {
8317 Bkinp::from_bits(val)
8318 }
8319 }
8320 impl From<Bkinp> for u8 {
8321 #[inline(always)]
8322 fn from(val: Bkinp) -> u8 {
8323 Bkinp::to_bits(val)
8324 }
8325 }
8326 #[repr(u8)]
8327 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8328 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8329 pub enum Bkp {
8330 #[doc = "Break input tim_brk is active low"]
8331 ACTIVE_LOW = 0x0,
8332 #[doc = "Break input tim_brk is active high"]
8333 ACTIVE_HIGH = 0x01,
8334 }
8335 impl Bkp {
8336 #[inline(always)]
8337 pub const fn from_bits(val: u8) -> Bkp {
8338 unsafe { core::mem::transmute(val & 0x01) }
8339 }
8340 #[inline(always)]
8341 pub const fn to_bits(self) -> u8 {
8342 unsafe { core::mem::transmute(self) }
8343 }
8344 }
8345 impl From<u8> for Bkp {
8346 #[inline(always)]
8347 fn from(val: u8) -> Bkp {
8348 Bkp::from_bits(val)
8349 }
8350 }
8351 impl From<Bkp> for u8 {
8352 #[inline(always)]
8353 fn from(val: Bkp) -> u8 {
8354 Bkp::to_bits(val)
8355 }
8356 }
8357 #[repr(u8)]
8358 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8359 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8360 pub enum Ccds {
8361 #[doc = "CCx DMA request sent when CCx event occurs"]
8362 ON_COMPARE = 0x0,
8363 #[doc = "CCx DMA request sent when update event occurs"]
8364 ON_UPDATE = 0x01,
8365 }
8366 impl Ccds {
8367 #[inline(always)]
8368 pub const fn from_bits(val: u8) -> Ccds {
8369 unsafe { core::mem::transmute(val & 0x01) }
8370 }
8371 #[inline(always)]
8372 pub const fn to_bits(self) -> u8 {
8373 unsafe { core::mem::transmute(self) }
8374 }
8375 }
8376 impl From<u8> for Ccds {
8377 #[inline(always)]
8378 fn from(val: u8) -> Ccds {
8379 Ccds::from_bits(val)
8380 }
8381 }
8382 impl From<Ccds> for u8 {
8383 #[inline(always)]
8384 fn from(val: Ccds) -> u8 {
8385 Ccds::to_bits(val)
8386 }
8387 }
8388 #[repr(u8)]
8389 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8390 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8391 pub enum CcmrInputCcs {
8392 _RESERVED_0 = 0x0,
8393 #[doc = "CCx channel is configured as input, normal mapping: ICx mapped to TIx"]
8394 TI4 = 0x01,
8395 #[doc = "CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4)"]
8396 TI3 = 0x02,
8397 #[doc = "CCx channel is configured as input, ICx is mapped on TRC"]
8398 TRC = 0x03,
8399 }
8400 impl CcmrInputCcs {
8401 #[inline(always)]
8402 pub const fn from_bits(val: u8) -> CcmrInputCcs {
8403 unsafe { core::mem::transmute(val & 0x03) }
8404 }
8405 #[inline(always)]
8406 pub const fn to_bits(self) -> u8 {
8407 unsafe { core::mem::transmute(self) }
8408 }
8409 }
8410 impl From<u8> for CcmrInputCcs {
8411 #[inline(always)]
8412 fn from(val: u8) -> CcmrInputCcs {
8413 CcmrInputCcs::from_bits(val)
8414 }
8415 }
8416 impl From<CcmrInputCcs> for u8 {
8417 #[inline(always)]
8418 fn from(val: CcmrInputCcs) -> u8 {
8419 CcmrInputCcs::to_bits(val)
8420 }
8421 }
8422 #[repr(u8)]
8423 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8424 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8425 pub enum CcmrOutputCcs {
8426 #[doc = "CCx channel is configured as output"]
8427 OUTPUT = 0x0,
8428 _RESERVED_1 = 0x01,
8429 _RESERVED_2 = 0x02,
8430 _RESERVED_3 = 0x03,
8431 }
8432 impl CcmrOutputCcs {
8433 #[inline(always)]
8434 pub const fn from_bits(val: u8) -> CcmrOutputCcs {
8435 unsafe { core::mem::transmute(val & 0x03) }
8436 }
8437 #[inline(always)]
8438 pub const fn to_bits(self) -> u8 {
8439 unsafe { core::mem::transmute(self) }
8440 }
8441 }
8442 impl From<u8> for CcmrOutputCcs {
8443 #[inline(always)]
8444 fn from(val: u8) -> CcmrOutputCcs {
8445 CcmrOutputCcs::from_bits(val)
8446 }
8447 }
8448 impl From<CcmrOutputCcs> for u8 {
8449 #[inline(always)]
8450 fn from(val: CcmrOutputCcs) -> u8 {
8451 CcmrOutputCcs::to_bits(val)
8452 }
8453 }
8454 #[repr(u8)]
8455 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8456 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8457 pub enum Ckd {
8458 #[doc = "t_DTS = t_CK_INT"]
8459 DIV1 = 0x0,
8460 #[doc = "t_DTS = 2 × t_CK_INT"]
8461 DIV2 = 0x01,
8462 #[doc = "t_DTS = 4 × t_CK_INT"]
8463 DIV4 = 0x02,
8464 _RESERVED_3 = 0x03,
8465 }
8466 impl Ckd {
8467 #[inline(always)]
8468 pub const fn from_bits(val: u8) -> Ckd {
8469 unsafe { core::mem::transmute(val & 0x03) }
8470 }
8471 #[inline(always)]
8472 pub const fn to_bits(self) -> u8 {
8473 unsafe { core::mem::transmute(self) }
8474 }
8475 }
8476 impl From<u8> for Ckd {
8477 #[inline(always)]
8478 fn from(val: u8) -> Ckd {
8479 Ckd::from_bits(val)
8480 }
8481 }
8482 impl From<Ckd> for u8 {
8483 #[inline(always)]
8484 fn from(val: Ckd) -> u8 {
8485 Ckd::to_bits(val)
8486 }
8487 }
8488 #[repr(u8)]
8489 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8490 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8491 pub enum Cms {
8492 #[doc = "The counter counts up or down depending on the direction bit"]
8493 EDGE_ALIGNED = 0x0,
8494 #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."]
8495 CENTER_ALIGNED1 = 0x01,
8496 #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."]
8497 CENTER_ALIGNED2 = 0x02,
8498 #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."]
8499 CENTER_ALIGNED3 = 0x03,
8500 }
8501 impl Cms {
8502 #[inline(always)]
8503 pub const fn from_bits(val: u8) -> Cms {
8504 unsafe { core::mem::transmute(val & 0x03) }
8505 }
8506 #[inline(always)]
8507 pub const fn to_bits(self) -> u8 {
8508 unsafe { core::mem::transmute(self) }
8509 }
8510 }
8511 impl From<u8> for Cms {
8512 #[inline(always)]
8513 fn from(val: u8) -> Cms {
8514 Cms::from_bits(val)
8515 }
8516 }
8517 impl From<Cms> for u8 {
8518 #[inline(always)]
8519 fn from(val: Cms) -> u8 {
8520 Cms::to_bits(val)
8521 }
8522 }
8523 #[repr(u8)]
8524 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8525 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8526 pub enum Dbss {
8527 _RESERVED_0 = 0x0,
8528 #[doc = "Update"]
8529 UPDATE = 0x01,
8530 #[doc = "CC1"]
8531 CC1 = 0x02,
8532 #[doc = "CC2"]
8533 CC2 = 0x03,
8534 #[doc = "CC3"]
8535 CC3 = 0x04,
8536 #[doc = "CC4"]
8537 CC4 = 0x05,
8538 #[doc = "COM"]
8539 COM = 0x06,
8540 #[doc = "Trigger"]
8541 TRIGGER = 0x07,
8542 _RESERVED_8 = 0x08,
8543 _RESERVED_9 = 0x09,
8544 _RESERVED_a = 0x0a,
8545 _RESERVED_b = 0x0b,
8546 _RESERVED_c = 0x0c,
8547 _RESERVED_d = 0x0d,
8548 _RESERVED_e = 0x0e,
8549 _RESERVED_f = 0x0f,
8550 }
8551 impl Dbss {
8552 #[inline(always)]
8553 pub const fn from_bits(val: u8) -> Dbss {
8554 unsafe { core::mem::transmute(val & 0x0f) }
8555 }
8556 #[inline(always)]
8557 pub const fn to_bits(self) -> u8 {
8558 unsafe { core::mem::transmute(self) }
8559 }
8560 }
8561 impl From<u8> for Dbss {
8562 #[inline(always)]
8563 fn from(val: u8) -> Dbss {
8564 Dbss::from_bits(val)
8565 }
8566 }
8567 impl From<Dbss> for u8 {
8568 #[inline(always)]
8569 fn from(val: Dbss) -> u8 {
8570 Dbss::to_bits(val)
8571 }
8572 }
8573 #[repr(u8)]
8574 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8575 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8576 pub enum Dir {
8577 #[doc = "Counter used as upcounter"]
8578 UP = 0x0,
8579 #[doc = "Counter used as downcounter"]
8580 DOWN = 0x01,
8581 }
8582 impl Dir {
8583 #[inline(always)]
8584 pub const fn from_bits(val: u8) -> Dir {
8585 unsafe { core::mem::transmute(val & 0x01) }
8586 }
8587 #[inline(always)]
8588 pub const fn to_bits(self) -> u8 {
8589 unsafe { core::mem::transmute(self) }
8590 }
8591 }
8592 impl From<u8> for Dir {
8593 #[inline(always)]
8594 fn from(val: u8) -> Dir {
8595 Dir::from_bits(val)
8596 }
8597 }
8598 impl From<Dir> for u8 {
8599 #[inline(always)]
8600 fn from(val: Dir) -> u8 {
8601 Dir::to_bits(val)
8602 }
8603 }
8604 #[repr(u8)]
8605 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8606 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8607 pub enum Dtae {
8608 #[doc = "Deadtime on rising and falling edges are identical, and defined with DTG\\[7:0\\]
8609register"]
8610 IDENTICAL = 0x0,
8611 #[doc = "Deadtime on rising edge is defined with DTG\\[7:0\\]
8612register and deadtime on falling edge is defined with DTGF\\[7:0\\]
8613bits."]
8614 DISTINCT = 0x01,
8615 }
8616 impl Dtae {
8617 #[inline(always)]
8618 pub const fn from_bits(val: u8) -> Dtae {
8619 unsafe { core::mem::transmute(val & 0x01) }
8620 }
8621 #[inline(always)]
8622 pub const fn to_bits(self) -> u8 {
8623 unsafe { core::mem::transmute(self) }
8624 }
8625 }
8626 impl From<u8> for Dtae {
8627 #[inline(always)]
8628 fn from(val: u8) -> Dtae {
8629 Dtae::from_bits(val)
8630 }
8631 }
8632 impl From<Dtae> for u8 {
8633 #[inline(always)]
8634 fn from(val: Dtae) -> u8 {
8635 Dtae::to_bits(val)
8636 }
8637 }
8638 #[repr(u8)]
8639 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8640 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8641 pub enum Etp {
8642 #[doc = "ETR is noninverted, active at high level or rising edge"]
8643 NOT_INVERTED = 0x0,
8644 #[doc = "ETR is inverted, active at low level or falling edge"]
8645 INVERTED = 0x01,
8646 }
8647 impl Etp {
8648 #[inline(always)]
8649 pub const fn from_bits(val: u8) -> Etp {
8650 unsafe { core::mem::transmute(val & 0x01) }
8651 }
8652 #[inline(always)]
8653 pub const fn to_bits(self) -> u8 {
8654 unsafe { core::mem::transmute(self) }
8655 }
8656 }
8657 impl From<u8> for Etp {
8658 #[inline(always)]
8659 fn from(val: u8) -> Etp {
8660 Etp::from_bits(val)
8661 }
8662 }
8663 impl From<Etp> for u8 {
8664 #[inline(always)]
8665 fn from(val: Etp) -> u8 {
8666 Etp::to_bits(val)
8667 }
8668 }
8669 #[repr(u8)]
8670 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8671 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8672 pub enum Etps {
8673 #[doc = "Prescaler OFF"]
8674 DIV1 = 0x0,
8675 #[doc = "ETRP frequency divided by 2"]
8676 DIV2 = 0x01,
8677 #[doc = "ETRP frequency divided by 4"]
8678 DIV4 = 0x02,
8679 #[doc = "ETRP frequency divided by 8"]
8680 DIV8 = 0x03,
8681 }
8682 impl Etps {
8683 #[inline(always)]
8684 pub const fn from_bits(val: u8) -> Etps {
8685 unsafe { core::mem::transmute(val & 0x03) }
8686 }
8687 #[inline(always)]
8688 pub const fn to_bits(self) -> u8 {
8689 unsafe { core::mem::transmute(self) }
8690 }
8691 }
8692 impl From<u8> for Etps {
8693 #[inline(always)]
8694 fn from(val: u8) -> Etps {
8695 Etps::from_bits(val)
8696 }
8697 }
8698 impl From<Etps> for u8 {
8699 #[inline(always)]
8700 fn from(val: Etps) -> u8 {
8701 Etps::to_bits(val)
8702 }
8703 }
8704 #[repr(u8)]
8705 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8706 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8707 pub enum Fidx {
8708 #[doc = "Index is always active"]
8709 ALWAYS_ACTIVE = 0x0,
8710 #[doc = "the first Index only resets the counter"]
8711 FIRST_ONLY = 0x01,
8712 }
8713 impl Fidx {
8714 #[inline(always)]
8715 pub const fn from_bits(val: u8) -> Fidx {
8716 unsafe { core::mem::transmute(val & 0x01) }
8717 }
8718 #[inline(always)]
8719 pub const fn to_bits(self) -> u8 {
8720 unsafe { core::mem::transmute(self) }
8721 }
8722 }
8723 impl From<u8> for Fidx {
8724 #[inline(always)]
8725 fn from(val: u8) -> Fidx {
8726 Fidx::from_bits(val)
8727 }
8728 }
8729 impl From<Fidx> for u8 {
8730 #[inline(always)]
8731 fn from(val: Fidx) -> u8 {
8732 Fidx::to_bits(val)
8733 }
8734 }
8735 #[repr(u8)]
8736 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8737 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8738 pub enum FilterValue {
8739 #[doc = "No filter, sampling is done at fDTS"]
8740 NO_FILTER = 0x0,
8741 #[doc = "fSAMPLING=fCK_INT, N=2"]
8742 FCK_INT_N2 = 0x01,
8743 #[doc = "fSAMPLING=fCK_INT, N=4"]
8744 FCK_INT_N4 = 0x02,
8745 #[doc = "fSAMPLING=fCK_INT, N=8"]
8746 FCK_INT_N8 = 0x03,
8747 #[doc = "fSAMPLING=fDTS/2, N=6"]
8748 FDTS_DIV2_N6 = 0x04,
8749 #[doc = "fSAMPLING=fDTS/2, N=8"]
8750 FDTS_DIV2_N8 = 0x05,
8751 #[doc = "fSAMPLING=fDTS/4, N=6"]
8752 FDTS_DIV4_N6 = 0x06,
8753 #[doc = "fSAMPLING=fDTS/4, N=8"]
8754 FDTS_DIV4_N8 = 0x07,
8755 #[doc = "fSAMPLING=fDTS/8, N=6"]
8756 FDTS_DIV8_N6 = 0x08,
8757 #[doc = "fSAMPLING=fDTS/8, N=8"]
8758 FDTS_DIV8_N8 = 0x09,
8759 #[doc = "fSAMPLING=fDTS/16, N=5"]
8760 FDTS_DIV16_N5 = 0x0a,
8761 #[doc = "fSAMPLING=fDTS/16, N=6"]
8762 FDTS_DIV16_N6 = 0x0b,
8763 #[doc = "fSAMPLING=fDTS/16, N=8"]
8764 FDTS_DIV16_N8 = 0x0c,
8765 #[doc = "fSAMPLING=fDTS/32, N=5"]
8766 FDTS_DIV32_N5 = 0x0d,
8767 #[doc = "fSAMPLING=fDTS/32, N=6"]
8768 FDTS_DIV32_N6 = 0x0e,
8769 #[doc = "fSAMPLING=fDTS/32, N=8"]
8770 FDTS_DIV32_N8 = 0x0f,
8771 }
8772 impl FilterValue {
8773 #[inline(always)]
8774 pub const fn from_bits(val: u8) -> FilterValue {
8775 unsafe { core::mem::transmute(val & 0x0f) }
8776 }
8777 #[inline(always)]
8778 pub const fn to_bits(self) -> u8 {
8779 unsafe { core::mem::transmute(self) }
8780 }
8781 }
8782 impl From<u8> for FilterValue {
8783 #[inline(always)]
8784 fn from(val: u8) -> FilterValue {
8785 FilterValue::from_bits(val)
8786 }
8787 }
8788 impl From<FilterValue> for u8 {
8789 #[inline(always)]
8790 fn from(val: FilterValue) -> u8 {
8791 FilterValue::to_bits(val)
8792 }
8793 }
8794 #[repr(u8)]
8795 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8796 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8797 pub enum Gc5c {
8798 #[doc = "No effect of TIM_OC5REF on TIM_OCxREFC (x=1-3)"]
8799 NO_EFFECT = 0x0,
8800 #[doc = "TIM_OCxREFC is the logical AND of TIM_OCxREF and TIM_OC5REF"]
8801 LOGICAL_AND = 0x01,
8802 }
8803 impl Gc5c {
8804 #[inline(always)]
8805 pub const fn from_bits(val: u8) -> Gc5c {
8806 unsafe { core::mem::transmute(val & 0x01) }
8807 }
8808 #[inline(always)]
8809 pub const fn to_bits(self) -> u8 {
8810 unsafe { core::mem::transmute(self) }
8811 }
8812 }
8813 impl From<u8> for Gc5c {
8814 #[inline(always)]
8815 fn from(val: u8) -> Gc5c {
8816 Gc5c::from_bits(val)
8817 }
8818 }
8819 impl From<Gc5c> for u8 {
8820 #[inline(always)]
8821 fn from(val: Gc5c) -> u8 {
8822 Gc5c::to_bits(val)
8823 }
8824 }
8825 #[repr(u8)]
8826 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8827 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8828 pub enum Iblk {
8829 #[doc = "Index always active"]
8830 ALWAYS_ACTIVE = 0x0,
8831 #[doc = "Index disabled when tim_ti3 input is active, as per CC3P bitfield"]
8832 CC3P = 0x01,
8833 #[doc = "Index disabled when tim_ti4 input is active, as per CC4P bitfield"]
8834 CC4P = 0x02,
8835 _RESERVED_3 = 0x03,
8836 }
8837 impl Iblk {
8838 #[inline(always)]
8839 pub const fn from_bits(val: u8) -> Iblk {
8840 unsafe { core::mem::transmute(val & 0x03) }
8841 }
8842 #[inline(always)]
8843 pub const fn to_bits(self) -> u8 {
8844 unsafe { core::mem::transmute(self) }
8845 }
8846 }
8847 impl From<u8> for Iblk {
8848 #[inline(always)]
8849 fn from(val: u8) -> Iblk {
8850 Iblk::from_bits(val)
8851 }
8852 }
8853 impl From<Iblk> for u8 {
8854 #[inline(always)]
8855 fn from(val: Iblk) -> u8 {
8856 Iblk::to_bits(val)
8857 }
8858 }
8859 #[repr(u8)]
8860 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8861 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8862 pub enum Idir {
8863 #[doc = "Index resets the counter whatever the direction"]
8864 BOTH = 0x0,
8865 #[doc = "Index resets the counter when up-counting only"]
8866 UP = 0x01,
8867 #[doc = "Index resets the counter when down-counting only"]
8868 DOWN = 0x02,
8869 _RESERVED_3 = 0x03,
8870 }
8871 impl Idir {
8872 #[inline(always)]
8873 pub const fn from_bits(val: u8) -> Idir {
8874 unsafe { core::mem::transmute(val & 0x03) }
8875 }
8876 #[inline(always)]
8877 pub const fn to_bits(self) -> u8 {
8878 unsafe { core::mem::transmute(self) }
8879 }
8880 }
8881 impl From<u8> for Idir {
8882 #[inline(always)]
8883 fn from(val: u8) -> Idir {
8884 Idir::from_bits(val)
8885 }
8886 }
8887 impl From<Idir> for u8 {
8888 #[inline(always)]
8889 fn from(val: Idir) -> u8 {
8890 Idir::to_bits(val)
8891 }
8892 }
8893 #[repr(u8)]
8894 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8895 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8896 pub enum Lock {
8897 #[doc = "No bit is write protected"]
8898 DISABLED = 0x0,
8899 #[doc = "DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written"]
8900 LEVEL1 = 0x01,
8901 #[doc = "LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written."]
8902 LEVEL2 = 0x02,
8903 #[doc = "LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written."]
8904 LEVEL3 = 0x03,
8905 }
8906 impl Lock {
8907 #[inline(always)]
8908 pub const fn from_bits(val: u8) -> Lock {
8909 unsafe { core::mem::transmute(val & 0x03) }
8910 }
8911 #[inline(always)]
8912 pub const fn to_bits(self) -> u8 {
8913 unsafe { core::mem::transmute(self) }
8914 }
8915 }
8916 impl From<u8> for Lock {
8917 #[inline(always)]
8918 fn from(val: u8) -> Lock {
8919 Lock::from_bits(val)
8920 }
8921 }
8922 impl From<Lock> for u8 {
8923 #[inline(always)]
8924 fn from(val: Lock) -> u8 {
8925 Lock::to_bits(val)
8926 }
8927 }
8928 #[repr(u8)]
8929 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8930 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8931 pub enum Mms {
8932 #[doc = "The UG bit from the TIMx_EGR register is used as trigger output"]
8933 RESET = 0x0,
8934 #[doc = "The counter enable signal, CNT_EN, is used as trigger output"]
8935 ENABLE = 0x01,
8936 #[doc = "The update event is selected as trigger output"]
8937 UPDATE = 0x02,
8938 #[doc = "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"]
8939 COMPARE_PULSE = 0x03,
8940 #[doc = "OC1REF signal is used as trigger output"]
8941 COMPARE_OC1 = 0x04,
8942 #[doc = "OC2REF signal is used as trigger output"]
8943 COMPARE_OC2 = 0x05,
8944 #[doc = "OC3REF signal is used as trigger output"]
8945 COMPARE_OC3 = 0x06,
8946 #[doc = "OC4REF signal is used as trigger output"]
8947 COMPARE_OC4 = 0x07,
8948 #[doc = "The encoder clock signal is used as trigger output"]
8949 ENCODER_CLOCK_OUTPUT = 0x08,
8950 _RESERVED_9 = 0x09,
8951 _RESERVED_a = 0x0a,
8952 _RESERVED_b = 0x0b,
8953 _RESERVED_c = 0x0c,
8954 _RESERVED_d = 0x0d,
8955 _RESERVED_e = 0x0e,
8956 _RESERVED_f = 0x0f,
8957 }
8958 impl Mms {
8959 #[inline(always)]
8960 pub const fn from_bits(val: u8) -> Mms {
8961 unsafe { core::mem::transmute(val & 0x0f) }
8962 }
8963 #[inline(always)]
8964 pub const fn to_bits(self) -> u8 {
8965 unsafe { core::mem::transmute(self) }
8966 }
8967 }
8968 impl From<u8> for Mms {
8969 #[inline(always)]
8970 fn from(val: u8) -> Mms {
8971 Mms::from_bits(val)
8972 }
8973 }
8974 impl From<Mms> for u8 {
8975 #[inline(always)]
8976 fn from(val: Mms) -> u8 {
8977 Mms::to_bits(val)
8978 }
8979 }
8980 #[repr(u8)]
8981 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
8982 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
8983 pub enum Mms2 {
8984 #[doc = "The UG bit from the TIMx_EGR register is used as TRGO2"]
8985 RESET = 0x0,
8986 #[doc = "The counter enable signal, CNT_EN, is used as TRGO2"]
8987 ENABLE = 0x01,
8988 #[doc = "The update event is selected as TRGO2"]
8989 UPDATE = 0x02,
8990 #[doc = "TRGO2 send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"]
8991 COMPARE_PULSE = 0x03,
8992 #[doc = "OC1REF signal is used as TRGO2"]
8993 COMPARE_OC1 = 0x04,
8994 #[doc = "OC2REF signal is used as TRGO2"]
8995 COMPARE_OC2 = 0x05,
8996 #[doc = "OC3REF signal is used as TRGO2"]
8997 COMPARE_OC3 = 0x06,
8998 #[doc = "OC4REF signal is used as TRGO2"]
8999 COMPARE_OC4 = 0x07,
9000 #[doc = "OC5REF signal is used as TRGO2"]
9001 COMPARE_OC5 = 0x08,
9002 #[doc = "OC6REF signal is used as TRGO2"]
9003 COMPARE_OC6 = 0x09,
9004 #[doc = "OC4REF rising or falling edges generate pulses on TRGO2"]
9005 COMPARE_PULSE_OC4 = 0x0a,
9006 #[doc = "OC6REF rising or falling edges generate pulses on TRGO2"]
9007 COMPARE_PULSE_OC6 = 0x0b,
9008 #[doc = "OC4REF or OC6REF rising edges generate pulses on TRGO2"]
9009 COMPARE_PULSE_OC4_OR_OC6_RISING = 0x0c,
9010 #[doc = "OC4REF rising or OC6REF falling edges generate pulses on TRGO2"]
9011 COMPARE_PULSE_OC4_RISING_OR_OC6_FALLING = 0x0d,
9012 #[doc = "OC5REF or OC6REF rising edges generate pulses on TRGO2"]
9013 COMPARE_PULSE_OC5_OR_OC6_RISING = 0x0e,
9014 #[doc = "OC5REF rising or OC6REF falling edges generate pulses on TRGO2"]
9015 COMPARE_PULSE_OC5_RISING_OR_OC6_FALLING = 0x0f,
9016 }
9017 impl Mms2 {
9018 #[inline(always)]
9019 pub const fn from_bits(val: u8) -> Mms2 {
9020 unsafe { core::mem::transmute(val & 0x0f) }
9021 }
9022 #[inline(always)]
9023 pub const fn to_bits(self) -> u8 {
9024 unsafe { core::mem::transmute(self) }
9025 }
9026 }
9027 impl From<u8> for Mms2 {
9028 #[inline(always)]
9029 fn from(val: u8) -> Mms2 {
9030 Mms2::from_bits(val)
9031 }
9032 }
9033 impl From<Mms2> for u8 {
9034 #[inline(always)]
9035 fn from(val: Mms2) -> u8 {
9036 Mms2::to_bits(val)
9037 }
9038 }
9039 #[repr(u8)]
9040 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9041 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9042 pub enum Msm {
9043 #[doc = "No action"]
9044 NO_SYNC = 0x0,
9045 #[doc = "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
9046 SYNC = 0x01,
9047 }
9048 impl Msm {
9049 #[inline(always)]
9050 pub const fn from_bits(val: u8) -> Msm {
9051 unsafe { core::mem::transmute(val & 0x01) }
9052 }
9053 #[inline(always)]
9054 pub const fn to_bits(self) -> u8 {
9055 unsafe { core::mem::transmute(self) }
9056 }
9057 }
9058 impl From<u8> for Msm {
9059 #[inline(always)]
9060 fn from(val: u8) -> Msm {
9061 Msm::from_bits(val)
9062 }
9063 }
9064 impl From<Msm> for u8 {
9065 #[inline(always)]
9066 fn from(val: Msm) -> u8 {
9067 Msm::to_bits(val)
9068 }
9069 }
9070 #[repr(u8)]
9071 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9072 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9073 pub enum Occs {
9074 #[doc = "tim_ocref_clr_int is connected to the tim_ocref_clr input"]
9075 INPUT = 0x0,
9076 #[doc = "tim_ocref_clr_int is connected to tim_etrf"]
9077 ETRF = 0x01,
9078 }
9079 impl Occs {
9080 #[inline(always)]
9081 pub const fn from_bits(val: u8) -> Occs {
9082 unsafe { core::mem::transmute(val & 0x01) }
9083 }
9084 #[inline(always)]
9085 pub const fn to_bits(self) -> u8 {
9086 unsafe { core::mem::transmute(self) }
9087 }
9088 }
9089 impl From<u8> for Occs {
9090 #[inline(always)]
9091 fn from(val: u8) -> Occs {
9092 Occs::from_bits(val)
9093 }
9094 }
9095 impl From<Occs> for u8 {
9096 #[inline(always)]
9097 fn from(val: Occs) -> u8 {
9098 Occs::to_bits(val)
9099 }
9100 }
9101 #[repr(u8)]
9102 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9103 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9104 pub enum Ocm {
9105 #[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"]
9106 FROZEN = 0x0,
9107 #[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"]
9108 ACTIVE_ON_MATCH = 0x01,
9109 #[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"]
9110 INACTIVE_ON_MATCH = 0x02,
9111 #[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy"]
9112 TOGGLE = 0x03,
9113 #[doc = "OCyREF is forced low"]
9114 FORCE_INACTIVE = 0x04,
9115 #[doc = "OCyREF is forced high"]
9116 FORCE_ACTIVE = 0x05,
9117 #[doc = "In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active"]
9118 PWM_MODE1 = 0x06,
9119 #[doc = "Inversely to PwmMode1"]
9120 PWM_MODE2 = 0x07,
9121 #[doc = "In up-counting mode, the channel is active until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update."]
9122 RETRIGERRABLE_OPM_MODE_1 = 0x08,
9123 #[doc = "In up-counting mode, the channel is inactive until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down- counting mode, the channel is active until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update."]
9124 RETRIGERRABLE_OPM_MODE_2 = 0x09,
9125 #[doc = "_reserved1"]
9126 _RESERVED1 = 0x0a,
9127 #[doc = "_reserved2"]
9128 _RESERVED2 = 0x0b,
9129 #[doc = "tim_oc1ref has the same behavior as in PWM mode 1. tim_oc1refc is the logical OR between tim_oc1ref and tim_oc2ref."]
9130 COMBINED_PWM_MODE_1 = 0x0c,
9131 #[doc = "tim_oc1ref has the same behavior as in PWM mode 2. tim_oc1refc is the logical AND between tim_oc1ref and tim_oc2ref."]
9132 COMBINED_PWM_MODE_2 = 0x0d,
9133 #[doc = "tim_oc1ref has the same behavior as in PWM mode 1. tim_oc1refc outputs tim_oc1ref when the counter is counting up, tim_oc2ref when it is counting down."]
9134 ASYMMETRIC_PWM_MODE_1 = 0x0e,
9135 #[doc = "tim_oc1ref has the same behavior as in PWM mode 2. tim_oc1refc outputs tim_oc1ref when the counter is counting up, tim_oc2ref when it is counting down."]
9136 ASYMMETRIC_PWM_MODE_2 = 0x0f,
9137 }
9138 impl Ocm {
9139 #[inline(always)]
9140 pub const fn from_bits(val: u8) -> Ocm {
9141 unsafe { core::mem::transmute(val & 0x0f) }
9142 }
9143 #[inline(always)]
9144 pub const fn to_bits(self) -> u8 {
9145 unsafe { core::mem::transmute(self) }
9146 }
9147 }
9148 impl From<u8> for Ocm {
9149 #[inline(always)]
9150 fn from(val: u8) -> Ocm {
9151 Ocm::from_bits(val)
9152 }
9153 }
9154 impl From<Ocm> for u8 {
9155 #[inline(always)]
9156 fn from(val: Ocm) -> u8 {
9157 Ocm::to_bits(val)
9158 }
9159 }
9160 #[repr(u8)]
9161 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9162 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9163 pub enum Ossi {
9164 #[doc = "When inactive, OC/OCN outputs are disabled"]
9165 DISABLED = 0x0,
9166 #[doc = "When inactive, OC/OCN outputs are forced to idle level"]
9167 IDLE_LEVEL = 0x01,
9168 }
9169 impl Ossi {
9170 #[inline(always)]
9171 pub const fn from_bits(val: u8) -> Ossi {
9172 unsafe { core::mem::transmute(val & 0x01) }
9173 }
9174 #[inline(always)]
9175 pub const fn to_bits(self) -> u8 {
9176 unsafe { core::mem::transmute(self) }
9177 }
9178 }
9179 impl From<u8> for Ossi {
9180 #[inline(always)]
9181 fn from(val: u8) -> Ossi {
9182 Ossi::from_bits(val)
9183 }
9184 }
9185 impl From<Ossi> for u8 {
9186 #[inline(always)]
9187 fn from(val: Ossi) -> u8 {
9188 Ossi::to_bits(val)
9189 }
9190 }
9191 #[repr(u8)]
9192 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9193 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9194 pub enum Ossr {
9195 #[doc = "When inactive, OC/OCN outputs are disabled"]
9196 DISABLED = 0x0,
9197 #[doc = "When inactive, OC/OCN outputs are enabled with their inactive level"]
9198 IDLE_LEVEL = 0x01,
9199 }
9200 impl Ossr {
9201 #[inline(always)]
9202 pub const fn from_bits(val: u8) -> Ossr {
9203 unsafe { core::mem::transmute(val & 0x01) }
9204 }
9205 #[inline(always)]
9206 pub const fn to_bits(self) -> u8 {
9207 unsafe { core::mem::transmute(self) }
9208 }
9209 }
9210 impl From<u8> for Ossr {
9211 #[inline(always)]
9212 fn from(val: u8) -> Ossr {
9213 Ossr::from_bits(val)
9214 }
9215 }
9216 impl From<Ossr> for u8 {
9217 #[inline(always)]
9218 fn from(val: Ossr) -> u8 {
9219 Ossr::to_bits(val)
9220 }
9221 }
9222 #[repr(u8)]
9223 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9224 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9225 pub enum Sms {
9226 #[doc = "Slave mode disabled - if CEN = '1' then the prescaler is clocked directly by the internal clock."]
9227 DISABLED = 0x0,
9228 #[doc = "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level."]
9229 ENCODER_MODE_1 = 0x01,
9230 #[doc = "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level."]
9231 ENCODER_MODE_2 = 0x02,
9232 #[doc = "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input."]
9233 ENCODER_MODE_3 = 0x03,
9234 #[doc = "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers."]
9235 RESET_MODE = 0x04,
9236 #[doc = "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled."]
9237 GATED_MODE = 0x05,
9238 #[doc = "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled."]
9239 TRIGGER_MODE = 0x06,
9240 #[doc = "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter."]
9241 EXT_CLOCK_MODE = 0x07,
9242 #[doc = "Rising edge of the selected trigger input (tim_trgi) reinitializes the counter, generates an update of the registers and starts the counter."]
9243 COMBINED_RESET_TRIGGER = 0x08,
9244 #[doc = "The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops and is reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled."]
9245 COMBINED_GATED_TRIGGER = 0x09,
9246 #[doc = "Encoder mode, Clock plus direction, x2 mode."]
9247 ENCODER_UP_X2 = 0x0a,
9248 #[doc = "Encoder mode, Clock plus direction, x1 mode, tim_ti2fp2 edge sensitivity is set by CC2P"]
9249 ENCODER_UP_X1 = 0x0b,
9250 #[doc = "Encoder mode, Directional Clock, x2 mode."]
9251 ENCODER_DIR_X2 = 0x0c,
9252 #[doc = "Encoder mode, Directional Clock, x1 mode, tim_ti1fp1 and tim_ti2fp2 edge sensitivity is set by CC1P and CC2P."]
9253 ENCODER_DIR_X1 = 0x0d,
9254 #[doc = "Quadrature encoder mode, x1 mode, counting on tim_ti1fp1 edges only, edge sensitivity is set by CC1P."]
9255 QUADRATURE_ENCODER_MODE_X1_TI1PF1 = 0x0e,
9256 #[doc = "Quadrature encoder mode, x1 mode, counting on tim_ti2fp2 edges only, edge sensitivity is set by CC2P."]
9257 QUADRATURE_ENCODER_MODE_X1_TI2PF2 = 0x0f,
9258 }
9259 impl Sms {
9260 #[inline(always)]
9261 pub const fn from_bits(val: u8) -> Sms {
9262 unsafe { core::mem::transmute(val & 0x0f) }
9263 }
9264 #[inline(always)]
9265 pub const fn to_bits(self) -> u8 {
9266 unsafe { core::mem::transmute(self) }
9267 }
9268 }
9269 impl From<u8> for Sms {
9270 #[inline(always)]
9271 fn from(val: u8) -> Sms {
9272 Sms::from_bits(val)
9273 }
9274 }
9275 impl From<Sms> for u8 {
9276 #[inline(always)]
9277 fn from(val: Sms) -> u8 {
9278 Sms::to_bits(val)
9279 }
9280 }
9281 #[repr(u8)]
9282 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9283 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9284 pub enum Smsps {
9285 #[doc = "The transfer is triggered by the Timer’s Update event"]
9286 UPDATE = 0x0,
9287 #[doc = "The transfer is triggered by the Index event"]
9288 INDEX = 0x01,
9289 }
9290 impl Smsps {
9291 #[inline(always)]
9292 pub const fn from_bits(val: u8) -> Smsps {
9293 unsafe { core::mem::transmute(val & 0x01) }
9294 }
9295 #[inline(always)]
9296 pub const fn to_bits(self) -> u8 {
9297 unsafe { core::mem::transmute(self) }
9298 }
9299 }
9300 impl From<u8> for Smsps {
9301 #[inline(always)]
9302 fn from(val: u8) -> Smsps {
9303 Smsps::from_bits(val)
9304 }
9305 }
9306 impl From<Smsps> for u8 {
9307 #[inline(always)]
9308 fn from(val: Smsps) -> u8 {
9309 Smsps::to_bits(val)
9310 }
9311 }
9312 #[repr(u8)]
9313 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9314 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9315 pub enum Ti1s {
9316 #[doc = "The TIMx_CH1 pin is connected to TI1 input"]
9317 NORMAL = 0x0,
9318 #[doc = "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"]
9319 XOR = 0x01,
9320 }
9321 impl Ti1s {
9322 #[inline(always)]
9323 pub const fn from_bits(val: u8) -> Ti1s {
9324 unsafe { core::mem::transmute(val & 0x01) }
9325 }
9326 #[inline(always)]
9327 pub const fn to_bits(self) -> u8 {
9328 unsafe { core::mem::transmute(self) }
9329 }
9330 }
9331 impl From<u8> for Ti1s {
9332 #[inline(always)]
9333 fn from(val: u8) -> Ti1s {
9334 Ti1s::from_bits(val)
9335 }
9336 }
9337 impl From<Ti1s> for u8 {
9338 #[inline(always)]
9339 fn from(val: Ti1s) -> u8 {
9340 Ti1s::to_bits(val)
9341 }
9342 }
9343 #[repr(u8)]
9344 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9345 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9346 pub enum Ts {
9347 #[doc = "Internal Trigger 0"]
9348 ITR0 = 0x0,
9349 #[doc = "Internal Trigger 1"]
9350 ITR1 = 0x01,
9351 #[doc = "Internal Trigger 2"]
9352 ITR2 = 0x02,
9353 #[doc = "Internal Trigger 3"]
9354 ITR3 = 0x03,
9355 #[doc = "TI1 Edge Detector"]
9356 TI1F_ED = 0x04,
9357 #[doc = "Filtered Timer Input 1"]
9358 TI1FP1 = 0x05,
9359 #[doc = "Filtered Timer Input 2"]
9360 TI2FP2 = 0x06,
9361 #[doc = "External Trigger input"]
9362 ETRF = 0x07,
9363 #[doc = "Internal Trigger 4"]
9364 ITR4 = 0x08,
9365 #[doc = "Internal Trigger 5"]
9366 ITR5 = 0x09,
9367 #[doc = "Internal Trigger 6"]
9368 ITR6 = 0x0a,
9369 #[doc = "Internal Trigger 7"]
9370 ITR7 = 0x0b,
9371 #[doc = "Internal Trigger 8"]
9372 ITR8 = 0x0c,
9373 #[doc = "Internal Trigger 9"]
9374 ITR9 = 0x0d,
9375 #[doc = "Internal Trigger 10"]
9376 ITR10 = 0x0e,
9377 #[doc = "Internal Trigger 11"]
9378 ITR11 = 0x0f,
9379 #[doc = "Internal Trigger 12"]
9380 ITR12 = 0x10,
9381 #[doc = "Internal Trigger 13"]
9382 ITR13 = 0x11,
9383 #[doc = "Internal Trigger 14"]
9384 ITR14 = 0x12,
9385 #[doc = "Internal Trigger 15"]
9386 ITR15 = 0x13,
9387 _RESERVED_14 = 0x14,
9388 _RESERVED_15 = 0x15,
9389 _RESERVED_16 = 0x16,
9390 _RESERVED_17 = 0x17,
9391 _RESERVED_18 = 0x18,
9392 _RESERVED_19 = 0x19,
9393 _RESERVED_1a = 0x1a,
9394 _RESERVED_1b = 0x1b,
9395 _RESERVED_1c = 0x1c,
9396 _RESERVED_1d = 0x1d,
9397 _RESERVED_1e = 0x1e,
9398 _RESERVED_1f = 0x1f,
9399 }
9400 impl Ts {
9401 #[inline(always)]
9402 pub const fn from_bits(val: u8) -> Ts {
9403 unsafe { core::mem::transmute(val & 0x1f) }
9404 }
9405 #[inline(always)]
9406 pub const fn to_bits(self) -> u8 {
9407 unsafe { core::mem::transmute(self) }
9408 }
9409 }
9410 impl From<u8> for Ts {
9411 #[inline(always)]
9412 fn from(val: u8) -> Ts {
9413 Ts::from_bits(val)
9414 }
9415 }
9416 impl From<Ts> for u8 {
9417 #[inline(always)]
9418 fn from(val: Ts) -> u8 {
9419 Ts::to_bits(val)
9420 }
9421 }
9422 #[repr(u8)]
9423 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
9424 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
9425 pub enum Urs {
9426 #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"]
9427 ANY_EVENT = 0x0,
9428 #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"]
9429 COUNTER_ONLY = 0x01,
9430 }
9431 impl Urs {
9432 #[inline(always)]
9433 pub const fn from_bits(val: u8) -> Urs {
9434 unsafe { core::mem::transmute(val & 0x01) }
9435 }
9436 #[inline(always)]
9437 pub const fn to_bits(self) -> u8 {
9438 unsafe { core::mem::transmute(self) }
9439 }
9440 }
9441 impl From<u8> for Urs {
9442 #[inline(always)]
9443 fn from(val: u8) -> Urs {
9444 Urs::from_bits(val)
9445 }
9446 }
9447 impl From<Urs> for u8 {
9448 #[inline(always)]
9449 fn from(val: Urs) -> u8 {
9450 Urs::to_bits(val)
9451 }
9452 }
9453}
9454