1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "USB Power Delivery interface"]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Ucpd {
9 ptr: *mut u8,
10}
11unsafe impl Send for Ucpd {}
12unsafe impl Sync for Ucpd {}
13impl Ucpd {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "configuration register 1"]
23 #[inline(always)]
24 pub const fn cfgr1(self) -> crate::common::Reg<regs::Cfgr1, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "configuration register 2"]
28 #[inline(always)]
29 pub const fn cfgr2(self) -> crate::common::Reg<regs::Cfgr2, crate::common::RW> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
31 }
32 #[doc = "configuration register 3"]
33 #[inline(always)]
34 pub const fn cfgr3(self) -> crate::common::Reg<regs::Cfgr3, crate::common::RW> {
35 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
36 }
37 #[doc = "control register"]
38 #[inline(always)]
39 pub const fn cr(self) -> crate::common::Reg<regs::Cr, crate::common::RW> {
40 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
41 }
42 #[doc = "interrupt mask register"]
43 #[inline(always)]
44 pub const fn imr(self) -> crate::common::Reg<regs::Imr, crate::common::RW> {
45 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x10usize) as _) }
46 }
47 #[doc = "status register"]
48 #[inline(always)]
49 pub const fn sr(self) -> crate::common::Reg<regs::Sr, crate::common::RW> {
50 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x14usize) as _) }
51 }
52 #[doc = "interrupt clear register"]
53 #[inline(always)]
54 pub const fn icr(self) -> crate::common::Reg<regs::Icr, crate::common::RW> {
55 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x18usize) as _) }
56 }
57 #[doc = "Tx ordered set type register"]
58 #[inline(always)]
59 pub const fn tx_ordsetr(self) -> crate::common::Reg<regs::TxOrdsetr, crate::common::RW> {
60 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) }
61 }
62 #[doc = "Tx payload size register"]
63 #[inline(always)]
64 pub const fn tx_payszr(self) -> crate::common::Reg<regs::TxPayszr, crate::common::RW> {
65 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x20usize) as _) }
66 }
67 #[doc = "Tx data register"]
68 #[inline(always)]
69 pub const fn txdr(self) -> crate::common::Reg<regs::Txdr, crate::common::RW> {
70 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x24usize) as _) }
71 }
72 #[inline(always)]
73 pub const fn rx_ordsetr(self) -> crate::common::Reg<regs::RxOrdsetr, crate::common::RW> {
74 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x28usize) as _) }
75 }
76 #[inline(always)]
77 pub const fn rx_payszr(self) -> crate::common::Reg<regs::RxPayszr, crate::common::RW> {
78 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
79 }
80 #[inline(always)]
81 pub const fn rxdr(self) -> crate::common::Reg<regs::Rxdr, crate::common::RW> {
82 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x30usize) as _) }
83 }
84 #[doc = "Rx ordered set extension register 1"]
85 #[inline(always)]
86 pub const fn rx_ordextr1(self) -> crate::common::Reg<regs::RxOrdextr1, crate::common::RW> {
87 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x34usize) as _) }
88 }
89 #[doc = "Rx ordered set extension register 2"]
90 #[inline(always)]
91 pub const fn rx_ordextr2(self) -> crate::common::Reg<regs::RxOrdextr2, crate::common::RW> {
92 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x38usize) as _) }
93 }
94 #[doc = "UCPD IP ID register"]
95 #[inline(always)]
96 pub const fn ipver(self) -> crate::common::Reg<regs::Ipver, crate::common::R> {
97 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x03f4usize) as _) }
98 }
99 #[doc = "UCPD IP ID register"]
100 #[inline(always)]
101 pub const fn ipid(self) -> crate::common::Reg<regs::Ipid, crate::common::R> {
102 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x03f8usize) as _) }
103 }
104 #[doc = "UCPD IP ID register"]
105 #[inline(always)]
106 pub const fn mid(self) -> crate::common::Reg<regs::Mid, crate::common::R> {
107 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x03fcusize) as _) }
108 }
109}
110pub mod regs {
111 #[doc = "configuration register 1"]
112 #[repr(transparent)]
113 #[derive(Copy, Clone, Eq, PartialEq)]
114 pub struct Cfgr1(pub u32);
115 impl Cfgr1 {
116 #[doc = "Division ratio for producing half-bit clock The bitfield determines the division ratio (the bitfield value plus one) of a clk divider producing half-bit clock (hbit_clk)."]
117 #[inline(always)]
118 pub const fn hbitclkdiv(&self) -> u8 {
119 let val = (self.0 >> 0usize) & 0x3f;
120 val as u8
121 }
122 #[doc = "Division ratio for producing half-bit clock The bitfield determines the division ratio (the bitfield value plus one) of a clk divider producing half-bit clock (hbit_clk)."]
123 #[inline(always)]
124 pub fn set_hbitclkdiv(&mut self, val: u8) {
125 self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
126 }
127 #[doc = "Division ratio for producing inter-frame gap timer clock The bitfield determines the division ratio (the bitfield value minus one) of a clk divider producing inter-frame gap timer clock (tInterFrameGap). The division ratio 15 is to apply for Tx clock at the USB PD 2.0 specification nominal value. The division ratios below 15 are to apply for Tx clock below nominal, and the division ratios above 15 for Tx clock above nominal."]
128 #[inline(always)]
129 pub const fn ifrgap(&self) -> u8 {
130 let val = (self.0 >> 6usize) & 0x1f;
131 val as u8
132 }
133 #[doc = "Division ratio for producing inter-frame gap timer clock The bitfield determines the division ratio (the bitfield value minus one) of a clk divider producing inter-frame gap timer clock (tInterFrameGap). The division ratio 15 is to apply for Tx clock at the USB PD 2.0 specification nominal value. The division ratios below 15 are to apply for Tx clock below nominal, and the division ratios above 15 for Tx clock above nominal."]
134 #[inline(always)]
135 pub fn set_ifrgap(&mut self, val: u8) {
136 self.0 = (self.0 & !(0x1f << 6usize)) | (((val as u32) & 0x1f) << 6usize);
137 }
138 #[doc = "Transition window duration The bitfield determines the division ratio (the bitfield value minus one) of a hbit_clk divider producing tTransitionWindow interval. Set a value that produces an interval of 12 to 20 us, taking into account the clk frequency and the HBITCLKDIV\\[5:0\\]
139bitfield setting."]
140 #[inline(always)]
141 pub const fn transwin(&self) -> u8 {
142 let val = (self.0 >> 11usize) & 0x1f;
143 val as u8
144 }
145 #[doc = "Transition window duration The bitfield determines the division ratio (the bitfield value minus one) of a hbit_clk divider producing tTransitionWindow interval. Set a value that produces an interval of 12 to 20 us, taking into account the clk frequency and the HBITCLKDIV\\[5:0\\]
146bitfield setting."]
147 #[inline(always)]
148 pub fn set_transwin(&mut self, val: u8) {
149 self.0 = (self.0 & !(0x1f << 11usize)) | (((val as u32) & 0x1f) << 11usize);
150 }
151 #[doc = "Pre-scaler division ratio for generating clk The bitfield determines the division ratio of a kernel clock pre-scaler producing peripheral clock (clk). It is recommended to use the pre-scaler so as to set the clk frequency in the range from 6 to 9 MHz."]
152 #[inline(always)]
153 pub const fn psc_usbpdclk(&self) -> super::vals::PscUsbpdclk {
154 let val = (self.0 >> 17usize) & 0x07;
155 super::vals::PscUsbpdclk::from_bits(val as u8)
156 }
157 #[doc = "Pre-scaler division ratio for generating clk The bitfield determines the division ratio of a kernel clock pre-scaler producing peripheral clock (clk). It is recommended to use the pre-scaler so as to set the clk frequency in the range from 6 to 9 MHz."]
158 #[inline(always)]
159 pub fn set_psc_usbpdclk(&mut self, val: super::vals::PscUsbpdclk) {
160 self.0 = (self.0 & !(0x07 << 17usize)) | (((val.to_bits() as u32) & 0x07) << 17usize);
161 }
162 #[doc = "Receiver ordered set enable The bitfield determines the types of ordered sets that the receiver must detect. When set/cleared, each bit enables/disables a specific function: 0bxxxxxxxx1: SOP detect enabled 0bxxxxxxx1x: SOP' detect enabled 0bxxxxxx1xx: SOP'' detect enabled 0bxxxxx1xxx: Hard Reset detect enabled 0bxxxx1xxxx: Cable Detect reset enabled 0bxxx1xxxxx: SOP'_Debug enabled 0bxx1xxxxxx: SOP''_Debug enabled 0bx1xxxxxxx: SOP extension#1 enabled 0b1xxxxxxxx: SOP extension#2 enabled"]
163 #[inline(always)]
164 pub const fn rxordseten(&self) -> u16 {
165 let val = (self.0 >> 20usize) & 0x01ff;
166 val as u16
167 }
168 #[doc = "Receiver ordered set enable The bitfield determines the types of ordered sets that the receiver must detect. When set/cleared, each bit enables/disables a specific function: 0bxxxxxxxx1: SOP detect enabled 0bxxxxxxx1x: SOP' detect enabled 0bxxxxxx1xx: SOP'' detect enabled 0bxxxxx1xxx: Hard Reset detect enabled 0bxxxx1xxxx: Cable Detect reset enabled 0bxxx1xxxxx: SOP'_Debug enabled 0bxx1xxxxxx: SOP''_Debug enabled 0bx1xxxxxxx: SOP extension#1 enabled 0b1xxxxxxxx: SOP extension#2 enabled"]
169 #[inline(always)]
170 pub fn set_rxordseten(&mut self, val: u16) {
171 self.0 = (self.0 & !(0x01ff << 20usize)) | (((val as u32) & 0x01ff) << 20usize);
172 }
173 #[doc = "Transmission DMA mode enable When set, the bit enables DMA mode for transmission."]
174 #[inline(always)]
175 pub const fn txdmaen(&self) -> bool {
176 let val = (self.0 >> 29usize) & 0x01;
177 val != 0
178 }
179 #[doc = "Transmission DMA mode enable When set, the bit enables DMA mode for transmission."]
180 #[inline(always)]
181 pub fn set_txdmaen(&mut self, val: bool) {
182 self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
183 }
184 #[doc = "Reception DMA mode enable When set, the bit enables DMA mode for reception."]
185 #[inline(always)]
186 pub const fn rxdmaen(&self) -> bool {
187 let val = (self.0 >> 30usize) & 0x01;
188 val != 0
189 }
190 #[doc = "Reception DMA mode enable When set, the bit enables DMA mode for reception."]
191 #[inline(always)]
192 pub fn set_rxdmaen(&mut self, val: bool) {
193 self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
194 }
195 #[doc = "peripheral enable General enable of the peripheral. Upon disabling, the peripheral instantly quits any ongoing activity and all control bits and bitfields default to their reset values. They must be set to their desired values each time the peripheral transits from disabled to enabled state."]
196 #[inline(always)]
197 pub const fn ucpden(&self) -> bool {
198 let val = (self.0 >> 31usize) & 0x01;
199 val != 0
200 }
201 #[doc = "peripheral enable General enable of the peripheral. Upon disabling, the peripheral instantly quits any ongoing activity and all control bits and bitfields default to their reset values. They must be set to their desired values each time the peripheral transits from disabled to enabled state."]
202 #[inline(always)]
203 pub fn set_ucpden(&mut self, val: bool) {
204 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
205 }
206 }
207 impl Default for Cfgr1 {
208 #[inline(always)]
209 fn default() -> Cfgr1 {
210 Cfgr1(0)
211 }
212 }
213 impl core::fmt::Debug for Cfgr1 {
214 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
215 f.debug_struct("Cfgr1")
216 .field("hbitclkdiv", &self.hbitclkdiv())
217 .field("ifrgap", &self.ifrgap())
218 .field("transwin", &self.transwin())
219 .field("psc_usbpdclk", &self.psc_usbpdclk())
220 .field("rxordseten", &self.rxordseten())
221 .field("txdmaen", &self.txdmaen())
222 .field("rxdmaen", &self.rxdmaen())
223 .field("ucpden", &self.ucpden())
224 .finish()
225 }
226 }
227 #[cfg(feature = "defmt")]
228 impl defmt::Format for Cfgr1 {
229 fn format(&self, f: defmt::Formatter) {
230 #[derive(defmt :: Format)]
231 struct Cfgr1 {
232 hbitclkdiv: u8,
233 ifrgap: u8,
234 transwin: u8,
235 psc_usbpdclk: super::vals::PscUsbpdclk,
236 rxordseten: u16,
237 txdmaen: bool,
238 rxdmaen: bool,
239 ucpden: bool,
240 }
241 let proxy = Cfgr1 {
242 hbitclkdiv: self.hbitclkdiv(),
243 ifrgap: self.ifrgap(),
244 transwin: self.transwin(),
245 psc_usbpdclk: self.psc_usbpdclk(),
246 rxordseten: self.rxordseten(),
247 txdmaen: self.txdmaen(),
248 rxdmaen: self.rxdmaen(),
249 ucpden: self.ucpden(),
250 };
251 defmt::write!(f, "{}", proxy)
252 }
253 }
254 #[doc = "configuration register 2"]
255 #[repr(transparent)]
256 #[derive(Copy, Clone, Eq, PartialEq)]
257 pub struct Cfgr2(pub u32);
258 impl Cfgr2 {
259 #[doc = "BMC decoder Rx pre-filter enable The sampling clock is that of the receiver (that is, after pre-scaler)."]
260 #[inline(always)]
261 pub const fn rxfiltdis(&self) -> bool {
262 let val = (self.0 >> 0usize) & 0x01;
263 val != 0
264 }
265 #[doc = "BMC decoder Rx pre-filter enable The sampling clock is that of the receiver (that is, after pre-scaler)."]
266 #[inline(always)]
267 pub fn set_rxfiltdis(&mut self, val: bool) {
268 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
269 }
270 #[doc = "BMC decoder Rx pre-filter sampling method Number of consistent consecutive samples before confirming a new value."]
271 #[inline(always)]
272 pub const fn rxfilt2n3(&self) -> bool {
273 let val = (self.0 >> 1usize) & 0x01;
274 val != 0
275 }
276 #[doc = "BMC decoder Rx pre-filter sampling method Number of consistent consecutive samples before confirming a new value."]
277 #[inline(always)]
278 pub fn set_rxfilt2n3(&mut self, val: bool) {
279 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
280 }
281 #[doc = "Force ClkReq clock request"]
282 #[inline(always)]
283 pub const fn forceclk(&self) -> bool {
284 let val = (self.0 >> 2usize) & 0x01;
285 val != 0
286 }
287 #[doc = "Force ClkReq clock request"]
288 #[inline(always)]
289 pub fn set_forceclk(&mut self, val: bool) {
290 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
291 }
292 #[doc = "Wakeup from Stop mode enable Setting the bit enables the ASYNC_INT signal."]
293 #[inline(always)]
294 pub const fn wupen(&self) -> bool {
295 let val = (self.0 >> 3usize) & 0x01;
296 val != 0
297 }
298 #[doc = "Wakeup from Stop mode enable Setting the bit enables the ASYNC_INT signal."]
299 #[inline(always)]
300 pub fn set_wupen(&mut self, val: bool) {
301 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
302 }
303 }
304 impl Default for Cfgr2 {
305 #[inline(always)]
306 fn default() -> Cfgr2 {
307 Cfgr2(0)
308 }
309 }
310 impl core::fmt::Debug for Cfgr2 {
311 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
312 f.debug_struct("Cfgr2")
313 .field("rxfiltdis", &self.rxfiltdis())
314 .field("rxfilt2n3", &self.rxfilt2n3())
315 .field("forceclk", &self.forceclk())
316 .field("wupen", &self.wupen())
317 .finish()
318 }
319 }
320 #[cfg(feature = "defmt")]
321 impl defmt::Format for Cfgr2 {
322 fn format(&self, f: defmt::Formatter) {
323 #[derive(defmt :: Format)]
324 struct Cfgr2 {
325 rxfiltdis: bool,
326 rxfilt2n3: bool,
327 forceclk: bool,
328 wupen: bool,
329 }
330 let proxy = Cfgr2 {
331 rxfiltdis: self.rxfiltdis(),
332 rxfilt2n3: self.rxfilt2n3(),
333 forceclk: self.forceclk(),
334 wupen: self.wupen(),
335 };
336 defmt::write!(f, "{}", proxy)
337 }
338 }
339 #[doc = "configuration register 3"]
340 #[repr(transparent)]
341 #[derive(Copy, Clone, Eq, PartialEq)]
342 pub struct Cfgr3(pub u32);
343 impl Cfgr3 {
344 #[doc = "SW trim value for Rd resistor on the CC1 line"]
345 #[inline(always)]
346 pub const fn trim_cc1_rd(&self) -> u8 {
347 let val = (self.0 >> 0usize) & 0x0f;
348 val as u8
349 }
350 #[doc = "SW trim value for Rd resistor on the CC1 line"]
351 #[inline(always)]
352 pub fn set_trim_cc1_rd(&mut self, val: u8) {
353 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
354 }
355 #[doc = "SW trim value for Rp current sources on the CC1 line"]
356 #[inline(always)]
357 pub const fn trim_cc1_rp(&self) -> u8 {
358 let val = (self.0 >> 9usize) & 0x0f;
359 val as u8
360 }
361 #[doc = "SW trim value for Rp current sources on the CC1 line"]
362 #[inline(always)]
363 pub fn set_trim_cc1_rp(&mut self, val: u8) {
364 self.0 = (self.0 & !(0x0f << 9usize)) | (((val as u32) & 0x0f) << 9usize);
365 }
366 #[doc = "SW trim value for Rd resistor on the CC2 line"]
367 #[inline(always)]
368 pub const fn trim_cc2_rd(&self) -> u8 {
369 let val = (self.0 >> 16usize) & 0x0f;
370 val as u8
371 }
372 #[doc = "SW trim value for Rd resistor on the CC2 line"]
373 #[inline(always)]
374 pub fn set_trim_cc2_rd(&mut self, val: u8) {
375 self.0 = (self.0 & !(0x0f << 16usize)) | (((val as u32) & 0x0f) << 16usize);
376 }
377 #[doc = "SW trim value for Rp current sources on the CC2 line"]
378 #[inline(always)]
379 pub const fn trim_cc2_rp(&self) -> u8 {
380 let val = (self.0 >> 25usize) & 0x0f;
381 val as u8
382 }
383 #[doc = "SW trim value for Rp current sources on the CC2 line"]
384 #[inline(always)]
385 pub fn set_trim_cc2_rp(&mut self, val: u8) {
386 self.0 = (self.0 & !(0x0f << 25usize)) | (((val as u32) & 0x0f) << 25usize);
387 }
388 }
389 impl Default for Cfgr3 {
390 #[inline(always)]
391 fn default() -> Cfgr3 {
392 Cfgr3(0)
393 }
394 }
395 impl core::fmt::Debug for Cfgr3 {
396 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
397 f.debug_struct("Cfgr3")
398 .field("trim_cc1_rd", &self.trim_cc1_rd())
399 .field("trim_cc1_rp", &self.trim_cc1_rp())
400 .field("trim_cc2_rd", &self.trim_cc2_rd())
401 .field("trim_cc2_rp", &self.trim_cc2_rp())
402 .finish()
403 }
404 }
405 #[cfg(feature = "defmt")]
406 impl defmt::Format for Cfgr3 {
407 fn format(&self, f: defmt::Formatter) {
408 #[derive(defmt :: Format)]
409 struct Cfgr3 {
410 trim_cc1_rd: u8,
411 trim_cc1_rp: u8,
412 trim_cc2_rd: u8,
413 trim_cc2_rp: u8,
414 }
415 let proxy = Cfgr3 {
416 trim_cc1_rd: self.trim_cc1_rd(),
417 trim_cc1_rp: self.trim_cc1_rp(),
418 trim_cc2_rd: self.trim_cc2_rd(),
419 trim_cc2_rp: self.trim_cc2_rp(),
420 };
421 defmt::write!(f, "{}", proxy)
422 }
423 }
424 #[doc = "control register"]
425 #[repr(transparent)]
426 #[derive(Copy, Clone, Eq, PartialEq)]
427 pub struct Cr(pub u32);
428 impl Cr {
429 #[doc = "Type of Tx packet Writing the bitfield triggers the action as follows, depending on the value: Others: invalid From V1.1 of the USB PD specification, there is a counter defined for the duration of the BIST Carrier Mode 2. To quit this mode correctly (after the \"tBISTContMode\" delay), disable the peripheral (UCPDEN = 0)."]
430 #[inline(always)]
431 pub const fn txmode(&self) -> super::vals::Txmode {
432 let val = (self.0 >> 0usize) & 0x03;
433 super::vals::Txmode::from_bits(val as u8)
434 }
435 #[doc = "Type of Tx packet Writing the bitfield triggers the action as follows, depending on the value: Others: invalid From V1.1 of the USB PD specification, there is a counter defined for the duration of the BIST Carrier Mode 2. To quit this mode correctly (after the \"tBISTContMode\" delay), disable the peripheral (UCPDEN = 0)."]
436 #[inline(always)]
437 pub fn set_txmode(&mut self, val: super::vals::Txmode) {
438 self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
439 }
440 #[doc = "Command to send a Tx packet The bit is cleared by hardware as soon as the packet transmission begins or is discarded."]
441 #[inline(always)]
442 pub const fn txsend(&self) -> bool {
443 let val = (self.0 >> 2usize) & 0x01;
444 val != 0
445 }
446 #[doc = "Command to send a Tx packet The bit is cleared by hardware as soon as the packet transmission begins or is discarded."]
447 #[inline(always)]
448 pub fn set_txsend(&mut self, val: bool) {
449 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
450 }
451 #[doc = "Command to send a Tx Hard Reset The bit is cleared by hardware as soon as the message transmission begins or is discarded."]
452 #[inline(always)]
453 pub const fn txhrst(&self) -> bool {
454 let val = (self.0 >> 3usize) & 0x01;
455 val != 0
456 }
457 #[doc = "Command to send a Tx Hard Reset The bit is cleared by hardware as soon as the message transmission begins or is discarded."]
458 #[inline(always)]
459 pub fn set_txhrst(&mut self, val: bool) {
460 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
461 }
462 #[doc = "Receiver mode Determines the mode of the receiver. When the bit is set, RXORDSET behaves normally, RXDR no longer receives bytes yet the CRC checking still proceeds as for a normal message."]
463 #[inline(always)]
464 pub const fn rxmode(&self) -> bool {
465 let val = (self.0 >> 4usize) & 0x01;
466 val != 0
467 }
468 #[doc = "Receiver mode Determines the mode of the receiver. When the bit is set, RXORDSET behaves normally, RXDR no longer receives bytes yet the CRC checking still proceeds as for a normal message."]
469 #[inline(always)]
470 pub fn set_rxmode(&mut self, val: bool) {
471 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
472 }
473 #[doc = "USB Power Delivery receiver enable Both CC1 and CC2 receivers are disabled when the bit is cleared. Only the CC receiver selected via the PHYCCSEL bit is enabled when the bit is set."]
474 #[inline(always)]
475 pub const fn phyrxen(&self) -> bool {
476 let val = (self.0 >> 5usize) & 0x01;
477 val != 0
478 }
479 #[doc = "USB Power Delivery receiver enable Both CC1 and CC2 receivers are disabled when the bit is cleared. Only the CC receiver selected via the PHYCCSEL bit is enabled when the bit is set."]
480 #[inline(always)]
481 pub fn set_phyrxen(&mut self, val: bool) {
482 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
483 }
484 #[doc = "CC1/CC2 line selector for USB Power Delivery signaling The selection depends on the cable orientation as discovered at attach."]
485 #[inline(always)]
486 pub const fn phyccsel(&self) -> super::vals::Phyccsel {
487 let val = (self.0 >> 6usize) & 0x01;
488 super::vals::Phyccsel::from_bits(val as u8)
489 }
490 #[doc = "CC1/CC2 line selector for USB Power Delivery signaling The selection depends on the cable orientation as discovered at attach."]
491 #[inline(always)]
492 pub fn set_phyccsel(&mut self, val: super::vals::Phyccsel) {
493 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize);
494 }
495 #[doc = "Analog PHY sub-mode Refer to TYPEC_VSTATE_CCx for the effect of this bitfield."]
496 #[inline(always)]
497 pub const fn anasubmode(&self) -> u8 {
498 let val = (self.0 >> 7usize) & 0x03;
499 val as u8
500 }
501 #[doc = "Analog PHY sub-mode Refer to TYPEC_VSTATE_CCx for the effect of this bitfield."]
502 #[inline(always)]
503 pub fn set_anasubmode(&mut self, val: u8) {
504 self.0 = (self.0 & !(0x03 << 7usize)) | (((val as u32) & 0x03) << 7usize);
505 }
506 #[doc = "Analog PHY operating mode The use of CC1 and CC2 depends on CCENABLE. Refer to ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx for the effect of this bitfield in conjunction with ANASUBMODE\\[1:0\\]."]
507 #[inline(always)]
508 pub const fn anamode(&self) -> super::vals::Anamode {
509 let val = (self.0 >> 9usize) & 0x01;
510 super::vals::Anamode::from_bits(val as u8)
511 }
512 #[doc = "Analog PHY operating mode The use of CC1 and CC2 depends on CCENABLE. Refer to ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx for the effect of this bitfield in conjunction with ANASUBMODE\\[1:0\\]."]
513 #[inline(always)]
514 pub fn set_anamode(&mut self, val: super::vals::Anamode) {
515 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.to_bits() as u32) & 0x01) << 9usize);
516 }
517 #[doc = "CC line enable This bitfield enables CC1 and CC2 line analog PHYs (pull-ups and pull-downs) according to ANAMODE and ANASUBMODE\\[1:0\\]
518setting. A single line PHY can be enabled when, for example, the other line is driven by VCONN via an external VCONN switch. Enabling both PHYs is the normal usage for sink/source."]
519 #[inline(always)]
520 pub const fn ccenable(&self) -> super::vals::Ccenable {
521 let val = (self.0 >> 10usize) & 0x03;
522 super::vals::Ccenable::from_bits(val as u8)
523 }
524 #[doc = "CC line enable This bitfield enables CC1 and CC2 line analog PHYs (pull-ups and pull-downs) according to ANAMODE and ANASUBMODE\\[1:0\\]
525setting. A single line PHY can be enabled when, for example, the other line is driven by VCONN via an external VCONN switch. Enabling both PHYs is the normal usage for sink/source."]
526 #[inline(always)]
527 pub fn set_ccenable(&mut self, val: super::vals::Ccenable) {
528 self.0 = (self.0 & !(0x03 << 10usize)) | (((val.to_bits() as u32) & 0x03) << 10usize);
529 }
530 #[doc = "VCONN switch enable for CC1"]
531 #[inline(always)]
532 pub const fn cc1vconnen(&self) -> bool {
533 let val = (self.0 >> 13usize) & 0x01;
534 val != 0
535 }
536 #[doc = "VCONN switch enable for CC1"]
537 #[inline(always)]
538 pub fn set_cc1vconnen(&mut self, val: bool) {
539 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
540 }
541 #[doc = "VCONN switch enable for CC2"]
542 #[inline(always)]
543 pub const fn cc2vconnen(&self) -> bool {
544 let val = (self.0 >> 14usize) & 0x01;
545 val != 0
546 }
547 #[doc = "VCONN switch enable for CC2"]
548 #[inline(always)]
549 pub fn set_cc2vconnen(&mut self, val: bool) {
550 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
551 }
552 #[doc = "Dead battery function enable The bit takes effect upon setting the USBPDstrobe bit of the SYS_CONFIG register. Dead battery function only operates if the external circuit is appropriately configured."]
553 #[inline(always)]
554 pub const fn dbatten(&self) -> bool {
555 let val = (self.0 >> 15usize) & 0x01;
556 val != 0
557 }
558 #[doc = "Dead battery function enable The bit takes effect upon setting the USBPDstrobe bit of the SYS_CONFIG register. Dead battery function only operates if the external circuit is appropriately configured."]
559 #[inline(always)]
560 pub fn set_dbatten(&mut self, val: bool) {
561 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
562 }
563 #[doc = "FRS event detection enable Setting the bit enables FRS Rx event (FRSEVT) detection on the CC line selected through the PHYCCSEL bit. 0: Disable Clear the bit when the device is attached to an FRS-incapable source/sink."]
564 #[inline(always)]
565 pub const fn frsrxen(&self) -> bool {
566 let val = (self.0 >> 16usize) & 0x01;
567 val != 0
568 }
569 #[doc = "FRS event detection enable Setting the bit enables FRS Rx event (FRSEVT) detection on the CC line selected through the PHYCCSEL bit. 0: Disable Clear the bit when the device is attached to an FRS-incapable source/sink."]
570 #[inline(always)]
571 pub fn set_frsrxen(&mut self, val: bool) {
572 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
573 }
574 #[doc = "FRS Tx signaling enable. Setting the bit enables FRS Tx signaling. The bit is cleared by hardware after a delay respecting the USB Power Delivery specification Revision 3.0."]
575 #[inline(always)]
576 pub const fn frstx(&self) -> bool {
577 let val = (self.0 >> 17usize) & 0x01;
578 val != 0
579 }
580 #[doc = "FRS Tx signaling enable. Setting the bit enables FRS Tx signaling. The bit is cleared by hardware after a delay respecting the USB Power Delivery specification Revision 3.0."]
581 #[inline(always)]
582 pub fn set_frstx(&mut self, val: bool) {
583 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
584 }
585 #[doc = "Rdch condition drive The bit drives Rdch condition on the CC line selected through the PHYCCSEL bit (thus associated with VCONN), by remaining set during the source-only UnattachedWait.SRC state, to respect the Type-C state. Refer to \"USB Type-C ECN for Source VCONN Discharge\". The CCENABLE\\[1:0\\]
586bitfield must be set accordingly, too."]
587 #[inline(always)]
588 pub const fn rdch(&self) -> bool {
589 let val = (self.0 >> 18usize) & 0x01;
590 val != 0
591 }
592 #[doc = "Rdch condition drive The bit drives Rdch condition on the CC line selected through the PHYCCSEL bit (thus associated with VCONN), by remaining set during the source-only UnattachedWait.SRC state, to respect the Type-C state. Refer to \"USB Type-C ECN for Source VCONN Discharge\". The CCENABLE\\[1:0\\]
593bitfield must be set accordingly, too."]
594 #[inline(always)]
595 pub fn set_rdch(&mut self, val: bool) {
596 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
597 }
598 #[doc = "CC1 Type-C detector disable The bit disables the Type-C detector on the CC1 line. When enabled, the Type-C detector for CC1 is configured through ANAMODE and ANASUBMODE\\[1:0\\]."]
599 #[inline(always)]
600 pub const fn cc1tcdis(&self) -> bool {
601 let val = (self.0 >> 20usize) & 0x01;
602 val != 0
603 }
604 #[doc = "CC1 Type-C detector disable The bit disables the Type-C detector on the CC1 line. When enabled, the Type-C detector for CC1 is configured through ANAMODE and ANASUBMODE\\[1:0\\]."]
605 #[inline(always)]
606 pub fn set_cc1tcdis(&mut self, val: bool) {
607 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
608 }
609 #[doc = "CC2 Type-C detector disable The bit disables the Type-C detector on the CC2 line. When enabled, the Type-C detector for CC2 is configured through ANAMODE and ANASUBMODE\\[1:0\\]."]
610 #[inline(always)]
611 pub const fn cc2tcdis(&self) -> bool {
612 let val = (self.0 >> 21usize) & 0x01;
613 val != 0
614 }
615 #[doc = "CC2 Type-C detector disable The bit disables the Type-C detector on the CC2 line. When enabled, the Type-C detector for CC2 is configured through ANAMODE and ANASUBMODE\\[1:0\\]."]
616 #[inline(always)]
617 pub fn set_cc2tcdis(&mut self, val: bool) {
618 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
619 }
620 }
621 impl Default for Cr {
622 #[inline(always)]
623 fn default() -> Cr {
624 Cr(0)
625 }
626 }
627 impl core::fmt::Debug for Cr {
628 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
629 f.debug_struct("Cr")
630 .field("txmode", &self.txmode())
631 .field("txsend", &self.txsend())
632 .field("txhrst", &self.txhrst())
633 .field("rxmode", &self.rxmode())
634 .field("phyrxen", &self.phyrxen())
635 .field("phyccsel", &self.phyccsel())
636 .field("anasubmode", &self.anasubmode())
637 .field("anamode", &self.anamode())
638 .field("ccenable", &self.ccenable())
639 .field("cc1vconnen", &self.cc1vconnen())
640 .field("cc2vconnen", &self.cc2vconnen())
641 .field("dbatten", &self.dbatten())
642 .field("frsrxen", &self.frsrxen())
643 .field("frstx", &self.frstx())
644 .field("rdch", &self.rdch())
645 .field("cc1tcdis", &self.cc1tcdis())
646 .field("cc2tcdis", &self.cc2tcdis())
647 .finish()
648 }
649 }
650 #[cfg(feature = "defmt")]
651 impl defmt::Format for Cr {
652 fn format(&self, f: defmt::Formatter) {
653 #[derive(defmt :: Format)]
654 struct Cr {
655 txmode: super::vals::Txmode,
656 txsend: bool,
657 txhrst: bool,
658 rxmode: bool,
659 phyrxen: bool,
660 phyccsel: super::vals::Phyccsel,
661 anasubmode: u8,
662 anamode: super::vals::Anamode,
663 ccenable: super::vals::Ccenable,
664 cc1vconnen: bool,
665 cc2vconnen: bool,
666 dbatten: bool,
667 frsrxen: bool,
668 frstx: bool,
669 rdch: bool,
670 cc1tcdis: bool,
671 cc2tcdis: bool,
672 }
673 let proxy = Cr {
674 txmode: self.txmode(),
675 txsend: self.txsend(),
676 txhrst: self.txhrst(),
677 rxmode: self.rxmode(),
678 phyrxen: self.phyrxen(),
679 phyccsel: self.phyccsel(),
680 anasubmode: self.anasubmode(),
681 anamode: self.anamode(),
682 ccenable: self.ccenable(),
683 cc1vconnen: self.cc1vconnen(),
684 cc2vconnen: self.cc2vconnen(),
685 dbatten: self.dbatten(),
686 frsrxen: self.frsrxen(),
687 frstx: self.frstx(),
688 rdch: self.rdch(),
689 cc1tcdis: self.cc1tcdis(),
690 cc2tcdis: self.cc2tcdis(),
691 };
692 defmt::write!(f, "{}", proxy)
693 }
694 }
695 #[doc = "interrupt clear register"]
696 #[repr(transparent)]
697 #[derive(Copy, Clone, Eq, PartialEq)]
698 pub struct Icr(pub u32);
699 impl Icr {
700 #[doc = "Tx message discard flag (TXMSGDISC) clear Setting the bit clears the TXMSGDISC flag in the SR register."]
701 #[inline(always)]
702 pub const fn txmsgdisccf(&self) -> bool {
703 let val = (self.0 >> 1usize) & 0x01;
704 val != 0
705 }
706 #[doc = "Tx message discard flag (TXMSGDISC) clear Setting the bit clears the TXMSGDISC flag in the SR register."]
707 #[inline(always)]
708 pub fn set_txmsgdisccf(&mut self, val: bool) {
709 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
710 }
711 #[doc = "Tx message send flag (TXMSGSENT) clear Setting the bit clears the TXMSGSENT flag in the SR register."]
712 #[inline(always)]
713 pub const fn txmsgsentcf(&self) -> bool {
714 let val = (self.0 >> 2usize) & 0x01;
715 val != 0
716 }
717 #[doc = "Tx message send flag (TXMSGSENT) clear Setting the bit clears the TXMSGSENT flag in the SR register."]
718 #[inline(always)]
719 pub fn set_txmsgsentcf(&mut self, val: bool) {
720 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
721 }
722 #[doc = "Tx message abort flag (TXMSGABT) clear Setting the bit clears the TXMSGABT flag in the SR register."]
723 #[inline(always)]
724 pub const fn txmsgabtcf(&self) -> bool {
725 let val = (self.0 >> 3usize) & 0x01;
726 val != 0
727 }
728 #[doc = "Tx message abort flag (TXMSGABT) clear Setting the bit clears the TXMSGABT flag in the SR register."]
729 #[inline(always)]
730 pub fn set_txmsgabtcf(&mut self, val: bool) {
731 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
732 }
733 #[doc = "Hard reset discard flag (HRSTDISC) clear Setting the bit clears the HRSTDISC flag in the SR register."]
734 #[inline(always)]
735 pub const fn hrstdisccf(&self) -> bool {
736 let val = (self.0 >> 4usize) & 0x01;
737 val != 0
738 }
739 #[doc = "Hard reset discard flag (HRSTDISC) clear Setting the bit clears the HRSTDISC flag in the SR register."]
740 #[inline(always)]
741 pub fn set_hrstdisccf(&mut self, val: bool) {
742 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
743 }
744 #[doc = "Hard reset send flag (HRSTSENT) clear Setting the bit clears the HRSTSENT flag in the SR register."]
745 #[inline(always)]
746 pub const fn hrstsentcf(&self) -> bool {
747 let val = (self.0 >> 5usize) & 0x01;
748 val != 0
749 }
750 #[doc = "Hard reset send flag (HRSTSENT) clear Setting the bit clears the HRSTSENT flag in the SR register."]
751 #[inline(always)]
752 pub fn set_hrstsentcf(&mut self, val: bool) {
753 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
754 }
755 #[doc = "Tx underflow flag (TXUND) clear Setting the bit clears the TXUND flag in the SR register."]
756 #[inline(always)]
757 pub const fn txundcf(&self) -> bool {
758 let val = (self.0 >> 6usize) & 0x01;
759 val != 0
760 }
761 #[doc = "Tx underflow flag (TXUND) clear Setting the bit clears the TXUND flag in the SR register."]
762 #[inline(always)]
763 pub fn set_txundcf(&mut self, val: bool) {
764 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
765 }
766 #[doc = "Rx ordered set detect flag (RXORDDET) clear Setting the bit clears the RXORDDET flag in the SR register."]
767 #[inline(always)]
768 pub const fn rxorddetcf(&self) -> bool {
769 let val = (self.0 >> 9usize) & 0x01;
770 val != 0
771 }
772 #[doc = "Rx ordered set detect flag (RXORDDET) clear Setting the bit clears the RXORDDET flag in the SR register."]
773 #[inline(always)]
774 pub fn set_rxorddetcf(&mut self, val: bool) {
775 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
776 }
777 #[doc = "Rx Hard Reset detect flag (RXHRSTDET) clear Setting the bit clears the RXHRSTDET flag in the SR register."]
778 #[inline(always)]
779 pub const fn rxhrstdetcf(&self) -> bool {
780 let val = (self.0 >> 10usize) & 0x01;
781 val != 0
782 }
783 #[doc = "Rx Hard Reset detect flag (RXHRSTDET) clear Setting the bit clears the RXHRSTDET flag in the SR register."]
784 #[inline(always)]
785 pub fn set_rxhrstdetcf(&mut self, val: bool) {
786 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
787 }
788 #[doc = "Rx overflow flag (RXOVR) clear Setting the bit clears the RXOVR flag in the SR register."]
789 #[inline(always)]
790 pub const fn rxovrcf(&self) -> bool {
791 let val = (self.0 >> 11usize) & 0x01;
792 val != 0
793 }
794 #[doc = "Rx overflow flag (RXOVR) clear Setting the bit clears the RXOVR flag in the SR register."]
795 #[inline(always)]
796 pub fn set_rxovrcf(&mut self, val: bool) {
797 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
798 }
799 #[doc = "Rx message received flag (RXMSGEND) clear Setting the bit clears the RXMSGEND flag in the SR register."]
800 #[inline(always)]
801 pub const fn rxmsgendcf(&self) -> bool {
802 let val = (self.0 >> 12usize) & 0x01;
803 val != 0
804 }
805 #[doc = "Rx message received flag (RXMSGEND) clear Setting the bit clears the RXMSGEND flag in the SR register."]
806 #[inline(always)]
807 pub fn set_rxmsgendcf(&mut self, val: bool) {
808 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
809 }
810 #[doc = "Type-C CC1 event flag (TYPECEVT1) clear Setting the bit clears the TYPECEVT1 flag in the SR register"]
811 #[inline(always)]
812 pub const fn typecevt1cf(&self) -> bool {
813 let val = (self.0 >> 14usize) & 0x01;
814 val != 0
815 }
816 #[doc = "Type-C CC1 event flag (TYPECEVT1) clear Setting the bit clears the TYPECEVT1 flag in the SR register"]
817 #[inline(always)]
818 pub fn set_typecevt1cf(&mut self, val: bool) {
819 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
820 }
821 #[doc = "Type-C CC2 line event flag (TYPECEVT2) clear Setting the bit clears the TYPECEVT2 flag in the SR register"]
822 #[inline(always)]
823 pub const fn typecevt2cf(&self) -> bool {
824 let val = (self.0 >> 15usize) & 0x01;
825 val != 0
826 }
827 #[doc = "Type-C CC2 line event flag (TYPECEVT2) clear Setting the bit clears the TYPECEVT2 flag in the SR register"]
828 #[inline(always)]
829 pub fn set_typecevt2cf(&mut self, val: bool) {
830 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
831 }
832 #[doc = "FRS event flag (FRSEVT) clear Setting the bit clears the FRSEVT flag in the SR register."]
833 #[inline(always)]
834 pub const fn frsevtcf(&self) -> bool {
835 let val = (self.0 >> 20usize) & 0x01;
836 val != 0
837 }
838 #[doc = "FRS event flag (FRSEVT) clear Setting the bit clears the FRSEVT flag in the SR register."]
839 #[inline(always)]
840 pub fn set_frsevtcf(&mut self, val: bool) {
841 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
842 }
843 }
844 impl Default for Icr {
845 #[inline(always)]
846 fn default() -> Icr {
847 Icr(0)
848 }
849 }
850 impl core::fmt::Debug for Icr {
851 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
852 f.debug_struct("Icr")
853 .field("txmsgdisccf", &self.txmsgdisccf())
854 .field("txmsgsentcf", &self.txmsgsentcf())
855 .field("txmsgabtcf", &self.txmsgabtcf())
856 .field("hrstdisccf", &self.hrstdisccf())
857 .field("hrstsentcf", &self.hrstsentcf())
858 .field("txundcf", &self.txundcf())
859 .field("rxorddetcf", &self.rxorddetcf())
860 .field("rxhrstdetcf", &self.rxhrstdetcf())
861 .field("rxovrcf", &self.rxovrcf())
862 .field("rxmsgendcf", &self.rxmsgendcf())
863 .field("typecevt1cf", &self.typecevt1cf())
864 .field("typecevt2cf", &self.typecevt2cf())
865 .field("frsevtcf", &self.frsevtcf())
866 .finish()
867 }
868 }
869 #[cfg(feature = "defmt")]
870 impl defmt::Format for Icr {
871 fn format(&self, f: defmt::Formatter) {
872 #[derive(defmt :: Format)]
873 struct Icr {
874 txmsgdisccf: bool,
875 txmsgsentcf: bool,
876 txmsgabtcf: bool,
877 hrstdisccf: bool,
878 hrstsentcf: bool,
879 txundcf: bool,
880 rxorddetcf: bool,
881 rxhrstdetcf: bool,
882 rxovrcf: bool,
883 rxmsgendcf: bool,
884 typecevt1cf: bool,
885 typecevt2cf: bool,
886 frsevtcf: bool,
887 }
888 let proxy = Icr {
889 txmsgdisccf: self.txmsgdisccf(),
890 txmsgsentcf: self.txmsgsentcf(),
891 txmsgabtcf: self.txmsgabtcf(),
892 hrstdisccf: self.hrstdisccf(),
893 hrstsentcf: self.hrstsentcf(),
894 txundcf: self.txundcf(),
895 rxorddetcf: self.rxorddetcf(),
896 rxhrstdetcf: self.rxhrstdetcf(),
897 rxovrcf: self.rxovrcf(),
898 rxmsgendcf: self.rxmsgendcf(),
899 typecevt1cf: self.typecevt1cf(),
900 typecevt2cf: self.typecevt2cf(),
901 frsevtcf: self.frsevtcf(),
902 };
903 defmt::write!(f, "{}", proxy)
904 }
905 }
906 #[doc = "interrupt mask register"]
907 #[repr(transparent)]
908 #[derive(Copy, Clone, Eq, PartialEq)]
909 pub struct Imr(pub u32);
910 impl Imr {
911 #[doc = "TXIS interrupt enable"]
912 #[inline(always)]
913 pub const fn txisie(&self) -> bool {
914 let val = (self.0 >> 0usize) & 0x01;
915 val != 0
916 }
917 #[doc = "TXIS interrupt enable"]
918 #[inline(always)]
919 pub fn set_txisie(&mut self, val: bool) {
920 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
921 }
922 #[doc = "TXMSGDISC interrupt enable"]
923 #[inline(always)]
924 pub const fn txmsgdiscie(&self) -> bool {
925 let val = (self.0 >> 1usize) & 0x01;
926 val != 0
927 }
928 #[doc = "TXMSGDISC interrupt enable"]
929 #[inline(always)]
930 pub fn set_txmsgdiscie(&mut self, val: bool) {
931 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
932 }
933 #[doc = "TXMSGSENT interrupt enable"]
934 #[inline(always)]
935 pub const fn txmsgsentie(&self) -> bool {
936 let val = (self.0 >> 2usize) & 0x01;
937 val != 0
938 }
939 #[doc = "TXMSGSENT interrupt enable"]
940 #[inline(always)]
941 pub fn set_txmsgsentie(&mut self, val: bool) {
942 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
943 }
944 #[doc = "TXMSGABT interrupt enable"]
945 #[inline(always)]
946 pub const fn txmsgabtie(&self) -> bool {
947 let val = (self.0 >> 3usize) & 0x01;
948 val != 0
949 }
950 #[doc = "TXMSGABT interrupt enable"]
951 #[inline(always)]
952 pub fn set_txmsgabtie(&mut self, val: bool) {
953 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
954 }
955 #[doc = "HRSTDISC interrupt enable"]
956 #[inline(always)]
957 pub const fn hrstdiscie(&self) -> bool {
958 let val = (self.0 >> 4usize) & 0x01;
959 val != 0
960 }
961 #[doc = "HRSTDISC interrupt enable"]
962 #[inline(always)]
963 pub fn set_hrstdiscie(&mut self, val: bool) {
964 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
965 }
966 #[doc = "HRSTSENT interrupt enable"]
967 #[inline(always)]
968 pub const fn hrstsentie(&self) -> bool {
969 let val = (self.0 >> 5usize) & 0x01;
970 val != 0
971 }
972 #[doc = "HRSTSENT interrupt enable"]
973 #[inline(always)]
974 pub fn set_hrstsentie(&mut self, val: bool) {
975 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
976 }
977 #[doc = "TXUND interrupt enable"]
978 #[inline(always)]
979 pub const fn txundie(&self) -> bool {
980 let val = (self.0 >> 6usize) & 0x01;
981 val != 0
982 }
983 #[doc = "TXUND interrupt enable"]
984 #[inline(always)]
985 pub fn set_txundie(&mut self, val: bool) {
986 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
987 }
988 #[doc = "RXNE interrupt enable"]
989 #[inline(always)]
990 pub const fn rxneie(&self) -> bool {
991 let val = (self.0 >> 8usize) & 0x01;
992 val != 0
993 }
994 #[doc = "RXNE interrupt enable"]
995 #[inline(always)]
996 pub fn set_rxneie(&mut self, val: bool) {
997 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
998 }
999 #[doc = "RXORDDET interrupt enable"]
1000 #[inline(always)]
1001 pub const fn rxorddetie(&self) -> bool {
1002 let val = (self.0 >> 9usize) & 0x01;
1003 val != 0
1004 }
1005 #[doc = "RXORDDET interrupt enable"]
1006 #[inline(always)]
1007 pub fn set_rxorddetie(&mut self, val: bool) {
1008 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
1009 }
1010 #[doc = "RXHRSTDET interrupt enable"]
1011 #[inline(always)]
1012 pub const fn rxhrstdetie(&self) -> bool {
1013 let val = (self.0 >> 10usize) & 0x01;
1014 val != 0
1015 }
1016 #[doc = "RXHRSTDET interrupt enable"]
1017 #[inline(always)]
1018 pub fn set_rxhrstdetie(&mut self, val: bool) {
1019 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
1020 }
1021 #[doc = "RXOVR interrupt enable"]
1022 #[inline(always)]
1023 pub const fn rxovrie(&self) -> bool {
1024 let val = (self.0 >> 11usize) & 0x01;
1025 val != 0
1026 }
1027 #[doc = "RXOVR interrupt enable"]
1028 #[inline(always)]
1029 pub fn set_rxovrie(&mut self, val: bool) {
1030 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
1031 }
1032 #[doc = "RXMSGEND interrupt enable"]
1033 #[inline(always)]
1034 pub const fn rxmsgendie(&self) -> bool {
1035 let val = (self.0 >> 12usize) & 0x01;
1036 val != 0
1037 }
1038 #[doc = "RXMSGEND interrupt enable"]
1039 #[inline(always)]
1040 pub fn set_rxmsgendie(&mut self, val: bool) {
1041 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
1042 }
1043 #[doc = "TYPECEVT1 interrupt enable"]
1044 #[inline(always)]
1045 pub const fn typecevt1ie(&self) -> bool {
1046 let val = (self.0 >> 14usize) & 0x01;
1047 val != 0
1048 }
1049 #[doc = "TYPECEVT1 interrupt enable"]
1050 #[inline(always)]
1051 pub fn set_typecevt1ie(&mut self, val: bool) {
1052 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
1053 }
1054 #[doc = "TYPECEVT2 interrupt enable"]
1055 #[inline(always)]
1056 pub const fn typecevt2ie(&self) -> bool {
1057 let val = (self.0 >> 15usize) & 0x01;
1058 val != 0
1059 }
1060 #[doc = "TYPECEVT2 interrupt enable"]
1061 #[inline(always)]
1062 pub fn set_typecevt2ie(&mut self, val: bool) {
1063 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
1064 }
1065 #[doc = "FRSEVT interrupt enable"]
1066 #[inline(always)]
1067 pub const fn frsevtie(&self) -> bool {
1068 let val = (self.0 >> 20usize) & 0x01;
1069 val != 0
1070 }
1071 #[doc = "FRSEVT interrupt enable"]
1072 #[inline(always)]
1073 pub fn set_frsevtie(&mut self, val: bool) {
1074 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
1075 }
1076 }
1077 impl Default for Imr {
1078 #[inline(always)]
1079 fn default() -> Imr {
1080 Imr(0)
1081 }
1082 }
1083 impl core::fmt::Debug for Imr {
1084 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1085 f.debug_struct("Imr")
1086 .field("txisie", &self.txisie())
1087 .field("txmsgdiscie", &self.txmsgdiscie())
1088 .field("txmsgsentie", &self.txmsgsentie())
1089 .field("txmsgabtie", &self.txmsgabtie())
1090 .field("hrstdiscie", &self.hrstdiscie())
1091 .field("hrstsentie", &self.hrstsentie())
1092 .field("txundie", &self.txundie())
1093 .field("rxneie", &self.rxneie())
1094 .field("rxorddetie", &self.rxorddetie())
1095 .field("rxhrstdetie", &self.rxhrstdetie())
1096 .field("rxovrie", &self.rxovrie())
1097 .field("rxmsgendie", &self.rxmsgendie())
1098 .field("typecevt1ie", &self.typecevt1ie())
1099 .field("typecevt2ie", &self.typecevt2ie())
1100 .field("frsevtie", &self.frsevtie())
1101 .finish()
1102 }
1103 }
1104 #[cfg(feature = "defmt")]
1105 impl defmt::Format for Imr {
1106 fn format(&self, f: defmt::Formatter) {
1107 #[derive(defmt :: Format)]
1108 struct Imr {
1109 txisie: bool,
1110 txmsgdiscie: bool,
1111 txmsgsentie: bool,
1112 txmsgabtie: bool,
1113 hrstdiscie: bool,
1114 hrstsentie: bool,
1115 txundie: bool,
1116 rxneie: bool,
1117 rxorddetie: bool,
1118 rxhrstdetie: bool,
1119 rxovrie: bool,
1120 rxmsgendie: bool,
1121 typecevt1ie: bool,
1122 typecevt2ie: bool,
1123 frsevtie: bool,
1124 }
1125 let proxy = Imr {
1126 txisie: self.txisie(),
1127 txmsgdiscie: self.txmsgdiscie(),
1128 txmsgsentie: self.txmsgsentie(),
1129 txmsgabtie: self.txmsgabtie(),
1130 hrstdiscie: self.hrstdiscie(),
1131 hrstsentie: self.hrstsentie(),
1132 txundie: self.txundie(),
1133 rxneie: self.rxneie(),
1134 rxorddetie: self.rxorddetie(),
1135 rxhrstdetie: self.rxhrstdetie(),
1136 rxovrie: self.rxovrie(),
1137 rxmsgendie: self.rxmsgendie(),
1138 typecevt1ie: self.typecevt1ie(),
1139 typecevt2ie: self.typecevt2ie(),
1140 frsevtie: self.frsevtie(),
1141 };
1142 defmt::write!(f, "{}", proxy)
1143 }
1144 }
1145 #[doc = "UCPD IP ID register"]
1146 #[repr(transparent)]
1147 #[derive(Copy, Clone, Eq, PartialEq)]
1148 pub struct Ipid(pub u32);
1149 impl Ipid {
1150 #[doc = "IPID"]
1151 #[inline(always)]
1152 pub const fn ipid(&self) -> u32 {
1153 let val = (self.0 >> 0usize) & 0xffff_ffff;
1154 val as u32
1155 }
1156 #[doc = "IPID"]
1157 #[inline(always)]
1158 pub fn set_ipid(&mut self, val: u32) {
1159 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1160 }
1161 }
1162 impl Default for Ipid {
1163 #[inline(always)]
1164 fn default() -> Ipid {
1165 Ipid(0)
1166 }
1167 }
1168 impl core::fmt::Debug for Ipid {
1169 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1170 f.debug_struct("Ipid").field("ipid", &self.ipid()).finish()
1171 }
1172 }
1173 #[cfg(feature = "defmt")]
1174 impl defmt::Format for Ipid {
1175 fn format(&self, f: defmt::Formatter) {
1176 #[derive(defmt :: Format)]
1177 struct Ipid {
1178 ipid: u32,
1179 }
1180 let proxy = Ipid { ipid: self.ipid() };
1181 defmt::write!(f, "{}", proxy)
1182 }
1183 }
1184 #[doc = "UCPD IP ID register"]
1185 #[repr(transparent)]
1186 #[derive(Copy, Clone, Eq, PartialEq)]
1187 pub struct Ipver(pub u32);
1188 impl Ipver {
1189 #[doc = "IPVER"]
1190 #[inline(always)]
1191 pub const fn ipver(&self) -> u32 {
1192 let val = (self.0 >> 0usize) & 0xffff_ffff;
1193 val as u32
1194 }
1195 #[doc = "IPVER"]
1196 #[inline(always)]
1197 pub fn set_ipver(&mut self, val: u32) {
1198 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1199 }
1200 }
1201 impl Default for Ipver {
1202 #[inline(always)]
1203 fn default() -> Ipver {
1204 Ipver(0)
1205 }
1206 }
1207 impl core::fmt::Debug for Ipver {
1208 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1209 f.debug_struct("Ipver").field("ipver", &self.ipver()).finish()
1210 }
1211 }
1212 #[cfg(feature = "defmt")]
1213 impl defmt::Format for Ipver {
1214 fn format(&self, f: defmt::Formatter) {
1215 #[derive(defmt :: Format)]
1216 struct Ipver {
1217 ipver: u32,
1218 }
1219 let proxy = Ipver { ipver: self.ipver() };
1220 defmt::write!(f, "{}", proxy)
1221 }
1222 }
1223 #[doc = "UCPD IP ID register"]
1224 #[repr(transparent)]
1225 #[derive(Copy, Clone, Eq, PartialEq)]
1226 pub struct Mid(pub u32);
1227 impl Mid {
1228 #[doc = "IPID"]
1229 #[inline(always)]
1230 pub const fn ipid(&self) -> u32 {
1231 let val = (self.0 >> 0usize) & 0xffff_ffff;
1232 val as u32
1233 }
1234 #[doc = "IPID"]
1235 #[inline(always)]
1236 pub fn set_ipid(&mut self, val: u32) {
1237 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1238 }
1239 }
1240 impl Default for Mid {
1241 #[inline(always)]
1242 fn default() -> Mid {
1243 Mid(0)
1244 }
1245 }
1246 impl core::fmt::Debug for Mid {
1247 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1248 f.debug_struct("Mid").field("ipid", &self.ipid()).finish()
1249 }
1250 }
1251 #[cfg(feature = "defmt")]
1252 impl defmt::Format for Mid {
1253 fn format(&self, f: defmt::Formatter) {
1254 #[derive(defmt :: Format)]
1255 struct Mid {
1256 ipid: u32,
1257 }
1258 let proxy = Mid { ipid: self.ipid() };
1259 defmt::write!(f, "{}", proxy)
1260 }
1261 }
1262 #[doc = "Rx ordered set extension register 1"]
1263 #[repr(transparent)]
1264 #[derive(Copy, Clone, Eq, PartialEq)]
1265 pub struct RxOrdextr1(pub u32);
1266 impl RxOrdextr1 {
1267 #[doc = "Ordered set 1 received The bitfield contains a full 20-bit sequence received, consisting of four K‑codes, each of five bits. The bit 0 (bit 0 of K‑code1) is receive first, the bit 19 (bit 4 of K‑code4) last."]
1268 #[inline(always)]
1269 pub const fn rxsopx1(&self) -> u32 {
1270 let val = (self.0 >> 0usize) & 0x000f_ffff;
1271 val as u32
1272 }
1273 #[doc = "Ordered set 1 received The bitfield contains a full 20-bit sequence received, consisting of four K‑codes, each of five bits. The bit 0 (bit 0 of K‑code1) is receive first, the bit 19 (bit 4 of K‑code4) last."]
1274 #[inline(always)]
1275 pub fn set_rxsopx1(&mut self, val: u32) {
1276 self.0 = (self.0 & !(0x000f_ffff << 0usize)) | (((val as u32) & 0x000f_ffff) << 0usize);
1277 }
1278 }
1279 impl Default for RxOrdextr1 {
1280 #[inline(always)]
1281 fn default() -> RxOrdextr1 {
1282 RxOrdextr1(0)
1283 }
1284 }
1285 impl core::fmt::Debug for RxOrdextr1 {
1286 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1287 f.debug_struct("RxOrdextr1").field("rxsopx1", &self.rxsopx1()).finish()
1288 }
1289 }
1290 #[cfg(feature = "defmt")]
1291 impl defmt::Format for RxOrdextr1 {
1292 fn format(&self, f: defmt::Formatter) {
1293 #[derive(defmt :: Format)]
1294 struct RxOrdextr1 {
1295 rxsopx1: u32,
1296 }
1297 let proxy = RxOrdextr1 {
1298 rxsopx1: self.rxsopx1(),
1299 };
1300 defmt::write!(f, "{}", proxy)
1301 }
1302 }
1303 #[doc = "Rx ordered set extension register 2"]
1304 #[repr(transparent)]
1305 #[derive(Copy, Clone, Eq, PartialEq)]
1306 pub struct RxOrdextr2(pub u32);
1307 impl RxOrdextr2 {
1308 #[doc = "Ordered set 2 received The bitfield contains a full 20-bit sequence received, consisting of four K‑codes, each of five bits. The bit 0 (bit 0 of K‑code1) is receive first, the bit 19 (bit 4 of K‑code4) last."]
1309 #[inline(always)]
1310 pub const fn rxsopx2(&self) -> u32 {
1311 let val = (self.0 >> 0usize) & 0x000f_ffff;
1312 val as u32
1313 }
1314 #[doc = "Ordered set 2 received The bitfield contains a full 20-bit sequence received, consisting of four K‑codes, each of five bits. The bit 0 (bit 0 of K‑code1) is receive first, the bit 19 (bit 4 of K‑code4) last."]
1315 #[inline(always)]
1316 pub fn set_rxsopx2(&mut self, val: u32) {
1317 self.0 = (self.0 & !(0x000f_ffff << 0usize)) | (((val as u32) & 0x000f_ffff) << 0usize);
1318 }
1319 }
1320 impl Default for RxOrdextr2 {
1321 #[inline(always)]
1322 fn default() -> RxOrdextr2 {
1323 RxOrdextr2(0)
1324 }
1325 }
1326 impl core::fmt::Debug for RxOrdextr2 {
1327 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1328 f.debug_struct("RxOrdextr2").field("rxsopx2", &self.rxsopx2()).finish()
1329 }
1330 }
1331 #[cfg(feature = "defmt")]
1332 impl defmt::Format for RxOrdextr2 {
1333 fn format(&self, f: defmt::Formatter) {
1334 #[derive(defmt :: Format)]
1335 struct RxOrdextr2 {
1336 rxsopx2: u32,
1337 }
1338 let proxy = RxOrdextr2 {
1339 rxsopx2: self.rxsopx2(),
1340 };
1341 defmt::write!(f, "{}", proxy)
1342 }
1343 }
1344 #[repr(transparent)]
1345 #[derive(Copy, Clone, Eq, PartialEq)]
1346 pub struct RxOrdsetr(pub u32);
1347 impl RxOrdsetr {
1348 #[doc = "Rx ordered set code detected"]
1349 #[inline(always)]
1350 pub const fn rxordset(&self) -> super::vals::Rxordset {
1351 let val = (self.0 >> 0usize) & 0x07;
1352 super::vals::Rxordset::from_bits(val as u8)
1353 }
1354 #[doc = "Rx ordered set code detected"]
1355 #[inline(always)]
1356 pub fn set_rxordset(&mut self, val: super::vals::Rxordset) {
1357 self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize);
1358 }
1359 #[doc = "The bit indicates the number of correct K‑codes. For debug purposes only."]
1360 #[inline(always)]
1361 pub const fn rxsop3of4(&self) -> bool {
1362 let val = (self.0 >> 3usize) & 0x01;
1363 val != 0
1364 }
1365 #[doc = "The bit indicates the number of correct K‑codes. For debug purposes only."]
1366 #[inline(always)]
1367 pub fn set_rxsop3of4(&mut self, val: bool) {
1368 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1369 }
1370 #[doc = "The bitfield is for debug purposes only. Others: Invalid"]
1371 #[inline(always)]
1372 pub const fn rxsopkinvalid(&self) -> super::vals::Rxsopkinvalid {
1373 let val = (self.0 >> 4usize) & 0x07;
1374 super::vals::Rxsopkinvalid::from_bits(val as u8)
1375 }
1376 #[doc = "The bitfield is for debug purposes only. Others: Invalid"]
1377 #[inline(always)]
1378 pub fn set_rxsopkinvalid(&mut self, val: super::vals::Rxsopkinvalid) {
1379 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32) & 0x07) << 4usize);
1380 }
1381 }
1382 impl Default for RxOrdsetr {
1383 #[inline(always)]
1384 fn default() -> RxOrdsetr {
1385 RxOrdsetr(0)
1386 }
1387 }
1388 impl core::fmt::Debug for RxOrdsetr {
1389 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1390 f.debug_struct("RxOrdsetr")
1391 .field("rxordset", &self.rxordset())
1392 .field("rxsop3of4", &self.rxsop3of4())
1393 .field("rxsopkinvalid", &self.rxsopkinvalid())
1394 .finish()
1395 }
1396 }
1397 #[cfg(feature = "defmt")]
1398 impl defmt::Format for RxOrdsetr {
1399 fn format(&self, f: defmt::Formatter) {
1400 #[derive(defmt :: Format)]
1401 struct RxOrdsetr {
1402 rxordset: super::vals::Rxordset,
1403 rxsop3of4: bool,
1404 rxsopkinvalid: super::vals::Rxsopkinvalid,
1405 }
1406 let proxy = RxOrdsetr {
1407 rxordset: self.rxordset(),
1408 rxsop3of4: self.rxsop3of4(),
1409 rxsopkinvalid: self.rxsopkinvalid(),
1410 };
1411 defmt::write!(f, "{}", proxy)
1412 }
1413 }
1414 #[repr(transparent)]
1415 #[derive(Copy, Clone, Eq, PartialEq)]
1416 pub struct RxPayszr(pub u32);
1417 impl RxPayszr {
1418 #[doc = "Rx payload size received This bitfield contains the number of bytes of a payload (including header but excluding CRC) received: each time a new data byte is received in the RXDR register, the bitfield value increments and the RXMSGEND flag is set (and an interrupt generated if enabled). The bitfield may return a spurious value when a byte reception is ongoing (the RXMSGEND flag is low)."]
1419 #[inline(always)]
1420 pub const fn rxpaysz(&self) -> u16 {
1421 let val = (self.0 >> 0usize) & 0x03ff;
1422 val as u16
1423 }
1424 #[doc = "Rx payload size received This bitfield contains the number of bytes of a payload (including header but excluding CRC) received: each time a new data byte is received in the RXDR register, the bitfield value increments and the RXMSGEND flag is set (and an interrupt generated if enabled). The bitfield may return a spurious value when a byte reception is ongoing (the RXMSGEND flag is low)."]
1425 #[inline(always)]
1426 pub fn set_rxpaysz(&mut self, val: u16) {
1427 self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize);
1428 }
1429 }
1430 impl Default for RxPayszr {
1431 #[inline(always)]
1432 fn default() -> RxPayszr {
1433 RxPayszr(0)
1434 }
1435 }
1436 impl core::fmt::Debug for RxPayszr {
1437 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1438 f.debug_struct("RxPayszr").field("rxpaysz", &self.rxpaysz()).finish()
1439 }
1440 }
1441 #[cfg(feature = "defmt")]
1442 impl defmt::Format for RxPayszr {
1443 fn format(&self, f: defmt::Formatter) {
1444 #[derive(defmt :: Format)]
1445 struct RxPayszr {
1446 rxpaysz: u16,
1447 }
1448 let proxy = RxPayszr {
1449 rxpaysz: self.rxpaysz(),
1450 };
1451 defmt::write!(f, "{}", proxy)
1452 }
1453 }
1454 #[repr(transparent)]
1455 #[derive(Copy, Clone, Eq, PartialEq)]
1456 pub struct Rxdr(pub u32);
1457 impl Rxdr {
1458 #[doc = "Data byte received"]
1459 #[inline(always)]
1460 pub const fn rxdata(&self) -> u8 {
1461 let val = (self.0 >> 0usize) & 0xff;
1462 val as u8
1463 }
1464 #[doc = "Data byte received"]
1465 #[inline(always)]
1466 pub fn set_rxdata(&mut self, val: u8) {
1467 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
1468 }
1469 }
1470 impl Default for Rxdr {
1471 #[inline(always)]
1472 fn default() -> Rxdr {
1473 Rxdr(0)
1474 }
1475 }
1476 impl core::fmt::Debug for Rxdr {
1477 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1478 f.debug_struct("Rxdr").field("rxdata", &self.rxdata()).finish()
1479 }
1480 }
1481 #[cfg(feature = "defmt")]
1482 impl defmt::Format for Rxdr {
1483 fn format(&self, f: defmt::Formatter) {
1484 #[derive(defmt :: Format)]
1485 struct Rxdr {
1486 rxdata: u8,
1487 }
1488 let proxy = Rxdr { rxdata: self.rxdata() };
1489 defmt::write!(f, "{}", proxy)
1490 }
1491 }
1492 #[doc = "status register"]
1493 #[repr(transparent)]
1494 #[derive(Copy, Clone, Eq, PartialEq)]
1495 pub struct Sr(pub u32);
1496 impl Sr {
1497 #[doc = "Transmit interrupt status The flag indicates that the TXDR register is empty and new data write is required (as the amount of data sent has not reached the payload size defined in the TXPAYSZ bitfield). The flag is cleared with the data write into the TXDR register."]
1498 #[inline(always)]
1499 pub const fn txis(&self) -> bool {
1500 let val = (self.0 >> 0usize) & 0x01;
1501 val != 0
1502 }
1503 #[doc = "Transmit interrupt status The flag indicates that the TXDR register is empty and new data write is required (as the amount of data sent has not reached the payload size defined in the TXPAYSZ bitfield). The flag is cleared with the data write into the TXDR register."]
1504 #[inline(always)]
1505 pub fn set_txis(&mut self, val: bool) {
1506 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1507 }
1508 #[doc = "Message transmission discarded The flag indicates that a message transmission was dropped. The flag is cleared by setting the TXMSGDISCCF bit. Transmission of a message can be dropped if there is a concurrent receive in progress or at excessive noise on the line. After a Tx message is discarded, the flag is only raised when the CC line becomes idle."]
1509 #[inline(always)]
1510 pub const fn txmsgdisc(&self) -> bool {
1511 let val = (self.0 >> 1usize) & 0x01;
1512 val != 0
1513 }
1514 #[doc = "Message transmission discarded The flag indicates that a message transmission was dropped. The flag is cleared by setting the TXMSGDISCCF bit. Transmission of a message can be dropped if there is a concurrent receive in progress or at excessive noise on the line. After a Tx message is discarded, the flag is only raised when the CC line becomes idle."]
1515 #[inline(always)]
1516 pub fn set_txmsgdisc(&mut self, val: bool) {
1517 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1518 }
1519 #[doc = "Message transmission completed The flag indicates the completion of packet transmission. It is cleared by setting the TXMSGSENTCF bit. In the event of a message transmission interrupted by a Hard Reset, the flag is not raised."]
1520 #[inline(always)]
1521 pub const fn txmsgsent(&self) -> bool {
1522 let val = (self.0 >> 2usize) & 0x01;
1523 val != 0
1524 }
1525 #[doc = "Message transmission completed The flag indicates the completion of packet transmission. It is cleared by setting the TXMSGSENTCF bit. In the event of a message transmission interrupted by a Hard Reset, the flag is not raised."]
1526 #[inline(always)]
1527 pub fn set_txmsgsent(&mut self, val: bool) {
1528 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1529 }
1530 #[doc = "Transmit message abort The flag indicates that a Tx message is aborted due to a subsequent Hard Reset message send request taking priority during transmit. It is cleared by setting the TXMSGABTCF bit."]
1531 #[inline(always)]
1532 pub const fn txmsgabt(&self) -> bool {
1533 let val = (self.0 >> 3usize) & 0x01;
1534 val != 0
1535 }
1536 #[doc = "Transmit message abort The flag indicates that a Tx message is aborted due to a subsequent Hard Reset message send request taking priority during transmit. It is cleared by setting the TXMSGABTCF bit."]
1537 #[inline(always)]
1538 pub fn set_txmsgabt(&mut self, val: bool) {
1539 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1540 }
1541 #[doc = "Hard Reset discarded The flag indicates that the Hard Reset message is discarded. The flag is cleared by setting the HRSTDISCCF bit."]
1542 #[inline(always)]
1543 pub const fn hrstdisc(&self) -> bool {
1544 let val = (self.0 >> 4usize) & 0x01;
1545 val != 0
1546 }
1547 #[doc = "Hard Reset discarded The flag indicates that the Hard Reset message is discarded. The flag is cleared by setting the HRSTDISCCF bit."]
1548 #[inline(always)]
1549 pub fn set_hrstdisc(&mut self, val: bool) {
1550 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1551 }
1552 #[doc = "Hard Reset message sent The flag indicates that the Hard Reset message is sent. The flag is cleared by setting the HRSTSENTCF bit."]
1553 #[inline(always)]
1554 pub const fn hrstsent(&self) -> bool {
1555 let val = (self.0 >> 5usize) & 0x01;
1556 val != 0
1557 }
1558 #[doc = "Hard Reset message sent The flag indicates that the Hard Reset message is sent. The flag is cleared by setting the HRSTSENTCF bit."]
1559 #[inline(always)]
1560 pub fn set_hrstsent(&mut self, val: bool) {
1561 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
1562 }
1563 #[doc = "Tx data underrun detection The flag indicates that the Tx data register (TXDR) was not written in time for a transmit message to execute normally. It is cleared by setting the TXUNDCF bit."]
1564 #[inline(always)]
1565 pub const fn txund(&self) -> bool {
1566 let val = (self.0 >> 6usize) & 0x01;
1567 val != 0
1568 }
1569 #[doc = "Tx data underrun detection The flag indicates that the Tx data register (TXDR) was not written in time for a transmit message to execute normally. It is cleared by setting the TXUNDCF bit."]
1570 #[inline(always)]
1571 pub fn set_txund(&mut self, val: bool) {
1572 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
1573 }
1574 #[doc = "Receive data register not empty detection The flag indicates that the RXDR register is not empty. It is automatically cleared upon reading RXDR."]
1575 #[inline(always)]
1576 pub const fn rxne(&self) -> bool {
1577 let val = (self.0 >> 8usize) & 0x01;
1578 val != 0
1579 }
1580 #[doc = "Receive data register not empty detection The flag indicates that the RXDR register is not empty. It is automatically cleared upon reading RXDR."]
1581 #[inline(always)]
1582 pub fn set_rxne(&mut self, val: bool) {
1583 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
1584 }
1585 #[doc = "Rx ordered set (4 K-codes) detection The flag indicates the detection of an ordered set. The relevant information is stored in the RXORDSET\\[2:0\\]
1586bitfield of the RX_ORDSET register. It is cleared by setting the RXORDDETCF bit."]
1587 #[inline(always)]
1588 pub const fn rxorddet(&self) -> bool {
1589 let val = (self.0 >> 9usize) & 0x01;
1590 val != 0
1591 }
1592 #[doc = "Rx ordered set (4 K-codes) detection The flag indicates the detection of an ordered set. The relevant information is stored in the RXORDSET\\[2:0\\]
1593bitfield of the RX_ORDSET register. It is cleared by setting the RXORDDETCF bit."]
1594 #[inline(always)]
1595 pub fn set_rxorddet(&mut self, val: bool) {
1596 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
1597 }
1598 #[doc = "Rx Hard Reset receipt detection The flag indicates the receipt of valid Hard Reset message. It is cleared by setting the RXHRSTDETCF bit."]
1599 #[inline(always)]
1600 pub const fn rxhrstdet(&self) -> bool {
1601 let val = (self.0 >> 10usize) & 0x01;
1602 val != 0
1603 }
1604 #[doc = "Rx Hard Reset receipt detection The flag indicates the receipt of valid Hard Reset message. It is cleared by setting the RXHRSTDETCF bit."]
1605 #[inline(always)]
1606 pub fn set_rxhrstdet(&mut self, val: bool) {
1607 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
1608 }
1609 #[doc = "Rx data overflow detection The flag indicates Rx data buffer overflow. It is cleared by setting the RXOVRCF bit. The buffer overflow can occur if the received data are not read fast enough."]
1610 #[inline(always)]
1611 pub const fn rxovr(&self) -> bool {
1612 let val = (self.0 >> 11usize) & 0x01;
1613 val != 0
1614 }
1615 #[doc = "Rx data overflow detection The flag indicates Rx data buffer overflow. It is cleared by setting the RXOVRCF bit. The buffer overflow can occur if the received data are not read fast enough."]
1616 #[inline(always)]
1617 pub fn set_rxovr(&mut self, val: bool) {
1618 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
1619 }
1620 #[doc = "Rx message received The flag indicates whether a message (except Hard Reset message) has been received, regardless the CRC value. The flag is cleared by setting the RXMSGENDCF bit. The RXERR flag set when the RXMSGEND flag goes high indicates errors in the last-received message."]
1621 #[inline(always)]
1622 pub const fn rxmsgend(&self) -> bool {
1623 let val = (self.0 >> 12usize) & 0x01;
1624 val != 0
1625 }
1626 #[doc = "Rx message received The flag indicates whether a message (except Hard Reset message) has been received, regardless the CRC value. The flag is cleared by setting the RXMSGENDCF bit. The RXERR flag set when the RXMSGEND flag goes high indicates errors in the last-received message."]
1627 #[inline(always)]
1628 pub fn set_rxmsgend(&mut self, val: bool) {
1629 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
1630 }
1631 #[doc = "Receive message error The flag indicates errors of the last Rx message declared (via RXMSGEND), such as incorrect CRC or truncated message (a line becoming static before EOP is met). It is asserted whenever the RXMSGEND flag is set."]
1632 #[inline(always)]
1633 pub const fn rxerr(&self) -> bool {
1634 let val = (self.0 >> 13usize) & 0x01;
1635 val != 0
1636 }
1637 #[doc = "Receive message error The flag indicates errors of the last Rx message declared (via RXMSGEND), such as incorrect CRC or truncated message (a line becoming static before EOP is met). It is asserted whenever the RXMSGEND flag is set."]
1638 #[inline(always)]
1639 pub fn set_rxerr(&mut self, val: bool) {
1640 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
1641 }
1642 #[doc = "Type-C voltage level event on CC1 line The flag indicates a change of the TYPEC_VSTATE_CC1\\[1:0\\]
1643bitfield value, which corresponds to a new Type-C event. It is cleared by setting the TYPECEVT2CF bit."]
1644 #[inline(always)]
1645 pub const fn typecevt1(&self) -> bool {
1646 let val = (self.0 >> 14usize) & 0x01;
1647 val != 0
1648 }
1649 #[doc = "Type-C voltage level event on CC1 line The flag indicates a change of the TYPEC_VSTATE_CC1\\[1:0\\]
1650bitfield value, which corresponds to a new Type-C event. It is cleared by setting the TYPECEVT2CF bit."]
1651 #[inline(always)]
1652 pub fn set_typecevt1(&mut self, val: bool) {
1653 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
1654 }
1655 #[doc = "Type-C voltage level event on CC2 line The flag indicates a change of the TYPEC_VSTATE_CC2\\[1:0\\]
1656bitfield value, which corresponds to a new Type-C event. It is cleared by setting the TYPECEVT2CF bit."]
1657 #[inline(always)]
1658 pub const fn typecevt2(&self) -> bool {
1659 let val = (self.0 >> 15usize) & 0x01;
1660 val != 0
1661 }
1662 #[doc = "Type-C voltage level event on CC2 line The flag indicates a change of the TYPEC_VSTATE_CC2\\[1:0\\]
1663bitfield value, which corresponds to a new Type-C event. It is cleared by setting the TYPECEVT2CF bit."]
1664 #[inline(always)]
1665 pub fn set_typecevt2(&mut self, val: bool) {
1666 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
1667 }
1668 #[doc = "The status bitfield indicates the voltage level on the CC1 line in its steady state. The voltage variation on the CC1 line during USB PD messages due to the BMC PHY modulation does not impact the bitfield value."]
1669 #[inline(always)]
1670 pub const fn typec_vstate_cc1(&self) -> super::vals::TypecVstateCc {
1671 let val = (self.0 >> 16usize) & 0x03;
1672 super::vals::TypecVstateCc::from_bits(val as u8)
1673 }
1674 #[doc = "The status bitfield indicates the voltage level on the CC1 line in its steady state. The voltage variation on the CC1 line during USB PD messages due to the BMC PHY modulation does not impact the bitfield value."]
1675 #[inline(always)]
1676 pub fn set_typec_vstate_cc1(&mut self, val: super::vals::TypecVstateCc) {
1677 self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize);
1678 }
1679 #[doc = "CC2 line voltage level The status bitfield indicates the voltage level on the CC2 line in its steady state. The voltage variation on the CC2 line during USB PD messages due to the BMC PHY modulation does not impact the bitfield value."]
1680 #[inline(always)]
1681 pub const fn typec_vstate_cc2(&self) -> super::vals::TypecVstateCc {
1682 let val = (self.0 >> 18usize) & 0x03;
1683 super::vals::TypecVstateCc::from_bits(val as u8)
1684 }
1685 #[doc = "CC2 line voltage level The status bitfield indicates the voltage level on the CC2 line in its steady state. The voltage variation on the CC2 line during USB PD messages due to the BMC PHY modulation does not impact the bitfield value."]
1686 #[inline(always)]
1687 pub fn set_typec_vstate_cc2(&mut self, val: super::vals::TypecVstateCc) {
1688 self.0 = (self.0 & !(0x03 << 18usize)) | (((val.to_bits() as u32) & 0x03) << 18usize);
1689 }
1690 #[doc = "FRS detection event The flag is cleared by setting the FRSEVTCF bit."]
1691 #[inline(always)]
1692 pub const fn frsevt(&self) -> bool {
1693 let val = (self.0 >> 20usize) & 0x01;
1694 val != 0
1695 }
1696 #[doc = "FRS detection event The flag is cleared by setting the FRSEVTCF bit."]
1697 #[inline(always)]
1698 pub fn set_frsevt(&mut self, val: bool) {
1699 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
1700 }
1701 }
1702 impl Default for Sr {
1703 #[inline(always)]
1704 fn default() -> Sr {
1705 Sr(0)
1706 }
1707 }
1708 impl core::fmt::Debug for Sr {
1709 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1710 f.debug_struct("Sr")
1711 .field("txis", &self.txis())
1712 .field("txmsgdisc", &self.txmsgdisc())
1713 .field("txmsgsent", &self.txmsgsent())
1714 .field("txmsgabt", &self.txmsgabt())
1715 .field("hrstdisc", &self.hrstdisc())
1716 .field("hrstsent", &self.hrstsent())
1717 .field("txund", &self.txund())
1718 .field("rxne", &self.rxne())
1719 .field("rxorddet", &self.rxorddet())
1720 .field("rxhrstdet", &self.rxhrstdet())
1721 .field("rxovr", &self.rxovr())
1722 .field("rxmsgend", &self.rxmsgend())
1723 .field("rxerr", &self.rxerr())
1724 .field("typecevt1", &self.typecevt1())
1725 .field("typecevt2", &self.typecevt2())
1726 .field("typec_vstate_cc1", &self.typec_vstate_cc1())
1727 .field("typec_vstate_cc2", &self.typec_vstate_cc2())
1728 .field("frsevt", &self.frsevt())
1729 .finish()
1730 }
1731 }
1732 #[cfg(feature = "defmt")]
1733 impl defmt::Format for Sr {
1734 fn format(&self, f: defmt::Formatter) {
1735 #[derive(defmt :: Format)]
1736 struct Sr {
1737 txis: bool,
1738 txmsgdisc: bool,
1739 txmsgsent: bool,
1740 txmsgabt: bool,
1741 hrstdisc: bool,
1742 hrstsent: bool,
1743 txund: bool,
1744 rxne: bool,
1745 rxorddet: bool,
1746 rxhrstdet: bool,
1747 rxovr: bool,
1748 rxmsgend: bool,
1749 rxerr: bool,
1750 typecevt1: bool,
1751 typecevt2: bool,
1752 typec_vstate_cc1: super::vals::TypecVstateCc,
1753 typec_vstate_cc2: super::vals::TypecVstateCc,
1754 frsevt: bool,
1755 }
1756 let proxy = Sr {
1757 txis: self.txis(),
1758 txmsgdisc: self.txmsgdisc(),
1759 txmsgsent: self.txmsgsent(),
1760 txmsgabt: self.txmsgabt(),
1761 hrstdisc: self.hrstdisc(),
1762 hrstsent: self.hrstsent(),
1763 txund: self.txund(),
1764 rxne: self.rxne(),
1765 rxorddet: self.rxorddet(),
1766 rxhrstdet: self.rxhrstdet(),
1767 rxovr: self.rxovr(),
1768 rxmsgend: self.rxmsgend(),
1769 rxerr: self.rxerr(),
1770 typecevt1: self.typecevt1(),
1771 typecevt2: self.typecevt2(),
1772 typec_vstate_cc1: self.typec_vstate_cc1(),
1773 typec_vstate_cc2: self.typec_vstate_cc2(),
1774 frsevt: self.frsevt(),
1775 };
1776 defmt::write!(f, "{}", proxy)
1777 }
1778 }
1779 #[doc = "Tx ordered set type register"]
1780 #[repr(transparent)]
1781 #[derive(Copy, Clone, Eq, PartialEq)]
1782 pub struct TxOrdsetr(pub u32);
1783 impl TxOrdsetr {
1784 #[doc = "Ordered set to transmit The bitfield determines a full 20-bit sequence to transmit, consisting of four K-codes, each of five bits, defining the packet to transmit. The bit 0 (bit 0 of K-code1) is the first, the bit 19 (bit 4 of K‑code4) the last."]
1785 #[inline(always)]
1786 pub const fn txordset(&self) -> u32 {
1787 let val = (self.0 >> 0usize) & 0x000f_ffff;
1788 val as u32
1789 }
1790 #[doc = "Ordered set to transmit The bitfield determines a full 20-bit sequence to transmit, consisting of four K-codes, each of five bits, defining the packet to transmit. The bit 0 (bit 0 of K-code1) is the first, the bit 19 (bit 4 of K‑code4) the last."]
1791 #[inline(always)]
1792 pub fn set_txordset(&mut self, val: u32) {
1793 self.0 = (self.0 & !(0x000f_ffff << 0usize)) | (((val as u32) & 0x000f_ffff) << 0usize);
1794 }
1795 }
1796 impl Default for TxOrdsetr {
1797 #[inline(always)]
1798 fn default() -> TxOrdsetr {
1799 TxOrdsetr(0)
1800 }
1801 }
1802 impl core::fmt::Debug for TxOrdsetr {
1803 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1804 f.debug_struct("TxOrdsetr").field("txordset", &self.txordset()).finish()
1805 }
1806 }
1807 #[cfg(feature = "defmt")]
1808 impl defmt::Format for TxOrdsetr {
1809 fn format(&self, f: defmt::Formatter) {
1810 #[derive(defmt :: Format)]
1811 struct TxOrdsetr {
1812 txordset: u32,
1813 }
1814 let proxy = TxOrdsetr {
1815 txordset: self.txordset(),
1816 };
1817 defmt::write!(f, "{}", proxy)
1818 }
1819 }
1820 #[doc = "Tx payload size register"]
1821 #[repr(transparent)]
1822 #[derive(Copy, Clone, Eq, PartialEq)]
1823 pub struct TxPayszr(pub u32);
1824 impl TxPayszr {
1825 #[doc = "Payload size yet to transmit The bitfield is modified by software and by hardware. It contains the number of bytes of a payload (including header but excluding CRC) yet to transmit: each time a data byte is written into the TXDR register, the bitfield value decrements and the TXIS bit is set, except when the bitfield value reaches zero. The enumerated values are standard payload sizes before the start of transmission."]
1826 #[inline(always)]
1827 pub const fn txpaysz(&self) -> u16 {
1828 let val = (self.0 >> 0usize) & 0x03ff;
1829 val as u16
1830 }
1831 #[doc = "Payload size yet to transmit The bitfield is modified by software and by hardware. It contains the number of bytes of a payload (including header but excluding CRC) yet to transmit: each time a data byte is written into the TXDR register, the bitfield value decrements and the TXIS bit is set, except when the bitfield value reaches zero. The enumerated values are standard payload sizes before the start of transmission."]
1832 #[inline(always)]
1833 pub fn set_txpaysz(&mut self, val: u16) {
1834 self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize);
1835 }
1836 }
1837 impl Default for TxPayszr {
1838 #[inline(always)]
1839 fn default() -> TxPayszr {
1840 TxPayszr(0)
1841 }
1842 }
1843 impl core::fmt::Debug for TxPayszr {
1844 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1845 f.debug_struct("TxPayszr").field("txpaysz", &self.txpaysz()).finish()
1846 }
1847 }
1848 #[cfg(feature = "defmt")]
1849 impl defmt::Format for TxPayszr {
1850 fn format(&self, f: defmt::Formatter) {
1851 #[derive(defmt :: Format)]
1852 struct TxPayszr {
1853 txpaysz: u16,
1854 }
1855 let proxy = TxPayszr {
1856 txpaysz: self.txpaysz(),
1857 };
1858 defmt::write!(f, "{}", proxy)
1859 }
1860 }
1861 #[doc = "Tx data register"]
1862 #[repr(transparent)]
1863 #[derive(Copy, Clone, Eq, PartialEq)]
1864 pub struct Txdr(pub u32);
1865 impl Txdr {
1866 #[doc = "Data byte to transmit"]
1867 #[inline(always)]
1868 pub const fn txdata(&self) -> u8 {
1869 let val = (self.0 >> 0usize) & 0xff;
1870 val as u8
1871 }
1872 #[doc = "Data byte to transmit"]
1873 #[inline(always)]
1874 pub fn set_txdata(&mut self, val: u8) {
1875 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
1876 }
1877 }
1878 impl Default for Txdr {
1879 #[inline(always)]
1880 fn default() -> Txdr {
1881 Txdr(0)
1882 }
1883 }
1884 impl core::fmt::Debug for Txdr {
1885 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1886 f.debug_struct("Txdr").field("txdata", &self.txdata()).finish()
1887 }
1888 }
1889 #[cfg(feature = "defmt")]
1890 impl defmt::Format for Txdr {
1891 fn format(&self, f: defmt::Formatter) {
1892 #[derive(defmt :: Format)]
1893 struct Txdr {
1894 txdata: u8,
1895 }
1896 let proxy = Txdr { txdata: self.txdata() };
1897 defmt::write!(f, "{}", proxy)
1898 }
1899 }
1900}
1901pub mod vals {
1902 #[repr(u8)]
1903 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1904 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1905 pub enum Anamode {
1906 #[doc = "Source"]
1907 SOURCE = 0x0,
1908 #[doc = "Sink"]
1909 SINK = 0x01,
1910 }
1911 impl Anamode {
1912 #[inline(always)]
1913 pub const fn from_bits(val: u8) -> Anamode {
1914 unsafe { core::mem::transmute(val & 0x01) }
1915 }
1916 #[inline(always)]
1917 pub const fn to_bits(self) -> u8 {
1918 unsafe { core::mem::transmute(self) }
1919 }
1920 }
1921 impl From<u8> for Anamode {
1922 #[inline(always)]
1923 fn from(val: u8) -> Anamode {
1924 Anamode::from_bits(val)
1925 }
1926 }
1927 impl From<Anamode> for u8 {
1928 #[inline(always)]
1929 fn from(val: Anamode) -> u8 {
1930 Anamode::to_bits(val)
1931 }
1932 }
1933 #[repr(u8)]
1934 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1935 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1936 pub enum Ccenable {
1937 #[doc = "Disable both PHYs"]
1938 DISABLED = 0x0,
1939 #[doc = "Enable CC1 PHY"]
1940 CC1 = 0x01,
1941 #[doc = "Enable CC2 PHY"]
1942 CC2 = 0x02,
1943 #[doc = "Enable CC1 and CC2 PHY"]
1944 BOTH = 0x03,
1945 }
1946 impl Ccenable {
1947 #[inline(always)]
1948 pub const fn from_bits(val: u8) -> Ccenable {
1949 unsafe { core::mem::transmute(val & 0x03) }
1950 }
1951 #[inline(always)]
1952 pub const fn to_bits(self) -> u8 {
1953 unsafe { core::mem::transmute(self) }
1954 }
1955 }
1956 impl From<u8> for Ccenable {
1957 #[inline(always)]
1958 fn from(val: u8) -> Ccenable {
1959 Ccenable::from_bits(val)
1960 }
1961 }
1962 impl From<Ccenable> for u8 {
1963 #[inline(always)]
1964 fn from(val: Ccenable) -> u8 {
1965 Ccenable::to_bits(val)
1966 }
1967 }
1968 #[repr(u8)]
1969 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
1970 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
1971 pub enum Phyccsel {
1972 #[doc = "Use CC1 IO for Power Delivery communication"]
1973 CC1 = 0x0,
1974 #[doc = "Use CC2 IO for Power Delivery communication"]
1975 CC2 = 0x01,
1976 }
1977 impl Phyccsel {
1978 #[inline(always)]
1979 pub const fn from_bits(val: u8) -> Phyccsel {
1980 unsafe { core::mem::transmute(val & 0x01) }
1981 }
1982 #[inline(always)]
1983 pub const fn to_bits(self) -> u8 {
1984 unsafe { core::mem::transmute(self) }
1985 }
1986 }
1987 impl From<u8> for Phyccsel {
1988 #[inline(always)]
1989 fn from(val: u8) -> Phyccsel {
1990 Phyccsel::from_bits(val)
1991 }
1992 }
1993 impl From<Phyccsel> for u8 {
1994 #[inline(always)]
1995 fn from(val: Phyccsel) -> u8 {
1996 Phyccsel::to_bits(val)
1997 }
1998 }
1999 #[repr(u8)]
2000 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2001 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2002 pub enum PscUsbpdclk {
2003 #[doc = "1 (bypass)"]
2004 DIV1 = 0x0,
2005 #[doc = "2"]
2006 DIV2 = 0x01,
2007 #[doc = "4"]
2008 DIV4 = 0x02,
2009 #[doc = "8"]
2010 DIV8 = 0x03,
2011 #[doc = "16"]
2012 DIV16 = 0x04,
2013 _RESERVED_5 = 0x05,
2014 _RESERVED_6 = 0x06,
2015 _RESERVED_7 = 0x07,
2016 }
2017 impl PscUsbpdclk {
2018 #[inline(always)]
2019 pub const fn from_bits(val: u8) -> PscUsbpdclk {
2020 unsafe { core::mem::transmute(val & 0x07) }
2021 }
2022 #[inline(always)]
2023 pub const fn to_bits(self) -> u8 {
2024 unsafe { core::mem::transmute(self) }
2025 }
2026 }
2027 impl From<u8> for PscUsbpdclk {
2028 #[inline(always)]
2029 fn from(val: u8) -> PscUsbpdclk {
2030 PscUsbpdclk::from_bits(val)
2031 }
2032 }
2033 impl From<PscUsbpdclk> for u8 {
2034 #[inline(always)]
2035 fn from(val: PscUsbpdclk) -> u8 {
2036 PscUsbpdclk::to_bits(val)
2037 }
2038 }
2039 #[repr(u8)]
2040 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2041 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2042 pub enum Rxordset {
2043 #[doc = "SOP code detected in receiver"]
2044 SOP = 0x0,
2045 #[doc = "SOP' code detected in receiver"]
2046 SOP_PRIME = 0x01,
2047 #[doc = "SOP'' code detected in receiver"]
2048 SOP_DOUBLE_PRIME = 0x02,
2049 #[doc = "SOP'_Debug detected in receiver"]
2050 SOP_PRIME_DEBUG = 0x03,
2051 #[doc = "SOP''_Debug detected in receiver"]
2052 SOP_DOUBLE_PRIME_DEBUG = 0x04,
2053 #[doc = "Cable Reset detected in receiver"]
2054 CABLE_RESET = 0x05,
2055 #[doc = "SOP extension#1 detected in receiver"]
2056 EXT1 = 0x06,
2057 #[doc = "SOP extension#2 detected in receiver"]
2058 EXT2 = 0x07,
2059 }
2060 impl Rxordset {
2061 #[inline(always)]
2062 pub const fn from_bits(val: u8) -> Rxordset {
2063 unsafe { core::mem::transmute(val & 0x07) }
2064 }
2065 #[inline(always)]
2066 pub const fn to_bits(self) -> u8 {
2067 unsafe { core::mem::transmute(self) }
2068 }
2069 }
2070 impl From<u8> for Rxordset {
2071 #[inline(always)]
2072 fn from(val: u8) -> Rxordset {
2073 Rxordset::from_bits(val)
2074 }
2075 }
2076 impl From<Rxordset> for u8 {
2077 #[inline(always)]
2078 fn from(val: Rxordset) -> u8 {
2079 Rxordset::to_bits(val)
2080 }
2081 }
2082 #[repr(u8)]
2083 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2084 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2085 pub enum Rxsopkinvalid {
2086 #[doc = "No K‑code corrupted"]
2087 NONE = 0x0,
2088 #[doc = "First K‑code corrupted"]
2089 FIRST = 0x01,
2090 #[doc = "Second K‑code corrupted"]
2091 SECOND = 0x02,
2092 #[doc = "Third K‑code corrupted"]
2093 THIRD = 0x03,
2094 #[doc = "Fourth K‑code corrupted"]
2095 FOURTH = 0x04,
2096 _RESERVED_5 = 0x05,
2097 _RESERVED_6 = 0x06,
2098 _RESERVED_7 = 0x07,
2099 }
2100 impl Rxsopkinvalid {
2101 #[inline(always)]
2102 pub const fn from_bits(val: u8) -> Rxsopkinvalid {
2103 unsafe { core::mem::transmute(val & 0x07) }
2104 }
2105 #[inline(always)]
2106 pub const fn to_bits(self) -> u8 {
2107 unsafe { core::mem::transmute(self) }
2108 }
2109 }
2110 impl From<u8> for Rxsopkinvalid {
2111 #[inline(always)]
2112 fn from(val: u8) -> Rxsopkinvalid {
2113 Rxsopkinvalid::from_bits(val)
2114 }
2115 }
2116 impl From<Rxsopkinvalid> for u8 {
2117 #[inline(always)]
2118 fn from(val: Rxsopkinvalid) -> u8 {
2119 Rxsopkinvalid::to_bits(val)
2120 }
2121 }
2122 #[repr(u8)]
2123 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2124 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2125 pub enum Txmode {
2126 #[doc = "Transmission of Tx packet previously defined in other registers"]
2127 PACKET = 0x0,
2128 #[doc = "Cable Reset sequence"]
2129 CABLE_RESET = 0x01,
2130 #[doc = "BIST test sequence (BIST Carrier Mode 2)"]
2131 BIST = 0x02,
2132 _RESERVED_3 = 0x03,
2133 }
2134 impl Txmode {
2135 #[inline(always)]
2136 pub const fn from_bits(val: u8) -> Txmode {
2137 unsafe { core::mem::transmute(val & 0x03) }
2138 }
2139 #[inline(always)]
2140 pub const fn to_bits(self) -> u8 {
2141 unsafe { core::mem::transmute(self) }
2142 }
2143 }
2144 impl From<u8> for Txmode {
2145 #[inline(always)]
2146 fn from(val: u8) -> Txmode {
2147 Txmode::from_bits(val)
2148 }
2149 }
2150 impl From<Txmode> for u8 {
2151 #[inline(always)]
2152 fn from(val: Txmode) -> u8 {
2153 Txmode::to_bits(val)
2154 }
2155 }
2156 #[repr(u8)]
2157 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
2158 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
2159 pub enum TypecVstateCc {
2160 #[doc = "Lowest"]
2161 LOWEST = 0x0,
2162 #[doc = "Low"]
2163 LOW = 0x01,
2164 #[doc = "High"]
2165 HIGH = 0x02,
2166 #[doc = "Highest"]
2167 HIGHEST = 0x03,
2168 }
2169 impl TypecVstateCc {
2170 #[inline(always)]
2171 pub const fn from_bits(val: u8) -> TypecVstateCc {
2172 unsafe { core::mem::transmute(val & 0x03) }
2173 }
2174 #[inline(always)]
2175 pub const fn to_bits(self) -> u8 {
2176 unsafe { core::mem::transmute(self) }
2177 }
2178 }
2179 impl From<u8> for TypecVstateCc {
2180 #[inline(always)]
2181 fn from(val: u8) -> TypecVstateCc {
2182 TypecVstateCc::from_bits(val)
2183 }
2184 }
2185 impl From<TypecVstateCc> for u8 {
2186 #[inline(always)]
2187 fn from(val: TypecVstateCc) -> u8 {
2188 TypecVstateCc::to_bits(val)
2189 }
2190 }
2191}
2192