1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "Voltage reference buffer."]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Vrefbuf {
9 ptr: *mut u8,
10}
11unsafe impl Send for Vrefbuf {}
12unsafe impl Sync for Vrefbuf {}
13impl Vrefbuf {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "VREFBUF control and status register."]
23 #[inline(always)]
24 pub const fn csr(self) -> crate::common::Reg<regs::Csr, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(count:0x0usize) as _) }
26 }
27 #[doc = "VREFBUF calibration control register."]
28 #[inline(always)]
29 pub const fn ccr(self) -> crate::common::Reg<regs::Ccr, crate::common::RW> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(count:0x04usize) as _) }
31 }
32}
33pub mod regs {
34 #[doc = "VREFBUF calibration control register."]
35 #[repr(transparent)]
36 #[derive(Copy, Clone, Eq, PartialEq)]
37 pub struct Ccr(pub u32);
38 impl Ccr {
39 #[doc = "Trimming code The TRIM code is a 6-bit unsigned data (minimum 000000, maximum 111111) that is set and updated according the mechanism described below. Reset: TRIM\\[5:0\\]
40is automatically initialized with the VRS = 0 trimming value stored in the Flash memory during the production test. VRS change: TRIM\\[5:0\\]
41is automatically initialized with the trimming value (corresponding to VRS setting) stored in the Flash memory during the production test. Write in TRIM\\[5:0\\]: User can modify the TRIM\\[5:0\\]
42with an arbitrary value. This is permanently disabling the control of the trimming value with VRS (until the device is reset). Note: If the user application performs the trimming, the trimming code must start from 000000 to 111111 in ascending order."]
43 #[inline(always)]
44 pub const fn trim(&self) -> u8 {
45 let val = (self.0 >> 0usize) & 0x3f;
46 val as u8
47 }
48 #[doc = "Trimming code The TRIM code is a 6-bit unsigned data (minimum 000000, maximum 111111) that is set and updated according the mechanism described below. Reset: TRIM\\[5:0\\]
49is automatically initialized with the VRS = 0 trimming value stored in the Flash memory during the production test. VRS change: TRIM\\[5:0\\]
50is automatically initialized with the trimming value (corresponding to VRS setting) stored in the Flash memory during the production test. Write in TRIM\\[5:0\\]: User can modify the TRIM\\[5:0\\]
51with an arbitrary value. This is permanently disabling the control of the trimming value with VRS (until the device is reset). Note: If the user application performs the trimming, the trimming code must start from 000000 to 111111 in ascending order."]
52 #[inline(always)]
53 pub fn set_trim(&mut self, val: u8) {
54 self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
55 }
56 }
57 impl Default for Ccr {
58 #[inline(always)]
59 fn default() -> Ccr {
60 Ccr(0)
61 }
62 }
63 impl core::fmt::Debug for Ccr {
64 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
65 f.debug_struct("Ccr").field("trim", &self.trim()).finish()
66 }
67 }
68 #[cfg(feature = "defmt")]
69 impl defmt::Format for Ccr {
70 fn format(&self, f: defmt::Formatter) {
71 #[derive(defmt :: Format)]
72 struct Ccr {
73 trim: u8,
74 }
75 let proxy = Ccr { trim: self.trim() };
76 defmt::write!(f, "{}", proxy)
77 }
78 }
79 #[doc = "VREFBUF control and status register."]
80 #[repr(transparent)]
81 #[derive(Copy, Clone, Eq, PartialEq)]
82 pub struct Csr(pub u32);
83 impl Csr {
84 #[doc = "Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode."]
85 #[inline(always)]
86 pub const fn envr(&self) -> bool {
87 let val = (self.0 >> 0usize) & 0x01;
88 val != 0
89 }
90 #[doc = "Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode."]
91 #[inline(always)]
92 pub fn set_envr(&mut self, val: bool) {
93 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
94 }
95 #[doc = "High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to for the mode descriptions depending on ENVR bit configuration."]
96 #[inline(always)]
97 pub const fn hiz(&self) -> super::vals::Hiz {
98 let val = (self.0 >> 1usize) & 0x01;
99 super::vals::Hiz::from_bits(val as u8)
100 }
101 #[doc = "High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to for the mode descriptions depending on ENVR bit configuration."]
102 #[inline(always)]
103 pub fn set_hiz(&mut self, val: super::vals::Hiz) {
104 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize);
105 }
106 #[doc = "Voltage reference buffer ready."]
107 #[inline(always)]
108 pub const fn vrr(&self) -> bool {
109 let val = (self.0 >> 3usize) & 0x01;
110 val != 0
111 }
112 #[doc = "Voltage reference buffer ready."]
113 #[inline(always)]
114 pub fn set_vrr(&mut self, val: bool) {
115 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
116 }
117 #[doc = "Voltage reference scale These bits select the value generated by the voltage reference buffer. VRS = 000: VREFBUF0 voltage selected. VRS = 001: VREFBUF1 voltage selected. VRS = 010: VREFBUF2 voltage selected. VRS = 011: VREFBUF3 voltage selected. Others: Reserved Note: Refer to the product datasheet for each VREFBUFx voltage setting value. The software can program this bitfield only when the VREFBUF is disabled (ENVR=0)."]
118 #[inline(always)]
119 pub const fn vrs(&self) -> super::vals::Vrs {
120 let val = (self.0 >> 4usize) & 0x07;
121 super::vals::Vrs::from_bits(val as u8)
122 }
123 #[doc = "Voltage reference scale These bits select the value generated by the voltage reference buffer. VRS = 000: VREFBUF0 voltage selected. VRS = 001: VREFBUF1 voltage selected. VRS = 010: VREFBUF2 voltage selected. VRS = 011: VREFBUF3 voltage selected. Others: Reserved Note: Refer to the product datasheet for each VREFBUFx voltage setting value. The software can program this bitfield only when the VREFBUF is disabled (ENVR=0)."]
124 #[inline(always)]
125 pub fn set_vrs(&mut self, val: super::vals::Vrs) {
126 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32) & 0x07) << 4usize);
127 }
128 }
129 impl Default for Csr {
130 #[inline(always)]
131 fn default() -> Csr {
132 Csr(0)
133 }
134 }
135 impl core::fmt::Debug for Csr {
136 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
137 f.debug_struct("Csr")
138 .field("envr", &self.envr())
139 .field("hiz", &self.hiz())
140 .field("vrr", &self.vrr())
141 .field("vrs", &self.vrs())
142 .finish()
143 }
144 }
145 #[cfg(feature = "defmt")]
146 impl defmt::Format for Csr {
147 fn format(&self, f: defmt::Formatter) {
148 #[derive(defmt :: Format)]
149 struct Csr {
150 envr: bool,
151 hiz: super::vals::Hiz,
152 vrr: bool,
153 vrs: super::vals::Vrs,
154 }
155 let proxy = Csr {
156 envr: self.envr(),
157 hiz: self.hiz(),
158 vrr: self.vrr(),
159 vrs: self.vrs(),
160 };
161 defmt::write!(f, "{}", proxy)
162 }
163 }
164}
165pub mod vals {
166 #[repr(u8)]
167 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
168 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
169 pub enum Hiz {
170 #[doc = "VREF+ pin is internally connected to the voltage reference buffer output."]
171 CONNECTED = 0x0,
172 #[doc = "VREF+ pin is high impedance."]
173 HIGH_Z = 0x01,
174 }
175 impl Hiz {
176 #[inline(always)]
177 pub const fn from_bits(val: u8) -> Hiz {
178 unsafe { core::mem::transmute(val & 0x01) }
179 }
180 #[inline(always)]
181 pub const fn to_bits(self) -> u8 {
182 unsafe { core::mem::transmute(self) }
183 }
184 }
185 impl From<u8> for Hiz {
186 #[inline(always)]
187 fn from(val: u8) -> Hiz {
188 Hiz::from_bits(val)
189 }
190 }
191 impl From<Hiz> for u8 {
192 #[inline(always)]
193 fn from(val: Hiz) -> u8 {
194 Hiz::to_bits(val)
195 }
196 }
197 #[repr(u8)]
198 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
199 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
200 pub enum Vrs {
201 #[doc = "Voltage reference set to around 2.5 V."]
202 VREF0 = 0x0,
203 #[doc = "Voltage reference set to around 2.048 V."]
204 VREF1 = 0x01,
205 #[doc = "Voltage reference set to around 1.8 V."]
206 VREF2 = 0x02,
207 #[doc = "Voltage reference set to around 1.5 V (ADC, DAC are not compatible with this setting)."]
208 VREF3 = 0x03,
209 _RESERVED_4 = 0x04,
210 _RESERVED_5 = 0x05,
211 _RESERVED_6 = 0x06,
212 _RESERVED_7 = 0x07,
213 }
214 impl Vrs {
215 #[inline(always)]
216 pub const fn from_bits(val: u8) -> Vrs {
217 unsafe { core::mem::transmute(val & 0x07) }
218 }
219 #[inline(always)]
220 pub const fn to_bits(self) -> u8 {
221 unsafe { core::mem::transmute(self) }
222 }
223 }
224 impl From<u8> for Vrs {
225 #[inline(always)]
226 fn from(val: u8) -> Vrs {
227 Vrs::from_bits(val)
228 }
229 }
230 impl From<Vrs> for u8 {
231 #[inline(always)]
232 fn from(val: Vrs) -> u8 {
233 Vrs::to_bits(val)
234 }
235 }
236}
237