1#![allow(clippy::missing_safety_doc)]
2#![allow(clippy::identity_op)]
3#![allow(clippy::unnecessary_cast)]
4#![allow(clippy::erasing_op)]
5
6#[doc = "Window watchdog"]
7#[derive(Copy, Clone, Eq, PartialEq)]
8pub struct Wwdg {
9 ptr: *mut u8,
10}
11unsafe impl Send for Wwdg {}
12unsafe impl Sync for Wwdg {}
13impl Wwdg {
14 #[inline(always)]
15 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
16 Self { ptr: ptr as _ }
17 }
18 #[inline(always)]
19 pub const fn as_ptr(&self) -> *mut () {
20 self.ptr as _
21 }
22 #[doc = "Control register"]
23 #[inline(always)]
24 pub const fn cr(self) -> crate::common::Reg<regs::Cr, crate::common::RW> {
25 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
26 }
27 #[doc = "Configuration register"]
28 #[inline(always)]
29 pub const fn cfr(self) -> crate::common::Reg<regs::Cfr, crate::common::RW> {
30 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
31 }
32 #[doc = "Status register"]
33 #[inline(always)]
34 pub const fn sr(self) -> crate::common::Reg<regs::Sr, crate::common::RW> {
35 unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
36 }
37}
38pub mod regs {
39 #[doc = "Configuration register"]
40 #[repr(transparent)]
41 #[derive(Copy, Clone, Eq, PartialEq)]
42 pub struct Cfr(pub u32);
43 impl Cfr {
44 #[doc = "7-bit window value"]
45 #[inline(always)]
46 pub const fn w(&self) -> u8 {
47 let val = (self.0 >> 0usize) & 0x7f;
48 val as u8
49 }
50 #[doc = "7-bit window value"]
51 #[inline(always)]
52 pub fn set_w(&mut self, val: u8) {
53 self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize);
54 }
55 #[doc = "Early wakeup interrupt"]
56 #[inline(always)]
57 pub const fn ewi(&self) -> bool {
58 let val = (self.0 >> 9usize) & 0x01;
59 val != 0
60 }
61 #[doc = "Early wakeup interrupt"]
62 #[inline(always)]
63 pub fn set_ewi(&mut self, val: bool) {
64 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
65 }
66 #[doc = "Timer base"]
67 #[inline(always)]
68 pub const fn wdgtb(&self) -> super::vals::Wdgtb {
69 let val = (self.0 >> 11usize) & 0x07;
70 super::vals::Wdgtb::from_bits(val as u8)
71 }
72 #[doc = "Timer base"]
73 #[inline(always)]
74 pub fn set_wdgtb(&mut self, val: super::vals::Wdgtb) {
75 self.0 = (self.0 & !(0x07 << 11usize)) | (((val.to_bits() as u32) & 0x07) << 11usize);
76 }
77 }
78 impl Default for Cfr {
79 #[inline(always)]
80 fn default() -> Cfr {
81 Cfr(0)
82 }
83 }
84 impl core::fmt::Debug for Cfr {
85 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
86 f.debug_struct("Cfr")
87 .field("w", &self.w())
88 .field("ewi", &self.ewi())
89 .field("wdgtb", &self.wdgtb())
90 .finish()
91 }
92 }
93 #[cfg(feature = "defmt")]
94 impl defmt::Format for Cfr {
95 fn format(&self, f: defmt::Formatter) {
96 #[derive(defmt :: Format)]
97 struct Cfr {
98 w: u8,
99 ewi: bool,
100 wdgtb: super::vals::Wdgtb,
101 }
102 let proxy = Cfr {
103 w: self.w(),
104 ewi: self.ewi(),
105 wdgtb: self.wdgtb(),
106 };
107 defmt::write!(f, "{}", proxy)
108 }
109 }
110 #[doc = "Control register"]
111 #[repr(transparent)]
112 #[derive(Copy, Clone, Eq, PartialEq)]
113 pub struct Cr(pub u32);
114 impl Cr {
115 #[doc = "7-bit counter (MSB to LSB)"]
116 #[inline(always)]
117 pub const fn t(&self) -> u8 {
118 let val = (self.0 >> 0usize) & 0x7f;
119 val as u8
120 }
121 #[doc = "7-bit counter (MSB to LSB)"]
122 #[inline(always)]
123 pub fn set_t(&mut self, val: u8) {
124 self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize);
125 }
126 #[doc = "Activation bit (true is enabled, false is disabled)"]
127 #[inline(always)]
128 pub const fn wdga(&self) -> bool {
129 let val = (self.0 >> 7usize) & 0x01;
130 val != 0
131 }
132 #[doc = "Activation bit (true is enabled, false is disabled)"]
133 #[inline(always)]
134 pub fn set_wdga(&mut self, val: bool) {
135 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
136 }
137 }
138 impl Default for Cr {
139 #[inline(always)]
140 fn default() -> Cr {
141 Cr(0)
142 }
143 }
144 impl core::fmt::Debug for Cr {
145 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
146 f.debug_struct("Cr")
147 .field("t", &self.t())
148 .field("wdga", &self.wdga())
149 .finish()
150 }
151 }
152 #[cfg(feature = "defmt")]
153 impl defmt::Format for Cr {
154 fn format(&self, f: defmt::Formatter) {
155 #[derive(defmt :: Format)]
156 struct Cr {
157 t: u8,
158 wdga: bool,
159 }
160 let proxy = Cr {
161 t: self.t(),
162 wdga: self.wdga(),
163 };
164 defmt::write!(f, "{}", proxy)
165 }
166 }
167 #[doc = "Status register"]
168 #[repr(transparent)]
169 #[derive(Copy, Clone, Eq, PartialEq)]
170 pub struct Sr(pub u32);
171 impl Sr {
172 #[doc = "Early wakeup interrupt flag"]
173 #[inline(always)]
174 pub const fn ewif(&self) -> bool {
175 let val = (self.0 >> 0usize) & 0x01;
176 val != 0
177 }
178 #[doc = "Early wakeup interrupt flag"]
179 #[inline(always)]
180 pub fn set_ewif(&mut self, val: bool) {
181 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
182 }
183 }
184 impl Default for Sr {
185 #[inline(always)]
186 fn default() -> Sr {
187 Sr(0)
188 }
189 }
190 impl core::fmt::Debug for Sr {
191 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
192 f.debug_struct("Sr").field("ewif", &self.ewif()).finish()
193 }
194 }
195 #[cfg(feature = "defmt")]
196 impl defmt::Format for Sr {
197 fn format(&self, f: defmt::Formatter) {
198 #[derive(defmt :: Format)]
199 struct Sr {
200 ewif: bool,
201 }
202 let proxy = Sr { ewif: self.ewif() };
203 defmt::write!(f, "{}", proxy)
204 }
205 }
206}
207pub mod vals {
208 #[repr(u8)]
209 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)]
210 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
211 pub enum Wdgtb {
212 #[doc = "Counter clock (PCLK1 div 4096) div 1"]
213 DIV1 = 0x0,
214 #[doc = "Counter clock (PCLK1 div 4096) div 2"]
215 DIV2 = 0x01,
216 #[doc = "Counter clock (PCLK1 div 4096) div 4"]
217 DIV4 = 0x02,
218 #[doc = "Counter clock (PCLK1 div 4096) div 8"]
219 DIV8 = 0x03,
220 #[doc = "Counter clock (PCLK1 div 4096) div 16"]
221 DIV16 = 0x04,
222 #[doc = "Counter clock (PCLK1 div 4096) div 32"]
223 DIV32 = 0x05,
224 #[doc = "Counter clock (PCLK1 div 4096) div 64"]
225 DIV64 = 0x06,
226 #[doc = "Counter clock (PCLK1 div 4096) div 128"]
227 DIV128 = 0x07,
228 }
229 impl Wdgtb {
230 #[inline(always)]
231 pub const fn from_bits(val: u8) -> Wdgtb {
232 unsafe { core::mem::transmute(val & 0x07) }
233 }
234 #[inline(always)]
235 pub const fn to_bits(self) -> u8 {
236 unsafe { core::mem::transmute(self) }
237 }
238 }
239 impl From<u8> for Wdgtb {
240 #[inline(always)]
241 fn from(val: u8) -> Wdgtb {
242 Wdgtb::from_bits(val)
243 }
244 }
245 impl From<Wdgtb> for u8 {
246 #[inline(always)]
247 fn from(val: Wdgtb) -> u8 {
248 Wdgtb::to_bits(val)
249 }
250 }
251}
252