1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Adc",
7 extends: None,
8 description: Some("ADC1."),
9 items: &[
10 BlockItem {
11 name: "isr",
12 description: Some("ADC interrupt and status register."),
13 array: None,
14 byte_offset: 0x0,
15 inner: BlockItemInner::Register(Register {
16 access: Access::ReadWrite,
17 bit_size: 32,
18 fieldset: Some("Isr"),
19 }),
20 },
21 BlockItem {
22 name: "ier",
23 description: Some("ADC interrupt enable register."),
24 array: None,
25 byte_offset: 0x4,
26 inner: BlockItemInner::Register(Register {
27 access: Access::ReadWrite,
28 bit_size: 32,
29 fieldset: Some("Ier"),
30 }),
31 },
32 BlockItem {
33 name: "cr",
34 description: Some("ADC control register."),
35 array: None,
36 byte_offset: 0x8,
37 inner: BlockItemInner::Register(Register {
38 access: Access::ReadWrite,
39 bit_size: 32,
40 fieldset: Some("Cr"),
41 }),
42 },
43 BlockItem {
44 name: "cfgr",
45 description: Some("ADC configuration register."),
46 array: None,
47 byte_offset: 0xc,
48 inner: BlockItemInner::Register(Register {
49 access: Access::ReadWrite,
50 bit_size: 32,
51 fieldset: Some("Cfgr"),
52 }),
53 },
54 BlockItem {
55 name: "cfgr2",
56 description: Some("ADC configuration register 2."),
57 array: None,
58 byte_offset: 0x10,
59 inner: BlockItemInner::Register(Register {
60 access: Access::ReadWrite,
61 bit_size: 32,
62 fieldset: Some("Cfgr2"),
63 }),
64 },
65 BlockItem {
66 name: "smpr",
67 description: Some("sampling time register 1-2"),
68 array: Some(Array::Regular(RegularArray { len: 2, stride: 4 })),
69 byte_offset: 0x14,
70 inner: BlockItemInner::Register(Register {
71 access: Access::ReadWrite,
72 bit_size: 32,
73 fieldset: Some("Smpr"),
74 }),
75 },
76 BlockItem {
77 name: "pcsel",
78 description: Some("ADC channel preselection register."),
79 array: None,
80 byte_offset: 0x1c,
81 inner: BlockItemInner::Register(Register {
82 access: Access::ReadWrite,
83 bit_size: 32,
84 fieldset: Some("Pcsel"),
85 }),
86 },
87 BlockItem {
88 name: "sqr1",
89 description: Some("ADC regular sequence register 1."),
90 array: None,
91 byte_offset: 0x30,
92 inner: BlockItemInner::Register(Register {
93 access: Access::ReadWrite,
94 bit_size: 32,
95 fieldset: Some("Sqr1"),
96 }),
97 },
98 BlockItem {
99 name: "sqr2",
100 description: Some("ADC regular sequence register 2."),
101 array: None,
102 byte_offset: 0x34,
103 inner: BlockItemInner::Register(Register {
104 access: Access::ReadWrite,
105 bit_size: 32,
106 fieldset: Some("Sqr2"),
107 }),
108 },
109 BlockItem {
110 name: "sqr3",
111 description: Some("ADC regular sequence register 3."),
112 array: None,
113 byte_offset: 0x38,
114 inner: BlockItemInner::Register(Register {
115 access: Access::ReadWrite,
116 bit_size: 32,
117 fieldset: Some("Sqr3"),
118 }),
119 },
120 BlockItem {
121 name: "sqr4",
122 description: Some("ADC regular sequence register 4."),
123 array: None,
124 byte_offset: 0x3c,
125 inner: BlockItemInner::Register(Register {
126 access: Access::ReadWrite,
127 bit_size: 32,
128 fieldset: Some("Sqr4"),
129 }),
130 },
131 BlockItem {
132 name: "dr",
133 description: Some("ADC regular Data Register."),
134 array: None,
135 byte_offset: 0x40,
136 inner: BlockItemInner::Register(Register {
137 access: Access::Read,
138 bit_size: 32,
139 fieldset: Some("Dr"),
140 }),
141 },
142 BlockItem {
143 name: "jsqr",
144 description: Some("ADC injected sequence register."),
145 array: None,
146 byte_offset: 0x4c,
147 inner: BlockItemInner::Register(Register {
148 access: Access::ReadWrite,
149 bit_size: 32,
150 fieldset: Some("Jsqr"),
151 }),
152 },
153 BlockItem {
154 name: "ofr",
155 description: Some("ADC offset register."),
156 array: Some(Array::Regular(RegularArray { len: 4, stride: 4 })),
157 byte_offset: 0x60,
158 inner: BlockItemInner::Register(Register {
159 access: Access::ReadWrite,
160 bit_size: 32,
161 fieldset: Some("Ofr"),
162 }),
163 },
164 BlockItem {
165 name: "gcomp",
166 description: Some("ADC gain compensation register."),
167 array: None,
168 byte_offset: 0x70,
169 inner: BlockItemInner::Register(Register {
170 access: Access::ReadWrite,
171 bit_size: 32,
172 fieldset: Some("Gcomp"),
173 }),
174 },
175 BlockItem {
176 name: "jdr",
177 description: Some("ADC injected data register."),
178 array: Some(Array::Regular(RegularArray { len: 4, stride: 4 })),
179 byte_offset: 0x80,
180 inner: BlockItemInner::Register(Register {
181 access: Access::Read,
182 bit_size: 32,
183 fieldset: Some("Jdr"),
184 }),
185 },
186 BlockItem {
187 name: "awd2cr",
188 description: Some("ADC analog watchdog 2 configuration register."),
189 array: None,
190 byte_offset: 0xa0,
191 inner: BlockItemInner::Register(Register {
192 access: Access::ReadWrite,
193 bit_size: 32,
194 fieldset: Some("Awd2cr"),
195 }),
196 },
197 BlockItem {
198 name: "awd3cr",
199 description: Some("ADC analog watchdog 3 configuration register."),
200 array: None,
201 byte_offset: 0xa4,
202 inner: BlockItemInner::Register(Register {
203 access: Access::ReadWrite,
204 bit_size: 32,
205 fieldset: Some("Awd3cr"),
206 }),
207 },
208 BlockItem {
209 name: "ltr1",
210 description: Some("ADC watchdog threshold register 1."),
211 array: None,
212 byte_offset: 0xa8,
213 inner: BlockItemInner::Register(Register {
214 access: Access::ReadWrite,
215 bit_size: 32,
216 fieldset: Some("Ltr1"),
217 }),
218 },
219 BlockItem {
220 name: "htr1",
221 description: Some("ADC watchdog threshold register 1."),
222 array: None,
223 byte_offset: 0xac,
224 inner: BlockItemInner::Register(Register {
225 access: Access::ReadWrite,
226 bit_size: 32,
227 fieldset: Some("Htr1"),
228 }),
229 },
230 BlockItem {
231 name: "ltr2",
232 description: Some("ADC watchdog lower threshold register 2."),
233 array: None,
234 byte_offset: 0xb0,
235 inner: BlockItemInner::Register(Register {
236 access: Access::ReadWrite,
237 bit_size: 32,
238 fieldset: Some("Ltr2"),
239 }),
240 },
241 BlockItem {
242 name: "htr2",
243 description: Some("ADC watchdog higher threshold register 2."),
244 array: None,
245 byte_offset: 0xb4,
246 inner: BlockItemInner::Register(Register {
247 access: Access::ReadWrite,
248 bit_size: 32,
249 fieldset: Some("Htr2"),
250 }),
251 },
252 BlockItem {
253 name: "ltr3",
254 description: Some("ADC watchdog lower threshold register 3."),
255 array: None,
256 byte_offset: 0xb8,
257 inner: BlockItemInner::Register(Register {
258 access: Access::ReadWrite,
259 bit_size: 32,
260 fieldset: Some("Ltr3"),
261 }),
262 },
263 BlockItem {
264 name: "htr3",
265 description: Some("ADC watchdog higher threshold register 3."),
266 array: None,
267 byte_offset: 0xbc,
268 inner: BlockItemInner::Register(Register {
269 access: Access::ReadWrite,
270 bit_size: 32,
271 fieldset: Some("Htr3"),
272 }),
273 },
274 BlockItem {
275 name: "difsel",
276 description: Some("ADC differential mode selection register."),
277 array: None,
278 byte_offset: 0xc0,
279 inner: BlockItemInner::Register(Register {
280 access: Access::ReadWrite,
281 bit_size: 32,
282 fieldset: Some("Difsel"),
283 }),
284 },
285 BlockItem {
286 name: "calfact",
287 description: Some("ADC user control register."),
288 array: None,
289 byte_offset: 0xc4,
290 inner: BlockItemInner::Register(Register {
291 access: Access::ReadWrite,
292 bit_size: 32,
293 fieldset: Some("Calfact"),
294 }),
295 },
296 BlockItem {
297 name: "calfact2",
298 description: Some("ADC calibration factor register."),
299 array: None,
300 byte_offset: 0xc8,
301 inner: BlockItemInner::Register(Register {
302 access: Access::ReadWrite,
303 bit_size: 32,
304 fieldset: Some("Calfact2"),
305 }),
306 },
307 ],
308 },
309 Block {
310 name: "Adc4",
311 extends: None,
312 description: Some("ADC4."),
313 items: &[
314 BlockItem {
315 name: "isr",
316 description: Some("ADC interrupt and status register."),
317 array: None,
318 byte_offset: 0x0,
319 inner: BlockItemInner::Register(Register {
320 access: Access::ReadWrite,
321 bit_size: 32,
322 fieldset: Some("Adc4Isr"),
323 }),
324 },
325 BlockItem {
326 name: "ier",
327 description: Some("ADC interrupt enable register."),
328 array: None,
329 byte_offset: 0x4,
330 inner: BlockItemInner::Register(Register {
331 access: Access::ReadWrite,
332 bit_size: 32,
333 fieldset: Some("Adc4Ier"),
334 }),
335 },
336 BlockItem {
337 name: "cr",
338 description: Some("ADC control register."),
339 array: None,
340 byte_offset: 0x8,
341 inner: BlockItemInner::Register(Register {
342 access: Access::ReadWrite,
343 bit_size: 32,
344 fieldset: Some("Adc4Cr"),
345 }),
346 },
347 BlockItem {
348 name: "cfgr1",
349 description: Some("ADC configuration register."),
350 array: None,
351 byte_offset: 0xc,
352 inner: BlockItemInner::Register(Register {
353 access: Access::ReadWrite,
354 bit_size: 32,
355 fieldset: Some("Adc4Cfgr1"),
356 }),
357 },
358 BlockItem {
359 name: "cfgr2",
360 description: Some("ADC configuration register 2."),
361 array: None,
362 byte_offset: 0x10,
363 inner: BlockItemInner::Register(Register {
364 access: Access::ReadWrite,
365 bit_size: 32,
366 fieldset: Some("Adc4Cfgr2"),
367 }),
368 },
369 BlockItem {
370 name: "smpr",
371 description: Some("ADC sample time register."),
372 array: None,
373 byte_offset: 0x14,
374 inner: BlockItemInner::Register(Register {
375 access: Access::ReadWrite,
376 bit_size: 32,
377 fieldset: Some("Adc4Smpr"),
378 }),
379 },
380 BlockItem {
381 name: "awd1tr",
382 description: Some("ADC watchdog threshold register."),
383 array: None,
384 byte_offset: 0x20,
385 inner: BlockItemInner::Register(Register {
386 access: Access::ReadWrite,
387 bit_size: 32,
388 fieldset: Some("Adc4Awdtr"),
389 }),
390 },
391 BlockItem {
392 name: "awd2tr",
393 description: Some("ADC watchdog threshold register."),
394 array: None,
395 byte_offset: 0x24,
396 inner: BlockItemInner::Register(Register {
397 access: Access::ReadWrite,
398 bit_size: 32,
399 fieldset: Some("Adc4Awdtr"),
400 }),
401 },
402 BlockItem {
403 name: "chselrmod0",
404 description: Some("ADC channel selection register [alternate]."),
405 array: None,
406 byte_offset: 0x28,
407 inner: BlockItemInner::Register(Register {
408 access: Access::ReadWrite,
409 bit_size: 32,
410 fieldset: Some("Adc4Chselrmod0"),
411 }),
412 },
413 BlockItem {
414 name: "chselrmod1",
415 description: Some("ADC channel selection register [alternate]."),
416 array: None,
417 byte_offset: 0x28,
418 inner: BlockItemInner::Register(Register {
419 access: Access::ReadWrite,
420 bit_size: 32,
421 fieldset: Some("Adc4Chselrmod1"),
422 }),
423 },
424 BlockItem {
425 name: "awd3tr",
426 description: Some("ADC watchdog threshold register."),
427 array: None,
428 byte_offset: 0x2c,
429 inner: BlockItemInner::Register(Register {
430 access: Access::ReadWrite,
431 bit_size: 32,
432 fieldset: Some("Adc4Awdtr"),
433 }),
434 },
435 BlockItem {
436 name: "dr",
437 description: Some("ADC data register."),
438 array: None,
439 byte_offset: 0x40,
440 inner: BlockItemInner::Register(Register {
441 access: Access::Read,
442 bit_size: 32,
443 fieldset: Some("Adc4Dr"),
444 }),
445 },
446 BlockItem {
447 name: "pwrr",
448 description: Some("ADC power register."),
449 array: None,
450 byte_offset: 0x44,
451 inner: BlockItemInner::Register(Register {
452 access: Access::ReadWrite,
453 bit_size: 32,
454 fieldset: Some("Adc4Pwrr"),
455 }),
456 },
457 BlockItem {
458 name: "awd2cr",
459 description: Some("ADC Analog Watchdog 2 Configuration register."),
460 array: None,
461 byte_offset: 0xa0,
462 inner: BlockItemInner::Register(Register {
463 access: Access::ReadWrite,
464 bit_size: 32,
465 fieldset: Some("Adc4Awdcr"),
466 }),
467 },
468 BlockItem {
469 name: "awd3cr",
470 description: Some("ADC Analog Watchdog 3 Configuration register."),
471 array: None,
472 byte_offset: 0xa4,
473 inner: BlockItemInner::Register(Register {
474 access: Access::ReadWrite,
475 bit_size: 32,
476 fieldset: Some("Adc4Awdcr"),
477 }),
478 },
479 BlockItem {
480 name: "calfact",
481 description: Some("ADC Calibration factor."),
482 array: None,
483 byte_offset: 0xc4,
484 inner: BlockItemInner::Register(Register {
485 access: Access::ReadWrite,
486 bit_size: 32,
487 fieldset: Some("Adc4Calfact"),
488 }),
489 },
490 BlockItem {
491 name: "or",
492 description: Some("ADC option register."),
493 array: None,
494 byte_offset: 0xd0,
495 inner: BlockItemInner::Register(Register {
496 access: Access::ReadWrite,
497 bit_size: 32,
498 fieldset: Some("Adc4Or"),
499 }),
500 },
501 BlockItem {
502 name: "ccr",
503 description: Some("ADC common configuration register."),
504 array: None,
505 byte_offset: 0x308,
506 inner: BlockItemInner::Register(Register {
507 access: Access::ReadWrite,
508 bit_size: 32,
509 fieldset: Some("Adc4Ccr"),
510 }),
511 },
512 ],
513 },
514 ],
515 fieldsets: &[
516 FieldSet {
517 name: "Adc4Awdcr",
518 extends: None,
519 description: Some("ADC Analog Watchdog Configuration register."),
520 bit_size: 32,
521 fields: &[Field {
522 name: "awdch",
523 description: Some("AWDCH0."),
524 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
525 bit_size: 1,
526 array: Some(Array::Regular(RegularArray { len: 24, stride: 1 })),
527 enumm: None,
528 }],
529 },
530 FieldSet {
531 name: "Adc4Awdtr",
532 extends: None,
533 description: Some("ADC watchdog threshold register."),
534 bit_size: 32,
535 fields: &[
536 Field {
537 name: "lt3",
538 description: Some("LT3."),
539 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
540 bit_size: 12,
541 array: None,
542 enumm: None,
543 },
544 Field {
545 name: "ht3",
546 description: Some("HT3."),
547 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
548 bit_size: 12,
549 array: None,
550 enumm: None,
551 },
552 ],
553 },
554 FieldSet {
555 name: "Adc4Calfact",
556 extends: None,
557 description: Some("ADC Calibration factor."),
558 bit_size: 32,
559 fields: &[Field {
560 name: "calfact",
561 description: Some("CALFACT."),
562 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
563 bit_size: 7,
564 array: None,
565 enumm: None,
566 }],
567 },
568 FieldSet {
569 name: "Adc4Ccr",
570 extends: None,
571 description: Some("ADC common configuration register."),
572 bit_size: 32,
573 fields: &[
574 Field {
575 name: "presc",
576 description: Some("PRESC."),
577 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }),
578 bit_size: 4,
579 array: None,
580 enumm: Some("Adc4Presc"),
581 },
582 Field {
583 name: "vrefen",
584 description: Some("VREFEN."),
585 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 22 }),
586 bit_size: 1,
587 array: None,
588 enumm: None,
589 },
590 Field {
591 name: "vsensesel",
592 description: Some("VSENSESEL."),
593 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 23 }),
594 bit_size: 1,
595 array: None,
596 enumm: None,
597 },
598 Field {
599 name: "vbaten",
600 description: Some("VBATEN."),
601 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
602 bit_size: 1,
603 array: None,
604 enumm: None,
605 },
606 ],
607 },
608 FieldSet {
609 name: "Adc4Cfgr1",
610 extends: None,
611 description: Some("ADC configuration register."),
612 bit_size: 32,
613 fields: &[
614 Field {
615 name: "dmaen",
616 description: Some("DMAEN."),
617 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
618 bit_size: 1,
619 array: None,
620 enumm: None,
621 },
622 Field {
623 name: "dmacfg",
624 description: Some("DMACFG."),
625 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
626 bit_size: 1,
627 array: None,
628 enumm: Some("Adc4Dmacfg"),
629 },
630 Field {
631 name: "res",
632 description: Some("RES."),
633 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
634 bit_size: 2,
635 array: None,
636 enumm: Some("Adc4Res"),
637 },
638 Field {
639 name: "scandir",
640 description: Some("SCANDIR."),
641 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
642 bit_size: 1,
643 array: None,
644 enumm: None,
645 },
646 Field {
647 name: "align",
648 description: Some("ALIGN."),
649 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
650 bit_size: 1,
651 array: None,
652 enumm: None,
653 },
654 Field {
655 name: "extsel",
656 description: Some("EXTSEL."),
657 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 6 }),
658 bit_size: 3,
659 array: None,
660 enumm: None,
661 },
662 Field {
663 name: "exten",
664 description: Some("EXTEN."),
665 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 10 }),
666 bit_size: 2,
667 array: None,
668 enumm: Some("Adc4Exten"),
669 },
670 Field {
671 name: "ovrmod",
672 description: Some("OVRMOD."),
673 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
674 bit_size: 1,
675 array: None,
676 enumm: None,
677 },
678 Field {
679 name: "cont",
680 description: Some("CONT."),
681 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 13 }),
682 bit_size: 1,
683 array: None,
684 enumm: None,
685 },
686 Field {
687 name: "wait",
688 description: Some("WAIT."),
689 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }),
690 bit_size: 1,
691 array: None,
692 enumm: None,
693 },
694 Field {
695 name: "discen",
696 description: Some("DISCEN."),
697 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
698 bit_size: 1,
699 array: None,
700 enumm: None,
701 },
702 Field {
703 name: "chselrmod",
704 description: Some("CHSELRMOD."),
705 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 21 }),
706 bit_size: 1,
707 array: None,
708 enumm: None,
709 },
710 Field {
711 name: "awd1sgl",
712 description: Some("AWD1SGL."),
713 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 22 }),
714 bit_size: 1,
715 array: None,
716 enumm: None,
717 },
718 Field {
719 name: "awd1en",
720 description: Some("AWD1EN."),
721 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 23 }),
722 bit_size: 1,
723 array: None,
724 enumm: None,
725 },
726 Field {
727 name: "awd1ch",
728 description: Some("AWD1CH."),
729 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 26 }),
730 bit_size: 5,
731 array: None,
732 enumm: None,
733 },
734 ],
735 },
736 FieldSet {
737 name: "Adc4Cfgr2",
738 extends: None,
739 description: Some("ADC configuration register 2."),
740 bit_size: 32,
741 fields: &[
742 Field {
743 name: "ovse",
744 description: Some("OVSE."),
745 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
746 bit_size: 1,
747 array: None,
748 enumm: None,
749 },
750 Field {
751 name: "ovsr",
752 description: Some("OVSR."),
753 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
754 bit_size: 3,
755 array: None,
756 enumm: Some("Adc4OversamplingRatio"),
757 },
758 Field {
759 name: "ovss",
760 description: Some("OVSS."),
761 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
762 bit_size: 4,
763 array: None,
764 enumm: None,
765 },
766 Field {
767 name: "tovs",
768 description: Some("TOVS."),
769 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
770 bit_size: 1,
771 array: None,
772 enumm: None,
773 },
774 Field {
775 name: "lftrig",
776 description: Some("LFTRIG."),
777 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 29 }),
778 bit_size: 1,
779 array: None,
780 enumm: None,
781 },
782 ],
783 },
784 FieldSet {
785 name: "Adc4Chselrmod0",
786 extends: None,
787 description: Some("ADC channel selection register [alternate]."),
788 bit_size: 32,
789 fields: &[Field {
790 name: "chsel",
791 description: Some("CHSEL."),
792 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
793 bit_size: 1,
794 array: Some(Array::Regular(RegularArray { len: 24, stride: 1 })),
795 enumm: None,
796 }],
797 },
798 FieldSet {
799 name: "Adc4Chselrmod1",
800 extends: None,
801 description: Some("ADC channel selection register [alternate]."),
802 bit_size: 32,
803 fields: &[Field {
804 name: "sq",
805 description: Some("SQ"),
806 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
807 bit_size: 4,
808 array: Some(Array::Regular(RegularArray { len: 8, stride: 4 })),
809 enumm: None,
810 }],
811 },
812 FieldSet {
813 name: "Adc4Cr",
814 extends: None,
815 description: Some("ADC control register."),
816 bit_size: 32,
817 fields: &[
818 Field {
819 name: "aden",
820 description: Some("ADEN."),
821 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
822 bit_size: 1,
823 array: None,
824 enumm: None,
825 },
826 Field {
827 name: "addis",
828 description: Some("ADDIS."),
829 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
830 bit_size: 1,
831 array: None,
832 enumm: None,
833 },
834 Field {
835 name: "adstart",
836 description: Some("ADSTART."),
837 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
838 bit_size: 1,
839 array: None,
840 enumm: None,
841 },
842 Field {
843 name: "adstp",
844 description: Some("ADSTP."),
845 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
846 bit_size: 1,
847 array: None,
848 enumm: None,
849 },
850 Field {
851 name: "advregen",
852 description: Some("ADVREGEN."),
853 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 28 }),
854 bit_size: 1,
855 array: None,
856 enumm: None,
857 },
858 Field {
859 name: "adcal",
860 description: Some("ADCAL."),
861 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 31 }),
862 bit_size: 1,
863 array: None,
864 enumm: None,
865 },
866 ],
867 },
868 FieldSet {
869 name: "Adc4Dr",
870 extends: None,
871 description: Some("ADC data register."),
872 bit_size: 32,
873 fields: &[Field {
874 name: "data",
875 description: Some("DATA."),
876 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
877 bit_size: 16,
878 array: None,
879 enumm: None,
880 }],
881 },
882 FieldSet {
883 name: "Adc4Ier",
884 extends: None,
885 description: Some("ADC interrupt enable register."),
886 bit_size: 32,
887 fields: &[
888 Field {
889 name: "adrdyie",
890 description: Some("ADRDYIE."),
891 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
892 bit_size: 1,
893 array: None,
894 enumm: None,
895 },
896 Field {
897 name: "eosmpie",
898 description: Some("EOSMPIE."),
899 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
900 bit_size: 1,
901 array: None,
902 enumm: None,
903 },
904 Field {
905 name: "eocie",
906 description: Some("EOCIE."),
907 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
908 bit_size: 1,
909 array: None,
910 enumm: None,
911 },
912 Field {
913 name: "eosie",
914 description: Some("EOSIE."),
915 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
916 bit_size: 1,
917 array: None,
918 enumm: None,
919 },
920 Field {
921 name: "ovrie",
922 description: Some("OVRIE."),
923 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
924 bit_size: 1,
925 array: None,
926 enumm: None,
927 },
928 Field {
929 name: "awdie",
930 description: Some("AWD1IE."),
931 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 7 }),
932 bit_size: 1,
933 array: Some(Array::Regular(RegularArray { len: 3, stride: 1 })),
934 enumm: None,
935 },
936 Field {
937 name: "eocalie",
938 description: Some("EOCALIE."),
939 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 11 }),
940 bit_size: 1,
941 array: None,
942 enumm: None,
943 },
944 Field {
945 name: "ldordyie",
946 description: Some("LDORDYIE."),
947 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
948 bit_size: 1,
949 array: None,
950 enumm: None,
951 },
952 ],
953 },
954 FieldSet {
955 name: "Adc4Isr",
956 extends: None,
957 description: Some("ADC interrupt and status register."),
958 bit_size: 32,
959 fields: &[
960 Field {
961 name: "adrdy",
962 description: Some("ADRDY."),
963 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
964 bit_size: 1,
965 array: None,
966 enumm: None,
967 },
968 Field {
969 name: "eosmp",
970 description: Some("EOSMP."),
971 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
972 bit_size: 1,
973 array: None,
974 enumm: None,
975 },
976 Field {
977 name: "eoc",
978 description: Some("EOC."),
979 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
980 bit_size: 1,
981 array: None,
982 enumm: None,
983 },
984 Field {
985 name: "eos",
986 description: Some("EOS."),
987 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
988 bit_size: 1,
989 array: None,
990 enumm: None,
991 },
992 Field {
993 name: "ovr",
994 description: Some("OVR."),
995 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
996 bit_size: 1,
997 array: None,
998 enumm: None,
999 },
1000 Field {
1001 name: "awd",
1002 description: Some("AWD1."),
1003 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 7 }),
1004 bit_size: 1,
1005 array: Some(Array::Regular(RegularArray { len: 3, stride: 1 })),
1006 enumm: None,
1007 },
1008 Field {
1009 name: "eocal",
1010 description: Some("EOCAL."),
1011 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 11 }),
1012 bit_size: 1,
1013 array: None,
1014 enumm: None,
1015 },
1016 Field {
1017 name: "ldordy",
1018 description: Some("LDORDY."),
1019 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
1020 bit_size: 1,
1021 array: None,
1022 enumm: None,
1023 },
1024 ],
1025 },
1026 FieldSet {
1027 name: "Adc4Or",
1028 extends: None,
1029 description: Some("ADC option register."),
1030 bit_size: 32,
1031 fields: &[Field {
1032 name: "chn21sel",
1033 description: Some("CHN21SEL."),
1034 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1035 bit_size: 1,
1036 array: None,
1037 enumm: None,
1038 }],
1039 },
1040 FieldSet {
1041 name: "Adc4Pwrr",
1042 extends: None,
1043 description: Some("ADC data register."),
1044 bit_size: 32,
1045 fields: &[
1046 Field {
1047 name: "autoff",
1048 description: Some("AUTOFF."),
1049 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1050 bit_size: 1,
1051 array: None,
1052 enumm: None,
1053 },
1054 Field {
1055 name: "dpd",
1056 description: Some("DPD."),
1057 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
1058 bit_size: 1,
1059 array: None,
1060 enumm: None,
1061 },
1062 Field {
1063 name: "vrefprot",
1064 description: Some("VREFPROT."),
1065 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
1066 bit_size: 1,
1067 array: None,
1068 enumm: None,
1069 },
1070 Field {
1071 name: "vrefsecsmp",
1072 description: Some("VREFSECSMP."),
1073 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
1074 bit_size: 1,
1075 array: None,
1076 enumm: None,
1077 },
1078 ],
1079 },
1080 FieldSet {
1081 name: "Adc4Smpr",
1082 extends: None,
1083 description: Some("ADC sample time register."),
1084 bit_size: 32,
1085 fields: &[
1086 Field {
1087 name: "smp",
1088 description: Some("SMP1."),
1089 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1090 bit_size: 3,
1091 array: Some(Array::Regular(RegularArray { len: 2, stride: 4 })),
1092 enumm: Some("Adc4SampleTime"),
1093 },
1094 Field {
1095 name: "smpsel",
1096 description: Some("SMPSEL0."),
1097 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
1098 bit_size: 1,
1099 array: Some(Array::Regular(RegularArray { len: 24, stride: 1 })),
1100 enumm: None,
1101 },
1102 ],
1103 },
1104 FieldSet {
1105 name: "Awd2cr",
1106 extends: None,
1107 description: Some("ADC analog watchdog 2 configuration register."),
1108 bit_size: 32,
1109 fields: &[Field {
1110 name: "awd2ch",
1111 description: Some("AWD2CH."),
1112 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1113 bit_size: 1,
1114 array: Some(Array::Regular(RegularArray { len: 20, stride: 1 })),
1115 enumm: None,
1116 }],
1117 },
1118 FieldSet {
1119 name: "Awd3cr",
1120 extends: None,
1121 description: Some("ADC analog watchdog 3 configuration register."),
1122 bit_size: 32,
1123 fields: &[Field {
1124 name: "awd3ch",
1125 description: Some("AWD3CH."),
1126 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1127 bit_size: 1,
1128 array: Some(Array::Regular(RegularArray { len: 20, stride: 1 })),
1129 enumm: None,
1130 }],
1131 },
1132 FieldSet {
1133 name: "Calfact",
1134 extends: None,
1135 description: Some("ADC user control register."),
1136 bit_size: 32,
1137 fields: &[
1138 Field {
1139 name: "i_apb_addr",
1140 description: Some("I_APB_ADDR."),
1141 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1142 bit_size: 8,
1143 array: None,
1144 enumm: None,
1145 },
1146 Field {
1147 name: "i_apb_data",
1148 description: Some("I_APB_DATA."),
1149 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
1150 bit_size: 8,
1151 array: None,
1152 enumm: None,
1153 },
1154 Field {
1155 name: "validity",
1156 description: Some("VALIDITY."),
1157 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
1158 bit_size: 1,
1159 array: None,
1160 enumm: None,
1161 },
1162 Field {
1163 name: "latch_coef",
1164 description: Some("LATCH_COEF."),
1165 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
1166 bit_size: 1,
1167 array: None,
1168 enumm: None,
1169 },
1170 Field {
1171 name: "capture_coef",
1172 description: Some("CAPTURE_COEF."),
1173 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 25 }),
1174 bit_size: 1,
1175 array: None,
1176 enumm: None,
1177 },
1178 ],
1179 },
1180 FieldSet {
1181 name: "Calfact2",
1182 extends: None,
1183 description: Some("ADC calibration factor register."),
1184 bit_size: 32,
1185 fields: &[Field {
1186 name: "calfact",
1187 description: Some("CALFACT."),
1188 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1189 bit_size: 32,
1190 array: None,
1191 enumm: None,
1192 }],
1193 },
1194 FieldSet {
1195 name: "Cfgr",
1196 extends: None,
1197 description: Some("ADC configuration register."),
1198 bit_size: 32,
1199 fields: &[
1200 Field {
1201 name: "dmngt",
1202 description: Some("DMNGT."),
1203 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1204 bit_size: 2,
1205 array: None,
1206 enumm: Some("Dmngt"),
1207 },
1208 Field {
1209 name: "res",
1210 description: Some("RES."),
1211 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
1212 bit_size: 2,
1213 array: None,
1214 enumm: Some("Res"),
1215 },
1216 Field {
1217 name: "extsel",
1218 description: Some("EXTSEL."),
1219 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
1220 bit_size: 5,
1221 array: None,
1222 enumm: None,
1223 },
1224 Field {
1225 name: "exten",
1226 description: Some("EXTEN."),
1227 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 10 }),
1228 bit_size: 2,
1229 array: None,
1230 enumm: Some("Exten"),
1231 },
1232 Field {
1233 name: "ovrmod",
1234 description: Some("OVRMOD."),
1235 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
1236 bit_size: 1,
1237 array: None,
1238 enumm: None,
1239 },
1240 Field {
1241 name: "cont",
1242 description: Some("CONT."),
1243 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 13 }),
1244 bit_size: 1,
1245 array: None,
1246 enumm: None,
1247 },
1248 Field {
1249 name: "autdly",
1250 description: Some("AUTDLY."),
1251 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }),
1252 bit_size: 1,
1253 array: None,
1254 enumm: None,
1255 },
1256 Field {
1257 name: "discen",
1258 description: Some("DISCEN."),
1259 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
1260 bit_size: 1,
1261 array: None,
1262 enumm: None,
1263 },
1264 Field {
1265 name: "discnum",
1266 description: Some("DISCNUM."),
1267 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 17 }),
1268 bit_size: 3,
1269 array: None,
1270 enumm: None,
1271 },
1272 Field {
1273 name: "jdiscen",
1274 description: Some("JDISCEN."),
1275 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 20 }),
1276 bit_size: 1,
1277 array: None,
1278 enumm: None,
1279 },
1280 Field {
1281 name: "awd1sgl",
1282 description: Some("AWD1SGL."),
1283 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 22 }),
1284 bit_size: 1,
1285 array: None,
1286 enumm: None,
1287 },
1288 Field {
1289 name: "awd1en",
1290 description: Some("AWD1EN."),
1291 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 23 }),
1292 bit_size: 1,
1293 array: None,
1294 enumm: None,
1295 },
1296 Field {
1297 name: "jawd1en",
1298 description: Some("JAWD1EN."),
1299 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
1300 bit_size: 1,
1301 array: None,
1302 enumm: None,
1303 },
1304 Field {
1305 name: "jauto",
1306 description: Some("JAUTO."),
1307 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 25 }),
1308 bit_size: 1,
1309 array: None,
1310 enumm: None,
1311 },
1312 Field {
1313 name: "awd1ch",
1314 description: Some("AWD1CH."),
1315 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 26 }),
1316 bit_size: 5,
1317 array: None,
1318 enumm: None,
1319 },
1320 ],
1321 },
1322 FieldSet {
1323 name: "Cfgr2",
1324 extends: None,
1325 description: Some("ADC configuration register 2."),
1326 bit_size: 32,
1327 fields: &[
1328 Field {
1329 name: "rovse",
1330 description: Some("ROVSE."),
1331 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1332 bit_size: 1,
1333 array: None,
1334 enumm: None,
1335 },
1336 Field {
1337 name: "jovse",
1338 description: Some("JOVSE."),
1339 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
1340 bit_size: 1,
1341 array: None,
1342 enumm: None,
1343 },
1344 Field {
1345 name: "ovss",
1346 description: Some("OVSS."),
1347 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
1348 bit_size: 4,
1349 array: None,
1350 enumm: None,
1351 },
1352 Field {
1353 name: "trovs",
1354 description: Some("TROVS."),
1355 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
1356 bit_size: 1,
1357 array: None,
1358 enumm: None,
1359 },
1360 Field {
1361 name: "rovsm",
1362 description: Some("ROVSM."),
1363 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 10 }),
1364 bit_size: 1,
1365 array: None,
1366 enumm: None,
1367 },
1368 Field {
1369 name: "bulb",
1370 description: Some("BULB."),
1371 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 13 }),
1372 bit_size: 1,
1373 array: None,
1374 enumm: None,
1375 },
1376 Field {
1377 name: "swtrig",
1378 description: Some("SWTRIG."),
1379 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }),
1380 bit_size: 1,
1381 array: None,
1382 enumm: None,
1383 },
1384 Field {
1385 name: "smptrig",
1386 description: Some("SMPTRIG."),
1387 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 15 }),
1388 bit_size: 1,
1389 array: None,
1390 enumm: None,
1391 },
1392 Field {
1393 name: "osvr",
1394 description: Some("OSVR."),
1395 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
1396 bit_size: 10,
1397 array: None,
1398 enumm: None,
1399 },
1400 Field {
1401 name: "lftrig",
1402 description: Some("LFTRIG."),
1403 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 27 }),
1404 bit_size: 1,
1405 array: None,
1406 enumm: None,
1407 },
1408 Field {
1409 name: "lshift",
1410 description: Some("LSHIFT."),
1411 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 28 }),
1412 bit_size: 4,
1413 array: None,
1414 enumm: None,
1415 },
1416 ],
1417 },
1418 FieldSet {
1419 name: "Cr",
1420 extends: None,
1421 description: Some("ADC control register."),
1422 bit_size: 32,
1423 fields: &[
1424 Field {
1425 name: "aden",
1426 description: Some("ADEN."),
1427 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1428 bit_size: 1,
1429 array: None,
1430 enumm: None,
1431 },
1432 Field {
1433 name: "addis",
1434 description: Some("ADDIS."),
1435 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
1436 bit_size: 1,
1437 array: None,
1438 enumm: None,
1439 },
1440 Field {
1441 name: "adstart",
1442 description: Some("ADSTART."),
1443 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
1444 bit_size: 1,
1445 array: None,
1446 enumm: None,
1447 },
1448 Field {
1449 name: "jadstart",
1450 description: Some("JADSTART."),
1451 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
1452 bit_size: 1,
1453 array: None,
1454 enumm: None,
1455 },
1456 Field {
1457 name: "adstp",
1458 description: Some("ADSTP."),
1459 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
1460 bit_size: 1,
1461 array: None,
1462 enumm: Some("Adstp"),
1463 },
1464 Field {
1465 name: "jadstp",
1466 description: Some("JADSTP."),
1467 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
1468 bit_size: 1,
1469 array: None,
1470 enumm: None,
1471 },
1472 Field {
1473 name: "adcallin",
1474 description: Some("ADCALLIN."),
1475 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
1476 bit_size: 1,
1477 array: None,
1478 enumm: None,
1479 },
1480 Field {
1481 name: "calindex",
1482 description: Some("CALINDEX."),
1483 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
1484 bit_size: 4,
1485 array: None,
1486 enumm: None,
1487 },
1488 Field {
1489 name: "advregen",
1490 description: Some("ADVREGEN."),
1491 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 28 }),
1492 bit_size: 1,
1493 array: None,
1494 enumm: None,
1495 },
1496 Field {
1497 name: "deeppwd",
1498 description: Some("DEEPPWD."),
1499 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 29 }),
1500 bit_size: 1,
1501 array: None,
1502 enumm: None,
1503 },
1504 Field {
1505 name: "adcal",
1506 description: Some("ADCAL."),
1507 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 31 }),
1508 bit_size: 1,
1509 array: None,
1510 enumm: None,
1511 },
1512 ],
1513 },
1514 FieldSet {
1515 name: "Difsel",
1516 extends: None,
1517 description: Some("ADC differential mode selection register."),
1518 bit_size: 32,
1519 fields: &[Field {
1520 name: "difsel",
1521 description: Some("channel differential or single-ended mode for channel"),
1522 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1523 bit_size: 1,
1524 array: Some(Array::Regular(RegularArray { len: 20, stride: 1 })),
1525 enumm: Some("Difsel"),
1526 }],
1527 },
1528 FieldSet {
1529 name: "Dr",
1530 extends: None,
1531 description: Some("ADC regular Data Register."),
1532 bit_size: 32,
1533 fields: &[Field {
1534 name: "rdata",
1535 description: Some("RDATA."),
1536 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1537 bit_size: 32,
1538 array: None,
1539 enumm: None,
1540 }],
1541 },
1542 FieldSet {
1543 name: "Gcomp",
1544 extends: None,
1545 description: Some("ADC gain compensation register."),
1546 bit_size: 32,
1547 fields: &[
1548 Field {
1549 name: "gcompcoeff",
1550 description: Some("GCOMPCOEFF."),
1551 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1552 bit_size: 14,
1553 array: None,
1554 enumm: None,
1555 },
1556 Field {
1557 name: "gcomp",
1558 description: Some("GCOMP."),
1559 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 31 }),
1560 bit_size: 1,
1561 array: None,
1562 enumm: None,
1563 },
1564 ],
1565 },
1566 FieldSet {
1567 name: "Htr1",
1568 extends: None,
1569 description: Some("ADC watchdog threshold register 1."),
1570 bit_size: 32,
1571 fields: &[
1572 Field {
1573 name: "htr1",
1574 description: Some("HTR1."),
1575 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1576 bit_size: 25,
1577 array: None,
1578 enumm: None,
1579 },
1580 Field {
1581 name: "awdfilt1",
1582 description: Some("AWDFILT1."),
1583 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 29 }),
1584 bit_size: 3,
1585 array: None,
1586 enumm: None,
1587 },
1588 ],
1589 },
1590 FieldSet {
1591 name: "Htr2",
1592 extends: None,
1593 description: Some("ADC watchdog higher threshold register 2."),
1594 bit_size: 32,
1595 fields: &[Field {
1596 name: "htr2",
1597 description: Some("HTR2."),
1598 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1599 bit_size: 25,
1600 array: None,
1601 enumm: None,
1602 }],
1603 },
1604 FieldSet {
1605 name: "Htr3",
1606 extends: None,
1607 description: Some("ADC watchdog higher threshold register 3."),
1608 bit_size: 32,
1609 fields: &[Field {
1610 name: "htr3",
1611 description: Some("HTR3."),
1612 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1613 bit_size: 25,
1614 array: None,
1615 enumm: None,
1616 }],
1617 },
1618 FieldSet {
1619 name: "Ier",
1620 extends: None,
1621 description: Some("ADC interrupt enable register."),
1622 bit_size: 32,
1623 fields: &[
1624 Field {
1625 name: "adrdyie",
1626 description: Some("ADRDYIE."),
1627 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1628 bit_size: 1,
1629 array: None,
1630 enumm: None,
1631 },
1632 Field {
1633 name: "eosmpie",
1634 description: Some("EOSMPIE."),
1635 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
1636 bit_size: 1,
1637 array: None,
1638 enumm: None,
1639 },
1640 Field {
1641 name: "eocie",
1642 description: Some("EOCIE."),
1643 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
1644 bit_size: 1,
1645 array: None,
1646 enumm: None,
1647 },
1648 Field {
1649 name: "eosie",
1650 description: Some("EOSIE."),
1651 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
1652 bit_size: 1,
1653 array: None,
1654 enumm: None,
1655 },
1656 Field {
1657 name: "ovrie",
1658 description: Some("OVRIE."),
1659 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
1660 bit_size: 1,
1661 array: None,
1662 enumm: None,
1663 },
1664 Field {
1665 name: "jeocie",
1666 description: Some("JEOCIE."),
1667 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
1668 bit_size: 1,
1669 array: None,
1670 enumm: None,
1671 },
1672 Field {
1673 name: "jeosie",
1674 description: Some("JEOSIE."),
1675 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 6 }),
1676 bit_size: 1,
1677 array: None,
1678 enumm: None,
1679 },
1680 Field {
1681 name: "awdie",
1682 description: Some("AWD1IE."),
1683 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 7 }),
1684 bit_size: 1,
1685 array: Some(Array::Regular(RegularArray { len: 3, stride: 1 })),
1686 enumm: None,
1687 },
1688 ],
1689 },
1690 FieldSet {
1691 name: "Isr",
1692 extends: None,
1693 description: Some("ADC interrupt and status register."),
1694 bit_size: 32,
1695 fields: &[
1696 Field {
1697 name: "adrdy",
1698 description: Some("ADRDY."),
1699 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1700 bit_size: 1,
1701 array: None,
1702 enumm: None,
1703 },
1704 Field {
1705 name: "eosmp",
1706 description: Some("EOSMP."),
1707 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
1708 bit_size: 1,
1709 array: None,
1710 enumm: None,
1711 },
1712 Field {
1713 name: "eoc",
1714 description: Some("EOC."),
1715 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
1716 bit_size: 1,
1717 array: None,
1718 enumm: None,
1719 },
1720 Field {
1721 name: "eos",
1722 description: Some("EOS."),
1723 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
1724 bit_size: 1,
1725 array: None,
1726 enumm: None,
1727 },
1728 Field {
1729 name: "ovr",
1730 description: Some("OVR."),
1731 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
1732 bit_size: 1,
1733 array: None,
1734 enumm: None,
1735 },
1736 Field {
1737 name: "jeoc",
1738 description: Some("JEOC."),
1739 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
1740 bit_size: 1,
1741 array: None,
1742 enumm: None,
1743 },
1744 Field {
1745 name: "jeos",
1746 description: Some("JEOS."),
1747 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 6 }),
1748 bit_size: 1,
1749 array: None,
1750 enumm: None,
1751 },
1752 Field {
1753 name: "awd",
1754 description: Some("AWD1."),
1755 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 7 }),
1756 bit_size: 1,
1757 array: Some(Array::Regular(RegularArray { len: 3, stride: 1 })),
1758 enumm: None,
1759 },
1760 Field {
1761 name: "ldordy",
1762 description: Some("LDORDY."),
1763 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
1764 bit_size: 1,
1765 array: None,
1766 enumm: None,
1767 },
1768 ],
1769 },
1770 FieldSet {
1771 name: "Jdr",
1772 extends: None,
1773 description: Some("ADC injected data register."),
1774 bit_size: 32,
1775 fields: &[Field {
1776 name: "jdata",
1777 description: Some("JDATA."),
1778 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1779 bit_size: 32,
1780 array: None,
1781 enumm: None,
1782 }],
1783 },
1784 FieldSet {
1785 name: "Jsqr",
1786 extends: None,
1787 description: Some("ADC injected sequence register."),
1788 bit_size: 32,
1789 fields: &[
1790 Field {
1791 name: "jl",
1792 description: Some("JL."),
1793 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1794 bit_size: 2,
1795 array: None,
1796 enumm: None,
1797 },
1798 Field {
1799 name: "jextsel",
1800 description: Some("JEXTSEL."),
1801 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
1802 bit_size: 5,
1803 array: None,
1804 enumm: None,
1805 },
1806 Field {
1807 name: "jexten",
1808 description: Some("JEXTEN."),
1809 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 7 }),
1810 bit_size: 2,
1811 array: None,
1812 enumm: None,
1813 },
1814 Field {
1815 name: "jsq",
1816 description: Some("JSQ1."),
1817 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
1818 bit_size: 5,
1819 array: Some(Array::Regular(RegularArray { len: 4, stride: 6 })),
1820 enumm: None,
1821 },
1822 ],
1823 },
1824 FieldSet {
1825 name: "Ltr1",
1826 extends: None,
1827 description: Some("ADC watchdog threshold register 1."),
1828 bit_size: 32,
1829 fields: &[Field {
1830 name: "ltr1",
1831 description: Some("LTR1."),
1832 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1833 bit_size: 25,
1834 array: None,
1835 enumm: None,
1836 }],
1837 },
1838 FieldSet {
1839 name: "Ltr2",
1840 extends: None,
1841 description: Some("ADC watchdog lower threshold register 2."),
1842 bit_size: 32,
1843 fields: &[Field {
1844 name: "ltr2",
1845 description: Some("LTR2."),
1846 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1847 bit_size: 25,
1848 array: None,
1849 enumm: None,
1850 }],
1851 },
1852 FieldSet {
1853 name: "Ltr3",
1854 extends: None,
1855 description: Some("ADC watchdog lower threshold register 3."),
1856 bit_size: 32,
1857 fields: &[Field {
1858 name: "ltr3",
1859 description: Some("LTR3."),
1860 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1861 bit_size: 25,
1862 array: None,
1863 enumm: None,
1864 }],
1865 },
1866 FieldSet {
1867 name: "Ofr",
1868 extends: None,
1869 description: Some("ADC offset register."),
1870 bit_size: 32,
1871 fields: &[
1872 Field {
1873 name: "offset",
1874 description: Some("OFFSET."),
1875 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1876 bit_size: 24,
1877 array: None,
1878 enumm: None,
1879 },
1880 Field {
1881 name: "posoff",
1882 description: Some("POSOFF."),
1883 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
1884 bit_size: 1,
1885 array: None,
1886 enumm: None,
1887 },
1888 Field {
1889 name: "usat",
1890 description: Some("USAT."),
1891 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 25 }),
1892 bit_size: 1,
1893 array: None,
1894 enumm: None,
1895 },
1896 Field {
1897 name: "ssat",
1898 description: Some("SSAT."),
1899 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 26 }),
1900 bit_size: 1,
1901 array: None,
1902 enumm: None,
1903 },
1904 Field {
1905 name: "offset_ch",
1906 description: Some("OFFSET_CH."),
1907 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 27 }),
1908 bit_size: 5,
1909 array: None,
1910 enumm: None,
1911 },
1912 ],
1913 },
1914 FieldSet {
1915 name: "Pcsel",
1916 extends: None,
1917 description: Some("ADC channel preselection register."),
1918 bit_size: 32,
1919 fields: &[Field {
1920 name: "pcsel",
1921 description: Some("PCSEL."),
1922 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1923 bit_size: 1,
1924 array: Some(Array::Regular(RegularArray { len: 20, stride: 1 })),
1925 enumm: Some("Pcsel"),
1926 }],
1927 },
1928 FieldSet {
1929 name: "Smpr",
1930 extends: None,
1931 description: Some("ADC sample time register 1."),
1932 bit_size: 32,
1933 fields: &[Field {
1934 name: "smp",
1935 description: Some("SMP0."),
1936 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1937 bit_size: 3,
1938 array: Some(Array::Regular(RegularArray { len: 10, stride: 3 })),
1939 enumm: Some("SampleTime"),
1940 }],
1941 },
1942 FieldSet {
1943 name: "Sqr1",
1944 extends: None,
1945 description: Some("ADC regular sequence register 1."),
1946 bit_size: 32,
1947 fields: &[
1948 Field {
1949 name: "l",
1950 description: Some("L."),
1951 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1952 bit_size: 4,
1953 array: None,
1954 enumm: None,
1955 },
1956 Field {
1957 name: "sq",
1958 description: Some("SQ1."),
1959 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 6 }),
1960 bit_size: 5,
1961 array: Some(Array::Regular(RegularArray { len: 4, stride: 6 })),
1962 enumm: None,
1963 },
1964 ],
1965 },
1966 FieldSet {
1967 name: "Sqr2",
1968 extends: None,
1969 description: Some("ADC regular sequence register 2."),
1970 bit_size: 32,
1971 fields: &[Field {
1972 name: "sq",
1973 description: Some("SQ5."),
1974 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1975 bit_size: 5,
1976 array: Some(Array::Regular(RegularArray { len: 5, stride: 6 })),
1977 enumm: None,
1978 }],
1979 },
1980 FieldSet {
1981 name: "Sqr3",
1982 extends: None,
1983 description: Some("ADC regular sequence register 3."),
1984 bit_size: 32,
1985 fields: &[Field {
1986 name: "sq",
1987 description: Some("SQ10."),
1988 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
1989 bit_size: 5,
1990 array: Some(Array::Regular(RegularArray { len: 5, stride: 6 })),
1991 enumm: None,
1992 }],
1993 },
1994 FieldSet {
1995 name: "Sqr4",
1996 extends: None,
1997 description: Some("ADC regular sequence register 4."),
1998 bit_size: 32,
1999 fields: &[Field {
2000 name: "sq",
2001 description: Some("SQ15."),
2002 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
2003 bit_size: 5,
2004 array: Some(Array::Regular(RegularArray { len: 2, stride: 6 })),
2005 enumm: None,
2006 }],
2007 },
2008 ],
2009 enums: &[
2010 Enum {
2011 name: "Adc4Dmacfg",
2012 description: None,
2013 bit_size: 1,
2014 variants: &[
2015 EnumVariant {
2016 name: "ONE_SHOT",
2017 description: Some("DMA One Shot mode selected"),
2018 value: 0,
2019 },
2020 EnumVariant {
2021 name: "CIRCULAR",
2022 description: Some("DMA Circular mode selected"),
2023 value: 1,
2024 },
2025 ],
2026 },
2027 Enum {
2028 name: "Adc4Exten",
2029 description: None,
2030 bit_size: 2,
2031 variants: &[
2032 EnumVariant {
2033 name: "DISABLED",
2034 description: Some("Trigger detection disabled"),
2035 value: 0,
2036 },
2037 EnumVariant {
2038 name: "RISING_EDGE",
2039 description: Some("Trigger detection on the rising edge"),
2040 value: 1,
2041 },
2042 EnumVariant {
2043 name: "FALLING_EDGE",
2044 description: Some("Trigger detection on the falling edge"),
2045 value: 2,
2046 },
2047 EnumVariant {
2048 name: "BOTH_EDGES",
2049 description: Some("Trigger detection on both the rising and falling edges"),
2050 value: 3,
2051 },
2052 ],
2053 },
2054 Enum {
2055 name: "Adc4OversamplingRatio",
2056 description: None,
2057 bit_size: 3,
2058 variants: &[
2059 EnumVariant {
2060 name: "OVERSAMPLE2X",
2061 description: Some("Oversample 2 times"),
2062 value: 0,
2063 },
2064 EnumVariant {
2065 name: "OVERSAMPLE4X",
2066 description: Some("Oversample 4 times"),
2067 value: 1,
2068 },
2069 EnumVariant {
2070 name: "OVERSAMPLE8X",
2071 description: Some("Oversample 8 times"),
2072 value: 2,
2073 },
2074 EnumVariant {
2075 name: "OVERSAMPLE16X",
2076 description: Some("Oversample 16 times"),
2077 value: 3,
2078 },
2079 EnumVariant {
2080 name: "OVERSAMPLE32X",
2081 description: Some("Oversample 32 times"),
2082 value: 4,
2083 },
2084 EnumVariant {
2085 name: "OVERSAMPLE64X",
2086 description: Some("Oversample 64 times"),
2087 value: 5,
2088 },
2089 EnumVariant {
2090 name: "OVERSAMPLE128X",
2091 description: Some("Oversample 128 times"),
2092 value: 6,
2093 },
2094 EnumVariant {
2095 name: "OVERSAMPLE256X",
2096 description: Some("Oversample 256 times"),
2097 value: 7,
2098 },
2099 ],
2100 },
2101 Enum {
2102 name: "Adc4Presc",
2103 description: None,
2104 bit_size: 4,
2105 variants: &[
2106 EnumVariant {
2107 name: "DIV1",
2108 description: Some("adc_ker_ck_input not divided"),
2109 value: 0,
2110 },
2111 EnumVariant {
2112 name: "DIV2",
2113 description: Some("adc_ker_ck_input divided by 2"),
2114 value: 1,
2115 },
2116 EnumVariant {
2117 name: "DIV4",
2118 description: Some("adc_ker_ck_input divided by 4"),
2119 value: 2,
2120 },
2121 EnumVariant {
2122 name: "DIV6",
2123 description: Some("adc_ker_ck_input divided by 6"),
2124 value: 3,
2125 },
2126 EnumVariant {
2127 name: "DIV8",
2128 description: Some("adc_ker_ck_input divided by 8"),
2129 value: 4,
2130 },
2131 EnumVariant {
2132 name: "DIV10",
2133 description: Some("adc_ker_ck_input divided by 10"),
2134 value: 5,
2135 },
2136 EnumVariant {
2137 name: "DIV12",
2138 description: Some("adc_ker_ck_input divided by 12"),
2139 value: 6,
2140 },
2141 EnumVariant {
2142 name: "DIV16",
2143 description: Some("adc_ker_ck_input divided by 16"),
2144 value: 7,
2145 },
2146 EnumVariant {
2147 name: "DIV32",
2148 description: Some("adc_ker_ck_input divided by 32"),
2149 value: 8,
2150 },
2151 EnumVariant {
2152 name: "DIV64",
2153 description: Some("adc_ker_ck_input divided by 64"),
2154 value: 9,
2155 },
2156 EnumVariant {
2157 name: "DIV128",
2158 description: Some("adc_ker_ck_input divided by 128"),
2159 value: 10,
2160 },
2161 EnumVariant {
2162 name: "DIV256",
2163 description: Some("adc_ker_ck_input divided by 256"),
2164 value: 11,
2165 },
2166 ],
2167 },
2168 Enum {
2169 name: "Adc4Res",
2170 description: None,
2171 bit_size: 2,
2172 variants: &[
2173 EnumVariant {
2174 name: "BITS12",
2175 description: Some("12-bit resolution"),
2176 value: 0,
2177 },
2178 EnumVariant {
2179 name: "BITS10",
2180 description: Some("10-bit resolution"),
2181 value: 1,
2182 },
2183 EnumVariant {
2184 name: "BITS8",
2185 description: Some("8-bit resolution"),
2186 value: 2,
2187 },
2188 EnumVariant {
2189 name: "BITS6",
2190 description: Some("6-bit resolution"),
2191 value: 3,
2192 },
2193 ],
2194 },
2195 Enum {
2196 name: "Adc4SampleTime",
2197 description: None,
2198 bit_size: 3,
2199 variants: &[
2200 EnumVariant {
2201 name: "CYCLES1_5",
2202 description: Some("1.5 ADC cycles"),
2203 value: 0,
2204 },
2205 EnumVariant {
2206 name: "CYCLES3_5",
2207 description: Some("3.5 ADC cycles"),
2208 value: 1,
2209 },
2210 EnumVariant {
2211 name: "CYCLES7_5",
2212 description: Some("7.5 ADC cycles"),
2213 value: 2,
2214 },
2215 EnumVariant {
2216 name: "CYCLES12_5",
2217 description: Some("12.5 ADC cycles"),
2218 value: 3,
2219 },
2220 EnumVariant {
2221 name: "CYCLES19_5",
2222 description: Some("19.5 ADC cycles"),
2223 value: 4,
2224 },
2225 EnumVariant {
2226 name: "CYCLES39_5",
2227 description: Some("39.5 ADC cycles"),
2228 value: 5,
2229 },
2230 EnumVariant {
2231 name: "CYCLES79_5",
2232 description: Some("79.5 ADC cycles"),
2233 value: 6,
2234 },
2235 EnumVariant {
2236 name: "CYCLES814_5",
2237 description: Some("160.5 ADC cycles"),
2238 value: 7,
2239 },
2240 ],
2241 },
2242 Enum {
2243 name: "Adstp",
2244 description: None,
2245 bit_size: 1,
2246 variants: &[EnumVariant {
2247 name: "STOP",
2248 description: Some("Stop conversion of channel"),
2249 value: 1,
2250 }],
2251 },
2252 Enum {
2253 name: "Difsel",
2254 description: None,
2255 bit_size: 1,
2256 variants: &[
2257 EnumVariant {
2258 name: "SINGLE_ENDED",
2259 description: Some("Input channel is configured in single-ended mode"),
2260 value: 0,
2261 },
2262 EnumVariant {
2263 name: "DIFFERENTIAL",
2264 description: Some("Input channel is configured in differential mode"),
2265 value: 1,
2266 },
2267 ],
2268 },
2269 Enum {
2270 name: "Dmngt",
2271 description: None,
2272 bit_size: 2,
2273 variants: &[
2274 EnumVariant {
2275 name: "DR",
2276 description: Some("Store output data in DR only"),
2277 value: 0,
2278 },
2279 EnumVariant {
2280 name: "DMA_ONE_SHOT",
2281 description: Some("DMA One Shot Mode selected"),
2282 value: 1,
2283 },
2284 EnumVariant {
2285 name: "MDF",
2286 description: Some("MDF mode selected"),
2287 value: 2,
2288 },
2289 EnumVariant {
2290 name: "DMA_CIRCULAR",
2291 description: Some("DMA Circular Mode selected"),
2292 value: 3,
2293 },
2294 ],
2295 },
2296 Enum {
2297 name: "Exten",
2298 description: None,
2299 bit_size: 2,
2300 variants: &[
2301 EnumVariant {
2302 name: "DISABLED",
2303 description: Some("Trigger detection disabled"),
2304 value: 0,
2305 },
2306 EnumVariant {
2307 name: "RISING_EDGE",
2308 description: Some("Trigger detection on the rising edge"),
2309 value: 1,
2310 },
2311 EnumVariant {
2312 name: "FALLING_EDGE",
2313 description: Some("Trigger detection on the falling edge"),
2314 value: 2,
2315 },
2316 EnumVariant {
2317 name: "BOTH_EDGES",
2318 description: Some("Trigger detection on both the rising and falling edges"),
2319 value: 3,
2320 },
2321 ],
2322 },
2323 Enum {
2324 name: "Pcsel",
2325 description: None,
2326 bit_size: 1,
2327 variants: &[
2328 EnumVariant {
2329 name: "NOT_PRESELECTED",
2330 description: Some("Input channel x is not pre-selected"),
2331 value: 0,
2332 },
2333 EnumVariant {
2334 name: "PRESELECTED",
2335 description: Some("Pre-select input channel x"),
2336 value: 1,
2337 },
2338 ],
2339 },
2340 Enum {
2341 name: "Res",
2342 description: None,
2343 bit_size: 2,
2344 variants: &[
2345 EnumVariant {
2346 name: "BITS14",
2347 description: Some("14-bit resolution"),
2348 value: 0,
2349 },
2350 EnumVariant {
2351 name: "BITS12",
2352 description: Some("12-bit resolution"),
2353 value: 1,
2354 },
2355 EnumVariant {
2356 name: "BITS10",
2357 description: Some("10-bit resolution"),
2358 value: 2,
2359 },
2360 EnumVariant {
2361 name: "BITS8",
2362 description: Some("8-bit resolution"),
2363 value: 3,
2364 },
2365 ],
2366 },
2367 Enum {
2368 name: "SampleTime",
2369 description: None,
2370 bit_size: 3,
2371 variants: &[
2372 EnumVariant {
2373 name: "CYCLES1_5",
2374 description: Some("1.5 ADC cycles"),
2375 value: 0,
2376 },
2377 EnumVariant {
2378 name: "CYCLES3_5",
2379 description: Some("3.5 ADC cycles"),
2380 value: 1,
2381 },
2382 EnumVariant {
2383 name: "CYCLES7_5",
2384 description: Some("7.5 ADC cycles"),
2385 value: 2,
2386 },
2387 EnumVariant {
2388 name: "CYCLES12_5",
2389 description: Some("12.5 ADC cycles"),
2390 value: 3,
2391 },
2392 EnumVariant {
2393 name: "CYCLES19_5",
2394 description: Some("19.5 ADC cycles"),
2395 value: 4,
2396 },
2397 EnumVariant {
2398 name: "CYCLES39_5",
2399 description: Some("39.5 ADC cycles"),
2400 value: 5,
2401 },
2402 EnumVariant {
2403 name: "CYCLES79_5",
2404 description: Some("79.5 ADC cycles"),
2405 value: 6,
2406 },
2407 EnumVariant {
2408 name: "CYCLES160_5",
2409 description: Some("160.5 ADC cycles"),
2410 value: 7,
2411 },
2412 ],
2413 },
2414 ],
2415};
2416