1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "AdcCommon",
7 extends: None,
8 description: Some(
9 "Analog-to-Digital Converter.",
10 ),
11 items: &[
12 BlockItem {
13 name: "csr",
14 description: Some(
15 "ADC common status register.",
16 ),
17 array: None,
18 byte_offset: 0x0,
19 inner: BlockItemInner::Register(
20 Register {
21 access: Access::Read,
22 bit_size: 32,
23 fieldset: Some(
24 "Csr",
25 ),
26 },
27 ),
28 },
29 BlockItem {
30 name: "ccr",
31 description: Some(
32 "ADC_CCR system control register.",
33 ),
34 array: None,
35 byte_offset: 0x8,
36 inner: BlockItemInner::Register(
37 Register {
38 access: Access::ReadWrite,
39 bit_size: 32,
40 fieldset: Some(
41 "Ccr",
42 ),
43 },
44 ),
45 },
46 BlockItem {
47 name: "cdr",
48 description: Some(
49 "ADC common regular data register for dual mode.",
50 ),
51 array: None,
52 byte_offset: 0xc,
53 inner: BlockItemInner::Register(
54 Register {
55 access: Access::Read,
56 bit_size: 32,
57 fieldset: Some(
58 "Cdr",
59 ),
60 },
61 ),
62 },
63 BlockItem {
64 name: "cdr2",
65 description: Some(
66 "ADC common regular data register for 32-bit dual mode.",
67 ),
68 array: None,
69 byte_offset: 0x10,
70 inner: BlockItemInner::Register(
71 Register {
72 access: Access::Read,
73 bit_size: 32,
74 fieldset: Some(
75 "Cdr2",
76 ),
77 },
78 ),
79 },
80 ],
81 },
82 ],
83 fieldsets: &[
84 FieldSet {
85 name: "Ccr",
86 extends: None,
87 description: Some(
88 "ADC_CCR system control register.",
89 ),
90 bit_size: 32,
91 fields: &[
92 Field {
93 name: "dual",
94 description: Some(
95 "Dual ADC mode selection These bits are written by software to select the operating mode. All the ADCs are independent: The configurations 00001 to 01001 correspond to the following operating modes: Dual mode, master and slave ADCs working together: All other combinations are reserved and must not be programmed Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL\u{a0}=\u{a0}0, JADSTART\u{a0}=\u{a0}0, ADSTART\u{a0}=\u{a0}0, ADSTP\u{a0}=\u{a0}0, ADDIS\u{a0}=\u{a0}0 and ADEN\u{a0}=\u{a0}0).",
96 ),
97 bit_offset: BitOffset::Regular(
98 RegularBitOffset {
99 offset: 0,
100 },
101 ),
102 bit_size: 5,
103 array: None,
104 enumm: Some(
105 "Dual",
106 ),
107 },
108 Field {
109 name: "delay",
110 description: Some(
111 "Delay between the end of the master ADC sampling phase and the beginning of the slave ADC sampling phase. These bits are set and cleared by software. These bits are used in dual interleaved modes. Refer to for the value of ADC resolution versus DELAY bits values. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL\u{a0}=\u{a0}0, JADSTART\u{a0}=\u{a0}0, ADSTART\u{a0}=\u{a0}0, ADSTP\u{a0}=\u{a0}0, ADDIS\u{a0}=\u{a0}0 and ADEN\u{a0}=\u{a0}0).",
112 ),
113 bit_offset: BitOffset::Regular(
114 RegularBitOffset {
115 offset: 8,
116 },
117 ),
118 bit_size: 4,
119 array: None,
120 enumm: None,
121 },
122 Field {
123 name: "damdf",
124 description: Some(
125 "Dual ADC Mode Data Format This bit-field is set and cleared by software. It specifies the data format in the common data register CDR. Note: The software is allowed to write these bits only when ADSTART\u{a0}=\u{a0}0 (which ensures that no regular conversion is ongoing).",
126 ),
127 bit_offset: BitOffset::Regular(
128 RegularBitOffset {
129 offset: 14,
130 },
131 ),
132 bit_size: 2,
133 array: None,
134 enumm: Some(
135 "Damdf",
136 ),
137 },
138 Field {
139 name: "presc",
140 description: Some(
141 "ADC prescaler These bits are set and cleared by software to select the frequency of the ADC clock. The clock is common to all ADCs. Others: Reserved, must not be used Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL\u{a0}=\u{a0}0, JADSTART\u{a0}=\u{a0}0, ADSTART\u{a0}=\u{a0}0, ADSTP\u{a0}=\u{a0}0, ADDIS\u{a0}=\u{a0}0 and ADEN\u{a0}=\u{a0}0).",
142 ),
143 bit_offset: BitOffset::Regular(
144 RegularBitOffset {
145 offset: 18,
146 },
147 ),
148 bit_size: 4,
149 array: None,
150 enumm: Some(
151 "Presc",
152 ),
153 },
154 Field {
155 name: "vrefen",
156 description: Some(
157 "VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT buffer. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL\u{a0}=\u{a0}0, JADSTART\u{a0}=\u{a0}0, ADSTART\u{a0}=\u{a0}0, ADSTP\u{a0}=\u{a0}0, ADDIS\u{a0}=\u{a0}0 and ADEN\u{a0}=\u{a0}0).",
158 ),
159 bit_offset: BitOffset::Regular(
160 RegularBitOffset {
161 offset: 22,
162 },
163 ),
164 bit_size: 1,
165 array: None,
166 enumm: None,
167 },
168 Field {
169 name: "vsenseen",
170 description: Some(
171 "Temperature sensor voltage selection This bit is set and cleared by software to control the temperature sensor channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL\u{a0}=\u{a0}0, JADSTART\u{a0}=\u{a0}0, ADSTART\u{a0}=\u{a0}0, ADSTP\u{a0}=\u{a0}0, ADDIS\u{a0}=\u{a0}0 and ADEN\u{a0}=\u{a0}0).",
172 ),
173 bit_offset: BitOffset::Regular(
174 RegularBitOffset {
175 offset: 23,
176 },
177 ),
178 bit_size: 1,
179 array: None,
180 enumm: None,
181 },
182 Field {
183 name: "vbaten",
184 description: Some(
185 "VBAT enable This bit is set and cleared by software to control the VBAT channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL\u{a0}=\u{a0}0, JADSTART\u{a0}=\u{a0}0, ADSTART\u{a0}=\u{a0}0, ADSTP\u{a0}=\u{a0}0, ADDIS\u{a0}=\u{a0}0 and ADEN\u{a0}=\u{a0}0).",
186 ),
187 bit_offset: BitOffset::Regular(
188 RegularBitOffset {
189 offset: 24,
190 },
191 ),
192 bit_size: 1,
193 array: None,
194 enumm: None,
195 },
196 ],
197 },
198 FieldSet {
199 name: "Cdr",
200 extends: None,
201 description: Some(
202 "ADC common regular data register for dual mode.",
203 ),
204 bit_size: 32,
205 fields: &[
206 Field {
207 name: "rdata_mst",
208 description: Some(
209 "Regular data of the master ADC. In dual mode, these bits contain the regular data of the master ADC. Refer to . The data alignment is applied as described in offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT)) In DAMDF[1:0]\u{a0}=\u{a0}11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains MST_ADC_DR[7:0].",
210 ),
211 bit_offset: BitOffset::Regular(
212 RegularBitOffset {
213 offset: 0,
214 },
215 ),
216 bit_size: 16,
217 array: None,
218 enumm: None,
219 },
220 Field {
221 name: "rdata_slv",
222 description: Some(
223 "Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC. Refer to Dual ADC modes. The data alignment is applied as described in offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT)).",
224 ),
225 bit_offset: BitOffset::Regular(
226 RegularBitOffset {
227 offset: 16,
228 },
229 ),
230 bit_size: 16,
231 array: None,
232 enumm: None,
233 },
234 ],
235 },
236 FieldSet {
237 name: "Cdr2",
238 extends: None,
239 description: Some(
240 "ADC common regular data register for 32-bit dual mode.",
241 ),
242 bit_size: 32,
243 fields: &[
244 Field {
245 name: "rdata_alt",
246 description: Some(
247 "Regular data of the master/slave alternated ADCs In dual mode, these bits alternatively contains the regular 32-bit data of the master and the slave ADC. Refer to . The data alignment is applied as described in (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT).",
248 ),
249 bit_offset: BitOffset::Regular(
250 RegularBitOffset {
251 offset: 0,
252 },
253 ),
254 bit_size: 32,
255 array: None,
256 enumm: None,
257 },
258 ],
259 },
260 FieldSet {
261 name: "Csr",
262 extends: None,
263 description: Some(
264 "ADC common status register.",
265 ),
266 bit_size: 32,
267 fields: &[
268 Field {
269 name: "adrdy_mst",
270 description: Some(
271 "Master ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register.",
272 ),
273 bit_offset: BitOffset::Regular(
274 RegularBitOffset {
275 offset: 0,
276 },
277 ),
278 bit_size: 1,
279 array: None,
280 enumm: None,
281 },
282 Field {
283 name: "eosmp_mst",
284 description: Some(
285 "End of Sampling phase flag of the master ADC This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register.",
286 ),
287 bit_offset: BitOffset::Regular(
288 RegularBitOffset {
289 offset: 1,
290 },
291 ),
292 bit_size: 1,
293 array: None,
294 enumm: None,
295 },
296 Field {
297 name: "eoc_mst",
298 description: Some(
299 "End of regular conversion of the master ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register.",
300 ),
301 bit_offset: BitOffset::Regular(
302 RegularBitOffset {
303 offset: 2,
304 },
305 ),
306 bit_size: 1,
307 array: None,
308 enumm: None,
309 },
310 Field {
311 name: "eos_mst",
312 description: Some(
313 "End of regular sequence flag of the master ADC This bit is a copy of the EOS bit in the corresponding ADC_ISR register.",
314 ),
315 bit_offset: BitOffset::Regular(
316 RegularBitOffset {
317 offset: 3,
318 },
319 ),
320 bit_size: 1,
321 array: None,
322 enumm: None,
323 },
324 Field {
325 name: "ovr_mst",
326 description: Some(
327 "Overrun flag of the master ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register.",
328 ),
329 bit_offset: BitOffset::Regular(
330 RegularBitOffset {
331 offset: 4,
332 },
333 ),
334 bit_size: 1,
335 array: None,
336 enumm: None,
337 },
338 Field {
339 name: "jeoc_mst",
340 description: Some(
341 "End of injected conversion flag of the master ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register.",
342 ),
343 bit_offset: BitOffset::Regular(
344 RegularBitOffset {
345 offset: 5,
346 },
347 ),
348 bit_size: 1,
349 array: None,
350 enumm: None,
351 },
352 Field {
353 name: "jeos_mst",
354 description: Some(
355 "End of injected sequence flag of the master ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register.",
356 ),
357 bit_offset: BitOffset::Regular(
358 RegularBitOffset {
359 offset: 6,
360 },
361 ),
362 bit_size: 1,
363 array: None,
364 enumm: None,
365 },
366 Field {
367 name: "awd_mst",
368 description: Some(
369 "Analog watchdog flags of the master ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register.",
370 ),
371 bit_offset: BitOffset::Regular(
372 RegularBitOffset {
373 offset: 7,
374 },
375 ),
376 bit_size: 1,
377 array: Some(
378 Array::Regular(
379 RegularArray {
380 len: 3,
381 stride: 1,
382 },
383 ),
384 ),
385 enumm: None,
386 },
387 Field {
388 name: "ldordy_mst",
389 description: Some(
390 "ADC voltage regulator ready flag of the master ADC This bit is a copy of the LDORDY bit of the corresponding ADC_ISR register.",
391 ),
392 bit_offset: BitOffset::Regular(
393 RegularBitOffset {
394 offset: 12,
395 },
396 ),
397 bit_size: 1,
398 array: None,
399 enumm: None,
400 },
401 Field {
402 name: "adrdy_slv",
403 description: Some(
404 "Slave ADC ready This bit is a copy of the ADRDY bit in the corresponding ADCx+1_ISR register.",
405 ),
406 bit_offset: BitOffset::Regular(
407 RegularBitOffset {
408 offset: 16,
409 },
410 ),
411 bit_size: 1,
412 array: None,
413 enumm: None,
414 },
415 Field {
416 name: "eosmp_slv",
417 description: Some(
418 "End of Sampling phase flag of the slave ADC This bit is a copy of the EOSMP2 bit in the corresponding ADCx+1_ISR register.",
419 ),
420 bit_offset: BitOffset::Regular(
421 RegularBitOffset {
422 offset: 17,
423 },
424 ),
425 bit_size: 1,
426 array: None,
427 enumm: None,
428 },
429 Field {
430 name: "eoc_slv",
431 description: Some(
432 "End of regular conversion of the slave ADC This bit is a copy of the EOC bit in the corresponding ADCx+1_ISR register.",
433 ),
434 bit_offset: BitOffset::Regular(
435 RegularBitOffset {
436 offset: 18,
437 },
438 ),
439 bit_size: 1,
440 array: None,
441 enumm: None,
442 },
443 Field {
444 name: "eos_slv",
445 description: Some(
446 "End of regular sequence flag of the slave ADC This bit is a copy of the EOS bit in the corresponding ADCx+1_ISR register.",
447 ),
448 bit_offset: BitOffset::Regular(
449 RegularBitOffset {
450 offset: 19,
451 },
452 ),
453 bit_size: 1,
454 array: None,
455 enumm: None,
456 },
457 Field {
458 name: "ovr_slv",
459 description: Some(
460 "Overrun flag of the slave ADC This bit is a copy of the OVR bit in the corresponding ADCx+1_ISR register.",
461 ),
462 bit_offset: BitOffset::Regular(
463 RegularBitOffset {
464 offset: 20,
465 },
466 ),
467 bit_size: 1,
468 array: None,
469 enumm: None,
470 },
471 Field {
472 name: "jeoc_slv",
473 description: Some(
474 "End of injected conversion flag of the slave ADC This bit is a copy of the JEOC bit in the corresponding ADCx+1_ISR register.",
475 ),
476 bit_offset: BitOffset::Regular(
477 RegularBitOffset {
478 offset: 21,
479 },
480 ),
481 bit_size: 1,
482 array: None,
483 enumm: None,
484 },
485 Field {
486 name: "jeos_slv",
487 description: Some(
488 "End of injected sequence flag of the slave ADC This bit is a copy of the JEOS bit in the corresponding ADCx+1_ISR register.",
489 ),
490 bit_offset: BitOffset::Regular(
491 RegularBitOffset {
492 offset: 22,
493 },
494 ),
495 bit_size: 1,
496 array: None,
497 enumm: None,
498 },
499 Field {
500 name: "awd1_slv",
501 description: Some(
502 "Analog watchdog 1 flag of the slave ADC This bit is a copy of the AWD1 bit in the corresponding ADCx+1_ISR register.",
503 ),
504 bit_offset: BitOffset::Regular(
505 RegularBitOffset {
506 offset: 23,
507 },
508 ),
509 bit_size: 1,
510 array: Some(
511 Array::Regular(
512 RegularArray {
513 len: 3,
514 stride: 1,
515 },
516 ),
517 ),
518 enumm: None,
519 },
520 Field {
521 name: "ldordy_slv",
522 description: Some(
523 "ADC voltage regulator ready flag of the slave ADC This bit is a copy of the LDORDY bit of the corresponding ADCx+1_ISR register.",
524 ),
525 bit_offset: BitOffset::Regular(
526 RegularBitOffset {
527 offset: 28,
528 },
529 ),
530 bit_size: 1,
531 array: None,
532 enumm: None,
533 },
534 ],
535 },
536 ],
537 enums: &[
538 Enum {
539 name: "Damdf",
540 description: None,
541 bit_size: 2,
542 variants: &[
543 EnumVariant {
544 name: "NO_PACK",
545 description: Some(
546 "Without data packing, CDR/CDR2 not used",
547 ),
548 value: 0,
549 },
550 EnumVariant {
551 name: "FORMAT32TO10",
552 description: Some(
553 "CDR formatted for 32-bit down to 10-bit resolution",
554 ),
555 value: 2,
556 },
557 EnumVariant {
558 name: "FORMAT8",
559 description: Some(
560 "CDR formatted for 8-bit resolution",
561 ),
562 value: 3,
563 },
564 ],
565 },
566 Enum {
567 name: "Dual",
568 description: None,
569 bit_size: 5,
570 variants: &[
571 EnumVariant {
572 name: "INDEPENDENT",
573 description: Some(
574 "Independent mode",
575 ),
576 value: 0,
577 },
578 EnumVariant {
579 name: "DUAL_RJ",
580 description: Some(
581 "Dual, combined regular simultaneous + injected simultaneous mode",
582 ),
583 value: 1,
584 },
585 EnumVariant {
586 name: "DUAL_RA",
587 description: Some(
588 "Dual, combined regular simultaneous + alternate trigger mode",
589 ),
590 value: 2,
591 },
592 EnumVariant {
593 name: "DUAL_IJ",
594 description: Some(
595 "Dual, combined interleaved mode + injected simultaneous mode",
596 ),
597 value: 3,
598 },
599 EnumVariant {
600 name: "DUAL_J",
601 description: Some(
602 "Dual, injected simultaneous mode only",
603 ),
604 value: 5,
605 },
606 EnumVariant {
607 name: "DUAL_R",
608 description: Some(
609 "Dual, regular simultaneous mode only",
610 ),
611 value: 6,
612 },
613 EnumVariant {
614 name: "DUAL_I",
615 description: Some(
616 "Dual, interleaved mode only",
617 ),
618 value: 7,
619 },
620 EnumVariant {
621 name: "DUAL_A",
622 description: Some(
623 "Dual, alternate trigger mode only",
624 ),
625 value: 9,
626 },
627 ],
628 },
629 Enum {
630 name: "Presc",
631 description: None,
632 bit_size: 4,
633 variants: &[
634 EnumVariant {
635 name: "DIV1",
636 description: Some(
637 "adc_ker_ck_input not divided",
638 ),
639 value: 0,
640 },
641 EnumVariant {
642 name: "DIV2",
643 description: Some(
644 "adc_ker_ck_input divided by 2",
645 ),
646 value: 1,
647 },
648 EnumVariant {
649 name: "DIV4",
650 description: Some(
651 "adc_ker_ck_input divided by 4",
652 ),
653 value: 2,
654 },
655 EnumVariant {
656 name: "DIV6",
657 description: Some(
658 "adc_ker_ck_input divided by 6",
659 ),
660 value: 3,
661 },
662 EnumVariant {
663 name: "DIV8",
664 description: Some(
665 "adc_ker_ck_input divided by 8",
666 ),
667 value: 4,
668 },
669 EnumVariant {
670 name: "DIV10",
671 description: Some(
672 "adc_ker_ck_input divided by 10",
673 ),
674 value: 5,
675 },
676 EnumVariant {
677 name: "DIV12",
678 description: Some(
679 "adc_ker_ck_input divided by 12",
680 ),
681 value: 6,
682 },
683 EnumVariant {
684 name: "DIV16",
685 description: Some(
686 "adc_ker_ck_input divided by 16",
687 ),
688 value: 7,
689 },
690 EnumVariant {
691 name: "DIV32",
692 description: Some(
693 "adc_ker_ck_input divided by 32",
694 ),
695 value: 8,
696 },
697 EnumVariant {
698 name: "DIV64",
699 description: Some(
700 "adc_ker_ck_input divided by 64",
701 ),
702 value: 9,
703 },
704 EnumVariant {
705 name: "DIV128",
706 description: Some(
707 "adc_ker_ck_input divided by 128",
708 ),
709 value: 10,
710 },
711 EnumVariant {
712 name: "DIV256",
713 description: Some(
714 "adc_ker_ck_input divided by 256",
715 ),
716 value: 11,
717 },
718 ],
719 },
720 ],
721};
722