1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Adf",
7 extends: None,
8 description: Some(
9 "ADF.",
10 ),
11 items: &[
12 BlockItem {
13 name: "gcr",
14 description: Some(
15 "ADF Global Control Register.",
16 ),
17 array: None,
18 byte_offset: 0x0,
19 inner: BlockItemInner::Register(
20 Register {
21 access: Access::ReadWrite,
22 bit_size: 32,
23 fieldset: Some(
24 "Gcr",
25 ),
26 },
27 ),
28 },
29 BlockItem {
30 name: "ckgcr",
31 description: Some(
32 "ADF clock generator control register.",
33 ),
34 array: None,
35 byte_offset: 0x4,
36 inner: BlockItemInner::Register(
37 Register {
38 access: Access::ReadWrite,
39 bit_size: 32,
40 fieldset: Some(
41 "Ckgcr",
42 ),
43 },
44 ),
45 },
46 BlockItem {
47 name: "sitfcr",
48 description: Some(
49 "ADF serial interface control register 0.",
50 ),
51 array: None,
52 byte_offset: 0x80,
53 inner: BlockItemInner::Register(
54 Register {
55 access: Access::ReadWrite,
56 bit_size: 32,
57 fieldset: Some(
58 "Sitfcr",
59 ),
60 },
61 ),
62 },
63 BlockItem {
64 name: "bsmxcr",
65 description: Some(
66 "ADF bitstream matrix control register 0.",
67 ),
68 array: None,
69 byte_offset: 0x84,
70 inner: BlockItemInner::Register(
71 Register {
72 access: Access::ReadWrite,
73 bit_size: 32,
74 fieldset: Some(
75 "Bsmxcr",
76 ),
77 },
78 ),
79 },
80 BlockItem {
81 name: "dfltcr",
82 description: Some(
83 "ADF digital filter control register 0.",
84 ),
85 array: None,
86 byte_offset: 0x88,
87 inner: BlockItemInner::Register(
88 Register {
89 access: Access::ReadWrite,
90 bit_size: 32,
91 fieldset: Some(
92 "Dfltcr",
93 ),
94 },
95 ),
96 },
97 BlockItem {
98 name: "dfltcicr",
99 description: Some(
100 "ADF digital filer configuration register 0.",
101 ),
102 array: None,
103 byte_offset: 0x8c,
104 inner: BlockItemInner::Register(
105 Register {
106 access: Access::ReadWrite,
107 bit_size: 32,
108 fieldset: Some(
109 "Dfltcicr",
110 ),
111 },
112 ),
113 },
114 BlockItem {
115 name: "dfltrsfr",
116 description: Some(
117 "ADF reshape filter configuration register 0.",
118 ),
119 array: None,
120 byte_offset: 0x90,
121 inner: BlockItemInner::Register(
122 Register {
123 access: Access::ReadWrite,
124 bit_size: 32,
125 fieldset: Some(
126 "Dfltrsfr",
127 ),
128 },
129 ),
130 },
131 BlockItem {
132 name: "dlycr",
133 description: Some(
134 "ADF delay control register 0.",
135 ),
136 array: None,
137 byte_offset: 0xa4,
138 inner: BlockItemInner::Register(
139 Register {
140 access: Access::ReadWrite,
141 bit_size: 32,
142 fieldset: Some(
143 "Dlycr",
144 ),
145 },
146 ),
147 },
148 BlockItem {
149 name: "dfltier",
150 description: Some(
151 "ADF DFLT0 interrupt enable register.",
152 ),
153 array: None,
154 byte_offset: 0xac,
155 inner: BlockItemInner::Register(
156 Register {
157 access: Access::ReadWrite,
158 bit_size: 32,
159 fieldset: Some(
160 "Dfltier",
161 ),
162 },
163 ),
164 },
165 BlockItem {
166 name: "dfltisr",
167 description: Some(
168 "ADF DFLT0 interrupt status register 0.",
169 ),
170 array: None,
171 byte_offset: 0xb0,
172 inner: BlockItemInner::Register(
173 Register {
174 access: Access::ReadWrite,
175 bit_size: 32,
176 fieldset: Some(
177 "Dfltisr",
178 ),
179 },
180 ),
181 },
182 BlockItem {
183 name: "sadcr",
184 description: Some(
185 "ADF SAD control register.",
186 ),
187 array: None,
188 byte_offset: 0xb8,
189 inner: BlockItemInner::Register(
190 Register {
191 access: Access::ReadWrite,
192 bit_size: 32,
193 fieldset: Some(
194 "Sadcr",
195 ),
196 },
197 ),
198 },
199 BlockItem {
200 name: "sadcfgr",
201 description: Some(
202 "ADF SAD configuration register.",
203 ),
204 array: None,
205 byte_offset: 0xbc,
206 inner: BlockItemInner::Register(
207 Register {
208 access: Access::ReadWrite,
209 bit_size: 32,
210 fieldset: Some(
211 "Sadcfgr",
212 ),
213 },
214 ),
215 },
216 BlockItem {
217 name: "sadsdlvr",
218 description: Some(
219 "ADF SAD sound level register.",
220 ),
221 array: None,
222 byte_offset: 0xc0,
223 inner: BlockItemInner::Register(
224 Register {
225 access: Access::Read,
226 bit_size: 32,
227 fieldset: Some(
228 "Sadsdlvr",
229 ),
230 },
231 ),
232 },
233 BlockItem {
234 name: "sadanlvr",
235 description: Some(
236 "ADF SAD ambient noise level register.",
237 ),
238 array: None,
239 byte_offset: 0xc4,
240 inner: BlockItemInner::Register(
241 Register {
242 access: Access::Read,
243 bit_size: 32,
244 fieldset: Some(
245 "Sadanlvr",
246 ),
247 },
248 ),
249 },
250 BlockItem {
251 name: "dfltdr",
252 description: Some(
253 "ADF digital filter data register 0.",
254 ),
255 array: None,
256 byte_offset: 0xf0,
257 inner: BlockItemInner::Register(
258 Register {
259 access: Access::Read,
260 bit_size: 32,
261 fieldset: Some(
262 "Dfltdr",
263 ),
264 },
265 ),
266 },
267 ],
268 },
269 ],
270 fieldsets: &[
271 FieldSet {
272 name: "Bsmxcr",
273 extends: None,
274 description: Some(
275 "ADF bitstream matrix control register 0.",
276 ),
277 bit_size: 32,
278 fields: &[
279 Field {
280 name: "bssel",
281 description: Some(
282 "Bitstream selection.",
283 ),
284 bit_offset: BitOffset::Regular(
285 RegularBitOffset {
286 offset: 0,
287 },
288 ),
289 bit_size: 5,
290 array: None,
291 enumm: Some(
292 "Bssel",
293 ),
294 },
295 Field {
296 name: "bsmxactive",
297 description: Some(
298 "BSMX active flag. This bit is set and cleared by hardware. It is used by the application to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when BSMXACTIVE is set to 0. This BSMXACTIVE flag cannot go to 0 if DFLT0 is enabled.",
299 ),
300 bit_offset: BitOffset::Regular(
301 RegularBitOffset {
302 offset: 31,
303 },
304 ),
305 bit_size: 1,
306 array: None,
307 enumm: None,
308 },
309 ],
310 },
311 FieldSet {
312 name: "Ckgcr",
313 extends: None,
314 description: Some(
315 "ADF clock generator control register.",
316 ),
317 bit_size: 32,
318 fields: &[
319 Field {
320 name: "ckgden",
321 description: Some(
322 "Clock generator dividers enable.",
323 ),
324 bit_offset: BitOffset::Regular(
325 RegularBitOffset {
326 offset: 0,
327 },
328 ),
329 bit_size: 1,
330 array: None,
331 enumm: None,
332 },
333 Field {
334 name: "cck0en",
335 description: Some(
336 "CCK0 clock enable. This bit is set and reset by software. It is used to control the generation of the bitstream clock on the CCK pin.",
337 ),
338 bit_offset: BitOffset::Regular(
339 RegularBitOffset {
340 offset: 1,
341 },
342 ),
343 bit_size: 1,
344 array: None,
345 enumm: Some(
346 "Ccken",
347 ),
348 },
349 Field {
350 name: "cck1en",
351 description: Some(
352 "CCK1 clock enable. This bit is set and reset by software. It is used to control the generation of the bitstream clock on the CCK pin.",
353 ),
354 bit_offset: BitOffset::Regular(
355 RegularBitOffset {
356 offset: 2,
357 },
358 ),
359 bit_size: 1,
360 array: None,
361 enumm: Some(
362 "Ccken",
363 ),
364 },
365 Field {
366 name: "ckgmod",
367 description: Some(
368 "Clock generator mode. This bit is set and reset by software. It is used to define the way the clock generator is enabled. This bit must not be changed if the filter is enabled (DFTEN = 1).",
369 ),
370 bit_offset: BitOffset::Regular(
371 RegularBitOffset {
372 offset: 4,
373 },
374 ),
375 bit_size: 1,
376 array: None,
377 enumm: Some(
378 "Ckgmod",
379 ),
380 },
381 Field {
382 name: "cck0dir",
383 description: Some(
384 "CCK0 direction. This bit is set and reset by software. It is used to control the direction of the ADF_CCK0 pin.",
385 ),
386 bit_offset: BitOffset::Regular(
387 RegularBitOffset {
388 offset: 5,
389 },
390 ),
391 bit_size: 1,
392 array: None,
393 enumm: Some(
394 "Cckdir",
395 ),
396 },
397 Field {
398 name: "cck1dir",
399 description: Some(
400 "CCK1 direction. This bit is set and reset by software. It is used to control the direction of the ADF_CCK1 pin.",
401 ),
402 bit_offset: BitOffset::Regular(
403 RegularBitOffset {
404 offset: 6,
405 },
406 ),
407 bit_size: 1,
408 array: None,
409 enumm: Some(
410 "Cckdir",
411 ),
412 },
413 Field {
414 name: "trgsens",
415 description: Some(
416 "CKGEN trigger sensitivity selection. This bit is set and cleared by software. It is used to select the trigger sensitivity of the trigger signals. This bit is not significant if the CKGMOD = 0.",
417 ),
418 bit_offset: BitOffset::Regular(
419 RegularBitOffset {
420 offset: 8,
421 },
422 ),
423 bit_size: 1,
424 array: None,
425 enumm: Some(
426 "Trgsens",
427 ),
428 },
429 Field {
430 name: "trgsrc",
431 description: Some(
432 "Digital filter trigger signal selection. This bit is set and cleared by software. It is used to select the trigger signal for the digital filter. This bit is not significant if the CKGMOD = 0.",
433 ),
434 bit_offset: BitOffset::Regular(
435 RegularBitOffset {
436 offset: 12,
437 },
438 ),
439 bit_size: 4,
440 array: None,
441 enumm: Some(
442 "Trgsrc",
443 ),
444 },
445 Field {
446 name: "cckdiv",
447 description: Some(
448 "Divider to control the CCK clock.",
449 ),
450 bit_offset: BitOffset::Regular(
451 RegularBitOffset {
452 offset: 16,
453 },
454 ),
455 bit_size: 4,
456 array: None,
457 enumm: Some(
458 "Cckdiv",
459 ),
460 },
461 Field {
462 name: "procdiv",
463 description: Some(
464 "Divider to control the serial interface clock.",
465 ),
466 bit_offset: BitOffset::Regular(
467 RegularBitOffset {
468 offset: 24,
469 },
470 ),
471 bit_size: 7,
472 array: None,
473 enumm: None,
474 },
475 Field {
476 name: "ckgactive",
477 description: Some(
478 "Clock generator active flag.",
479 ),
480 bit_offset: BitOffset::Regular(
481 RegularBitOffset {
482 offset: 31,
483 },
484 ),
485 bit_size: 1,
486 array: None,
487 enumm: None,
488 },
489 ],
490 },
491 FieldSet {
492 name: "Dfltcicr",
493 extends: None,
494 description: Some(
495 "ADF digital filer configuration register 0.",
496 ),
497 bit_size: 32,
498 fields: &[
499 Field {
500 name: "datsrc",
501 description: Some(
502 "Source data for the digital filter.",
503 ),
504 bit_offset: BitOffset::Regular(
505 RegularBitOffset {
506 offset: 0,
507 },
508 ),
509 bit_size: 2,
510 array: None,
511 enumm: Some(
512 "Datsrc",
513 ),
514 },
515 Field {
516 name: "cicmod",
517 description: Some(
518 "Select the CIC order.",
519 ),
520 bit_offset: BitOffset::Regular(
521 RegularBitOffset {
522 offset: 4,
523 },
524 ),
525 bit_size: 3,
526 array: None,
527 enumm: Some(
528 "Cicmod",
529 ),
530 },
531 Field {
532 name: "mcicd",
533 description: Some(
534 "CIC decimation ratio selection. This bitfield is set and cleared by software.It is used to select the CIC decimation ratio. A decimation ratio smaller than two is not allowed. The decimation ratio is given by (CICDEC+1).",
535 ),
536 bit_offset: BitOffset::Regular(
537 RegularBitOffset {
538 offset: 8,
539 },
540 ),
541 bit_size: 9,
542 array: None,
543 enumm: None,
544 },
545 Field {
546 name: "scale",
547 description: Some(
548 "Scaling factor selection. This bitfield is set and cleared by software. It is used to select the gain to be applied at CIC output. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back this bitfield informs the application on the current gain value.",
549 ),
550 bit_offset: BitOffset::Regular(
551 RegularBitOffset {
552 offset: 20,
553 },
554 ),
555 bit_size: 6,
556 array: None,
557 enumm: None,
558 },
559 ],
560 },
561 FieldSet {
562 name: "Dfltcr",
563 extends: None,
564 description: Some(
565 "ADF digital filter control register 0.",
566 ),
567 bit_size: 32,
568 fields: &[
569 Field {
570 name: "dflten",
571 description: Some(
572 "DFLT enable. This bit is set and reset by software. It is used to enable the digital filter.",
573 ),
574 bit_offset: BitOffset::Regular(
575 RegularBitOffset {
576 offset: 0,
577 },
578 ),
579 bit_size: 1,
580 array: None,
581 enumm: None,
582 },
583 Field {
584 name: "dmaen",
585 description: Some(
586 "DMA requests enable. This bit is set and reset by software. It is used to control the generation of DMA request to transfer the processed samples into the memory.",
587 ),
588 bit_offset: BitOffset::Regular(
589 RegularBitOffset {
590 offset: 1,
591 },
592 ),
593 bit_size: 1,
594 array: None,
595 enumm: None,
596 },
597 Field {
598 name: "fth",
599 description: Some(
600 "RXFIFO threshold selection.",
601 ),
602 bit_offset: BitOffset::Regular(
603 RegularBitOffset {
604 offset: 2,
605 },
606 ),
607 bit_size: 1,
608 array: None,
609 enumm: Some(
610 "Rxfifo",
611 ),
612 },
613 Field {
614 name: "acqmod",
615 description: Some(
616 "DFLT trigger mode.",
617 ),
618 bit_offset: BitOffset::Regular(
619 RegularBitOffset {
620 offset: 4,
621 },
622 ),
623 bit_size: 3,
624 array: None,
625 enumm: Some(
626 "Acqmod",
627 ),
628 },
629 Field {
630 name: "trgsrc",
631 description: Some(
632 "DFLT trigger signal selection.",
633 ),
634 bit_offset: BitOffset::Regular(
635 RegularBitOffset {
636 offset: 12,
637 },
638 ),
639 bit_size: 4,
640 array: None,
641 enumm: None,
642 },
643 Field {
644 name: "nbdis",
645 description: Some(
646 "Number of samples to be discarded.",
647 ),
648 bit_offset: BitOffset::Regular(
649 RegularBitOffset {
650 offset: 20,
651 },
652 ),
653 bit_size: 8,
654 array: None,
655 enumm: None,
656 },
657 Field {
658 name: "dfltrun",
659 description: Some(
660 "DFLT run status flag.",
661 ),
662 bit_offset: BitOffset::Regular(
663 RegularBitOffset {
664 offset: 30,
665 },
666 ),
667 bit_size: 1,
668 array: None,
669 enumm: None,
670 },
671 Field {
672 name: "dfltactive",
673 description: Some(
674 "DFLT active flag.",
675 ),
676 bit_offset: BitOffset::Regular(
677 RegularBitOffset {
678 offset: 31,
679 },
680 ),
681 bit_size: 1,
682 array: None,
683 enumm: None,
684 },
685 ],
686 },
687 FieldSet {
688 name: "Dfltdr",
689 extends: None,
690 description: Some(
691 "ADF digital filter data register 0.",
692 ),
693 bit_size: 32,
694 fields: &[
695 Field {
696 name: "dr",
697 description: Some(
698 "DR. Data processed by DFT",
699 ),
700 bit_offset: BitOffset::Regular(
701 RegularBitOffset {
702 offset: 8,
703 },
704 ),
705 bit_size: 24,
706 array: None,
707 enumm: None,
708 },
709 ],
710 },
711 FieldSet {
712 name: "Dfltier",
713 extends: None,
714 description: Some(
715 "ADF DFLT interrupt enable register.",
716 ),
717 bit_size: 32,
718 fields: &[
719 Field {
720 name: "fthie",
721 description: Some(
722 "RXFIFO threshold interrupt enable.",
723 ),
724 bit_offset: BitOffset::Regular(
725 RegularBitOffset {
726 offset: 0,
727 },
728 ),
729 bit_size: 1,
730 array: None,
731 enumm: None,
732 },
733 Field {
734 name: "dovrie",
735 description: Some(
736 "Data overflow interrupt enable.",
737 ),
738 bit_offset: BitOffset::Regular(
739 RegularBitOffset {
740 offset: 1,
741 },
742 ),
743 bit_size: 1,
744 array: None,
745 enumm: None,
746 },
747 Field {
748 name: "satie",
749 description: Some(
750 "Saturation detection interrupt enable.",
751 ),
752 bit_offset: BitOffset::Regular(
753 RegularBitOffset {
754 offset: 9,
755 },
756 ),
757 bit_size: 1,
758 array: None,
759 enumm: None,
760 },
761 Field {
762 name: "ckabie",
763 description: Some(
764 "Clock absence detection interrupt enable.",
765 ),
766 bit_offset: BitOffset::Regular(
767 RegularBitOffset {
768 offset: 10,
769 },
770 ),
771 bit_size: 1,
772 array: None,
773 enumm: None,
774 },
775 Field {
776 name: "rfovrie",
777 description: Some(
778 "Reshape filter overrun interrupt enable.",
779 ),
780 bit_offset: BitOffset::Regular(
781 RegularBitOffset {
782 offset: 11,
783 },
784 ),
785 bit_size: 1,
786 array: None,
787 enumm: None,
788 },
789 Field {
790 name: "sddetie",
791 description: Some(
792 "Sound activity detection interrupt enable.",
793 ),
794 bit_offset: BitOffset::Regular(
795 RegularBitOffset {
796 offset: 12,
797 },
798 ),
799 bit_size: 1,
800 array: None,
801 enumm: None,
802 },
803 Field {
804 name: "sdlvlie",
805 description: Some(
806 "SAD sound-level value ready enable.",
807 ),
808 bit_offset: BitOffset::Regular(
809 RegularBitOffset {
810 offset: 13,
811 },
812 ),
813 bit_size: 1,
814 array: None,
815 enumm: None,
816 },
817 ],
818 },
819 FieldSet {
820 name: "Dfltisr",
821 extends: None,
822 description: Some(
823 "ADF DFLT interrupt status register 0.",
824 ),
825 bit_size: 32,
826 fields: &[
827 Field {
828 name: "fthf",
829 description: Some(
830 "RXFIFO threshold flag.",
831 ),
832 bit_offset: BitOffset::Regular(
833 RegularBitOffset {
834 offset: 0,
835 },
836 ),
837 bit_size: 1,
838 array: None,
839 enumm: None,
840 },
841 Field {
842 name: "dovrf",
843 description: Some(
844 "Data overflow flag.",
845 ),
846 bit_offset: BitOffset::Regular(
847 RegularBitOffset {
848 offset: 1,
849 },
850 ),
851 bit_size: 1,
852 array: None,
853 enumm: None,
854 },
855 Field {
856 name: "rxnef",
857 description: Some(
858 "RXFIFO not empty flag.",
859 ),
860 bit_offset: BitOffset::Regular(
861 RegularBitOffset {
862 offset: 3,
863 },
864 ),
865 bit_size: 1,
866 array: None,
867 enumm: None,
868 },
869 Field {
870 name: "satf",
871 description: Some(
872 "Saturation detection flag.",
873 ),
874 bit_offset: BitOffset::Regular(
875 RegularBitOffset {
876 offset: 9,
877 },
878 ),
879 bit_size: 1,
880 array: None,
881 enumm: None,
882 },
883 Field {
884 name: "ckabf",
885 description: Some(
886 "Clock absence detection flag.",
887 ),
888 bit_offset: BitOffset::Regular(
889 RegularBitOffset {
890 offset: 10,
891 },
892 ),
893 bit_size: 1,
894 array: None,
895 enumm: None,
896 },
897 Field {
898 name: "rfovrf",
899 description: Some(
900 "Reshape filter overrun detection flag.",
901 ),
902 bit_offset: BitOffset::Regular(
903 RegularBitOffset {
904 offset: 11,
905 },
906 ),
907 bit_size: 1,
908 array: None,
909 enumm: None,
910 },
911 Field {
912 name: "sddetf",
913 description: Some(
914 "Sound activity detection flag.",
915 ),
916 bit_offset: BitOffset::Regular(
917 RegularBitOffset {
918 offset: 12,
919 },
920 ),
921 bit_size: 1,
922 array: None,
923 enumm: None,
924 },
925 Field {
926 name: "sdlvlf",
927 description: Some(
928 "Sound level value ready flag.",
929 ),
930 bit_offset: BitOffset::Regular(
931 RegularBitOffset {
932 offset: 13,
933 },
934 ),
935 bit_size: 1,
936 array: None,
937 enumm: None,
938 },
939 ],
940 },
941 FieldSet {
942 name: "Dfltrsfr",
943 extends: None,
944 description: Some(
945 "ADF reshape filter configuration register.",
946 ),
947 bit_size: 32,
948 fields: &[
949 Field {
950 name: "rsfltbyp",
951 description: Some(
952 "Reshaper filter bypass.",
953 ),
954 bit_offset: BitOffset::Regular(
955 RegularBitOffset {
956 offset: 0,
957 },
958 ),
959 bit_size: 1,
960 array: None,
961 enumm: None,
962 },
963 Field {
964 name: "rsfltd",
965 description: Some(
966 "Reshaper filter decimation ratio.",
967 ),
968 bit_offset: BitOffset::Regular(
969 RegularBitOffset {
970 offset: 4,
971 },
972 ),
973 bit_size: 1,
974 array: None,
975 enumm: Some(
976 "Rsfltd",
977 ),
978 },
979 Field {
980 name: "hpfbyp",
981 description: Some(
982 "High-pass filter bypass. This bit is set and cleared by software. It is used to bypass the high-pass filter.",
983 ),
984 bit_offset: BitOffset::Regular(
985 RegularBitOffset {
986 offset: 7,
987 },
988 ),
989 bit_size: 1,
990 array: None,
991 enumm: None,
992 },
993 Field {
994 name: "hpfc",
995 description: Some(
996 "High-pass filter cut-off frequency. This bitfield is set and cleared by software. it is used to select the cut-off frequency of the high-pass filter. F PCM represents the sampling frequency at HPF input.",
997 ),
998 bit_offset: BitOffset::Regular(
999 RegularBitOffset {
1000 offset: 8,
1001 },
1002 ),
1003 bit_size: 2,
1004 array: None,
1005 enumm: Some(
1006 "Hpfc",
1007 ),
1008 },
1009 ],
1010 },
1011 FieldSet {
1012 name: "Dlycr",
1013 extends: None,
1014 description: Some(
1015 "ADF delay control register.",
1016 ),
1017 bit_size: 32,
1018 fields: &[
1019 Field {
1020 name: "skpdly",
1021 description: Some(
1022 "Delay to apply to a bitstream. This bitfield is set and cleared by software. It defines the number of input samples that are skipped. Skipping is applied immediately after writing to this bitfield, if SKPBF = 0 and DFLTEN = 1. If SKPBF = 1, the value written into the register is ignored by the delay state machine.",
1023 ),
1024 bit_offset: BitOffset::Regular(
1025 RegularBitOffset {
1026 offset: 0,
1027 },
1028 ),
1029 bit_size: 7,
1030 array: None,
1031 enumm: None,
1032 },
1033 Field {
1034 name: "skpbf",
1035 description: Some(
1036 "Skip busy flag.",
1037 ),
1038 bit_offset: BitOffset::Regular(
1039 RegularBitOffset {
1040 offset: 31,
1041 },
1042 ),
1043 bit_size: 1,
1044 array: None,
1045 enumm: None,
1046 },
1047 ],
1048 },
1049 FieldSet {
1050 name: "Gcr",
1051 extends: None,
1052 description: Some(
1053 "ADF Global Control Register.",
1054 ),
1055 bit_size: 32,
1056 fields: &[
1057 Field {
1058 name: "trgo",
1059 description: Some(
1060 "Trigger output control Set by software and reset by.",
1061 ),
1062 bit_offset: BitOffset::Regular(
1063 RegularBitOffset {
1064 offset: 0,
1065 },
1066 ),
1067 bit_size: 1,
1068 array: None,
1069 enumm: None,
1070 },
1071 ],
1072 },
1073 FieldSet {
1074 name: "Sadanlvr",
1075 extends: None,
1076 description: Some(
1077 "ADF SAD ambient noise level register. This bitfield is set by hardware. It contains the latest ambient noise level computed by the SAD. To refresh this bitfield, the SDLVLF flag must be cleared.",
1078 ),
1079 bit_size: 32,
1080 fields: &[
1081 Field {
1082 name: "anlvl",
1083 description: Some(
1084 "ANLVL.",
1085 ),
1086 bit_offset: BitOffset::Regular(
1087 RegularBitOffset {
1088 offset: 0,
1089 },
1090 ),
1091 bit_size: 15,
1092 array: None,
1093 enumm: None,
1094 },
1095 ],
1096 },
1097 FieldSet {
1098 name: "Sadcfgr",
1099 extends: None,
1100 description: Some(
1101 "ADF SAD configuration register.",
1102 ),
1103 bit_size: 32,
1104 fields: &[
1105 Field {
1106 name: "snthr",
1107 description: Some(
1108 "SNTHR.",
1109 ),
1110 bit_offset: BitOffset::Regular(
1111 RegularBitOffset {
1112 offset: 0,
1113 },
1114 ),
1115 bit_size: 4,
1116 array: None,
1117 enumm: Some(
1118 "Snthr",
1119 ),
1120 },
1121 Field {
1122 name: "anslp",
1123 description: Some(
1124 "ANSLP.",
1125 ),
1126 bit_offset: BitOffset::Regular(
1127 RegularBitOffset {
1128 offset: 4,
1129 },
1130 ),
1131 bit_size: 3,
1132 array: None,
1133 enumm: None,
1134 },
1135 Field {
1136 name: "lfrnb",
1137 description: Some(
1138 "LFRNB.",
1139 ),
1140 bit_offset: BitOffset::Regular(
1141 RegularBitOffset {
1142 offset: 8,
1143 },
1144 ),
1145 bit_size: 3,
1146 array: None,
1147 enumm: Some(
1148 "Lfrnb",
1149 ),
1150 },
1151 Field {
1152 name: "hgovr",
1153 description: Some(
1154 "Hangover time window.",
1155 ),
1156 bit_offset: BitOffset::Regular(
1157 RegularBitOffset {
1158 offset: 12,
1159 },
1160 ),
1161 bit_size: 3,
1162 array: None,
1163 enumm: Some(
1164 "Hgovr",
1165 ),
1166 },
1167 Field {
1168 name: "anmin",
1169 description: Some(
1170 "ANMIN.",
1171 ),
1172 bit_offset: BitOffset::Regular(
1173 RegularBitOffset {
1174 offset: 16,
1175 },
1176 ),
1177 bit_size: 13,
1178 array: None,
1179 enumm: None,
1180 },
1181 ],
1182 },
1183 FieldSet {
1184 name: "Sadcr",
1185 extends: None,
1186 description: Some(
1187 "ADF Sound activity detector (SAD) control register.",
1188 ),
1189 bit_size: 32,
1190 fields: &[
1191 Field {
1192 name: "saden",
1193 description: Some(
1194 "Sound activity detector enable.",
1195 ),
1196 bit_offset: BitOffset::Regular(
1197 RegularBitOffset {
1198 offset: 0,
1199 },
1200 ),
1201 bit_size: 1,
1202 array: None,
1203 enumm: None,
1204 },
1205 Field {
1206 name: "datcap",
1207 description: Some(
1208 "Data capture mode.",
1209 ),
1210 bit_offset: BitOffset::Regular(
1211 RegularBitOffset {
1212 offset: 1,
1213 },
1214 ),
1215 bit_size: 2,
1216 array: None,
1217 enumm: Some(
1218 "Datcap",
1219 ),
1220 },
1221 Field {
1222 name: "detcfg",
1223 description: Some(
1224 "Sound trigger event configuration.",
1225 ),
1226 bit_offset: BitOffset::Regular(
1227 RegularBitOffset {
1228 offset: 3,
1229 },
1230 ),
1231 bit_size: 1,
1232 array: None,
1233 enumm: Some(
1234 "Detcfg",
1235 ),
1236 },
1237 Field {
1238 name: "sadst",
1239 description: Some(
1240 "SAD state.",
1241 ),
1242 bit_offset: BitOffset::Regular(
1243 RegularBitOffset {
1244 offset: 4,
1245 },
1246 ),
1247 bit_size: 2,
1248 array: None,
1249 enumm: Some(
1250 "Sadst",
1251 ),
1252 },
1253 Field {
1254 name: "hysten",
1255 description: Some(
1256 "Hysteresis enable.",
1257 ),
1258 bit_offset: BitOffset::Regular(
1259 RegularBitOffset {
1260 offset: 7,
1261 },
1262 ),
1263 bit_size: 1,
1264 array: None,
1265 enumm: None,
1266 },
1267 Field {
1268 name: "frsize",
1269 description: Some(
1270 "Frame size.",
1271 ),
1272 bit_offset: BitOffset::Regular(
1273 RegularBitOffset {
1274 offset: 8,
1275 },
1276 ),
1277 bit_size: 3,
1278 array: None,
1279 enumm: Some(
1280 "Frsize",
1281 ),
1282 },
1283 Field {
1284 name: "sadmod",
1285 description: Some(
1286 "Sound activity detector working mode.",
1287 ),
1288 bit_offset: BitOffset::Regular(
1289 RegularBitOffset {
1290 offset: 12,
1291 },
1292 ),
1293 bit_size: 2,
1294 array: None,
1295 enumm: Some(
1296 "Sadmod",
1297 ),
1298 },
1299 Field {
1300 name: "sadactive",
1301 description: Some(
1302 "SAD Active flag.",
1303 ),
1304 bit_offset: BitOffset::Regular(
1305 RegularBitOffset {
1306 offset: 31,
1307 },
1308 ),
1309 bit_size: 1,
1310 array: None,
1311 enumm: None,
1312 },
1313 ],
1314 },
1315 FieldSet {
1316 name: "Sadsdlvr",
1317 extends: None,
1318 description: Some(
1319 "ADF SAD sound level register.",
1320 ),
1321 bit_size: 32,
1322 fields: &[
1323 Field {
1324 name: "sdlvl",
1325 description: Some(
1326 "Short term sound level. This bitfield is set by hardware. It contains the latest sound level computed by the SAD. To refresh this value, SDLVLF must be cleared.",
1327 ),
1328 bit_offset: BitOffset::Regular(
1329 RegularBitOffset {
1330 offset: 0,
1331 },
1332 ),
1333 bit_size: 15,
1334 array: None,
1335 enumm: None,
1336 },
1337 ],
1338 },
1339 FieldSet {
1340 name: "Sitfcr",
1341 extends: None,
1342 description: Some(
1343 "ADF serial interface control register 0.",
1344 ),
1345 bit_size: 32,
1346 fields: &[
1347 Field {
1348 name: "sitfen",
1349 description: None,
1350 bit_offset: BitOffset::Regular(
1351 RegularBitOffset {
1352 offset: 0,
1353 },
1354 ),
1355 bit_size: 1,
1356 array: None,
1357 enumm: None,
1358 },
1359 Field {
1360 name: "scksrc",
1361 description: None,
1362 bit_offset: BitOffset::Regular(
1363 RegularBitOffset {
1364 offset: 1,
1365 },
1366 ),
1367 bit_size: 2,
1368 array: None,
1369 enumm: Some(
1370 "Scksrc",
1371 ),
1372 },
1373 Field {
1374 name: "sitfmod",
1375 description: None,
1376 bit_offset: BitOffset::Regular(
1377 RegularBitOffset {
1378 offset: 4,
1379 },
1380 ),
1381 bit_size: 2,
1382 array: None,
1383 enumm: Some(
1384 "Sitfmod",
1385 ),
1386 },
1387 Field {
1388 name: "sth",
1389 description: Some(
1390 "Manchester symbol threshold/SPI threshold. This bitfield is set and cleared by software. It is used for Manchester mode to define the expected symbol threshold levels (seer to Manchester mode for details on computation). In addition this bitfield is used to define the timeout value for the clock absence detection in Normal SPI mode. STH[4:0] values lower than four are invalid.",
1391 ),
1392 bit_offset: BitOffset::Regular(
1393 RegularBitOffset {
1394 offset: 8,
1395 },
1396 ),
1397 bit_size: 5,
1398 array: None,
1399 enumm: None,
1400 },
1401 Field {
1402 name: "sitfactive",
1403 description: Some(
1404 "SITFACTIVE.",
1405 ),
1406 bit_offset: BitOffset::Regular(
1407 RegularBitOffset {
1408 offset: 31,
1409 },
1410 ),
1411 bit_size: 1,
1412 array: None,
1413 enumm: None,
1414 },
1415 ],
1416 },
1417 ],
1418 enums: &[
1419 Enum {
1420 name: "Acqmod",
1421 description: Some(
1422 "DFLT trigger mode. This bitfield is set and cleared by software. It is used to select the trigger mode of the DFLT0.",
1423 ),
1424 bit_size: 3,
1425 variants: &[
1426 EnumVariant {
1427 name: "ASYNCHRONOUS_CONTINUOUS",
1428 description: Some(
1429 "Asynchronous continuous acquisition mode.",
1430 ),
1431 value: 0,
1432 },
1433 EnumVariant {
1434 name: "ASYNCHRONOUS_SINGLE_SHOT",
1435 description: Some(
1436 "Asynchronous single-shot acquisition mode",
1437 ),
1438 value: 1,
1439 },
1440 EnumVariant {
1441 name: "SYNCRONOUS_CONTINUOUS",
1442 description: Some(
1443 "Synchronous continuous acquisition mode.",
1444 ),
1445 value: 2,
1446 },
1447 EnumVariant {
1448 name: "SYNCRONOUS_SINGLE_SHOT",
1449 description: Some(
1450 "Synchronous single-shot acquisition mode.",
1451 ),
1452 value: 3,
1453 },
1454 EnumVariant {
1455 name: "WINDOW_CONTINUOUS",
1456 description: Some(
1457 "Window continuous acquisition mode.",
1458 ),
1459 value: 4,
1460 },
1461 ],
1462 },
1463 Enum {
1464 name: "Bssel",
1465 description: Some(
1466 "Bitstream selection. This bitfield is set and cleared by software. It is used to select the bitstream to be used by the DFLT0.",
1467 ),
1468 bit_size: 5,
1469 variants: &[
1470 EnumVariant {
1471 name: "BS0_R",
1472 description: Some(
1473 "bsx_r provided to DFLTy (and SCDy).",
1474 ),
1475 value: 0,
1476 },
1477 EnumVariant {
1478 name: "BS0_F",
1479 description: Some(
1480 "bsx_f provided to DFLTy (and SCDy).",
1481 ),
1482 value: 1,
1483 },
1484 EnumVariant {
1485 name: "BS1_R",
1486 description: Some(
1487 "bsx_r provided to DFLTy (and SCDy).",
1488 ),
1489 value: 2,
1490 },
1491 EnumVariant {
1492 name: "BS1_F",
1493 description: Some(
1494 "bsx_f provided to DFLTy (and SCDy).",
1495 ),
1496 value: 3,
1497 },
1498 EnumVariant {
1499 name: "BS2_R",
1500 description: Some(
1501 "bsx_r provided to DFLTy (and SCDy).",
1502 ),
1503 value: 4,
1504 },
1505 EnumVariant {
1506 name: "BS2_F",
1507 description: Some(
1508 "bsx_f provided to DFLTy (and SCDy).",
1509 ),
1510 value: 5,
1511 },
1512 EnumVariant {
1513 name: "BS3_R",
1514 description: Some(
1515 "bsx_r provided to DFLTy (and SCDy).",
1516 ),
1517 value: 6,
1518 },
1519 EnumVariant {
1520 name: "BS3_F",
1521 description: Some(
1522 "bsx_f provided to DFLTy (and SCDy).",
1523 ),
1524 value: 7,
1525 },
1526 EnumVariant {
1527 name: "BS4_R",
1528 description: Some(
1529 "bsx_r provided to DFLTy (and SCDy).",
1530 ),
1531 value: 8,
1532 },
1533 EnumVariant {
1534 name: "BS4_F",
1535 description: Some(
1536 "bsx_f provided to DFLTy (and SCDy).",
1537 ),
1538 value: 9,
1539 },
1540 EnumVariant {
1541 name: "BS5_R",
1542 description: Some(
1543 "bsx_r provided to DFLTy (and SCDy).",
1544 ),
1545 value: 10,
1546 },
1547 EnumVariant {
1548 name: "BS5_F",
1549 description: Some(
1550 "bsx_f provided to DFLTy (and SCDy).",
1551 ),
1552 value: 11,
1553 },
1554 EnumVariant {
1555 name: "BS6_R",
1556 description: Some(
1557 "bsx_r provided to DFLTy (and SCDy).",
1558 ),
1559 value: 12,
1560 },
1561 EnumVariant {
1562 name: "BS6_F",
1563 description: Some(
1564 "bsx_f provided to DFLTy (and SCDy).",
1565 ),
1566 value: 13,
1567 },
1568 EnumVariant {
1569 name: "BS7_R",
1570 description: Some(
1571 "bsx_r provided to DFLTy (and SCDy).",
1572 ),
1573 value: 14,
1574 },
1575 EnumVariant {
1576 name: "BS7_F",
1577 description: Some(
1578 "bsx_f provided to DFLTy (and SCDy).",
1579 ),
1580 value: 15,
1581 },
1582 EnumVariant {
1583 name: "BS8_R",
1584 description: Some(
1585 "bsx_r provided to DFLTy (and SCDy).",
1586 ),
1587 value: 16,
1588 },
1589 EnumVariant {
1590 name: "BS8_F",
1591 description: Some(
1592 "bsx_f provided to DFLTy (and SCDy).",
1593 ),
1594 value: 17,
1595 },
1596 EnumVariant {
1597 name: "BS9_R",
1598 description: Some(
1599 "bsx_r provided to DFLTy (and SCDy).",
1600 ),
1601 value: 18,
1602 },
1603 EnumVariant {
1604 name: "BS9_F",
1605 description: Some(
1606 "bsx_f provided to DFLTy (and SCDy).",
1607 ),
1608 value: 19,
1609 },
1610 EnumVariant {
1611 name: "BS10_R",
1612 description: Some(
1613 "bsx_r provided to DFLTy (and SCDy).",
1614 ),
1615 value: 20,
1616 },
1617 EnumVariant {
1618 name: "BS10_F",
1619 description: Some(
1620 "bsx_f provided to DFLTy (and SCDy).",
1621 ),
1622 value: 21,
1623 },
1624 EnumVariant {
1625 name: "BS11_R",
1626 description: Some(
1627 "bsx_r provided to DFLTy (and SCDy).",
1628 ),
1629 value: 22,
1630 },
1631 EnumVariant {
1632 name: "BS11_F",
1633 description: Some(
1634 "bsx_f provided to DFLTy (and SCDy).",
1635 ),
1636 value: 23,
1637 },
1638 EnumVariant {
1639 name: "BS12_R",
1640 description: Some(
1641 "bsx_r provided to DFLTy (and SCDy).",
1642 ),
1643 value: 24,
1644 },
1645 EnumVariant {
1646 name: "BS12_F",
1647 description: Some(
1648 "bsx_f provided to DFLTy (and SCDy).",
1649 ),
1650 value: 25,
1651 },
1652 EnumVariant {
1653 name: "BS13_R",
1654 description: Some(
1655 "bsx_r provided to DFLTy (and SCDy).",
1656 ),
1657 value: 26,
1658 },
1659 EnumVariant {
1660 name: "BS13_F",
1661 description: Some(
1662 "bsx_f provided to DFLTy (and SCDy).",
1663 ),
1664 value: 27,
1665 },
1666 EnumVariant {
1667 name: "BS14_R",
1668 description: Some(
1669 "bsx_r provided to DFLTy (and SCDy).",
1670 ),
1671 value: 28,
1672 },
1673 EnumVariant {
1674 name: "BS14_F",
1675 description: Some(
1676 "bsx_f provided to DFLTy (and SCDy).",
1677 ),
1678 value: 29,
1679 },
1680 EnumVariant {
1681 name: "BS15_R",
1682 description: Some(
1683 "bsx_r provided to DFLTy (and SCDy).",
1684 ),
1685 value: 30,
1686 },
1687 EnumVariant {
1688 name: "BS15_F",
1689 description: Some(
1690 "bsx_f provided to DFLTy (and SCDy).",
1691 ),
1692 value: 31,
1693 },
1694 ],
1695 },
1696 Enum {
1697 name: "Cckdir",
1698 description: Some(
1699 "CCK1 direction. This bit is set and reset by software. It is used to control the direction of the ADF_CCK1 pin.",
1700 ),
1701 bit_size: 1,
1702 variants: &[
1703 EnumVariant {
1704 name: "INPUT",
1705 description: Some(
1706 "CCK is an input.",
1707 ),
1708 value: 0,
1709 },
1710 EnumVariant {
1711 name: "OUTPUT",
1712 description: Some(
1713 "CCK is an output.",
1714 ),
1715 value: 1,
1716 },
1717 ],
1718 },
1719 Enum {
1720 name: "Cckdiv",
1721 description: Some(
1722 "Divider to control the CCK clock. This bit is set and reset by software. It is used to control the frequency of the bitstream clock on the CCK pin.",
1723 ),
1724 bit_size: 4,
1725 variants: &[
1726 EnumVariant {
1727 name: "DIV1",
1728 description: Some(
1729 "The ADF_CCK clock is adf_proc_ck.",
1730 ),
1731 value: 0,
1732 },
1733 EnumVariant {
1734 name: "DIV2",
1735 description: Some(
1736 "The ADF_CCK clock is adf_proc_ck divided by 2.",
1737 ),
1738 value: 1,
1739 },
1740 EnumVariant {
1741 name: "DIV3",
1742 description: Some(
1743 "The ADF_CCK clock is adf_proc_ck divided by 3.",
1744 ),
1745 value: 2,
1746 },
1747 EnumVariant {
1748 name: "DIV4",
1749 description: Some(
1750 "The ADF_CCK clock is adf_proc_ck divided by 4.",
1751 ),
1752 value: 3,
1753 },
1754 EnumVariant {
1755 name: "DIV5",
1756 description: Some(
1757 "The ADF_CCK clock is adf_proc_ck divided by 5.",
1758 ),
1759 value: 4,
1760 },
1761 EnumVariant {
1762 name: "DIV6",
1763 description: Some(
1764 "The ADF_CCK clock is adf_proc_ck divided by 6.",
1765 ),
1766 value: 5,
1767 },
1768 EnumVariant {
1769 name: "DIV7",
1770 description: Some(
1771 "The ADF_CCK clock is adf_proc_ck divided by 7.",
1772 ),
1773 value: 6,
1774 },
1775 EnumVariant {
1776 name: "DIV8",
1777 description: Some(
1778 "The ADF_CCK clock is adf_proc_ck divided by 8.",
1779 ),
1780 value: 7,
1781 },
1782 EnumVariant {
1783 name: "DIV9",
1784 description: Some(
1785 "The ADF_CCK clock is adf_proc_ck divided by 9.",
1786 ),
1787 value: 8,
1788 },
1789 EnumVariant {
1790 name: "DIV10",
1791 description: Some(
1792 "The ADF_CCK clock is adf_proc_ck divided by 10.",
1793 ),
1794 value: 9,
1795 },
1796 EnumVariant {
1797 name: "DIV11",
1798 description: Some(
1799 "The ADF_CCK clock is adf_proc_ck divided by 11.",
1800 ),
1801 value: 10,
1802 },
1803 EnumVariant {
1804 name: "DIV12",
1805 description: Some(
1806 "The ADF_CCK clock is adf_proc_ck divided by 12.",
1807 ),
1808 value: 11,
1809 },
1810 EnumVariant {
1811 name: "DIV13",
1812 description: Some(
1813 "The ADF_CCK clock is adf_proc_ck divided by 13.",
1814 ),
1815 value: 12,
1816 },
1817 EnumVariant {
1818 name: "DIV14",
1819 description: Some(
1820 "The ADF_CCK clock is adf_proc_ck divided by 14.",
1821 ),
1822 value: 13,
1823 },
1824 EnumVariant {
1825 name: "DIV15",
1826 description: Some(
1827 "The ADF_CCK clock is adf_proc_ck divided by 15.",
1828 ),
1829 value: 14,
1830 },
1831 EnumVariant {
1832 name: "DIV16",
1833 description: Some(
1834 "The ADF_CCK clock is adf_proc_ck divided by 16.",
1835 ),
1836 value: 15,
1837 },
1838 ],
1839 },
1840 Enum {
1841 name: "Ccken",
1842 description: Some(
1843 "CCK clock enable. This bit is set and reset by software. It is used to control the generation of the bitstream clock on the CCK pin.",
1844 ),
1845 bit_size: 1,
1846 variants: &[
1847 EnumVariant {
1848 name: "NOT_GENERATED",
1849 description: Some(
1850 "Bitstream clock not generated.",
1851 ),
1852 value: 0,
1853 },
1854 EnumVariant {
1855 name: "GENERATED",
1856 description: Some(
1857 "Bitstream clock generated on the CCK pin.",
1858 ),
1859 value: 1,
1860 },
1861 ],
1862 },
1863 Enum {
1864 name: "Cicmod",
1865 description: Some(
1866 "Select the CIC order. This bitfield is set and cleared by software. It is used to select the MCIC order.",
1867 ),
1868 bit_size: 3,
1869 variants: &[
1870 EnumVariant {
1871 name: "SINC4",
1872 description: Some(
1873 "MCIC configured in single Sinc4 filter.",
1874 ),
1875 value: 4,
1876 },
1877 EnumVariant {
1878 name: "SINC5",
1879 description: Some(
1880 "MCIC configured in single Sinc5 filter.",
1881 ),
1882 value: 5,
1883 },
1884 ],
1885 },
1886 Enum {
1887 name: "Ckgmod",
1888 description: Some(
1889 "Clock generator mode. This bit is set and reset by software. It is used to define the way the clock generator is enabled. This bit must not be changed if the filter is enabled (DFTEN = 1).",
1890 ),
1891 bit_size: 1,
1892 variants: &[
1893 EnumVariant {
1894 name: "IMMEDIATE",
1895 description: Some(
1896 "The kernel clock is provided to the dividers as soon as CKGDEN is set to 1.",
1897 ),
1898 value: 0,
1899 },
1900 EnumVariant {
1901 name: "TRIGGER",
1902 description: Some(
1903 "The kernel clock is provided to the dividers when CKGDEN is set to 1 and the trigger condition met.",
1904 ),
1905 value: 1,
1906 },
1907 ],
1908 },
1909 Enum {
1910 name: "Datcap",
1911 description: Some(
1912 "Data capture mode. This bitfield is set and cleared by software. It is used to define in which conditions, the samples provided by DLFT0 are stored into the memory.",
1913 ),
1914 bit_size: 2,
1915 variants: &[
1916 EnumVariant {
1917 name: "DISABLED",
1918 description: Some(
1919 "Samples from DFLT0 not transfered into the memory.",
1920 ),
1921 value: 0,
1922 },
1923 EnumVariant {
1924 name: "ON_DETECTED",
1925 description: Some(
1926 "Samples from DFLT0 transfered into the memory when SAD is in DETECT state.",
1927 ),
1928 value: 1,
1929 },
1930 EnumVariant {
1931 name: "ENABLED",
1932 description: Some(
1933 "Samples from DFLT0 transfered into memory when SAD and DFLT0 are enabled.",
1934 ),
1935 value: 2,
1936 },
1937 ],
1938 },
1939 Enum {
1940 name: "Datsrc",
1941 description: Some(
1942 "Source data for the digital filter.",
1943 ),
1944 bit_size: 2,
1945 variants: &[
1946 EnumVariant {
1947 name: "BSMX",
1948 description: Some(
1949 "Stream coming from the BSMX selected",
1950 ),
1951 value: 0,
1952 },
1953 EnumVariant {
1954 name: "ADCITF1",
1955 description: Some(
1956 "Stream coming from the ADCITF1 selected",
1957 ),
1958 value: 2,
1959 },
1960 EnumVariant {
1961 name: "ADCITF2",
1962 description: Some(
1963 "Stream coming from the ADCITF2 selected",
1964 ),
1965 value: 3,
1966 },
1967 ],
1968 },
1969 Enum {
1970 name: "Detcfg",
1971 description: Some(
1972 "Sound trigger event configuration. This bit is set and cleared by software. It is used to define if the sddet_evt event is generated only when the SAD enters to MONITOR state or when the SAD enters or exits the DETECT state.",
1973 ),
1974 bit_size: 1,
1975 variants: &[
1976 EnumVariant {
1977 name: "MONITOR",
1978 description: Some(
1979 "sddet_evt generated when SAD enters the MONITOR state.",
1980 ),
1981 value: 0,
1982 },
1983 EnumVariant {
1984 name: "DETECT",
1985 description: Some(
1986 "sddet_evt generated when SAD enters or exits the DETECT state.",
1987 ),
1988 value: 1,
1989 },
1990 ],
1991 },
1992 Enum {
1993 name: "Frsize",
1994 description: Some(
1995 "Frame size. This bitfield is set and cleared by software. it is used to define the size of one frame and also to define how many samples are taken into account to compute the short-term signal level.",
1996 ),
1997 bit_size: 3,
1998 variants: &[
1999 EnumVariant {
2000 name: "SAMPLES8",
2001 description: Some(
2002 "8 sample.",
2003 ),
2004 value: 0,
2005 },
2006 EnumVariant {
2007 name: "SAMPLES16",
2008 description: Some(
2009 "16 samples.",
2010 ),
2011 value: 1,
2012 },
2013 EnumVariant {
2014 name: "SAMPLES32",
2015 description: Some(
2016 "32 samples.",
2017 ),
2018 value: 2,
2019 },
2020 EnumVariant {
2021 name: "SAMPLES64",
2022 description: Some(
2023 "64 samples.",
2024 ),
2025 value: 3,
2026 },
2027 EnumVariant {
2028 name: "SAMPLES128",
2029 description: Some(
2030 "128 samples.",
2031 ),
2032 value: 4,
2033 },
2034 EnumVariant {
2035 name: "SAMPLES256",
2036 description: Some(
2037 "256 samples.",
2038 ),
2039 value: 5,
2040 },
2041 EnumVariant {
2042 name: "SAMPLES512",
2043 description: Some(
2044 "512 samples.",
2045 ),
2046 value: 6,
2047 },
2048 ],
2049 },
2050 Enum {
2051 name: "Hgovr",
2052 description: Some(
2053 "Hangover time window. This bitfield is set and cleared by software. It is used to select the hangover time window.",
2054 ),
2055 bit_size: 3,
2056 variants: &[
2057 EnumVariant {
2058 name: "FRAMES_4",
2059 description: Some(
2060 "SAD back to MONITOR state if sound is below threshold for 4 frames.",
2061 ),
2062 value: 0,
2063 },
2064 EnumVariant {
2065 name: "FRAMES_8",
2066 description: Some(
2067 "SAD back to MONITOR state if sound is below threshold for 4 frames.",
2068 ),
2069 value: 1,
2070 },
2071 EnumVariant {
2072 name: "FRAMES_16",
2073 description: Some(
2074 "SAD back to MONITOR state if sound is below threshold for 4 frames.",
2075 ),
2076 value: 2,
2077 },
2078 EnumVariant {
2079 name: "FRAMES_32",
2080 description: Some(
2081 "SAD back to MONITOR state if sound is below threshold for 4 frames.",
2082 ),
2083 value: 3,
2084 },
2085 EnumVariant {
2086 name: "FRAMES_64",
2087 description: Some(
2088 "SAD back to MONITOR state if sound is below threshold for 4 frames.",
2089 ),
2090 value: 4,
2091 },
2092 EnumVariant {
2093 name: "FRAMES_128",
2094 description: Some(
2095 "SAD back to MONITOR state if sound is below threshold for 4 frames.",
2096 ),
2097 value: 5,
2098 },
2099 EnumVariant {
2100 name: "FRAMES_256",
2101 description: Some(
2102 "SAD back to MONITOR state if sound is below threshold for 4 frames.",
2103 ),
2104 value: 6,
2105 },
2106 EnumVariant {
2107 name: "FRAMES_512",
2108 description: Some(
2109 "SAD back to MONITOR state if sound is below threshold for 4 frames.",
2110 ),
2111 value: 7,
2112 },
2113 ],
2114 },
2115 Enum {
2116 name: "Hpfc",
2117 description: Some(
2118 "High-pass filter cut-off frequency. This bitfield is set and cleared by software. it is used to select the cut-off frequency of the high-pass filter. F PCM represents the sampling frequency at HPF input.",
2119 ),
2120 bit_size: 2,
2121 variants: &[
2122 EnumVariant {
2123 name: "LOW",
2124 description: Some(
2125 "Cut-off frequency = 0.000625 x FPCM.",
2126 ),
2127 value: 0,
2128 },
2129 EnumVariant {
2130 name: "MEDIUM",
2131 description: Some(
2132 "Cut-off frequency = 0.00125 x FPCM.",
2133 ),
2134 value: 1,
2135 },
2136 EnumVariant {
2137 name: "HIGH",
2138 description: Some(
2139 "Cut-off frequency = 0.00250 x FPCM",
2140 ),
2141 value: 2,
2142 },
2143 EnumVariant {
2144 name: "MAXIMUM",
2145 description: Some(
2146 "Cut-off frequency = 0.00950 x FPCM",
2147 ),
2148 value: 3,
2149 },
2150 ],
2151 },
2152 Enum {
2153 name: "Lfrnb",
2154 description: Some(
2155 "LFRNB. This bitfield is set and cleared by software. It is used to define the number of learning frames to perform the first estimate of the noise level.",
2156 ),
2157 bit_size: 3,
2158 variants: &[
2159 EnumVariant {
2160 name: "FRAMES_2",
2161 description: Some(
2162 "2 samples.",
2163 ),
2164 value: 0,
2165 },
2166 EnumVariant {
2167 name: "FRAMES_4",
2168 description: Some(
2169 "4 samples.",
2170 ),
2171 value: 1,
2172 },
2173 EnumVariant {
2174 name: "FRAMES_8",
2175 description: Some(
2176 "8 samples.",
2177 ),
2178 value: 2,
2179 },
2180 EnumVariant {
2181 name: "FRAMES_16",
2182 description: Some(
2183 "16 samples.",
2184 ),
2185 value: 3,
2186 },
2187 EnumVariant {
2188 name: "FRAMES_32",
2189 description: Some(
2190 "32 samples.",
2191 ),
2192 value: 4,
2193 },
2194 ],
2195 },
2196 Enum {
2197 name: "Rsfltd",
2198 description: Some(
2199 "Reshaper filter decimation ratio. This bitfield is set and cleared by software. It is used to select the decimation ratio of the reshaper filter.",
2200 ),
2201 bit_size: 1,
2202 variants: &[
2203 EnumVariant {
2204 name: "DECIMATION4",
2205 description: Some(
2206 "Decimation ratio is 4 (default value).",
2207 ),
2208 value: 0,
2209 },
2210 EnumVariant {
2211 name: "DECIMATION1",
2212 description: Some(
2213 "Decimation ratio is 1.",
2214 ),
2215 value: 1,
2216 },
2217 ],
2218 },
2219 Enum {
2220 name: "Rxfifo",
2221 description: Some(
2222 "RXFIFO threshold selection. This bitfield is set and cleared by software. It is used to select the RXFIFO threshold.",
2223 ),
2224 bit_size: 1,
2225 variants: &[
2226 EnumVariant {
2227 name: "NOT_EMPTY",
2228 description: Some(
2229 "RXFIFO threshold event generated when the RXFIFO is not empty",
2230 ),
2231 value: 0,
2232 },
2233 EnumVariant {
2234 name: "HALF_FULL",
2235 description: Some(
2236 "RXFIFO threshold event generated when the RXFIFO is half-full",
2237 ),
2238 value: 1,
2239 },
2240 ],
2241 },
2242 Enum {
2243 name: "Sadmod",
2244 description: Some(
2245 "SAD working mode. This bitfield is set and cleared by software. It is used to define the way the SAD works",
2246 ),
2247 bit_size: 2,
2248 variants: &[
2249 EnumVariant {
2250 name: "THRESHOLD_ESTIMATED_AMBIENT_NOISE",
2251 description: Some(
2252 "Threshold value computed according to the estimated ambient noise. The SAD triggers when the sound level (SDLVL) is bigger than the defined threshold. In this mode, the SAD works like a voice activity detector.",
2253 ),
2254 value: 0,
2255 },
2256 EnumVariant {
2257 name: "THRESHOLD_MINIMUM_NOISELEVEL",
2258 description: Some(
2259 "Threshold value equal to ANMIN[12:0], multiplied by the gain selected by SNTHR[3:0] The SAD triggers when the sound level (SDLVL) is bigger than the defined threshold. In this mode, the SAD works like a sound detector.",
2260 ),
2261 value: 1,
2262 },
2263 EnumVariant {
2264 name: "THRESHOLD_MINIMUM_NOISELEVELX4",
2265 description: Some(
2266 "Threshold value given by 4 x ANMIN[12:0]. The SAD triggers when the estimated ambient noise (ANLVL), multiplied by the gain selected by SNTHR[3:0] is bigger than the defined threshold. In this mode, the SAD is working like an ambient noise estimator. Hysteresis function cannot be used in this mode.",
2267 ),
2268 value: 2,
2269 },
2270 ],
2271 },
2272 Enum {
2273 name: "Sadst",
2274 description: Some(
2275 "SAD state. This bitfield is set and cleared by hardware. It indicates the SAD state and is meaningful only when SADEN = 1.",
2276 ),
2277 bit_size: 2,
2278 variants: &[
2279 EnumVariant {
2280 name: "LEARN",
2281 description: Some(
2282 "SAD in LEARN state.",
2283 ),
2284 value: 0,
2285 },
2286 EnumVariant {
2287 name: "MONITOR",
2288 description: Some(
2289 "SAD in MONITOR state.",
2290 ),
2291 value: 1,
2292 },
2293 EnumVariant {
2294 name: "DETECT",
2295 description: Some(
2296 "SAD in DETECT state.",
2297 ),
2298 value: 2,
2299 },
2300 ],
2301 },
2302 Enum {
2303 name: "Scksrc",
2304 description: Some(
2305 "Serial clock source. This bitfield is set and cleared by software. It is used to select the clock source of the serial interface.",
2306 ),
2307 bit_size: 2,
2308 variants: &[
2309 EnumVariant {
2310 name: "CCK0",
2311 description: Some(
2312 "Serial clock source is CCK0.",
2313 ),
2314 value: 0,
2315 },
2316 EnumVariant {
2317 name: "CCK1",
2318 description: Some(
2319 "Serial clock source is CCK1.",
2320 ),
2321 value: 1,
2322 },
2323 EnumVariant {
2324 name: "CKI0",
2325 description: Some(
2326 "Serial clock source is CCI0.",
2327 ),
2328 value: 2,
2329 },
2330 EnumVariant {
2331 name: "CKI1",
2332 description: Some(
2333 "Serial clock source is CCI1.",
2334 ),
2335 value: 3,
2336 },
2337 ],
2338 },
2339 Enum {
2340 name: "Sitfmod",
2341 description: Some(
2342 "Serial interface mode. This bitfield is set and cleared by software. It is used to select the serial interface mode.",
2343 ),
2344 bit_size: 2,
2345 variants: &[
2346 EnumVariant {
2347 name: "MASTER_SPI",
2348 description: Some(
2349 "LF_MASTER SPI mode.",
2350 ),
2351 value: 0,
2352 },
2353 EnumVariant {
2354 name: "NORMAL_SPI",
2355 description: Some(
2356 "Normal SPI mode.",
2357 ),
2358 value: 1,
2359 },
2360 EnumVariant {
2361 name: "MANCHESTER_FALLING",
2362 description: Some(
2363 "Manchester mode rising edge = logic 0, falling edge = logic 1.",
2364 ),
2365 value: 2,
2366 },
2367 EnumVariant {
2368 name: "MANCHESTER_RISING",
2369 description: Some(
2370 "Manchester mode rising edge = logic 1, falling edge = logic 0.",
2371 ),
2372 value: 3,
2373 },
2374 ],
2375 },
2376 Enum {
2377 name: "Snthr",
2378 description: Some(
2379 "SNTHR. This bitfield is set and cleared by software. It is used to select the gain to be applied at CIC output. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back this bitfield informs the application on the current gain value.",
2380 ),
2381 bit_size: 4,
2382 variants: &[
2383 EnumVariant {
2384 name: "NOISE_PLUS_3_5",
2385 description: Some(
2386 "Threshold is 3.5 dB higher than ANLVL",
2387 ),
2388 value: 0,
2389 },
2390 EnumVariant {
2391 name: "NOISE_PLUS_6_0",
2392 description: Some(
2393 "Threshold is 6.0 dB higher than ANLVL",
2394 ),
2395 value: 1,
2396 },
2397 EnumVariant {
2398 name: "NOISE_PLUS_9_5",
2399 description: Some(
2400 "Threshold is 9.5 dB higher than ANLVL",
2401 ),
2402 value: 2,
2403 },
2404 EnumVariant {
2405 name: "NOISE_PLUS_12",
2406 description: Some(
2407 "Threshold is 12 dB higher than ANLVL",
2408 ),
2409 value: 3,
2410 },
2411 EnumVariant {
2412 name: "NOISE_PLUS_15_6",
2413 description: Some(
2414 "Threshold is 15.6 dB higher than ANLVL",
2415 ),
2416 value: 4,
2417 },
2418 EnumVariant {
2419 name: "NOISE_PLUS_18",
2420 description: Some(
2421 "Threshold is 18 dB higher than ANLVL",
2422 ),
2423 value: 5,
2424 },
2425 EnumVariant {
2426 name: "NOISE_PLUS_21_6",
2427 description: Some(
2428 "Threshold is 21.6 dB higher than ANLVL",
2429 ),
2430 value: 6,
2431 },
2432 EnumVariant {
2433 name: "NOISE_PLUS_24_1",
2434 description: Some(
2435 "Threshold is 24.1 dB higher than ANLVL",
2436 ),
2437 value: 7,
2438 },
2439 EnumVariant {
2440 name: "NOISE_PLUS_27_6",
2441 description: Some(
2442 "Threshold is 27.6 dB higher than ANLVL",
2443 ),
2444 value: 8,
2445 },
2446 EnumVariant {
2447 name: "NOISE_PLUS_30_1",
2448 description: Some(
2449 "Threshold is 30.1 dB higher than ANLVL",
2450 ),
2451 value: 9,
2452 },
2453 ],
2454 },
2455 Enum {
2456 name: "Trgsens",
2457 description: Some(
2458 "CKGEN trigger sensitivity selection. This bit is set and cleared by software. It is used to select the trigger sensitivity of the trigger signals. This bit is not significant if the CKGMOD = 0.",
2459 ),
2460 bit_size: 1,
2461 variants: &[
2462 EnumVariant {
2463 name: "RISING_EDGE",
2464 description: Some(
2465 "A rising edge event triggers the activation of CKGEN dividers.",
2466 ),
2467 value: 0,
2468 },
2469 EnumVariant {
2470 name: "FALLING_EDGE",
2471 description: Some(
2472 "A falling edge even triggers the activation of CKGEN dividers.",
2473 ),
2474 value: 1,
2475 },
2476 ],
2477 },
2478 Enum {
2479 name: "Trgsrc",
2480 description: Some(
2481 "Digital filter trigger signal selection.",
2482 ),
2483 bit_size: 4,
2484 variants: &[
2485 EnumVariant {
2486 name: "TRGO",
2487 description: Some(
2488 "TRGO Selected.",
2489 ),
2490 value: 0,
2491 },
2492 EnumVariant {
2493 name: "TRG1",
2494 description: Some(
2495 "adf_trg1 selected.",
2496 ),
2497 value: 2,
2498 },
2499 ],
2500 },
2501 ],
2502};
2503