1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[Block {
5 name: "Aes",
6 extends: None,
7 description: Some("Advanced encryption standard hardware accelerator"),
8 items: &[
9 BlockItem {
10 name: "cr",
11 description: Some("Control register"),
12 array: None,
13 byte_offset: 0x0,
14 inner: BlockItemInner::Register(Register {
15 access: Access::ReadWrite,
16 bit_size: 32,
17 fieldset: Some("Cr"),
18 }),
19 },
20 BlockItem {
21 name: "sr",
22 description: Some("Status register"),
23 array: None,
24 byte_offset: 0x4,
25 inner: BlockItemInner::Register(Register {
26 access: Access::ReadWrite,
27 bit_size: 32,
28 fieldset: Some("Sr"),
29 }),
30 },
31 BlockItem {
32 name: "dinr",
33 description: Some("Data input register"),
34 array: None,
35 byte_offset: 0x8,
36 inner: BlockItemInner::Register(Register {
37 access: Access::ReadWrite,
38 bit_size: 32,
39 fieldset: None,
40 }),
41 },
42 BlockItem {
43 name: "doutr",
44 description: Some("Data output register"),
45 array: None,
46 byte_offset: 0xc,
47 inner: BlockItemInner::Register(Register {
48 access: Access::ReadWrite,
49 bit_size: 32,
50 fieldset: None,
51 }),
52 },
53 BlockItem {
54 name: "keyr",
55 description: Some("Key register"),
56 array: Some(Array::Cursed(CursedArray {
57 offsets: &[0, 4, 8, 12, 32, 36, 40, 44],
58 })),
59 byte_offset: 0x10,
60 inner: BlockItemInner::Register(Register {
61 access: Access::ReadWrite,
62 bit_size: 32,
63 fieldset: None,
64 }),
65 },
66 BlockItem {
67 name: "ivr",
68 description: Some("Initialization vector register"),
69 array: Some(Array::Regular(RegularArray { len: 4, stride: 4 })),
70 byte_offset: 0x20,
71 inner: BlockItemInner::Register(Register {
72 access: Access::ReadWrite,
73 bit_size: 32,
74 fieldset: None,
75 }),
76 },
77 BlockItem {
78 name: "suspr",
79 description: Some("Suspend register"),
80 array: Some(Array::Regular(RegularArray { len: 8, stride: 4 })),
81 byte_offset: 0x40,
82 inner: BlockItemInner::Register(Register {
83 access: Access::ReadWrite,
84 bit_size: 32,
85 fieldset: None,
86 }),
87 },
88 BlockItem {
89 name: "ier",
90 description: Some("interrupt enable register"),
91 array: None,
92 byte_offset: 0x300,
93 inner: BlockItemInner::Register(Register {
94 access: Access::ReadWrite,
95 bit_size: 32,
96 fieldset: Some("Ier"),
97 }),
98 },
99 BlockItem {
100 name: "isr",
101 description: Some("interrupt status register"),
102 array: None,
103 byte_offset: 0x304,
104 inner: BlockItemInner::Register(Register {
105 access: Access::ReadWrite,
106 bit_size: 32,
107 fieldset: Some("Isr"),
108 }),
109 },
110 BlockItem {
111 name: "icr",
112 description: Some("interrupt clear register"),
113 array: None,
114 byte_offset: 0x308,
115 inner: BlockItemInner::Register(Register {
116 access: Access::ReadWrite,
117 bit_size: 32,
118 fieldset: Some("Icr"),
119 }),
120 },
121 ],
122 }],
123 fieldsets: &[
124 FieldSet {
125 name: "Cr",
126 extends: None,
127 description: Some("Control register"),
128 bit_size: 32,
129 fields: &[
130 Field {
131 name: "en",
132 description: Some("AES enable"),
133 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
134 bit_size: 1,
135 array: None,
136 enumm: None,
137 },
138 Field {
139 name: "datatype",
140 description: Some("Data type selection"),
141 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
142 bit_size: 2,
143 array: None,
144 enumm: Some("Datatype"),
145 },
146 Field {
147 name: "mode",
148 description: Some("Operating mode"),
149 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
150 bit_size: 2,
151 array: None,
152 enumm: Some("Mode"),
153 },
154 Field {
155 name: "chmod",
156 description: Some("Chaining mode selection"),
157 bit_offset: BitOffset::Cursed(CursedBitOffset {
158 ranges: &[5..=6, 16..=16],
159 }),
160 bit_size: 3,
161 array: None,
162 enumm: Some("Chmod"),
163 },
164 Field {
165 name: "dmainen",
166 description: Some("Enable DMA management of data input phase"),
167 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 11 }),
168 bit_size: 1,
169 array: None,
170 enumm: None,
171 },
172 Field {
173 name: "dmaouten",
174 description: Some("Enable DMA management of data output phase"),
175 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
176 bit_size: 1,
177 array: None,
178 enumm: None,
179 },
180 Field {
181 name: "gcmph",
182 description: Some("GCM or CCM phase selection"),
183 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 13 }),
184 bit_size: 2,
185 array: None,
186 enumm: Some("Gcmph"),
187 },
188 Field {
189 name: "keysize",
190 description: Some("Key size selection"),
191 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }),
192 bit_size: 1,
193 array: None,
194 enumm: None,
195 },
196 Field {
197 name: "npblb",
198 description: Some("Number of padding bytes in last block of payload"),
199 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 20 }),
200 bit_size: 4,
201 array: None,
202 enumm: None,
203 },
204 Field {
205 name: "kmod",
206 description: Some("Key mode selection"),
207 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
208 bit_size: 2,
209 array: None,
210 enumm: None,
211 },
212 Field {
213 name: "iprst",
214 description: Some("AES peripheral software reset"),
215 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 31 }),
216 bit_size: 1,
217 array: None,
218 enumm: None,
219 },
220 ],
221 },
222 FieldSet {
223 name: "Icr",
224 extends: None,
225 description: Some("Interrupt clear register"),
226 bit_size: 32,
227 fields: &[
228 Field {
229 name: "ccf",
230 description: Some("Computation complete flag clear"),
231 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
232 bit_size: 1,
233 array: None,
234 enumm: None,
235 },
236 Field {
237 name: "rweif",
238 description: Some("Read or write error interrupt flag clear"),
239 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
240 bit_size: 1,
241 array: None,
242 enumm: None,
243 },
244 Field {
245 name: "keif",
246 description: Some("Key error interrupt flag clear"),
247 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
248 bit_size: 1,
249 array: None,
250 enumm: None,
251 },
252 ],
253 },
254 FieldSet {
255 name: "Ier",
256 extends: None,
257 description: Some("Interrupt enable register"),
258 bit_size: 32,
259 fields: &[
260 Field {
261 name: "ccfie",
262 description: Some("Computation complete flag interrupt enable"),
263 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
264 bit_size: 1,
265 array: None,
266 enumm: None,
267 },
268 Field {
269 name: "rweie",
270 description: Some("Read or write error interrupt enable"),
271 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
272 bit_size: 1,
273 array: None,
274 enumm: None,
275 },
276 Field {
277 name: "keie",
278 description: Some("Key error interrupt enable"),
279 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
280 bit_size: 1,
281 array: None,
282 enumm: None,
283 },
284 ],
285 },
286 FieldSet {
287 name: "Isr",
288 extends: None,
289 description: Some("Interrupt status register"),
290 bit_size: 32,
291 fields: &[
292 Field {
293 name: "ccf",
294 description: Some("Computation complete flag"),
295 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
296 bit_size: 1,
297 array: None,
298 enumm: None,
299 },
300 Field {
301 name: "rweif",
302 description: Some("Read or write error interrupt flag"),
303 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
304 bit_size: 1,
305 array: None,
306 enumm: None,
307 },
308 Field {
309 name: "keif",
310 description: Some("Key error interrupt flag"),
311 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
312 bit_size: 1,
313 array: None,
314 enumm: None,
315 },
316 ],
317 },
318 FieldSet {
319 name: "Sr",
320 extends: None,
321 description: Some("Status register"),
322 bit_size: 32,
323 fields: &[
324 Field {
325 name: "ccf",
326 description: Some("Computation complete flag"),
327 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
328 bit_size: 1,
329 array: None,
330 enumm: None,
331 },
332 Field {
333 name: "rderr",
334 description: Some("Read error flag"),
335 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
336 bit_size: 1,
337 array: None,
338 enumm: None,
339 },
340 Field {
341 name: "wrerr",
342 description: Some("Write error flag"),
343 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
344 bit_size: 1,
345 array: None,
346 enumm: None,
347 },
348 Field {
349 name: "busy",
350 description: Some("Busy flag"),
351 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
352 bit_size: 1,
353 array: None,
354 enumm: None,
355 },
356 Field {
357 name: "keyvalid",
358 description: Some("Key valid flag"),
359 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 7 }),
360 bit_size: 1,
361 array: None,
362 enumm: None,
363 },
364 ],
365 },
366 ],
367 enums: &[
368 Enum {
369 name: "Chmod",
370 description: None,
371 bit_size: 3,
372 variants: &[
373 EnumVariant {
374 name: "ECB",
375 description: Some("Electronic codebook"),
376 value: 0,
377 },
378 EnumVariant {
379 name: "CBC",
380 description: Some("Cipher-block chaining"),
381 value: 1,
382 },
383 EnumVariant {
384 name: "CTR",
385 description: Some("Counter mode"),
386 value: 2,
387 },
388 EnumVariant {
389 name: "GCM_GMAC",
390 description: Some("Galois counter mode and Galois message authentication code"),
391 value: 3,
392 },
393 EnumVariant {
394 name: "CCM",
395 description: Some("Counter with CBC-MAC"),
396 value: 4,
397 },
398 ],
399 },
400 Enum {
401 name: "Datatype",
402 description: None,
403 bit_size: 2,
404 variants: &[
405 EnumVariant {
406 name: "NONE",
407 description: Some("Word"),
408 value: 0,
409 },
410 EnumVariant {
411 name: "HALF_WORD",
412 description: Some("Half-word (16-bit)"),
413 value: 1,
414 },
415 EnumVariant {
416 name: "BYTE",
417 description: Some("Byte (8-bit)"),
418 value: 2,
419 },
420 EnumVariant {
421 name: "BIT",
422 description: Some("Bit"),
423 value: 3,
424 },
425 ],
426 },
427 Enum {
428 name: "Gcmph",
429 description: None,
430 bit_size: 2,
431 variants: &[
432 EnumVariant {
433 name: "INIT_PHASE",
434 description: Some("Init phase"),
435 value: 0,
436 },
437 EnumVariant {
438 name: "HEADER_PHASE",
439 description: Some("Header phase"),
440 value: 1,
441 },
442 EnumVariant {
443 name: "PAYLOAD_PHASE",
444 description: Some("Payload phase"),
445 value: 2,
446 },
447 EnumVariant {
448 name: "FINAL_PHASE",
449 description: Some("Final phase"),
450 value: 3,
451 },
452 ],
453 },
454 Enum {
455 name: "Mode",
456 description: None,
457 bit_size: 2,
458 variants: &[
459 EnumVariant {
460 name: "MODE1",
461 description: Some("Encryption"),
462 value: 0,
463 },
464 EnumVariant {
465 name: "MODE2",
466 description: Some("Key derivation (or key preparation for ECB/CBC decryption)"),
467 value: 1,
468 },
469 EnumVariant {
470 name: "MODE3",
471 description: Some("Decryption"),
472 value: 2,
473 },
474 ],
475 },
476 ],
477};
478