1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Fdcan",
7 extends: None,
8 description: Some(
9 "Controller area network with flexible data rate (FD)",
10 ),
11 items: &[
12 BlockItem {
13 name: "crel",
14 description: Some(
15 "FDCAN core release register",
16 ),
17 array: None,
18 byte_offset: 0x0,
19 inner: BlockItemInner::Register(
20 Register {
21 access: Access::ReadWrite,
22 bit_size: 32,
23 fieldset: Some(
24 "Crel",
25 ),
26 },
27 ),
28 },
29 BlockItem {
30 name: "endn",
31 description: Some(
32 "FDCAN endian register",
33 ),
34 array: None,
35 byte_offset: 0x4,
36 inner: BlockItemInner::Register(
37 Register {
38 access: Access::ReadWrite,
39 bit_size: 32,
40 fieldset: Some(
41 "Endn",
42 ),
43 },
44 ),
45 },
46 BlockItem {
47 name: "dbtp",
48 description: Some(
49 "FDCAN data bit timing and prescaler register",
50 ),
51 array: None,
52 byte_offset: 0xc,
53 inner: BlockItemInner::Register(
54 Register {
55 access: Access::ReadWrite,
56 bit_size: 32,
57 fieldset: Some(
58 "Dbtp",
59 ),
60 },
61 ),
62 },
63 BlockItem {
64 name: "test",
65 description: Some(
66 "FDCAN test register",
67 ),
68 array: None,
69 byte_offset: 0x10,
70 inner: BlockItemInner::Register(
71 Register {
72 access: Access::ReadWrite,
73 bit_size: 32,
74 fieldset: Some(
75 "Test",
76 ),
77 },
78 ),
79 },
80 BlockItem {
81 name: "rwd",
82 description: Some(
83 "FDCAN RAM watchdog register",
84 ),
85 array: None,
86 byte_offset: 0x14,
87 inner: BlockItemInner::Register(
88 Register {
89 access: Access::ReadWrite,
90 bit_size: 32,
91 fieldset: Some(
92 "Rwd",
93 ),
94 },
95 ),
96 },
97 BlockItem {
98 name: "cccr",
99 description: Some(
100 "FDCAN CC control register",
101 ),
102 array: None,
103 byte_offset: 0x18,
104 inner: BlockItemInner::Register(
105 Register {
106 access: Access::ReadWrite,
107 bit_size: 32,
108 fieldset: Some(
109 "Cccr",
110 ),
111 },
112 ),
113 },
114 BlockItem {
115 name: "nbtp",
116 description: Some(
117 "FDCAN nominal bit timing and prescaler register",
118 ),
119 array: None,
120 byte_offset: 0x1c,
121 inner: BlockItemInner::Register(
122 Register {
123 access: Access::ReadWrite,
124 bit_size: 32,
125 fieldset: Some(
126 "Nbtp",
127 ),
128 },
129 ),
130 },
131 BlockItem {
132 name: "tscc",
133 description: Some(
134 "FDCAN timestamp counter configuration register",
135 ),
136 array: None,
137 byte_offset: 0x20,
138 inner: BlockItemInner::Register(
139 Register {
140 access: Access::ReadWrite,
141 bit_size: 32,
142 fieldset: Some(
143 "Tscc",
144 ),
145 },
146 ),
147 },
148 BlockItem {
149 name: "tscv",
150 description: Some(
151 "FDCAN timestamp counter value register",
152 ),
153 array: None,
154 byte_offset: 0x24,
155 inner: BlockItemInner::Register(
156 Register {
157 access: Access::ReadWrite,
158 bit_size: 32,
159 fieldset: Some(
160 "Tscv",
161 ),
162 },
163 ),
164 },
165 BlockItem {
166 name: "tocc",
167 description: Some(
168 "FDCAN timeout counter configuration register",
169 ),
170 array: None,
171 byte_offset: 0x28,
172 inner: BlockItemInner::Register(
173 Register {
174 access: Access::ReadWrite,
175 bit_size: 32,
176 fieldset: Some(
177 "Tocc",
178 ),
179 },
180 ),
181 },
182 BlockItem {
183 name: "tocv",
184 description: Some(
185 "FDCAN timeout counter value register",
186 ),
187 array: None,
188 byte_offset: 0x2c,
189 inner: BlockItemInner::Register(
190 Register {
191 access: Access::ReadWrite,
192 bit_size: 32,
193 fieldset: Some(
194 "Tocv",
195 ),
196 },
197 ),
198 },
199 BlockItem {
200 name: "ecr",
201 description: Some(
202 "FDCAN error counter register",
203 ),
204 array: None,
205 byte_offset: 0x40,
206 inner: BlockItemInner::Register(
207 Register {
208 access: Access::ReadWrite,
209 bit_size: 32,
210 fieldset: Some(
211 "Ecr",
212 ),
213 },
214 ),
215 },
216 BlockItem {
217 name: "psr",
218 description: Some(
219 "FDCAN protocol status register",
220 ),
221 array: None,
222 byte_offset: 0x44,
223 inner: BlockItemInner::Register(
224 Register {
225 access: Access::ReadWrite,
226 bit_size: 32,
227 fieldset: Some(
228 "Psr",
229 ),
230 },
231 ),
232 },
233 BlockItem {
234 name: "tdcr",
235 description: Some(
236 "FDCAN transmitter delay compensation register",
237 ),
238 array: None,
239 byte_offset: 0x48,
240 inner: BlockItemInner::Register(
241 Register {
242 access: Access::ReadWrite,
243 bit_size: 32,
244 fieldset: Some(
245 "Tdcr",
246 ),
247 },
248 ),
249 },
250 BlockItem {
251 name: "ir",
252 description: Some(
253 "FDCAN interrupt register",
254 ),
255 array: None,
256 byte_offset: 0x50,
257 inner: BlockItemInner::Register(
258 Register {
259 access: Access::ReadWrite,
260 bit_size: 32,
261 fieldset: Some(
262 "Ir",
263 ),
264 },
265 ),
266 },
267 BlockItem {
268 name: "ie",
269 description: Some(
270 "FDCAN interrupt enable register",
271 ),
272 array: None,
273 byte_offset: 0x54,
274 inner: BlockItemInner::Register(
275 Register {
276 access: Access::ReadWrite,
277 bit_size: 32,
278 fieldset: Some(
279 "Ie",
280 ),
281 },
282 ),
283 },
284 BlockItem {
285 name: "ils",
286 description: Some(
287 "FDCAN interrupt line select register",
288 ),
289 array: None,
290 byte_offset: 0x58,
291 inner: BlockItemInner::Register(
292 Register {
293 access: Access::ReadWrite,
294 bit_size: 32,
295 fieldset: Some(
296 "Ils",
297 ),
298 },
299 ),
300 },
301 BlockItem {
302 name: "ile",
303 description: Some(
304 "FDCAN interrupt line enable register",
305 ),
306 array: None,
307 byte_offset: 0x5c,
308 inner: BlockItemInner::Register(
309 Register {
310 access: Access::ReadWrite,
311 bit_size: 32,
312 fieldset: Some(
313 "Ile",
314 ),
315 },
316 ),
317 },
318 BlockItem {
319 name: "rxgfc",
320 description: Some(
321 "FDCAN global filter configuration register",
322 ),
323 array: None,
324 byte_offset: 0x80,
325 inner: BlockItemInner::Register(
326 Register {
327 access: Access::ReadWrite,
328 bit_size: 32,
329 fieldset: Some(
330 "Rxgfc",
331 ),
332 },
333 ),
334 },
335 BlockItem {
336 name: "xidam",
337 description: Some(
338 "FDCAN extended ID and mask register",
339 ),
340 array: None,
341 byte_offset: 0x84,
342 inner: BlockItemInner::Register(
343 Register {
344 access: Access::ReadWrite,
345 bit_size: 32,
346 fieldset: Some(
347 "Xidam",
348 ),
349 },
350 ),
351 },
352 BlockItem {
353 name: "hpms",
354 description: Some(
355 "FDCAN high-priority message status register",
356 ),
357 array: None,
358 byte_offset: 0x88,
359 inner: BlockItemInner::Register(
360 Register {
361 access: Access::ReadWrite,
362 bit_size: 32,
363 fieldset: Some(
364 "Hpms",
365 ),
366 },
367 ),
368 },
369 BlockItem {
370 name: "rxfs",
371 description: Some(
372 "FDCAN Rx FIFO X status register",
373 ),
374 array: Some(
375 Array::Cursed(
376 CursedArray {
377 offsets: &[
378 0,
379 8,
380 ],
381 },
382 ),
383 ),
384 byte_offset: 0x90,
385 inner: BlockItemInner::Register(
386 Register {
387 access: Access::ReadWrite,
388 bit_size: 32,
389 fieldset: Some(
390 "Rxfs",
391 ),
392 },
393 ),
394 },
395 BlockItem {
396 name: "rxfa",
397 description: Some(
398 "CAN Rx FIFO X acknowledge register",
399 ),
400 array: Some(
401 Array::Cursed(
402 CursedArray {
403 offsets: &[
404 0,
405 8,
406 ],
407 },
408 ),
409 ),
410 byte_offset: 0x94,
411 inner: BlockItemInner::Register(
412 Register {
413 access: Access::ReadWrite,
414 bit_size: 32,
415 fieldset: Some(
416 "Rxfa",
417 ),
418 },
419 ),
420 },
421 BlockItem {
422 name: "txbc",
423 description: Some(
424 "FDCAN Tx buffer configuration register",
425 ),
426 array: None,
427 byte_offset: 0xc0,
428 inner: BlockItemInner::Register(
429 Register {
430 access: Access::ReadWrite,
431 bit_size: 32,
432 fieldset: Some(
433 "Txbc",
434 ),
435 },
436 ),
437 },
438 BlockItem {
439 name: "txfqs",
440 description: Some(
441 "FDCAN Tx FIFO/queue status register",
442 ),
443 array: None,
444 byte_offset: 0xc4,
445 inner: BlockItemInner::Register(
446 Register {
447 access: Access::ReadWrite,
448 bit_size: 32,
449 fieldset: Some(
450 "Txfqs",
451 ),
452 },
453 ),
454 },
455 BlockItem {
456 name: "txbrp",
457 description: Some(
458 "FDCAN Tx buffer request pending register",
459 ),
460 array: None,
461 byte_offset: 0xc8,
462 inner: BlockItemInner::Register(
463 Register {
464 access: Access::ReadWrite,
465 bit_size: 32,
466 fieldset: Some(
467 "Txbrp",
468 ),
469 },
470 ),
471 },
472 BlockItem {
473 name: "txbar",
474 description: Some(
475 "FDCAN Tx buffer add request register",
476 ),
477 array: None,
478 byte_offset: 0xcc,
479 inner: BlockItemInner::Register(
480 Register {
481 access: Access::ReadWrite,
482 bit_size: 32,
483 fieldset: Some(
484 "Txbar",
485 ),
486 },
487 ),
488 },
489 BlockItem {
490 name: "txbcr",
491 description: Some(
492 "FDCAN Tx buffer cancellation request register",
493 ),
494 array: None,
495 byte_offset: 0xd0,
496 inner: BlockItemInner::Register(
497 Register {
498 access: Access::ReadWrite,
499 bit_size: 32,
500 fieldset: Some(
501 "Txbcr",
502 ),
503 },
504 ),
505 },
506 BlockItem {
507 name: "txbto",
508 description: Some(
509 "FDCAN Tx buffer transmission occurred register",
510 ),
511 array: None,
512 byte_offset: 0xd4,
513 inner: BlockItemInner::Register(
514 Register {
515 access: Access::ReadWrite,
516 bit_size: 32,
517 fieldset: Some(
518 "Txbto",
519 ),
520 },
521 ),
522 },
523 BlockItem {
524 name: "txbcf",
525 description: Some(
526 "FDCAN Tx buffer cancellation finished register",
527 ),
528 array: None,
529 byte_offset: 0xd8,
530 inner: BlockItemInner::Register(
531 Register {
532 access: Access::ReadWrite,
533 bit_size: 32,
534 fieldset: Some(
535 "Txbcf",
536 ),
537 },
538 ),
539 },
540 BlockItem {
541 name: "txbtie",
542 description: Some(
543 "FDCAN Tx buffer transmission interrupt enable register",
544 ),
545 array: None,
546 byte_offset: 0xdc,
547 inner: BlockItemInner::Register(
548 Register {
549 access: Access::ReadWrite,
550 bit_size: 32,
551 fieldset: Some(
552 "Txbtie",
553 ),
554 },
555 ),
556 },
557 BlockItem {
558 name: "txbcie",
559 description: Some(
560 "FDCAN Tx buffer cancellation finished interrupt enable register",
561 ),
562 array: None,
563 byte_offset: 0xe0,
564 inner: BlockItemInner::Register(
565 Register {
566 access: Access::ReadWrite,
567 bit_size: 32,
568 fieldset: Some(
569 "Txbcie",
570 ),
571 },
572 ),
573 },
574 BlockItem {
575 name: "txefs",
576 description: Some(
577 "FDCAN Tx event FIFO status register",
578 ),
579 array: None,
580 byte_offset: 0xe4,
581 inner: BlockItemInner::Register(
582 Register {
583 access: Access::ReadWrite,
584 bit_size: 32,
585 fieldset: Some(
586 "Txefs",
587 ),
588 },
589 ),
590 },
591 BlockItem {
592 name: "txefa",
593 description: Some(
594 "FDCAN Tx event FIFO acknowledge register",
595 ),
596 array: None,
597 byte_offset: 0xe8,
598 inner: BlockItemInner::Register(
599 Register {
600 access: Access::ReadWrite,
601 bit_size: 32,
602 fieldset: Some(
603 "Txefa",
604 ),
605 },
606 ),
607 },
608 BlockItem {
609 name: "ckdiv",
610 description: Some(
611 "FDCAN CFG clock divider register",
612 ),
613 array: None,
614 byte_offset: 0x100,
615 inner: BlockItemInner::Register(
616 Register {
617 access: Access::ReadWrite,
618 bit_size: 32,
619 fieldset: Some(
620 "Ckdiv",
621 ),
622 },
623 ),
624 },
625 ],
626 },
627 ],
628 fieldsets: &[
629 FieldSet {
630 name: "Cccr",
631 extends: None,
632 description: Some(
633 "FDCAN CC control register",
634 ),
635 bit_size: 32,
636 fields: &[
637 Field {
638 name: "init",
639 description: Some(
640 "Initialization",
641 ),
642 bit_offset: BitOffset::Regular(
643 RegularBitOffset {
644 offset: 0,
645 },
646 ),
647 bit_size: 1,
648 array: None,
649 enumm: None,
650 },
651 Field {
652 name: "cce",
653 description: Some(
654 "Configuration change enable",
655 ),
656 bit_offset: BitOffset::Regular(
657 RegularBitOffset {
658 offset: 1,
659 },
660 ),
661 bit_size: 1,
662 array: None,
663 enumm: None,
664 },
665 Field {
666 name: "asm",
667 description: Some(
668 "ASM restricted operation mode. The restricted operation mode is intended for applications that adapt themselves to different CAN bit rates. The application tests different bit rates and leaves the Restricted operation Mode after it has received a valid frame. In the optional Restricted operation Mode the node is able to transmit and receive data and remote frames and it gives acknowledge to valid frames, but it does not send active error frames or overload frames. In case of an error condition or overload condition, it does not send dominant bits, instead it waits for the occurrence of bus idle condition to resynchronize itself to the CAN communication. The error counters are not incremented. Bit ASM can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the software at any time",
669 ),
670 bit_offset: BitOffset::Regular(
671 RegularBitOffset {
672 offset: 2,
673 },
674 ),
675 bit_size: 1,
676 array: None,
677 enumm: None,
678 },
679 Field {
680 name: "csa",
681 description: Some(
682 "Clock stop acknowledge",
683 ),
684 bit_offset: BitOffset::Regular(
685 RegularBitOffset {
686 offset: 3,
687 },
688 ),
689 bit_size: 1,
690 array: None,
691 enumm: None,
692 },
693 Field {
694 name: "csr",
695 description: Some(
696 "Clock stop request",
697 ),
698 bit_offset: BitOffset::Regular(
699 RegularBitOffset {
700 offset: 4,
701 },
702 ),
703 bit_size: 1,
704 array: None,
705 enumm: None,
706 },
707 Field {
708 name: "mon",
709 description: Some(
710 "Bus monitoring mode. Bit MON can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the Host at any time",
711 ),
712 bit_offset: BitOffset::Regular(
713 RegularBitOffset {
714 offset: 5,
715 },
716 ),
717 bit_size: 1,
718 array: None,
719 enumm: None,
720 },
721 Field {
722 name: "dar",
723 description: Some(
724 "Disable automatic retransmission",
725 ),
726 bit_offset: BitOffset::Regular(
727 RegularBitOffset {
728 offset: 6,
729 },
730 ),
731 bit_size: 1,
732 array: None,
733 enumm: None,
734 },
735 Field {
736 name: "test",
737 description: Some(
738 "Test mode enable",
739 ),
740 bit_offset: BitOffset::Regular(
741 RegularBitOffset {
742 offset: 7,
743 },
744 ),
745 bit_size: 1,
746 array: None,
747 enumm: None,
748 },
749 Field {
750 name: "fdoe",
751 description: Some(
752 "FD operation enable",
753 ),
754 bit_offset: BitOffset::Regular(
755 RegularBitOffset {
756 offset: 8,
757 },
758 ),
759 bit_size: 1,
760 array: None,
761 enumm: None,
762 },
763 Field {
764 name: "brse",
765 description: Some(
766 "FDCAN bit rate switching",
767 ),
768 bit_offset: BitOffset::Regular(
769 RegularBitOffset {
770 offset: 9,
771 },
772 ),
773 bit_size: 1,
774 array: None,
775 enumm: None,
776 },
777 Field {
778 name: "pxhd",
779 description: Some(
780 "Protocol exception handling disable",
781 ),
782 bit_offset: BitOffset::Regular(
783 RegularBitOffset {
784 offset: 12,
785 },
786 ),
787 bit_size: 1,
788 array: None,
789 enumm: None,
790 },
791 Field {
792 name: "efbi",
793 description: Some(
794 "Edge filtering during bus integration",
795 ),
796 bit_offset: BitOffset::Regular(
797 RegularBitOffset {
798 offset: 13,
799 },
800 ),
801 bit_size: 1,
802 array: None,
803 enumm: None,
804 },
805 Field {
806 name: "txp",
807 description: Some(
808 "If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame",
809 ),
810 bit_offset: BitOffset::Regular(
811 RegularBitOffset {
812 offset: 14,
813 },
814 ),
815 bit_size: 1,
816 array: None,
817 enumm: None,
818 },
819 Field {
820 name: "niso",
821 description: Some(
822 "Non ISO operation. If this bit is set, the FDCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0",
823 ),
824 bit_offset: BitOffset::Regular(
825 RegularBitOffset {
826 offset: 15,
827 },
828 ),
829 bit_size: 1,
830 array: None,
831 enumm: None,
832 },
833 ],
834 },
835 FieldSet {
836 name: "Ckdiv",
837 extends: None,
838 description: Some(
839 "FDCAN CFG clock divider register",
840 ),
841 bit_size: 32,
842 fields: &[
843 Field {
844 name: "pdiv",
845 description: Some(
846 "input clock divider. The APB clock could be divided prior to be used by the CAN sub system. The rate must be computed using the divider output clock. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1",
847 ),
848 bit_offset: BitOffset::Regular(
849 RegularBitOffset {
850 offset: 0,
851 },
852 ),
853 bit_size: 4,
854 array: None,
855 enumm: Some(
856 "Pdiv",
857 ),
858 },
859 ],
860 },
861 FieldSet {
862 name: "Crel",
863 extends: None,
864 description: Some(
865 "FDCAN core release register",
866 ),
867 bit_size: 32,
868 fields: &[
869 Field {
870 name: "day",
871 description: Some(
872 "DAY",
873 ),
874 bit_offset: BitOffset::Regular(
875 RegularBitOffset {
876 offset: 0,
877 },
878 ),
879 bit_size: 8,
880 array: None,
881 enumm: None,
882 },
883 Field {
884 name: "mon",
885 description: Some(
886 "MON",
887 ),
888 bit_offset: BitOffset::Regular(
889 RegularBitOffset {
890 offset: 8,
891 },
892 ),
893 bit_size: 8,
894 array: None,
895 enumm: None,
896 },
897 Field {
898 name: "year",
899 description: Some(
900 "YEAR",
901 ),
902 bit_offset: BitOffset::Regular(
903 RegularBitOffset {
904 offset: 16,
905 },
906 ),
907 bit_size: 4,
908 array: None,
909 enumm: None,
910 },
911 Field {
912 name: "substep",
913 description: Some(
914 "SUBSTEP",
915 ),
916 bit_offset: BitOffset::Regular(
917 RegularBitOffset {
918 offset: 20,
919 },
920 ),
921 bit_size: 4,
922 array: None,
923 enumm: None,
924 },
925 Field {
926 name: "step",
927 description: Some(
928 "STEP",
929 ),
930 bit_offset: BitOffset::Regular(
931 RegularBitOffset {
932 offset: 24,
933 },
934 ),
935 bit_size: 4,
936 array: None,
937 enumm: None,
938 },
939 Field {
940 name: "rel",
941 description: Some(
942 "REL",
943 ),
944 bit_offset: BitOffset::Regular(
945 RegularBitOffset {
946 offset: 28,
947 },
948 ),
949 bit_size: 4,
950 array: None,
951 enumm: None,
952 },
953 ],
954 },
955 FieldSet {
956 name: "Dbtp",
957 extends: None,
958 description: Some(
959 "FDCAN data bit timing and prescaler register",
960 ),
961 bit_size: 32,
962 fields: &[
963 Field {
964 name: "dsjw",
965 description: Some(
966 "Synchronization jump width. Must always be smaller than DTSEG2, valid values are 0 to 15. The value used by the hardware is the one programmed, incremented by 1: tSJW = (DSJW + 1) x tq.",
967 ),
968 bit_offset: BitOffset::Regular(
969 RegularBitOffset {
970 offset: 0,
971 },
972 ),
973 bit_size: 4,
974 array: None,
975 enumm: None,
976 },
977 Field {
978 name: "dtseg2",
979 description: Some(
980 "Data time segment after sample point. Valid values are 0 to 15. The value used by the hardware is the one programmed, incremented by 1, i.e. tBS2 = (DTSEG2 + 1) x tq",
981 ),
982 bit_offset: BitOffset::Regular(
983 RegularBitOffset {
984 offset: 4,
985 },
986 ),
987 bit_size: 4,
988 array: None,
989 enumm: None,
990 },
991 Field {
992 name: "dtseg1",
993 description: Some(
994 "Data time segment before sample point. Valid values are 0 to 31. The value used by the hardware is the one programmed, incremented by 1, i.e. tBS1 = (DTSEG1 + 1) x tq",
995 ),
996 bit_offset: BitOffset::Regular(
997 RegularBitOffset {
998 offset: 8,
999 },
1000 ),
1001 bit_size: 5,
1002 array: None,
1003 enumm: None,
1004 },
1005 Field {
1006 name: "dbrp",
1007 description: Some(
1008 "Data bit rate prescaler. The value by which the oscillator frequency is divided to generate the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31. The hardware interpreters this value as the value programmed plus 1",
1009 ),
1010 bit_offset: BitOffset::Regular(
1011 RegularBitOffset {
1012 offset: 16,
1013 },
1014 ),
1015 bit_size: 5,
1016 array: None,
1017 enumm: None,
1018 },
1019 Field {
1020 name: "tdc",
1021 description: Some(
1022 "Transceiver delay compensation",
1023 ),
1024 bit_offset: BitOffset::Regular(
1025 RegularBitOffset {
1026 offset: 23,
1027 },
1028 ),
1029 bit_size: 1,
1030 array: None,
1031 enumm: None,
1032 },
1033 ],
1034 },
1035 FieldSet {
1036 name: "Ecr",
1037 extends: None,
1038 description: Some(
1039 "FDCAN error counter register",
1040 ),
1041 bit_size: 32,
1042 fields: &[
1043 Field {
1044 name: "tec",
1045 description: Some(
1046 "Transmit error counter. Actual state of the transmit error counter, values between 0 and 255. When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented",
1047 ),
1048 bit_offset: BitOffset::Regular(
1049 RegularBitOffset {
1050 offset: 0,
1051 },
1052 ),
1053 bit_size: 8,
1054 array: None,
1055 enumm: None,
1056 },
1057 Field {
1058 name: "rec",
1059 description: Some(
1060 "Receive error counter. Actual state of the receive error counter, values between 0 and 127",
1061 ),
1062 bit_offset: BitOffset::Regular(
1063 RegularBitOffset {
1064 offset: 8,
1065 },
1066 ),
1067 bit_size: 7,
1068 array: None,
1069 enumm: None,
1070 },
1071 Field {
1072 name: "rp",
1073 description: Some(
1074 "Receive error passive",
1075 ),
1076 bit_offset: BitOffset::Regular(
1077 RegularBitOffset {
1078 offset: 15,
1079 },
1080 ),
1081 bit_size: 1,
1082 array: None,
1083 enumm: None,
1084 },
1085 Field {
1086 name: "cel",
1087 description: Some(
1088 "CAN error logging. The counter is incremented each time when a CAN protocol error causes the transmit error counter or the receive error counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR[ELO]. Access type is RX: reset on read.",
1089 ),
1090 bit_offset: BitOffset::Regular(
1091 RegularBitOffset {
1092 offset: 16,
1093 },
1094 ),
1095 bit_size: 8,
1096 array: None,
1097 enumm: None,
1098 },
1099 ],
1100 },
1101 FieldSet {
1102 name: "Endn",
1103 extends: None,
1104 description: Some(
1105 "FDCAN endian register",
1106 ),
1107 bit_size: 32,
1108 fields: &[
1109 Field {
1110 name: "etv",
1111 description: Some(
1112 "Endianness test value. The endianness test value is 0x8765 4321",
1113 ),
1114 bit_offset: BitOffset::Regular(
1115 RegularBitOffset {
1116 offset: 0,
1117 },
1118 ),
1119 bit_size: 32,
1120 array: None,
1121 enumm: None,
1122 },
1123 ],
1124 },
1125 FieldSet {
1126 name: "Hpms",
1127 extends: None,
1128 description: Some(
1129 "FDCAN high-priority message status register",
1130 ),
1131 bit_size: 32,
1132 fields: &[
1133 Field {
1134 name: "bidx",
1135 description: Some(
1136 "Buffer index. Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = 1",
1137 ),
1138 bit_offset: BitOffset::Regular(
1139 RegularBitOffset {
1140 offset: 0,
1141 },
1142 ),
1143 bit_size: 3,
1144 array: None,
1145 enumm: None,
1146 },
1147 Field {
1148 name: "msi",
1149 description: Some(
1150 "Message storage indicator",
1151 ),
1152 bit_offset: BitOffset::Regular(
1153 RegularBitOffset {
1154 offset: 6,
1155 },
1156 ),
1157 bit_size: 2,
1158 array: None,
1159 enumm: Some(
1160 "Msi",
1161 ),
1162 },
1163 Field {
1164 name: "fidx",
1165 description: Some(
1166 "Filter index. Index of matching filter element. Range is 0 to RXGFC[LSS] - 1 or RXGFC[LSE] - 1",
1167 ),
1168 bit_offset: BitOffset::Regular(
1169 RegularBitOffset {
1170 offset: 8,
1171 },
1172 ),
1173 bit_size: 5,
1174 array: None,
1175 enumm: None,
1176 },
1177 Field {
1178 name: "flst",
1179 description: Some(
1180 "Filter list. Indicates the filter list of the matching filter element",
1181 ),
1182 bit_offset: BitOffset::Regular(
1183 RegularBitOffset {
1184 offset: 15,
1185 },
1186 ),
1187 bit_size: 1,
1188 array: None,
1189 enumm: None,
1190 },
1191 ],
1192 },
1193 FieldSet {
1194 name: "Ie",
1195 extends: None,
1196 description: Some(
1197 "FDCAN interrupt enable register",
1198 ),
1199 bit_size: 32,
1200 fields: &[
1201 Field {
1202 name: "rfne",
1203 description: Some(
1204 "Rx FIFO X new message interrupt enable",
1205 ),
1206 bit_offset: BitOffset::Regular(
1207 RegularBitOffset {
1208 offset: 0,
1209 },
1210 ),
1211 bit_size: 1,
1212 array: Some(
1213 Array::Cursed(
1214 CursedArray {
1215 offsets: &[
1216 0,
1217 3,
1218 ],
1219 },
1220 ),
1221 ),
1222 enumm: None,
1223 },
1224 Field {
1225 name: "rffe",
1226 description: Some(
1227 "Rx FIFO X full interrupt enable",
1228 ),
1229 bit_offset: BitOffset::Regular(
1230 RegularBitOffset {
1231 offset: 1,
1232 },
1233 ),
1234 bit_size: 1,
1235 array: Some(
1236 Array::Cursed(
1237 CursedArray {
1238 offsets: &[
1239 0,
1240 3,
1241 ],
1242 },
1243 ),
1244 ),
1245 enumm: None,
1246 },
1247 Field {
1248 name: "rfle",
1249 description: Some(
1250 "Rx FIFO X message lost interrupt enable",
1251 ),
1252 bit_offset: BitOffset::Regular(
1253 RegularBitOffset {
1254 offset: 2,
1255 },
1256 ),
1257 bit_size: 1,
1258 array: Some(
1259 Array::Cursed(
1260 CursedArray {
1261 offsets: &[
1262 0,
1263 3,
1264 ],
1265 },
1266 ),
1267 ),
1268 enumm: None,
1269 },
1270 Field {
1271 name: "hpme",
1272 description: Some(
1273 "High-priority message interrupt enable",
1274 ),
1275 bit_offset: BitOffset::Regular(
1276 RegularBitOffset {
1277 offset: 6,
1278 },
1279 ),
1280 bit_size: 1,
1281 array: None,
1282 enumm: None,
1283 },
1284 Field {
1285 name: "tce",
1286 description: Some(
1287 "Transmission completed interrupt enable",
1288 ),
1289 bit_offset: BitOffset::Regular(
1290 RegularBitOffset {
1291 offset: 7,
1292 },
1293 ),
1294 bit_size: 1,
1295 array: None,
1296 enumm: None,
1297 },
1298 Field {
1299 name: "tcfe",
1300 description: Some(
1301 "Transmission cancellation finished interrupt enable",
1302 ),
1303 bit_offset: BitOffset::Regular(
1304 RegularBitOffset {
1305 offset: 8,
1306 },
1307 ),
1308 bit_size: 1,
1309 array: None,
1310 enumm: None,
1311 },
1312 Field {
1313 name: "tfee",
1314 description: Some(
1315 "Tx FIFO empty interrupt enable",
1316 ),
1317 bit_offset: BitOffset::Regular(
1318 RegularBitOffset {
1319 offset: 9,
1320 },
1321 ),
1322 bit_size: 1,
1323 array: None,
1324 enumm: None,
1325 },
1326 Field {
1327 name: "tefne",
1328 description: Some(
1329 "Tx event FIFO new entry interrupt enable",
1330 ),
1331 bit_offset: BitOffset::Regular(
1332 RegularBitOffset {
1333 offset: 10,
1334 },
1335 ),
1336 bit_size: 1,
1337 array: None,
1338 enumm: None,
1339 },
1340 Field {
1341 name: "teffe",
1342 description: Some(
1343 "Tx event FIFO full interrupt enable",
1344 ),
1345 bit_offset: BitOffset::Regular(
1346 RegularBitOffset {
1347 offset: 11,
1348 },
1349 ),
1350 bit_size: 1,
1351 array: None,
1352 enumm: None,
1353 },
1354 Field {
1355 name: "tefle",
1356 description: Some(
1357 "Tx event FIFO element lost interrupt enable",
1358 ),
1359 bit_offset: BitOffset::Regular(
1360 RegularBitOffset {
1361 offset: 12,
1362 },
1363 ),
1364 bit_size: 1,
1365 array: None,
1366 enumm: None,
1367 },
1368 Field {
1369 name: "tswe",
1370 description: Some(
1371 "Timestamp wraparound interrupt enable",
1372 ),
1373 bit_offset: BitOffset::Regular(
1374 RegularBitOffset {
1375 offset: 13,
1376 },
1377 ),
1378 bit_size: 1,
1379 array: None,
1380 enumm: None,
1381 },
1382 Field {
1383 name: "mrafe",
1384 description: Some(
1385 "Message RAM access failure interrupt enable",
1386 ),
1387 bit_offset: BitOffset::Regular(
1388 RegularBitOffset {
1389 offset: 14,
1390 },
1391 ),
1392 bit_size: 1,
1393 array: None,
1394 enumm: None,
1395 },
1396 Field {
1397 name: "tooe",
1398 description: Some(
1399 "Timeout occurred interrupt enable",
1400 ),
1401 bit_offset: BitOffset::Regular(
1402 RegularBitOffset {
1403 offset: 15,
1404 },
1405 ),
1406 bit_size: 1,
1407 array: None,
1408 enumm: None,
1409 },
1410 Field {
1411 name: "eloe",
1412 description: Some(
1413 "Error logging overflow interrupt enable",
1414 ),
1415 bit_offset: BitOffset::Regular(
1416 RegularBitOffset {
1417 offset: 16,
1418 },
1419 ),
1420 bit_size: 1,
1421 array: None,
1422 enumm: None,
1423 },
1424 Field {
1425 name: "epe",
1426 description: Some(
1427 "Error passive interrupt enable",
1428 ),
1429 bit_offset: BitOffset::Regular(
1430 RegularBitOffset {
1431 offset: 17,
1432 },
1433 ),
1434 bit_size: 1,
1435 array: None,
1436 enumm: None,
1437 },
1438 Field {
1439 name: "ewe",
1440 description: Some(
1441 "Warning status interrupt enable",
1442 ),
1443 bit_offset: BitOffset::Regular(
1444 RegularBitOffset {
1445 offset: 18,
1446 },
1447 ),
1448 bit_size: 1,
1449 array: None,
1450 enumm: None,
1451 },
1452 Field {
1453 name: "boe",
1454 description: Some(
1455 "Bus_Off status enable",
1456 ),
1457 bit_offset: BitOffset::Regular(
1458 RegularBitOffset {
1459 offset: 19,
1460 },
1461 ),
1462 bit_size: 1,
1463 array: None,
1464 enumm: None,
1465 },
1466 Field {
1467 name: "wdie",
1468 description: Some(
1469 "Watchdog interrupt enable",
1470 ),
1471 bit_offset: BitOffset::Regular(
1472 RegularBitOffset {
1473 offset: 20,
1474 },
1475 ),
1476 bit_size: 1,
1477 array: None,
1478 enumm: None,
1479 },
1480 Field {
1481 name: "peae",
1482 description: Some(
1483 "Protocol error in arbitration phase enable",
1484 ),
1485 bit_offset: BitOffset::Regular(
1486 RegularBitOffset {
1487 offset: 21,
1488 },
1489 ),
1490 bit_size: 1,
1491 array: None,
1492 enumm: None,
1493 },
1494 Field {
1495 name: "pede",
1496 description: Some(
1497 "Protocol error in data phase enable",
1498 ),
1499 bit_offset: BitOffset::Regular(
1500 RegularBitOffset {
1501 offset: 22,
1502 },
1503 ),
1504 bit_size: 1,
1505 array: None,
1506 enumm: None,
1507 },
1508 Field {
1509 name: "arae",
1510 description: Some(
1511 "Access to reserved address enable",
1512 ),
1513 bit_offset: BitOffset::Regular(
1514 RegularBitOffset {
1515 offset: 23,
1516 },
1517 ),
1518 bit_size: 1,
1519 array: None,
1520 enumm: None,
1521 },
1522 ],
1523 },
1524 FieldSet {
1525 name: "Ile",
1526 extends: None,
1527 description: Some(
1528 "FDCAN interrupt line enable register",
1529 ),
1530 bit_size: 32,
1531 fields: &[
1532 Field {
1533 name: "eint0",
1534 description: Some(
1535 "Enable interrupt line 0",
1536 ),
1537 bit_offset: BitOffset::Regular(
1538 RegularBitOffset {
1539 offset: 0,
1540 },
1541 ),
1542 bit_size: 1,
1543 array: None,
1544 enumm: None,
1545 },
1546 Field {
1547 name: "eint1",
1548 description: Some(
1549 "Enable interrupt line 1",
1550 ),
1551 bit_offset: BitOffset::Regular(
1552 RegularBitOffset {
1553 offset: 1,
1554 },
1555 ),
1556 bit_size: 1,
1557 array: None,
1558 enumm: None,
1559 },
1560 ],
1561 },
1562 FieldSet {
1563 name: "Ils",
1564 extends: None,
1565 description: Some(
1566 "FDCAN interrupt line select register",
1567 ),
1568 bit_size: 32,
1569 fields: &[
1570 Field {
1571 name: "rxfifo",
1572 description: Some(
1573 "RX FIFO bit grouping the following interruption. RFLL: Rx FIFO X message lost interrupt line RFFL: Rx FIFO X full interrupt line RFNL: Rx FIFO X new message interrupt line.",
1574 ),
1575 bit_offset: BitOffset::Regular(
1576 RegularBitOffset {
1577 offset: 0,
1578 },
1579 ),
1580 bit_size: 1,
1581 array: Some(
1582 Array::Regular(
1583 RegularArray {
1584 len: 2,
1585 stride: 1,
1586 },
1587 ),
1588 ),
1589 enumm: None,
1590 },
1591 Field {
1592 name: "smsg",
1593 description: Some(
1594 "Status message bit grouping the following interruption. TCFL: Transmission cancellation finished interrupt line TCL: Transmission completed interrupt line HPML: High-priority message interrupt line.",
1595 ),
1596 bit_offset: BitOffset::Regular(
1597 RegularBitOffset {
1598 offset: 2,
1599 },
1600 ),
1601 bit_size: 1,
1602 array: None,
1603 enumm: None,
1604 },
1605 Field {
1606 name: "tferr",
1607 description: Some(
1608 "Tx FIFO ERROR grouping the following interruption. TEFLL: Tx event FIFO element lost interrupt line TEFFL: Tx event FIFO full interrupt line TEFNL: Tx event FIFO new entry interrupt line TFEL: Tx FIFO empty interrupt line.",
1609 ),
1610 bit_offset: BitOffset::Regular(
1611 RegularBitOffset {
1612 offset: 3,
1613 },
1614 ),
1615 bit_size: 1,
1616 array: None,
1617 enumm: None,
1618 },
1619 Field {
1620 name: "misc",
1621 description: Some(
1622 "Interrupt regrouping the following interruption. TOOL: Timeout occurred interrupt line MRAFL: Message RAM access failure interrupt line TSWL: Timestamp wraparound interrupt line.",
1623 ),
1624 bit_offset: BitOffset::Regular(
1625 RegularBitOffset {
1626 offset: 4,
1627 },
1628 ),
1629 bit_size: 1,
1630 array: None,
1631 enumm: None,
1632 },
1633 Field {
1634 name: "berr",
1635 description: Some(
1636 "Bit and line error grouping the following interruption. EPL Error passive interrupt line ELOL: Error logging overflow interrupt line.",
1637 ),
1638 bit_offset: BitOffset::Regular(
1639 RegularBitOffset {
1640 offset: 5,
1641 },
1642 ),
1643 bit_size: 1,
1644 array: None,
1645 enumm: None,
1646 },
1647 Field {
1648 name: "perr",
1649 description: Some(
1650 "Protocol error grouping the following interruption. ARAL: Access to reserved address line PEDL: Protocol error in data phase line PEAL: Protocol error in arbitration phase line WDIL: Watchdog interrupt line BOL: Bus_Off status EWL: Warning status interrupt line.",
1651 ),
1652 bit_offset: BitOffset::Regular(
1653 RegularBitOffset {
1654 offset: 6,
1655 },
1656 ),
1657 bit_size: 1,
1658 array: None,
1659 enumm: None,
1660 },
1661 ],
1662 },
1663 FieldSet {
1664 name: "Ir",
1665 extends: None,
1666 description: Some(
1667 "FDCAN interrupt register",
1668 ),
1669 bit_size: 32,
1670 fields: &[
1671 Field {
1672 name: "rfn",
1673 description: Some(
1674 "Rx FIFO X new message",
1675 ),
1676 bit_offset: BitOffset::Regular(
1677 RegularBitOffset {
1678 offset: 0,
1679 },
1680 ),
1681 bit_size: 1,
1682 array: Some(
1683 Array::Cursed(
1684 CursedArray {
1685 offsets: &[
1686 0,
1687 3,
1688 ],
1689 },
1690 ),
1691 ),
1692 enumm: None,
1693 },
1694 Field {
1695 name: "rff",
1696 description: Some(
1697 "Rx FIFO X full",
1698 ),
1699 bit_offset: BitOffset::Regular(
1700 RegularBitOffset {
1701 offset: 1,
1702 },
1703 ),
1704 bit_size: 1,
1705 array: Some(
1706 Array::Cursed(
1707 CursedArray {
1708 offsets: &[
1709 0,
1710 3,
1711 ],
1712 },
1713 ),
1714 ),
1715 enumm: None,
1716 },
1717 Field {
1718 name: "rfl",
1719 description: Some(
1720 "Rx FIFO X message lost",
1721 ),
1722 bit_offset: BitOffset::Regular(
1723 RegularBitOffset {
1724 offset: 2,
1725 },
1726 ),
1727 bit_size: 1,
1728 array: Some(
1729 Array::Cursed(
1730 CursedArray {
1731 offsets: &[
1732 0,
1733 3,
1734 ],
1735 },
1736 ),
1737 ),
1738 enumm: None,
1739 },
1740 Field {
1741 name: "hpm",
1742 description: Some(
1743 "High-priority message",
1744 ),
1745 bit_offset: BitOffset::Regular(
1746 RegularBitOffset {
1747 offset: 6,
1748 },
1749 ),
1750 bit_size: 1,
1751 array: None,
1752 enumm: None,
1753 },
1754 Field {
1755 name: "tc",
1756 description: Some(
1757 "Transmission completed",
1758 ),
1759 bit_offset: BitOffset::Regular(
1760 RegularBitOffset {
1761 offset: 7,
1762 },
1763 ),
1764 bit_size: 1,
1765 array: None,
1766 enumm: None,
1767 },
1768 Field {
1769 name: "tcf",
1770 description: Some(
1771 "Transmission cancellation finished",
1772 ),
1773 bit_offset: BitOffset::Regular(
1774 RegularBitOffset {
1775 offset: 8,
1776 },
1777 ),
1778 bit_size: 1,
1779 array: None,
1780 enumm: None,
1781 },
1782 Field {
1783 name: "tfe",
1784 description: Some(
1785 "Tx FIFO empty",
1786 ),
1787 bit_offset: BitOffset::Regular(
1788 RegularBitOffset {
1789 offset: 9,
1790 },
1791 ),
1792 bit_size: 1,
1793 array: None,
1794 enumm: None,
1795 },
1796 Field {
1797 name: "tefn",
1798 description: Some(
1799 "Tx event FIFO New Entry",
1800 ),
1801 bit_offset: BitOffset::Regular(
1802 RegularBitOffset {
1803 offset: 10,
1804 },
1805 ),
1806 bit_size: 1,
1807 array: None,
1808 enumm: None,
1809 },
1810 Field {
1811 name: "teff",
1812 description: Some(
1813 "Tx event FIFO full",
1814 ),
1815 bit_offset: BitOffset::Regular(
1816 RegularBitOffset {
1817 offset: 11,
1818 },
1819 ),
1820 bit_size: 1,
1821 array: None,
1822 enumm: None,
1823 },
1824 Field {
1825 name: "tefl",
1826 description: Some(
1827 "Tx event FIFO element lost",
1828 ),
1829 bit_offset: BitOffset::Regular(
1830 RegularBitOffset {
1831 offset: 12,
1832 },
1833 ),
1834 bit_size: 1,
1835 array: None,
1836 enumm: None,
1837 },
1838 Field {
1839 name: "tsw",
1840 description: Some(
1841 "Timestamp wraparound",
1842 ),
1843 bit_offset: BitOffset::Regular(
1844 RegularBitOffset {
1845 offset: 13,
1846 },
1847 ),
1848 bit_size: 1,
1849 array: None,
1850 enumm: None,
1851 },
1852 Field {
1853 name: "mraf",
1854 description: Some(
1855 "Message RAM access failure. The flag is set when the Rx handler: has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx handler starts processing of the following message. was unable to write a message to the message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated. The partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the FDCAN is switched into Restricted operation Mode (see mode). To leave Restricted operation Mode, the Host CPU has to reset CCCR.ASM.",
1856 ),
1857 bit_offset: BitOffset::Regular(
1858 RegularBitOffset {
1859 offset: 14,
1860 },
1861 ),
1862 bit_size: 1,
1863 array: None,
1864 enumm: None,
1865 },
1866 Field {
1867 name: "too",
1868 description: Some(
1869 "Timeout occurred",
1870 ),
1871 bit_offset: BitOffset::Regular(
1872 RegularBitOffset {
1873 offset: 15,
1874 },
1875 ),
1876 bit_size: 1,
1877 array: None,
1878 enumm: None,
1879 },
1880 Field {
1881 name: "elo",
1882 description: Some(
1883 "Error logging overflow",
1884 ),
1885 bit_offset: BitOffset::Regular(
1886 RegularBitOffset {
1887 offset: 16,
1888 },
1889 ),
1890 bit_size: 1,
1891 array: None,
1892 enumm: None,
1893 },
1894 Field {
1895 name: "ep",
1896 description: Some(
1897 "Error passive",
1898 ),
1899 bit_offset: BitOffset::Regular(
1900 RegularBitOffset {
1901 offset: 17,
1902 },
1903 ),
1904 bit_size: 1,
1905 array: None,
1906 enumm: None,
1907 },
1908 Field {
1909 name: "ew",
1910 description: Some(
1911 "Warning status",
1912 ),
1913 bit_offset: BitOffset::Regular(
1914 RegularBitOffset {
1915 offset: 18,
1916 },
1917 ),
1918 bit_size: 1,
1919 array: None,
1920 enumm: None,
1921 },
1922 Field {
1923 name: "bo",
1924 description: Some(
1925 "Bus_Off status",
1926 ),
1927 bit_offset: BitOffset::Regular(
1928 RegularBitOffset {
1929 offset: 19,
1930 },
1931 ),
1932 bit_size: 1,
1933 array: None,
1934 enumm: None,
1935 },
1936 Field {
1937 name: "wdi",
1938 description: Some(
1939 "Watchdog interrupt",
1940 ),
1941 bit_offset: BitOffset::Regular(
1942 RegularBitOffset {
1943 offset: 20,
1944 },
1945 ),
1946 bit_size: 1,
1947 array: None,
1948 enumm: None,
1949 },
1950 Field {
1951 name: "pea",
1952 description: Some(
1953 "Protocol error in arbitration phase (nominal bit time is used)",
1954 ),
1955 bit_offset: BitOffset::Regular(
1956 RegularBitOffset {
1957 offset: 21,
1958 },
1959 ),
1960 bit_size: 1,
1961 array: None,
1962 enumm: None,
1963 },
1964 Field {
1965 name: "ped",
1966 description: Some(
1967 "Protocol error in data phase (data bit time is used)",
1968 ),
1969 bit_offset: BitOffset::Regular(
1970 RegularBitOffset {
1971 offset: 22,
1972 },
1973 ),
1974 bit_size: 1,
1975 array: None,
1976 enumm: None,
1977 },
1978 Field {
1979 name: "ara",
1980 description: Some(
1981 "Access to reserved address",
1982 ),
1983 bit_offset: BitOffset::Regular(
1984 RegularBitOffset {
1985 offset: 23,
1986 },
1987 ),
1988 bit_size: 1,
1989 array: None,
1990 enumm: None,
1991 },
1992 ],
1993 },
1994 FieldSet {
1995 name: "Nbtp",
1996 extends: None,
1997 description: Some(
1998 "FDCAN nominal bit timing and prescaler register",
1999 ),
2000 bit_size: 32,
2001 fields: &[
2002 Field {
2003 name: "ntseg2",
2004 description: Some(
2005 "Nominal time segment after sample point. Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used",
2006 ),
2007 bit_offset: BitOffset::Regular(
2008 RegularBitOffset {
2009 offset: 0,
2010 },
2011 ),
2012 bit_size: 7,
2013 array: None,
2014 enumm: None,
2015 },
2016 Field {
2017 name: "ntseg1",
2018 description: Some(
2019 "Nominal time segment before sample point. Valid values are 0 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1",
2020 ),
2021 bit_offset: BitOffset::Regular(
2022 RegularBitOffset {
2023 offset: 8,
2024 },
2025 ),
2026 bit_size: 8,
2027 array: None,
2028 enumm: None,
2029 },
2030 Field {
2031 name: "nbrp",
2032 description: Some(
2033 "Bit rate prescaler. Value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1",
2034 ),
2035 bit_offset: BitOffset::Regular(
2036 RegularBitOffset {
2037 offset: 16,
2038 },
2039 ),
2040 bit_size: 9,
2041 array: None,
2042 enumm: None,
2043 },
2044 Field {
2045 name: "nsjw",
2046 description: Some(
2047 "Nominal (re)synchronization jump width. Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that the used value is the one programmed incremented by one. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1",
2048 ),
2049 bit_offset: BitOffset::Regular(
2050 RegularBitOffset {
2051 offset: 25,
2052 },
2053 ),
2054 bit_size: 7,
2055 array: None,
2056 enumm: None,
2057 },
2058 ],
2059 },
2060 FieldSet {
2061 name: "Psr",
2062 extends: None,
2063 description: Some(
2064 "FDCAN protocol status register",
2065 ),
2066 bit_size: 32,
2067 fields: &[
2068 Field {
2069 name: "lec",
2070 description: Some(
2071 "Last error code. The LEC indicates the type of the last error to occur on the CAN bus. This field is cleared to 0 when a message has been transferred (reception or transmission) without error. Access type is RS: set on read.",
2072 ),
2073 bit_offset: BitOffset::Regular(
2074 RegularBitOffset {
2075 offset: 0,
2076 },
2077 ),
2078 bit_size: 3,
2079 array: None,
2080 enumm: Some(
2081 "Lec",
2082 ),
2083 },
2084 Field {
2085 name: "act",
2086 description: Some(
2087 "Activity. Monitors the module’s CAN communication state",
2088 ),
2089 bit_offset: BitOffset::Regular(
2090 RegularBitOffset {
2091 offset: 3,
2092 },
2093 ),
2094 bit_size: 2,
2095 array: None,
2096 enumm: Some(
2097 "Act",
2098 ),
2099 },
2100 Field {
2101 name: "ep",
2102 description: Some(
2103 "Error passive",
2104 ),
2105 bit_offset: BitOffset::Regular(
2106 RegularBitOffset {
2107 offset: 5,
2108 },
2109 ),
2110 bit_size: 1,
2111 array: None,
2112 enumm: None,
2113 },
2114 Field {
2115 name: "ew",
2116 description: Some(
2117 "Warning Sstatus",
2118 ),
2119 bit_offset: BitOffset::Regular(
2120 RegularBitOffset {
2121 offset: 6,
2122 },
2123 ),
2124 bit_size: 1,
2125 array: None,
2126 enumm: None,
2127 },
2128 Field {
2129 name: "bo",
2130 description: Some(
2131 "Bus_Off status",
2132 ),
2133 bit_offset: BitOffset::Regular(
2134 RegularBitOffset {
2135 offset: 7,
2136 },
2137 ),
2138 bit_size: 1,
2139 array: None,
2140 enumm: None,
2141 },
2142 Field {
2143 name: "dlec",
2144 description: Some(
2145 "Data last error code. Type of last error that occurred in the data phase of a FDCAN format frame with its BRS flag set. Coding is the same as for LEC. This field is cleared to 0 when a FDCAN format frame with its BRS flag set has been transferred (reception or transmission) without error. Access type is RS: set on read.",
2146 ),
2147 bit_offset: BitOffset::Regular(
2148 RegularBitOffset {
2149 offset: 8,
2150 },
2151 ),
2152 bit_size: 3,
2153 array: None,
2154 enumm: None,
2155 },
2156 Field {
2157 name: "resi",
2158 description: Some(
2159 "ESI flag of last received FDCAN message. This bit is set together with REDL, independent of acceptance filtering. Access type is RX: reset on read.",
2160 ),
2161 bit_offset: BitOffset::Regular(
2162 RegularBitOffset {
2163 offset: 11,
2164 },
2165 ),
2166 bit_size: 1,
2167 array: None,
2168 enumm: None,
2169 },
2170 Field {
2171 name: "rbrs",
2172 description: Some(
2173 "BRS flag of last received FDCAN message. This bit is set together with REDL, independent of acceptance filtering. Access type is RX: reset on read.",
2174 ),
2175 bit_offset: BitOffset::Regular(
2176 RegularBitOffset {
2177 offset: 12,
2178 },
2179 ),
2180 bit_size: 1,
2181 array: None,
2182 enumm: None,
2183 },
2184 Field {
2185 name: "redl",
2186 description: Some(
2187 "Received FDCAN message. This bit is set independent of acceptance filtering. Access type is RX: reset on read.",
2188 ),
2189 bit_offset: BitOffset::Regular(
2190 RegularBitOffset {
2191 offset: 13,
2192 },
2193 ),
2194 bit_size: 1,
2195 array: None,
2196 enumm: None,
2197 },
2198 Field {
2199 name: "pxe",
2200 description: Some(
2201 "Protocol exception event",
2202 ),
2203 bit_offset: BitOffset::Regular(
2204 RegularBitOffset {
2205 offset: 14,
2206 },
2207 ),
2208 bit_size: 1,
2209 array: None,
2210 enumm: None,
2211 },
2212 Field {
2213 name: "tdcv",
2214 description: Some(
2215 "Transmitter delay compensation value. Position of the secondary sample point, defined by the sum of the measured delay from FDCAN_TX to FDCAN_RX and TDCR.TDCO. The SSP position is, in the data phase, the number of minimum time quanta (mtq) between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq",
2216 ),
2217 bit_offset: BitOffset::Regular(
2218 RegularBitOffset {
2219 offset: 16,
2220 },
2221 ),
2222 bit_size: 7,
2223 array: None,
2224 enumm: None,
2225 },
2226 ],
2227 },
2228 FieldSet {
2229 name: "Rwd",
2230 extends: None,
2231 description: Some(
2232 "FDCAN RAM watchdog register",
2233 ),
2234 bit_size: 32,
2235 fields: &[
2236 Field {
2237 name: "wdc",
2238 description: Some(
2239 "Watchdog configuration. Start value of the message RAM watchdog counter. With the reset value of 00, the counter is disabled. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of FDCAN_CCCR register are set to 1",
2240 ),
2241 bit_offset: BitOffset::Regular(
2242 RegularBitOffset {
2243 offset: 0,
2244 },
2245 ),
2246 bit_size: 8,
2247 array: None,
2248 enumm: None,
2249 },
2250 Field {
2251 name: "wdv",
2252 description: Some(
2253 "Watchdog value. Actual message RAM watchdog counter value",
2254 ),
2255 bit_offset: BitOffset::Regular(
2256 RegularBitOffset {
2257 offset: 8,
2258 },
2259 ),
2260 bit_size: 8,
2261 array: None,
2262 enumm: None,
2263 },
2264 ],
2265 },
2266 FieldSet {
2267 name: "Rxfa",
2268 extends: None,
2269 description: Some(
2270 "CAN Rx FIFO X acknowledge register",
2271 ),
2272 bit_size: 32,
2273 fields: &[
2274 Field {
2275 name: "fai",
2276 description: Some(
2277 "Rx FIFO X acknowledge index. After the Host has read a message or a sequence of messages from Rx FIFO X it has to write the buffer index of the last element read from Rx FIFO X to FAI. This sets the Rx FIFO X get index RXFS[FGI] to FAI + 1 and update the FIFO X fill level RXFS[FFL]",
2278 ),
2279 bit_offset: BitOffset::Regular(
2280 RegularBitOffset {
2281 offset: 0,
2282 },
2283 ),
2284 bit_size: 3,
2285 array: None,
2286 enumm: None,
2287 },
2288 ],
2289 },
2290 FieldSet {
2291 name: "Rxfs",
2292 extends: None,
2293 description: Some(
2294 "FDCAN Rx FIFO X status register",
2295 ),
2296 bit_size: 32,
2297 fields: &[
2298 Field {
2299 name: "ffl",
2300 description: Some(
2301 "Rx FIFO X fill level. Number of elements stored in Rx FIFO X, range 0 to 3",
2302 ),
2303 bit_offset: BitOffset::Regular(
2304 RegularBitOffset {
2305 offset: 0,
2306 },
2307 ),
2308 bit_size: 4,
2309 array: None,
2310 enumm: None,
2311 },
2312 Field {
2313 name: "fgi",
2314 description: Some(
2315 "Rx FIFO X get index. Rx FIFO X read index pointer, range 0 to 2",
2316 ),
2317 bit_offset: BitOffset::Regular(
2318 RegularBitOffset {
2319 offset: 8,
2320 },
2321 ),
2322 bit_size: 2,
2323 array: None,
2324 enumm: None,
2325 },
2326 Field {
2327 name: "fpi",
2328 description: Some(
2329 "Rx FIFO X put index. Rx FIFO X write index pointer, range 0 to 2",
2330 ),
2331 bit_offset: BitOffset::Regular(
2332 RegularBitOffset {
2333 offset: 16,
2334 },
2335 ),
2336 bit_size: 2,
2337 array: None,
2338 enumm: None,
2339 },
2340 Field {
2341 name: "ff",
2342 description: Some(
2343 "Rx FIFO X full",
2344 ),
2345 bit_offset: BitOffset::Regular(
2346 RegularBitOffset {
2347 offset: 24,
2348 },
2349 ),
2350 bit_size: 1,
2351 array: None,
2352 enumm: None,
2353 },
2354 Field {
2355 name: "rfl",
2356 description: Some(
2357 "Rx FIFO X message lost. This bit is a copy of interrupt flag IR[RFL]. When IR[RFL] is reset, this bit is also reset",
2358 ),
2359 bit_offset: BitOffset::Regular(
2360 RegularBitOffset {
2361 offset: 25,
2362 },
2363 ),
2364 bit_size: 1,
2365 array: None,
2366 enumm: None,
2367 },
2368 ],
2369 },
2370 FieldSet {
2371 name: "Rxgfc",
2372 extends: None,
2373 description: Some(
2374 "FDCAN global filter configuration register",
2375 ),
2376 bit_size: 32,
2377 fields: &[
2378 Field {
2379 name: "rrfe",
2380 description: Some(
2381 "Reject remote frames extended. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1",
2382 ),
2383 bit_offset: BitOffset::Regular(
2384 RegularBitOffset {
2385 offset: 0,
2386 },
2387 ),
2388 bit_size: 1,
2389 array: None,
2390 enumm: None,
2391 },
2392 Field {
2393 name: "rrfs",
2394 description: Some(
2395 "Reject remote frames standard. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1",
2396 ),
2397 bit_offset: BitOffset::Regular(
2398 RegularBitOffset {
2399 offset: 1,
2400 },
2401 ),
2402 bit_size: 1,
2403 array: None,
2404 enumm: None,
2405 },
2406 Field {
2407 name: "anfe",
2408 description: Some(
2409 "Accept non-matching frames extended. Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1",
2410 ),
2411 bit_offset: BitOffset::Regular(
2412 RegularBitOffset {
2413 offset: 2,
2414 },
2415 ),
2416 bit_size: 2,
2417 array: None,
2418 enumm: Some(
2419 "Anfe",
2420 ),
2421 },
2422 Field {
2423 name: "anfs",
2424 description: Some(
2425 "Accept Non-matching frames standard. Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1",
2426 ),
2427 bit_offset: BitOffset::Regular(
2428 RegularBitOffset {
2429 offset: 4,
2430 },
2431 ),
2432 bit_size: 2,
2433 array: None,
2434 enumm: Some(
2435 "Anfs",
2436 ),
2437 },
2438 Field {
2439 name: "f1om",
2440 description: Some(
2441 "FIFO 1 operation mode (overwrite or blocking). This is a protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1",
2442 ),
2443 bit_offset: BitOffset::Regular(
2444 RegularBitOffset {
2445 offset: 8,
2446 },
2447 ),
2448 bit_size: 1,
2449 array: None,
2450 enumm: None,
2451 },
2452 Field {
2453 name: "f0om",
2454 description: Some(
2455 "FIFO 0 operation mode (overwrite or blocking). This is protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1",
2456 ),
2457 bit_offset: BitOffset::Regular(
2458 RegularBitOffset {
2459 offset: 9,
2460 },
2461 ),
2462 bit_size: 1,
2463 array: None,
2464 enumm: None,
2465 },
2466 Field {
2467 name: "lss",
2468 description: Some(
2469 "List size standard. >28: Values greater than 28 are interpreted as 28. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.",
2470 ),
2471 bit_offset: BitOffset::Regular(
2472 RegularBitOffset {
2473 offset: 16,
2474 },
2475 ),
2476 bit_size: 5,
2477 array: None,
2478 enumm: None,
2479 },
2480 Field {
2481 name: "lse",
2482 description: Some(
2483 "List size extended. >8: Values greater than 8 are interpreted as 8. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.",
2484 ),
2485 bit_offset: BitOffset::Regular(
2486 RegularBitOffset {
2487 offset: 24,
2488 },
2489 ),
2490 bit_size: 4,
2491 array: None,
2492 enumm: None,
2493 },
2494 ],
2495 },
2496 FieldSet {
2497 name: "Tdcr",
2498 extends: None,
2499 description: Some(
2500 "FDCAN transmitter delay compensation register",
2501 ),
2502 bit_size: 32,
2503 fields: &[
2504 Field {
2505 name: "tdcf",
2506 description: Some(
2507 "Transmitter delay compensation filter window length. Defines the minimum value for the SSP position, dominant edges on FDCAN_RX that would result in an earlier SSP position are ignored for transmitter delay measurements. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1",
2508 ),
2509 bit_offset: BitOffset::Regular(
2510 RegularBitOffset {
2511 offset: 0,
2512 },
2513 ),
2514 bit_size: 7,
2515 array: None,
2516 enumm: None,
2517 },
2518 Field {
2519 name: "tdco",
2520 description: Some(
2521 "Transmitter delay compensation offset. Offset value defining the distance between the measured delay from FDCAN_TX to FDCAN_RX and the secondary sample point. Valid values are 0 to 127 mtq. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1",
2522 ),
2523 bit_offset: BitOffset::Regular(
2524 RegularBitOffset {
2525 offset: 8,
2526 },
2527 ),
2528 bit_size: 7,
2529 array: None,
2530 enumm: None,
2531 },
2532 ],
2533 },
2534 FieldSet {
2535 name: "Test",
2536 extends: None,
2537 description: Some(
2538 "FDCAN test register",
2539 ),
2540 bit_size: 32,
2541 fields: &[
2542 Field {
2543 name: "lbck",
2544 description: Some(
2545 "Loop back mode",
2546 ),
2547 bit_offset: BitOffset::Regular(
2548 RegularBitOffset {
2549 offset: 4,
2550 },
2551 ),
2552 bit_size: 1,
2553 array: None,
2554 enumm: None,
2555 },
2556 Field {
2557 name: "tx",
2558 description: Some(
2559 "Control of transmit pin",
2560 ),
2561 bit_offset: BitOffset::Regular(
2562 RegularBitOffset {
2563 offset: 5,
2564 },
2565 ),
2566 bit_size: 2,
2567 array: None,
2568 enumm: Some(
2569 "Tx",
2570 ),
2571 },
2572 Field {
2573 name: "rx",
2574 description: Some(
2575 "Receive pin. Monitors the actual value of pin FDCANx_RX",
2576 ),
2577 bit_offset: BitOffset::Regular(
2578 RegularBitOffset {
2579 offset: 7,
2580 },
2581 ),
2582 bit_size: 1,
2583 array: None,
2584 enumm: None,
2585 },
2586 ],
2587 },
2588 FieldSet {
2589 name: "Tocc",
2590 extends: None,
2591 description: Some(
2592 "FDCAN timeout counter configuration register",
2593 ),
2594 bit_size: 32,
2595 fields: &[
2596 Field {
2597 name: "etoc",
2598 description: Some(
2599 "Timeout counter enable. This is a protected write (P) bit, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1",
2600 ),
2601 bit_offset: BitOffset::Regular(
2602 RegularBitOffset {
2603 offset: 0,
2604 },
2605 ),
2606 bit_size: 1,
2607 array: None,
2608 enumm: None,
2609 },
2610 Field {
2611 name: "tos",
2612 description: Some(
2613 "Timeout select. When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC[TOP] and continues down-counting. When the timeout counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC[TOP]. Down-counting is started when the first FIFO element is stored. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1",
2614 ),
2615 bit_offset: BitOffset::Regular(
2616 RegularBitOffset {
2617 offset: 1,
2618 },
2619 ),
2620 bit_size: 2,
2621 array: None,
2622 enumm: Some(
2623 "Tos",
2624 ),
2625 },
2626 Field {
2627 name: "top",
2628 description: Some(
2629 "Timeout period. Start value of the timeout counter (down-counter). Configures the timeout period",
2630 ),
2631 bit_offset: BitOffset::Regular(
2632 RegularBitOffset {
2633 offset: 16,
2634 },
2635 ),
2636 bit_size: 16,
2637 array: None,
2638 enumm: None,
2639 },
2640 ],
2641 },
2642 FieldSet {
2643 name: "Tocv",
2644 extends: None,
2645 description: Some(
2646 "FDCAN timeout counter value register",
2647 ),
2648 bit_size: 32,
2649 fields: &[
2650 Field {
2651 name: "toc",
2652 description: Some(
2653 "Timeout counter. The timeout counter is decremented in multiples of CAN bit times [1 … 16] depending on the configuration of TSCC.TCP. When decremented to 0, interrupt flag IR.TOO is set and the timeout counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS",
2654 ),
2655 bit_offset: BitOffset::Regular(
2656 RegularBitOffset {
2657 offset: 0,
2658 },
2659 ),
2660 bit_size: 16,
2661 array: None,
2662 enumm: None,
2663 },
2664 ],
2665 },
2666 FieldSet {
2667 name: "Tscc",
2668 extends: None,
2669 description: Some(
2670 "FDCAN timestamp counter configuration register",
2671 ),
2672 bit_size: 32,
2673 fields: &[
2674 Field {
2675 name: "tss",
2676 description: Some(
2677 "Timestamp select. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1",
2678 ),
2679 bit_offset: BitOffset::Regular(
2680 RegularBitOffset {
2681 offset: 0,
2682 },
2683 ),
2684 bit_size: 2,
2685 array: None,
2686 enumm: Some(
2687 "Tss",
2688 ),
2689 },
2690 Field {
2691 name: "tcp",
2692 description: Some(
2693 "Timestamp counter prescaler. Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1 … 16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. In CAN FD mode the internal timestamp counter TCP does not provide a constant time base due to the different CAN bit times between arbitration phase and data phase. Thus CAN FD requires an external counter for timestamp generation (TSS = 10). These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1",
2694 ),
2695 bit_offset: BitOffset::Regular(
2696 RegularBitOffset {
2697 offset: 16,
2698 },
2699 ),
2700 bit_size: 4,
2701 array: None,
2702 enumm: None,
2703 },
2704 ],
2705 },
2706 FieldSet {
2707 name: "Tscv",
2708 extends: None,
2709 description: Some(
2710 "FDCAN timestamp counter value register",
2711 ),
2712 bit_size: 32,
2713 fields: &[
2714 Field {
2715 name: "tsc",
2716 description: Some(
2717 "Timestamp counter. The internal/external timestamp counter value is captured on start of frame (both Rx and Tx). When TSCC[TSS] = 01, the timestamp counter is incremented in multiples of CAN bit times [1 … 16] depending on the configuration of TSCC[TCP]. A wrap around sets interrupt flag IR[TSW]. Write access resets the counter to 0. When TSCC.TSS = 10, TSC reflects the external timestamp counter value. A write access has no impact",
2718 ),
2719 bit_offset: BitOffset::Regular(
2720 RegularBitOffset {
2721 offset: 0,
2722 },
2723 ),
2724 bit_size: 16,
2725 array: None,
2726 enumm: None,
2727 },
2728 ],
2729 },
2730 FieldSet {
2731 name: "Txbar",
2732 extends: None,
2733 description: Some(
2734 "FDCAN Tx buffer add request register",
2735 ),
2736 bit_size: 32,
2737 fields: &[
2738 Field {
2739 name: "ar",
2740 description: Some(
2741 "Add request. Each Tx buffer has its own add request bit. Writing a 1 sets the corresponding add request bit; writing a 0 has no impact. This enables the Host to set transmission requests for multiple Tx buffers with one write to TXBAR. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed",
2742 ),
2743 bit_offset: BitOffset::Regular(
2744 RegularBitOffset {
2745 offset: 0,
2746 },
2747 ),
2748 bit_size: 1,
2749 array: Some(
2750 Array::Regular(
2751 RegularArray {
2752 len: 3,
2753 stride: 1,
2754 },
2755 ),
2756 ),
2757 enumm: None,
2758 },
2759 ],
2760 },
2761 FieldSet {
2762 name: "Txbc",
2763 extends: None,
2764 description: Some(
2765 "FDCAN Tx buffer configuration register",
2766 ),
2767 bit_size: 32,
2768 fields: &[
2769 Field {
2770 name: "tfqm",
2771 description: Some(
2772 "Tx FIFO/queue mode. This is a protected write (P) bit, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1",
2773 ),
2774 bit_offset: BitOffset::Regular(
2775 RegularBitOffset {
2776 offset: 24,
2777 },
2778 ),
2779 bit_size: 1,
2780 array: None,
2781 enumm: Some(
2782 "Tfqm",
2783 ),
2784 },
2785 ],
2786 },
2787 FieldSet {
2788 name: "Txbcf",
2789 extends: None,
2790 description: Some(
2791 "FDCAN Tx buffer cancellation finished register",
2792 ),
2793 bit_size: 32,
2794 fields: &[
2795 Field {
2796 name: "cf",
2797 description: Some(
2798 "Cancellation finished. Each Tx buffer has its own CF bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR",
2799 ),
2800 bit_offset: BitOffset::Regular(
2801 RegularBitOffset {
2802 offset: 0,
2803 },
2804 ),
2805 bit_size: 1,
2806 array: Some(
2807 Array::Regular(
2808 RegularArray {
2809 len: 3,
2810 stride: 1,
2811 },
2812 ),
2813 ),
2814 enumm: None,
2815 },
2816 ],
2817 },
2818 FieldSet {
2819 name: "Txbcie",
2820 extends: None,
2821 description: Some(
2822 "FDCAN Tx buffer cancellation finished interrupt enable register",
2823 ),
2824 bit_size: 32,
2825 fields: &[
2826 Field {
2827 name: "cfie",
2828 description: Some(
2829 "Cancellation finished interrupt enable.. Each Tx buffer has its own CFIE bit",
2830 ),
2831 bit_offset: BitOffset::Regular(
2832 RegularBitOffset {
2833 offset: 0,
2834 },
2835 ),
2836 bit_size: 1,
2837 array: Some(
2838 Array::Regular(
2839 RegularArray {
2840 len: 3,
2841 stride: 1,
2842 },
2843 ),
2844 ),
2845 enumm: None,
2846 },
2847 ],
2848 },
2849 FieldSet {
2850 name: "Txbcr",
2851 extends: None,
2852 description: Some(
2853 "FDCAN Tx buffer cancellation request register",
2854 ),
2855 bit_size: 32,
2856 fields: &[
2857 Field {
2858 name: "cr",
2859 description: Some(
2860 "Cancellation request. Each Tx buffer has its own cancellation request bit. Writing a 1 sets the corresponding CR bit; writing a 0 has no impact. This enables the Host to set cancellation requests for multiple Tx buffers with one write to TXBCR. The bits remain set until the corresponding TXBRP bit is reset",
2861 ),
2862 bit_offset: BitOffset::Regular(
2863 RegularBitOffset {
2864 offset: 0,
2865 },
2866 ),
2867 bit_size: 1,
2868 array: Some(
2869 Array::Regular(
2870 RegularArray {
2871 len: 3,
2872 stride: 1,
2873 },
2874 ),
2875 ),
2876 enumm: None,
2877 },
2878 ],
2879 },
2880 FieldSet {
2881 name: "Txbrp",
2882 extends: None,
2883 description: Some(
2884 "FDCAN Tx buffer request pending register",
2885 ),
2886 bit_size: 32,
2887 fields: &[
2888 Field {
2889 name: "trp",
2890 description: Some(
2891 "Transmission request pending. Each Tx buffer has its own transmission request pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been canceled via register TXBCR. After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with the highest priority (Tx buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signaled via TXBCF after successful transmission together with the corresponding TXBTO bit when the transmission has not yet been started at the point of cancellation when the transmission has been aborted due to lost arbitration when an error occurred during frame transmission In DAR mode all transmissions are automatically canceled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions",
2892 ),
2893 bit_offset: BitOffset::Regular(
2894 RegularBitOffset {
2895 offset: 0,
2896 },
2897 ),
2898 bit_size: 1,
2899 array: Some(
2900 Array::Regular(
2901 RegularArray {
2902 len: 3,
2903 stride: 1,
2904 },
2905 ),
2906 ),
2907 enumm: None,
2908 },
2909 ],
2910 },
2911 FieldSet {
2912 name: "Txbtie",
2913 extends: None,
2914 description: Some(
2915 "FDCAN Tx buffer transmission interrupt enable register",
2916 ),
2917 bit_size: 32,
2918 fields: &[
2919 Field {
2920 name: "tie",
2921 description: Some(
2922 "Transmission interrupt enable. Each Tx buffer has its own TIE bit",
2923 ),
2924 bit_offset: BitOffset::Regular(
2925 RegularBitOffset {
2926 offset: 0,
2927 },
2928 ),
2929 bit_size: 1,
2930 array: Some(
2931 Array::Regular(
2932 RegularArray {
2933 len: 3,
2934 stride: 1,
2935 },
2936 ),
2937 ),
2938 enumm: None,
2939 },
2940 ],
2941 },
2942 FieldSet {
2943 name: "Txbto",
2944 extends: None,
2945 description: Some(
2946 "FDCAN Tx buffer transmission occurred register",
2947 ),
2948 bit_size: 32,
2949 fields: &[
2950 Field {
2951 name: "to",
2952 description: Some(
2953 "Transmission occurred.. Each Tx buffer has its own TO bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR",
2954 ),
2955 bit_offset: BitOffset::Regular(
2956 RegularBitOffset {
2957 offset: 0,
2958 },
2959 ),
2960 bit_size: 1,
2961 array: Some(
2962 Array::Regular(
2963 RegularArray {
2964 len: 3,
2965 stride: 1,
2966 },
2967 ),
2968 ),
2969 enumm: None,
2970 },
2971 ],
2972 },
2973 FieldSet {
2974 name: "Txefa",
2975 extends: None,
2976 description: Some(
2977 "FDCAN Tx event FIFO acknowledge register",
2978 ),
2979 bit_size: 32,
2980 fields: &[
2981 Field {
2982 name: "efai",
2983 description: Some(
2984 "Event FIFO acknowledge index. After the Host has read an element or a sequence of elements from the Tx event FIFO, it has to write the index of the last element read from Tx event FIFO to EFAI. This sets the Tx event FIFO get index TXEFS[EFGI] to EFAI + 1 and updates the FIFO 0 fill level TXEFS[EFFL]",
2985 ),
2986 bit_offset: BitOffset::Regular(
2987 RegularBitOffset {
2988 offset: 0,
2989 },
2990 ),
2991 bit_size: 2,
2992 array: None,
2993 enumm: None,
2994 },
2995 ],
2996 },
2997 FieldSet {
2998 name: "Txefs",
2999 extends: None,
3000 description: Some(
3001 "FDCAN Tx event FIFO status register",
3002 ),
3003 bit_size: 32,
3004 fields: &[
3005 Field {
3006 name: "effl",
3007 description: Some(
3008 "Event FIFO fill level. Number of elements stored in Tx event FIFO, range 0 to 3",
3009 ),
3010 bit_offset: BitOffset::Regular(
3011 RegularBitOffset {
3012 offset: 0,
3013 },
3014 ),
3015 bit_size: 3,
3016 array: None,
3017 enumm: None,
3018 },
3019 Field {
3020 name: "efgi",
3021 description: Some(
3022 "Event FIFO get index. Tx event FIFO read index pointer, range 0 to 3",
3023 ),
3024 bit_offset: BitOffset::Regular(
3025 RegularBitOffset {
3026 offset: 8,
3027 },
3028 ),
3029 bit_size: 2,
3030 array: None,
3031 enumm: None,
3032 },
3033 Field {
3034 name: "efpi",
3035 description: Some(
3036 "Event FIFO put index. Tx event FIFO write index pointer, range 0 to 3",
3037 ),
3038 bit_offset: BitOffset::Regular(
3039 RegularBitOffset {
3040 offset: 16,
3041 },
3042 ),
3043 bit_size: 2,
3044 array: None,
3045 enumm: None,
3046 },
3047 Field {
3048 name: "eff",
3049 description: Some(
3050 "Event FIFO full",
3051 ),
3052 bit_offset: BitOffset::Regular(
3053 RegularBitOffset {
3054 offset: 24,
3055 },
3056 ),
3057 bit_size: 1,
3058 array: None,
3059 enumm: None,
3060 },
3061 Field {
3062 name: "tefl",
3063 description: Some(
3064 "Tx event FIFO element lost. This bit is a copy of interrupt flag IR[TEFL]. When IR[TEFL] is reset, this bit is also reset. 0 No Tx event FIFO element lost 1 Tx event FIFO element lost, also set after write attempt to Tx event FIFO of size 0",
3065 ),
3066 bit_offset: BitOffset::Regular(
3067 RegularBitOffset {
3068 offset: 25,
3069 },
3070 ),
3071 bit_size: 1,
3072 array: None,
3073 enumm: None,
3074 },
3075 ],
3076 },
3077 FieldSet {
3078 name: "Txfqs",
3079 extends: None,
3080 description: Some(
3081 "FDCAN Tx FIFO/queue status register",
3082 ),
3083 bit_size: 32,
3084 fields: &[
3085 Field {
3086 name: "tffl",
3087 description: Some(
3088 "Tx FIFO free level. Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 3. Read as 0 when Tx queue operation is configured (TXBC[TFQM] = 1)",
3089 ),
3090 bit_offset: BitOffset::Regular(
3091 RegularBitOffset {
3092 offset: 0,
3093 },
3094 ),
3095 bit_size: 3,
3096 array: None,
3097 enumm: None,
3098 },
3099 Field {
3100 name: "tfgi",
3101 description: Some(
3102 "Tx FIFO get index. Tx FIFO read index pointer, range 0 to 3. Read as 0 when Tx queue operation is configured (TXBC.TFQM = 1)",
3103 ),
3104 bit_offset: BitOffset::Regular(
3105 RegularBitOffset {
3106 offset: 8,
3107 },
3108 ),
3109 bit_size: 2,
3110 array: None,
3111 enumm: None,
3112 },
3113 Field {
3114 name: "tfqpi",
3115 description: Some(
3116 "Tx FIFO/queue put index. Tx FIFO/queue write index pointer, range 0 to 3",
3117 ),
3118 bit_offset: BitOffset::Regular(
3119 RegularBitOffset {
3120 offset: 16,
3121 },
3122 ),
3123 bit_size: 2,
3124 array: None,
3125 enumm: None,
3126 },
3127 Field {
3128 name: "tfqf",
3129 description: Some(
3130 "Tx FIFO/queue full",
3131 ),
3132 bit_offset: BitOffset::Regular(
3133 RegularBitOffset {
3134 offset: 21,
3135 },
3136 ),
3137 bit_size: 1,
3138 array: None,
3139 enumm: None,
3140 },
3141 ],
3142 },
3143 FieldSet {
3144 name: "Xidam",
3145 extends: None,
3146 description: Some(
3147 "FDCAN extended ID and mask register",
3148 ),
3149 bit_size: 32,
3150 fields: &[
3151 Field {
3152 name: "eidm",
3153 description: Some(
3154 "Extended ID mask. For acceptance filtering of extended frames the Extended ID AND Mask is AND-ed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to 1 the mask is not active. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1",
3155 ),
3156 bit_offset: BitOffset::Regular(
3157 RegularBitOffset {
3158 offset: 0,
3159 },
3160 ),
3161 bit_size: 29,
3162 array: None,
3163 enumm: None,
3164 },
3165 ],
3166 },
3167 ],
3168 enums: &[
3169 Enum {
3170 name: "Act",
3171 description: None,
3172 bit_size: 2,
3173 variants: &[
3174 EnumVariant {
3175 name: "SYNC",
3176 description: Some(
3177 "Synchronizing: node is synchronizing on CAN communication.",
3178 ),
3179 value: 0,
3180 },
3181 EnumVariant {
3182 name: "IDLE",
3183 description: Some(
3184 "Idle: node is neither receiver nor transmitter.",
3185 ),
3186 value: 1,
3187 },
3188 EnumVariant {
3189 name: "RX",
3190 description: Some(
3191 "Receiver: node is operating as receiver.",
3192 ),
3193 value: 2,
3194 },
3195 EnumVariant {
3196 name: "TX",
3197 description: Some(
3198 "Transmitter: node is operating as transmitter.",
3199 ),
3200 value: 3,
3201 },
3202 ],
3203 },
3204 Enum {
3205 name: "Anfe",
3206 description: None,
3207 bit_size: 2,
3208 variants: &[
3209 EnumVariant {
3210 name: "ACCEPT_FIFO_0",
3211 description: Some(
3212 "Accept in Rx FIFO 0",
3213 ),
3214 value: 0,
3215 },
3216 EnumVariant {
3217 name: "ACCEPT_FIFO_1",
3218 description: Some(
3219 "Accept in Rx FIFO 1",
3220 ),
3221 value: 1,
3222 },
3223 EnumVariant {
3224 name: "REJECT",
3225 description: Some(
3226 "Reject",
3227 ),
3228 value: 2,
3229 },
3230 ],
3231 },
3232 Enum {
3233 name: "Anfs",
3234 description: None,
3235 bit_size: 2,
3236 variants: &[
3237 EnumVariant {
3238 name: "ACCEPT_FIFO_0",
3239 description: Some(
3240 "Accept in Rx FIFO 0",
3241 ),
3242 value: 0,
3243 },
3244 EnumVariant {
3245 name: "ACCEPT_FIFO_1",
3246 description: Some(
3247 "Accept in Rx FIFO 1",
3248 ),
3249 value: 1,
3250 },
3251 EnumVariant {
3252 name: "REJECT",
3253 description: Some(
3254 "Reject",
3255 ),
3256 value: 2,
3257 },
3258 ],
3259 },
3260 Enum {
3261 name: "Lec",
3262 description: None,
3263 bit_size: 3,
3264 variants: &[
3265 EnumVariant {
3266 name: "NO_ERROR",
3267 description: Some(
3268 "No Error: No error occurred since LEC has been reset by successful reception or transmission.",
3269 ),
3270 value: 0,
3271 },
3272 EnumVariant {
3273 name: "STUFF",
3274 description: Some(
3275 "Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.",
3276 ),
3277 value: 1,
3278 },
3279 EnumVariant {
3280 name: "FORM",
3281 description: Some(
3282 "Form Error: A fixed format part of a received frame has the wrong format.",
3283 ),
3284 value: 2,
3285 },
3286 EnumVariant {
3287 name: "ACK",
3288 description: Some(
3289 "AckError: The message transmitted by the FDCAN was not acknowledged by another node.",
3290 ),
3291 value: 3,
3292 },
3293 EnumVariant {
3294 name: "BIT_1",
3295 description: Some(
3296 "Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant.",
3297 ),
3298 value: 4,
3299 },
3300 EnumVariant {
3301 name: "BIT_0",
3302 description: Some(
3303 "Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).",
3304 ),
3305 value: 5,
3306 },
3307 EnumVariant {
3308 name: "CRC",
3309 description: Some(
3310 "CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data.",
3311 ),
3312 value: 6,
3313 },
3314 EnumVariant {
3315 name: "NO_CHANGE",
3316 description: Some(
3317 "NoChange: Any read access to the Protocol status register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol status register.",
3318 ),
3319 value: 7,
3320 },
3321 ],
3322 },
3323 Enum {
3324 name: "Msi",
3325 description: None,
3326 bit_size: 2,
3327 variants: &[
3328 EnumVariant {
3329 name: "NO_FIFO",
3330 description: Some(
3331 "No FIFO selected",
3332 ),
3333 value: 0,
3334 },
3335 EnumVariant {
3336 name: "OVERRUN",
3337 description: Some(
3338 "FIFO overrun",
3339 ),
3340 value: 1,
3341 },
3342 EnumVariant {
3343 name: "FIFO_0",
3344 description: Some(
3345 "Message stored in FIFO 0",
3346 ),
3347 value: 2,
3348 },
3349 EnumVariant {
3350 name: "FIFO_1",
3351 description: Some(
3352 "Message stored in FIFO 1",
3353 ),
3354 value: 3,
3355 },
3356 ],
3357 },
3358 Enum {
3359 name: "Pdiv",
3360 description: None,
3361 bit_size: 4,
3362 variants: &[
3363 EnumVariant {
3364 name: "DIV_1",
3365 description: Some(
3366 "Divide by 1",
3367 ),
3368 value: 0,
3369 },
3370 EnumVariant {
3371 name: "DIV_2",
3372 description: Some(
3373 "Divide by 2",
3374 ),
3375 value: 1,
3376 },
3377 EnumVariant {
3378 name: "DIV_4",
3379 description: Some(
3380 "Divide by 4",
3381 ),
3382 value: 2,
3383 },
3384 EnumVariant {
3385 name: "DIV_6",
3386 description: Some(
3387 "Divide by 6",
3388 ),
3389 value: 3,
3390 },
3391 EnumVariant {
3392 name: "DIV_8",
3393 description: Some(
3394 "Divide by 8",
3395 ),
3396 value: 4,
3397 },
3398 EnumVariant {
3399 name: "DIV_10",
3400 description: Some(
3401 "Divide by 10",
3402 ),
3403 value: 5,
3404 },
3405 EnumVariant {
3406 name: "DIV_12",
3407 description: Some(
3408 "Divide by 12",
3409 ),
3410 value: 6,
3411 },
3412 EnumVariant {
3413 name: "DIV_14",
3414 description: Some(
3415 "Divide by 14",
3416 ),
3417 value: 7,
3418 },
3419 EnumVariant {
3420 name: "DIV_16",
3421 description: Some(
3422 "Divide by 16",
3423 ),
3424 value: 8,
3425 },
3426 EnumVariant {
3427 name: "DIV_18",
3428 description: Some(
3429 "Divide by 18",
3430 ),
3431 value: 9,
3432 },
3433 EnumVariant {
3434 name: "DIV_20",
3435 description: Some(
3436 "Divide by 20",
3437 ),
3438 value: 10,
3439 },
3440 EnumVariant {
3441 name: "DIV_22",
3442 description: Some(
3443 "Divide by 22",
3444 ),
3445 value: 11,
3446 },
3447 EnumVariant {
3448 name: "DIV_24",
3449 description: Some(
3450 "Divide by 24",
3451 ),
3452 value: 12,
3453 },
3454 EnumVariant {
3455 name: "DIV_26",
3456 description: Some(
3457 "Divide by 26",
3458 ),
3459 value: 13,
3460 },
3461 EnumVariant {
3462 name: "DIV_28",
3463 description: Some(
3464 "Divide by 28",
3465 ),
3466 value: 14,
3467 },
3468 EnumVariant {
3469 name: "DIV_30",
3470 description: Some(
3471 "Divide by 30",
3472 ),
3473 value: 15,
3474 },
3475 ],
3476 },
3477 Enum {
3478 name: "Tfqm",
3479 description: None,
3480 bit_size: 1,
3481 variants: &[
3482 EnumVariant {
3483 name: "FIFO",
3484 description: Some(
3485 "Tx FIFO operation",
3486 ),
3487 value: 0,
3488 },
3489 EnumVariant {
3490 name: "QUEUE",
3491 description: Some(
3492 "Tx queue operation",
3493 ),
3494 value: 1,
3495 },
3496 ],
3497 },
3498 Enum {
3499 name: "Tos",
3500 description: None,
3501 bit_size: 2,
3502 variants: &[
3503 EnumVariant {
3504 name: "CONTINUOUS",
3505 description: Some(
3506 "Continuous operation",
3507 ),
3508 value: 0,
3509 },
3510 EnumVariant {
3511 name: "TX_EVENT_FIFO",
3512 description: Some(
3513 "Timeout controlled by Tx event FIFO",
3514 ),
3515 value: 1,
3516 },
3517 EnumVariant {
3518 name: "RX_FIFO_0",
3519 description: Some(
3520 "Timeout controlled by Rx FIFO 0",
3521 ),
3522 value: 2,
3523 },
3524 EnumVariant {
3525 name: "RX_FIFO_1",
3526 description: Some(
3527 "Timeout controlled by Rx FIFO 1",
3528 ),
3529 value: 3,
3530 },
3531 ],
3532 },
3533 Enum {
3534 name: "Tss",
3535 description: None,
3536 bit_size: 2,
3537 variants: &[
3538 EnumVariant {
3539 name: "ZERO",
3540 description: Some(
3541 "Timestamp counter value always 0x0000",
3542 ),
3543 value: 0,
3544 },
3545 EnumVariant {
3546 name: "INCREMENT",
3547 description: Some(
3548 "Timestamp counter value incremented according to TCP",
3549 ),
3550 value: 1,
3551 },
3552 EnumVariant {
3553 name: "EXTERNAL",
3554 description: Some(
3555 "External timestamp counter from TIM3 value (tim3_cnt[0:15])",
3556 ),
3557 value: 2,
3558 },
3559 ],
3560 },
3561 Enum {
3562 name: "Tx",
3563 description: None,
3564 bit_size: 2,
3565 variants: &[
3566 EnumVariant {
3567 name: "RESET",
3568 description: Some(
3569 "Reset value, FDCANx_TX TX is controlled by the CAN core, updated at the end of the CAN bit time",
3570 ),
3571 value: 0,
3572 },
3573 EnumVariant {
3574 name: "SAMPLE_POINT",
3575 description: Some(
3576 "Sample point can be monitored at pin FDCANx_TX",
3577 ),
3578 value: 1,
3579 },
3580 EnumVariant {
3581 name: "DOMINANT",
3582 description: Some(
3583 "Dominant (0) level at pin FDCANx_TX",
3584 ),
3585 value: 2,
3586 },
3587 EnumVariant {
3588 name: "RECESSIVE",
3589 description: Some(
3590 "Recessive (1) at pin FDCANx_TX",
3591 ),
3592 value: 3,
3593 },
3594 ],
3595 },
3596 ],
3597};
3598