| 1 | |
| 2 | use crate::metadata::ir::*; |
| 3 | pub(crate) static REGISTERS: IR = IR { |
| 4 | blocks: &[Block { |
| 5 | name: "Crc" , |
| 6 | extends: None, |
| 7 | description: Some("Cyclic Redundancy Check calculation unit" ), |
| 8 | items: &[ |
| 9 | BlockItem { |
| 10 | name: "dr16" , |
| 11 | description: Some("Data register - half-word sized" ), |
| 12 | array: None, |
| 13 | byte_offset: 0x0, |
| 14 | inner: BlockItemInner::Register(Register { |
| 15 | access: Access::ReadWrite, |
| 16 | bit_size: 16, |
| 17 | fieldset: None, |
| 18 | }), |
| 19 | }, |
| 20 | BlockItem { |
| 21 | name: "dr32" , |
| 22 | description: Some("Data register" ), |
| 23 | array: None, |
| 24 | byte_offset: 0x0, |
| 25 | inner: BlockItemInner::Register(Register { |
| 26 | access: Access::ReadWrite, |
| 27 | bit_size: 32, |
| 28 | fieldset: None, |
| 29 | }), |
| 30 | }, |
| 31 | BlockItem { |
| 32 | name: "dr8" , |
| 33 | description: Some("Data register - byte sized" ), |
| 34 | array: None, |
| 35 | byte_offset: 0x0, |
| 36 | inner: BlockItemInner::Register(Register { |
| 37 | access: Access::ReadWrite, |
| 38 | bit_size: 8, |
| 39 | fieldset: None, |
| 40 | }), |
| 41 | }, |
| 42 | BlockItem { |
| 43 | name: "idr" , |
| 44 | description: Some("Independent Data register" ), |
| 45 | array: None, |
| 46 | byte_offset: 0x4, |
| 47 | inner: BlockItemInner::Register(Register { |
| 48 | access: Access::ReadWrite, |
| 49 | bit_size: 32, |
| 50 | fieldset: None, |
| 51 | }), |
| 52 | }, |
| 53 | BlockItem { |
| 54 | name: "cr" , |
| 55 | description: Some("Control register" ), |
| 56 | array: None, |
| 57 | byte_offset: 0x8, |
| 58 | inner: BlockItemInner::Register(Register { |
| 59 | access: Access::ReadWrite, |
| 60 | bit_size: 32, |
| 61 | fieldset: Some("Cr" ), |
| 62 | }), |
| 63 | }, |
| 64 | BlockItem { |
| 65 | name: "init" , |
| 66 | description: Some("Initial CRC value" ), |
| 67 | array: None, |
| 68 | byte_offset: 0x10, |
| 69 | inner: BlockItemInner::Register(Register { |
| 70 | access: Access::ReadWrite, |
| 71 | bit_size: 32, |
| 72 | fieldset: None, |
| 73 | }), |
| 74 | }, |
| 75 | BlockItem { |
| 76 | name: "pol" , |
| 77 | description: Some("CRC polynomial" ), |
| 78 | array: None, |
| 79 | byte_offset: 0x14, |
| 80 | inner: BlockItemInner::Register(Register { |
| 81 | access: Access::ReadWrite, |
| 82 | bit_size: 32, |
| 83 | fieldset: None, |
| 84 | }), |
| 85 | }, |
| 86 | ], |
| 87 | }], |
| 88 | fieldsets: &[FieldSet { |
| 89 | name: "Cr" , |
| 90 | extends: None, |
| 91 | description: Some("Control register" ), |
| 92 | bit_size: 32, |
| 93 | fields: &[ |
| 94 | Field { |
| 95 | name: "reset" , |
| 96 | description: Some("RESET bit" ), |
| 97 | bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }), |
| 98 | bit_size: 1, |
| 99 | array: None, |
| 100 | enumm: None, |
| 101 | }, |
| 102 | Field { |
| 103 | name: "polysize" , |
| 104 | description: Some("Polynomial size" ), |
| 105 | bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }), |
| 106 | bit_size: 2, |
| 107 | array: None, |
| 108 | enumm: Some("Polysize" ), |
| 109 | }, |
| 110 | Field { |
| 111 | name: "rev_in" , |
| 112 | description: Some("Reverse input data" ), |
| 113 | bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }), |
| 114 | bit_size: 2, |
| 115 | array: None, |
| 116 | enumm: Some("RevIn" ), |
| 117 | }, |
| 118 | Field { |
| 119 | name: "rev_out" , |
| 120 | description: Some("Reverse output data" ), |
| 121 | bit_offset: BitOffset::Regular(RegularBitOffset { offset: 7 }), |
| 122 | bit_size: 1, |
| 123 | array: None, |
| 124 | enumm: Some("RevOut" ), |
| 125 | }, |
| 126 | ], |
| 127 | }], |
| 128 | enums: &[ |
| 129 | Enum { |
| 130 | name: "Polysize" , |
| 131 | description: None, |
| 132 | bit_size: 2, |
| 133 | variants: &[ |
| 134 | EnumVariant { |
| 135 | name: "POLYSIZE32" , |
| 136 | description: Some("32-bit polynomial" ), |
| 137 | value: 0, |
| 138 | }, |
| 139 | EnumVariant { |
| 140 | name: "POLYSIZE16" , |
| 141 | description: Some("16-bit polynomial" ), |
| 142 | value: 1, |
| 143 | }, |
| 144 | EnumVariant { |
| 145 | name: "POLYSIZE8" , |
| 146 | description: Some("8-bit polynomial" ), |
| 147 | value: 2, |
| 148 | }, |
| 149 | EnumVariant { |
| 150 | name: "POLYSIZE7" , |
| 151 | description: Some("7-bit polynomial" ), |
| 152 | value: 3, |
| 153 | }, |
| 154 | ], |
| 155 | }, |
| 156 | Enum { |
| 157 | name: "RevIn" , |
| 158 | description: None, |
| 159 | bit_size: 2, |
| 160 | variants: &[ |
| 161 | EnumVariant { |
| 162 | name: "NORMAL" , |
| 163 | description: Some("Bit order not affected" ), |
| 164 | value: 0, |
| 165 | }, |
| 166 | EnumVariant { |
| 167 | name: "BYTE" , |
| 168 | description: Some("Bit reversal done by byte" ), |
| 169 | value: 1, |
| 170 | }, |
| 171 | EnumVariant { |
| 172 | name: "HALF_WORD" , |
| 173 | description: Some("Bit reversal done by half-word" ), |
| 174 | value: 2, |
| 175 | }, |
| 176 | EnumVariant { |
| 177 | name: "WORD" , |
| 178 | description: Some("Bit reversal done by word" ), |
| 179 | value: 3, |
| 180 | }, |
| 181 | ], |
| 182 | }, |
| 183 | Enum { |
| 184 | name: "RevOut" , |
| 185 | description: None, |
| 186 | bit_size: 1, |
| 187 | variants: &[ |
| 188 | EnumVariant { |
| 189 | name: "NORMAL" , |
| 190 | description: Some("Bit order not affected" ), |
| 191 | value: 0, |
| 192 | }, |
| 193 | EnumVariant { |
| 194 | name: "REVERSED" , |
| 195 | description: Some("Bit reversed output" ), |
| 196 | value: 1, |
| 197 | }, |
| 198 | ], |
| 199 | }, |
| 200 | ], |
| 201 | }; |
| 202 | |