1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[Block {
5 name: "Crs",
6 extends: None,
7 description: Some("Clock recovery system"),
8 items: &[
9 BlockItem {
10 name: "cr",
11 description: Some("control register"),
12 array: None,
13 byte_offset: 0x0,
14 inner: BlockItemInner::Register(Register {
15 access: Access::ReadWrite,
16 bit_size: 32,
17 fieldset: Some("Cr"),
18 }),
19 },
20 BlockItem {
21 name: "cfgr",
22 description: Some("configuration register"),
23 array: None,
24 byte_offset: 0x4,
25 inner: BlockItemInner::Register(Register {
26 access: Access::ReadWrite,
27 bit_size: 32,
28 fieldset: Some("Cfgr"),
29 }),
30 },
31 BlockItem {
32 name: "isr",
33 description: Some("interrupt and status register"),
34 array: None,
35 byte_offset: 0x8,
36 inner: BlockItemInner::Register(Register {
37 access: Access::Read,
38 bit_size: 32,
39 fieldset: Some("Isr"),
40 }),
41 },
42 BlockItem {
43 name: "icr",
44 description: Some("interrupt flag clear register"),
45 array: None,
46 byte_offset: 0xc,
47 inner: BlockItemInner::Register(Register {
48 access: Access::ReadWrite,
49 bit_size: 32,
50 fieldset: Some("Icr"),
51 }),
52 },
53 ],
54 }],
55 fieldsets: &[
56 FieldSet {
57 name: "Cfgr",
58 extends: None,
59 description: Some("configuration register"),
60 bit_size: 32,
61 fields: &[
62 Field {
63 name: "reload",
64 description: Some("Counter reload value"),
65 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
66 bit_size: 16,
67 array: None,
68 enumm: None,
69 },
70 Field {
71 name: "felim",
72 description: Some("Frequency error limit"),
73 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
74 bit_size: 8,
75 array: None,
76 enumm: None,
77 },
78 Field {
79 name: "syncdiv",
80 description: Some("SYNC divider"),
81 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
82 bit_size: 3,
83 array: None,
84 enumm: None,
85 },
86 Field {
87 name: "syncsrc",
88 description: Some("SYNC signal source selection"),
89 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 28 }),
90 bit_size: 2,
91 array: None,
92 enumm: Some("Syncsrc"),
93 },
94 Field {
95 name: "syncpol",
96 description: Some("SYNC polarity selection"),
97 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 31 }),
98 bit_size: 1,
99 array: None,
100 enumm: None,
101 },
102 ],
103 },
104 FieldSet {
105 name: "Cr",
106 extends: None,
107 description: Some("control register"),
108 bit_size: 32,
109 fields: &[
110 Field {
111 name: "syncokie",
112 description: Some("SYNC event OK interrupt enable"),
113 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
114 bit_size: 1,
115 array: None,
116 enumm: None,
117 },
118 Field {
119 name: "syncwarnie",
120 description: Some("SYNC warning interrupt enable"),
121 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
122 bit_size: 1,
123 array: None,
124 enumm: None,
125 },
126 Field {
127 name: "errie",
128 description: Some("Synchronization or trimming error interrupt enable"),
129 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
130 bit_size: 1,
131 array: None,
132 enumm: None,
133 },
134 Field {
135 name: "esyncie",
136 description: Some("Expected SYNC interrupt enable"),
137 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
138 bit_size: 1,
139 array: None,
140 enumm: None,
141 },
142 Field {
143 name: "cen",
144 description: Some("Frequency error counter enable"),
145 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
146 bit_size: 1,
147 array: None,
148 enumm: None,
149 },
150 Field {
151 name: "autotrimen",
152 description: Some("Automatic trimming enable"),
153 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 6 }),
154 bit_size: 1,
155 array: None,
156 enumm: None,
157 },
158 Field {
159 name: "swsync",
160 description: Some("Generate software SYNC event"),
161 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 7 }),
162 bit_size: 1,
163 array: None,
164 enumm: None,
165 },
166 Field {
167 name: "trim",
168 description: Some("HSI48 oscillator smooth trimming"),
169 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
170 bit_size: 6,
171 array: None,
172 enumm: None,
173 },
174 ],
175 },
176 FieldSet {
177 name: "Icr",
178 extends: None,
179 description: Some("interrupt flag clear register"),
180 bit_size: 32,
181 fields: &[
182 Field {
183 name: "syncokc",
184 description: Some("SYNC event OK clear flag"),
185 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
186 bit_size: 1,
187 array: None,
188 enumm: None,
189 },
190 Field {
191 name: "syncwarnc",
192 description: Some("SYNC warning clear flag"),
193 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
194 bit_size: 1,
195 array: None,
196 enumm: None,
197 },
198 Field {
199 name: "errc",
200 description: Some("Error clear flag"),
201 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
202 bit_size: 1,
203 array: None,
204 enumm: None,
205 },
206 Field {
207 name: "esyncc",
208 description: Some("Expected SYNC clear flag"),
209 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
210 bit_size: 1,
211 array: None,
212 enumm: None,
213 },
214 ],
215 },
216 FieldSet {
217 name: "Isr",
218 extends: None,
219 description: Some("interrupt and status register"),
220 bit_size: 32,
221 fields: &[
222 Field {
223 name: "syncokf",
224 description: Some("SYNC event OK flag"),
225 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
226 bit_size: 1,
227 array: None,
228 enumm: None,
229 },
230 Field {
231 name: "syncwarnf",
232 description: Some("SYNC warning flag"),
233 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
234 bit_size: 1,
235 array: None,
236 enumm: None,
237 },
238 Field {
239 name: "errf",
240 description: Some("Error flag"),
241 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
242 bit_size: 1,
243 array: None,
244 enumm: None,
245 },
246 Field {
247 name: "esyncf",
248 description: Some("Expected SYNC flag"),
249 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
250 bit_size: 1,
251 array: None,
252 enumm: None,
253 },
254 Field {
255 name: "syncerr",
256 description: Some("SYNC error"),
257 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
258 bit_size: 1,
259 array: None,
260 enumm: None,
261 },
262 Field {
263 name: "syncmiss",
264 description: Some("SYNC missed"),
265 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
266 bit_size: 1,
267 array: None,
268 enumm: None,
269 },
270 Field {
271 name: "trimovf",
272 description: Some("Trimming overflow or underflow"),
273 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 10 }),
274 bit_size: 1,
275 array: None,
276 enumm: None,
277 },
278 Field {
279 name: "fedir",
280 description: Some("Frequency error direction"),
281 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 15 }),
282 bit_size: 1,
283 array: None,
284 enumm: None,
285 },
286 Field {
287 name: "fecap",
288 description: Some("Frequency error capture"),
289 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
290 bit_size: 16,
291 array: None,
292 enumm: None,
293 },
294 ],
295 },
296 ],
297 enums: &[Enum {
298 name: "Syncsrc",
299 description: None,
300 bit_size: 2,
301 variants: &[
302 EnumVariant {
303 name: "GPIO",
304 description: Some("GPIO selected as SYNC signal source"),
305 value: 0,
306 },
307 EnumVariant {
308 name: "LSE",
309 description: Some("LSE selected as SYNC signal source"),
310 value: 1,
311 },
312 EnumVariant {
313 name: "USB",
314 description: Some("USB SOF selected as SYNC signal source"),
315 value: 2,
316 },
317 ],
318 }],
319};
320