1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[Block {
5 name: "Dac",
6 extends: None,
7 description: Some("Digital-to-analog converter"),
8 items: &[
9 BlockItem {
10 name: "cr",
11 description: Some("control register"),
12 array: None,
13 byte_offset: 0x0,
14 inner: BlockItemInner::Register(Register {
15 access: Access::ReadWrite,
16 bit_size: 32,
17 fieldset: Some("Cr"),
18 }),
19 },
20 BlockItem {
21 name: "swtrigr",
22 description: Some("software trigger register"),
23 array: None,
24 byte_offset: 0x4,
25 inner: BlockItemInner::Register(Register {
26 access: Access::Write,
27 bit_size: 32,
28 fieldset: Some("Swtrigr"),
29 }),
30 },
31 BlockItem {
32 name: "dhr12r",
33 description: Some("channel 12-bit right-aligned data holding register"),
34 array: Some(Array::Regular(RegularArray { len: 2, stride: 12 })),
35 byte_offset: 0x8,
36 inner: BlockItemInner::Register(Register {
37 access: Access::ReadWrite,
38 bit_size: 32,
39 fieldset: Some("Dhr12r"),
40 }),
41 },
42 BlockItem {
43 name: "dhr12l",
44 description: Some("channel 12-bit left-aligned data holding register"),
45 array: Some(Array::Regular(RegularArray { len: 2, stride: 12 })),
46 byte_offset: 0xc,
47 inner: BlockItemInner::Register(Register {
48 access: Access::ReadWrite,
49 bit_size: 32,
50 fieldset: Some("Dhr12l"),
51 }),
52 },
53 BlockItem {
54 name: "dhr8r",
55 description: Some("channel 8-bit right-aligned data holding register"),
56 array: Some(Array::Regular(RegularArray { len: 2, stride: 12 })),
57 byte_offset: 0x10,
58 inner: BlockItemInner::Register(Register {
59 access: Access::ReadWrite,
60 bit_size: 32,
61 fieldset: Some("Dhr8r"),
62 }),
63 },
64 BlockItem {
65 name: "dhr12rd",
66 description: Some("dual 12-bit right-aligned data holding register"),
67 array: None,
68 byte_offset: 0x20,
69 inner: BlockItemInner::Register(Register {
70 access: Access::ReadWrite,
71 bit_size: 32,
72 fieldset: Some("Dhr12rd"),
73 }),
74 },
75 BlockItem {
76 name: "dhr12ld",
77 description: Some("dual 12-bit left aligned data holding register"),
78 array: None,
79 byte_offset: 0x24,
80 inner: BlockItemInner::Register(Register {
81 access: Access::ReadWrite,
82 bit_size: 32,
83 fieldset: Some("Dhr12ld"),
84 }),
85 },
86 BlockItem {
87 name: "dhr8rd",
88 description: Some("dual 8-bit right aligned data holding register"),
89 array: None,
90 byte_offset: 0x28,
91 inner: BlockItemInner::Register(Register {
92 access: Access::ReadWrite,
93 bit_size: 32,
94 fieldset: Some("Dhr8rd"),
95 }),
96 },
97 BlockItem {
98 name: "dor",
99 description: Some("channel data output register"),
100 array: Some(Array::Regular(RegularArray { len: 2, stride: 4 })),
101 byte_offset: 0x2c,
102 inner: BlockItemInner::Register(Register {
103 access: Access::Read,
104 bit_size: 32,
105 fieldset: Some("Dor"),
106 }),
107 },
108 BlockItem {
109 name: "sr",
110 description: Some("status register"),
111 array: None,
112 byte_offset: 0x34,
113 inner: BlockItemInner::Register(Register {
114 access: Access::ReadWrite,
115 bit_size: 32,
116 fieldset: Some("Sr"),
117 }),
118 },
119 BlockItem {
120 name: "ccr",
121 description: Some("calibration control register"),
122 array: None,
123 byte_offset: 0x38,
124 inner: BlockItemInner::Register(Register {
125 access: Access::ReadWrite,
126 bit_size: 32,
127 fieldset: Some("Ccr"),
128 }),
129 },
130 BlockItem {
131 name: "mcr",
132 description: Some("mode control register"),
133 array: None,
134 byte_offset: 0x3c,
135 inner: BlockItemInner::Register(Register {
136 access: Access::ReadWrite,
137 bit_size: 32,
138 fieldset: Some("Mcr"),
139 }),
140 },
141 BlockItem {
142 name: "shsr",
143 description: Some("sample and hold sample time register"),
144 array: Some(Array::Regular(RegularArray { len: 2, stride: 4 })),
145 byte_offset: 0x40,
146 inner: BlockItemInner::Register(Register {
147 access: Access::ReadWrite,
148 bit_size: 32,
149 fieldset: Some("Shsr"),
150 }),
151 },
152 BlockItem {
153 name: "shhr",
154 description: Some("sample and hold hold time register"),
155 array: None,
156 byte_offset: 0x48,
157 inner: BlockItemInner::Register(Register {
158 access: Access::ReadWrite,
159 bit_size: 32,
160 fieldset: Some("Shhr"),
161 }),
162 },
163 BlockItem {
164 name: "shrr",
165 description: Some("sample and hold refresh time register"),
166 array: None,
167 byte_offset: 0x4c,
168 inner: BlockItemInner::Register(Register {
169 access: Access::ReadWrite,
170 bit_size: 32,
171 fieldset: Some("Shrr"),
172 }),
173 },
174 ],
175 }],
176 fieldsets: &[
177 FieldSet {
178 name: "Ccr",
179 extends: None,
180 description: Some("calibration control register"),
181 bit_size: 32,
182 fields: &[Field {
183 name: "otrim",
184 description: Some("channel offset trimming value"),
185 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
186 bit_size: 5,
187 array: Some(Array::Regular(RegularArray { len: 2, stride: 16 })),
188 enumm: None,
189 }],
190 },
191 FieldSet {
192 name: "Cr",
193 extends: None,
194 description: Some("control register"),
195 bit_size: 32,
196 fields: &[
197 Field {
198 name: "en",
199 description: Some("channel enable"),
200 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
201 bit_size: 1,
202 array: Some(Array::Regular(RegularArray { len: 2, stride: 16 })),
203 enumm: None,
204 },
205 Field {
206 name: "ten",
207 description: Some("channel trigger enable"),
208 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
209 bit_size: 1,
210 array: Some(Array::Regular(RegularArray { len: 2, stride: 16 })),
211 enumm: None,
212 },
213 Field {
214 name: "tsel",
215 description: Some("channel trigger selection"),
216 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
217 bit_size: 4,
218 array: Some(Array::Regular(RegularArray { len: 2, stride: 16 })),
219 enumm: None,
220 },
221 Field {
222 name: "wave",
223 description: Some("channel noise/triangle wave generation enable"),
224 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 6 }),
225 bit_size: 2,
226 array: Some(Array::Regular(RegularArray { len: 2, stride: 16 })),
227 enumm: Some("Wave"),
228 },
229 Field {
230 name: "mamp",
231 description: Some("channel mask/amplitude selector"),
232 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
233 bit_size: 4,
234 array: Some(Array::Regular(RegularArray { len: 2, stride: 16 })),
235 enumm: None,
236 },
237 Field {
238 name: "dmaen",
239 description: Some("channel DMA enable"),
240 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
241 bit_size: 1,
242 array: Some(Array::Regular(RegularArray { len: 2, stride: 16 })),
243 enumm: None,
244 },
245 Field {
246 name: "dmaudrie",
247 description: Some("channel DMA Underrun Interrupt enable"),
248 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 13 }),
249 bit_size: 1,
250 array: Some(Array::Regular(RegularArray { len: 2, stride: 16 })),
251 enumm: None,
252 },
253 Field {
254 name: "cen",
255 description: Some("DAC channel calibration enable"),
256 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }),
257 bit_size: 1,
258 array: Some(Array::Regular(RegularArray { len: 2, stride: 16 })),
259 enumm: None,
260 },
261 ],
262 },
263 FieldSet {
264 name: "Dhr12l",
265 extends: None,
266 description: Some("channel 12-bit left-aligned data holding register"),
267 bit_size: 32,
268 fields: &[
269 Field {
270 name: "dhr",
271 description: Some("channel 12-bit left-aligned data"),
272 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
273 bit_size: 12,
274 array: None,
275 enumm: None,
276 },
277 Field {
278 name: "dhrb",
279 description: Some("channel 12-bit left-aligned data B"),
280 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 20 }),
281 bit_size: 12,
282 array: None,
283 enumm: None,
284 },
285 ],
286 },
287 FieldSet {
288 name: "Dhr12ld",
289 extends: None,
290 description: Some("dual 12-bit left aligned data holding register"),
291 bit_size: 32,
292 fields: &[Field {
293 name: "dhr",
294 description: Some("channel 12-bit left-aligned data"),
295 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
296 bit_size: 12,
297 array: Some(Array::Regular(RegularArray { len: 2, stride: 16 })),
298 enumm: None,
299 }],
300 },
301 FieldSet {
302 name: "Dhr12r",
303 extends: None,
304 description: Some("channel 12-bit right-aligned data holding register"),
305 bit_size: 32,
306 fields: &[
307 Field {
308 name: "dhr",
309 description: Some("channel 12-bit right-aligned data"),
310 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
311 bit_size: 12,
312 array: None,
313 enumm: None,
314 },
315 Field {
316 name: "dhrb",
317 description: Some("channel 12-bit right-aligned data B"),
318 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
319 bit_size: 12,
320 array: None,
321 enumm: None,
322 },
323 ],
324 },
325 FieldSet {
326 name: "Dhr12rd",
327 extends: None,
328 description: Some("dual 12-bit right-aligned data holding register"),
329 bit_size: 32,
330 fields: &[Field {
331 name: "dhr",
332 description: Some("channel 12-bit right-aligned data"),
333 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
334 bit_size: 12,
335 array: Some(Array::Regular(RegularArray { len: 2, stride: 16 })),
336 enumm: None,
337 }],
338 },
339 FieldSet {
340 name: "Dhr8r",
341 extends: None,
342 description: Some("channel 8-bit right-aligned data holding register"),
343 bit_size: 32,
344 fields: &[
345 Field {
346 name: "dhr",
347 description: Some("channel 8-bit right-aligned data"),
348 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
349 bit_size: 8,
350 array: None,
351 enumm: None,
352 },
353 Field {
354 name: "dhrb",
355 description: Some("channel 8-bit right-aligned data B"),
356 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
357 bit_size: 8,
358 array: None,
359 enumm: None,
360 },
361 ],
362 },
363 FieldSet {
364 name: "Dhr8rd",
365 extends: None,
366 description: Some("dual 8-bit right aligned data holding register"),
367 bit_size: 32,
368 fields: &[Field {
369 name: "dhr",
370 description: Some("channel 8-bit right-aligned data"),
371 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
372 bit_size: 8,
373 array: Some(Array::Regular(RegularArray { len: 2, stride: 8 })),
374 enumm: None,
375 }],
376 },
377 FieldSet {
378 name: "Dor",
379 extends: None,
380 description: Some("channel data output register"),
381 bit_size: 32,
382 fields: &[
383 Field {
384 name: "dor",
385 description: Some("channel data output"),
386 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
387 bit_size: 12,
388 array: None,
389 enumm: None,
390 },
391 Field {
392 name: "dorb",
393 description: Some("channel data output B"),
394 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
395 bit_size: 12,
396 array: None,
397 enumm: None,
398 },
399 ],
400 },
401 FieldSet {
402 name: "Mcr",
403 extends: None,
404 description: Some("mode control register"),
405 bit_size: 32,
406 fields: &[
407 Field {
408 name: "mode",
409 description: Some("DAC channel mode"),
410 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
411 bit_size: 3,
412 array: Some(Array::Regular(RegularArray { len: 2, stride: 16 })),
413 enumm: Some("Mode"),
414 },
415 Field {
416 name: "dmadouble",
417 description: Some("channel DMA double data mode."),
418 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
419 bit_size: 1,
420 array: Some(Array::Regular(RegularArray { len: 2, stride: 16 })),
421 enumm: None,
422 },
423 Field {
424 name: "sinformat",
425 description: Some("enable signed format for DAC channel"),
426 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
427 bit_size: 1,
428 array: Some(Array::Regular(RegularArray { len: 2, stride: 16 })),
429 enumm: None,
430 },
431 Field {
432 name: "hfsel",
433 description: Some("high frequency interface mode selection"),
434 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }),
435 bit_size: 2,
436 array: None,
437 enumm: None,
438 },
439 ],
440 },
441 FieldSet {
442 name: "Shhr",
443 extends: None,
444 description: Some("sample and hold hold time register"),
445 bit_size: 32,
446 fields: &[Field {
447 name: "thold",
448 description: Some("channel hold time"),
449 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
450 bit_size: 10,
451 array: Some(Array::Regular(RegularArray { len: 2, stride: 16 })),
452 enumm: None,
453 }],
454 },
455 FieldSet {
456 name: "Shrr",
457 extends: None,
458 description: Some("sample and hold refresh time register"),
459 bit_size: 32,
460 fields: &[Field {
461 name: "trefresh",
462 description: Some("channel refresh time"),
463 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
464 bit_size: 8,
465 array: Some(Array::Regular(RegularArray { len: 2, stride: 16 })),
466 enumm: None,
467 }],
468 },
469 FieldSet {
470 name: "Shsr",
471 extends: None,
472 description: Some("sample and hold sample time register"),
473 bit_size: 32,
474 fields: &[Field {
475 name: "tsample",
476 description: Some("channel sample time"),
477 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
478 bit_size: 10,
479 array: None,
480 enumm: None,
481 }],
482 },
483 FieldSet {
484 name: "Sr",
485 extends: None,
486 description: Some("status register"),
487 bit_size: 32,
488 fields: &[
489 Field {
490 name: "dacrdy",
491 description: Some("channel ready status bit"),
492 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 11 }),
493 bit_size: 1,
494 array: Some(Array::Regular(RegularArray { len: 2, stride: 16 })),
495 enumm: None,
496 },
497 Field {
498 name: "dorstat",
499 description: Some("channel output register status bit"),
500 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
501 bit_size: 1,
502 array: Some(Array::Regular(RegularArray { len: 2, stride: 16 })),
503 enumm: None,
504 },
505 Field {
506 name: "dmaudr",
507 description: Some("channel DMA underrun flag"),
508 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 13 }),
509 bit_size: 1,
510 array: Some(Array::Regular(RegularArray { len: 2, stride: 16 })),
511 enumm: None,
512 },
513 Field {
514 name: "cal_flag",
515 description: Some("channel calibration offset status"),
516 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }),
517 bit_size: 1,
518 array: Some(Array::Regular(RegularArray { len: 2, stride: 16 })),
519 enumm: None,
520 },
521 Field {
522 name: "bwst",
523 description: Some("channel busy writing sample time flag"),
524 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 15 }),
525 bit_size: 1,
526 array: Some(Array::Regular(RegularArray { len: 2, stride: 16 })),
527 enumm: None,
528 },
529 ],
530 },
531 FieldSet {
532 name: "Swtrigr",
533 extends: None,
534 description: Some("software trigger register"),
535 bit_size: 32,
536 fields: &[
537 Field {
538 name: "swtrig",
539 description: Some("channel software trigger"),
540 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
541 bit_size: 1,
542 array: Some(Array::Regular(RegularArray { len: 2, stride: 1 })),
543 enumm: None,
544 },
545 Field {
546 name: "swtrigb",
547 description: Some("channel software trigger B"),
548 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
549 bit_size: 1,
550 array: Some(Array::Regular(RegularArray { len: 2, stride: 1 })),
551 enumm: None,
552 },
553 ],
554 },
555 ],
556 enums: &[
557 Enum {
558 name: "Mode",
559 description: None,
560 bit_size: 3,
561 variants: &[
562 EnumVariant {
563 name: "NORMAL_EXT_BUFEN",
564 description: Some("Normal mode, external pin only, buffer enabled"),
565 value: 0,
566 },
567 EnumVariant {
568 name: "NORMAL_EXT_INT_BUFEN",
569 description: Some("Normal mode, external pin and internal peripherals, buffer enabled"),
570 value: 1,
571 },
572 EnumVariant {
573 name: "NORMAL_EXT_BUFDIS",
574 description: Some("Normal mode, external pin only, buffer disabled"),
575 value: 2,
576 },
577 EnumVariant {
578 name: "NORMAL_INT_BUFDIS",
579 description: Some("Normal mode, internal peripherals only, buffer disabled"),
580 value: 3,
581 },
582 EnumVariant {
583 name: "SAMPHOLD_EXT_BUFEN",
584 description: Some("Sample and hold mode, external pin only, buffer enabled"),
585 value: 4,
586 },
587 EnumVariant {
588 name: "SAMPHOLD_EXT_INT_BUFEN",
589 description: Some("Sample and hold mode, external pin and internal peripherals, buffer enabled"),
590 value: 5,
591 },
592 EnumVariant {
593 name: "SAMPHOLD_EXT_INT_BUFDIS",
594 description: Some("Sample and hold mode, external pin and internal peripherals, buffer disabled"),
595 value: 6,
596 },
597 EnumVariant {
598 name: "SAMPHOLD_INT_BUFDIS",
599 description: Some("Sample and hold mode, internal peripherals only, buffer disabled"),
600 value: 7,
601 },
602 ],
603 },
604 Enum {
605 name: "Wave",
606 description: None,
607 bit_size: 2,
608 variants: &[
609 EnumVariant {
610 name: "DISABLED",
611 description: Some("Wave generation disabled"),
612 value: 0,
613 },
614 EnumVariant {
615 name: "NOISE",
616 description: Some("Noise wave generation enabled"),
617 value: 1,
618 },
619 EnumVariant {
620 name: "TRIANGLE",
621 description: Some("Triangle wave generation enabled"),
622 value: 2,
623 },
624 ],
625 },
626 ],
627};
628