1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Dbgmcu",
7 extends: None,
8 description: Some(
9 "MCU debug component",
10 ),
11 items: &[
12 BlockItem {
13 name: "idcode",
14 description: Some(
15 "DBGMCU_IDCODE",
16 ),
17 array: None,
18 byte_offset: 0x0,
19 inner: BlockItemInner::Register(
20 Register {
21 access: Access::Read,
22 bit_size: 32,
23 fieldset: Some(
24 "Idcode",
25 ),
26 },
27 ),
28 },
29 BlockItem {
30 name: "cr",
31 description: Some(
32 "Debug MCU configuration\r register",
33 ),
34 array: None,
35 byte_offset: 0x4,
36 inner: BlockItemInner::Register(
37 Register {
38 access: Access::ReadWrite,
39 bit_size: 32,
40 fieldset: Some(
41 "Cr",
42 ),
43 },
44 ),
45 },
46 BlockItem {
47 name: "apb1lfzr",
48 description: Some(
49 "Debug MCU APB1L peripheral freeze\r register",
50 ),
51 array: None,
52 byte_offset: 0x8,
53 inner: BlockItemInner::Register(
54 Register {
55 access: Access::ReadWrite,
56 bit_size: 32,
57 fieldset: Some(
58 "Apb1lfzr",
59 ),
60 },
61 ),
62 },
63 BlockItem {
64 name: "apb1hfzr",
65 description: Some(
66 "Debug MCU APB1H peripheral freeze register",
67 ),
68 array: None,
69 byte_offset: 0xc,
70 inner: BlockItemInner::Register(
71 Register {
72 access: Access::ReadWrite,
73 bit_size: 32,
74 fieldset: Some(
75 "Apb1hfzr",
76 ),
77 },
78 ),
79 },
80 BlockItem {
81 name: "apb2fzr",
82 description: Some(
83 "Debug MCU APB2 peripheral freeze register",
84 ),
85 array: None,
86 byte_offset: 0x10,
87 inner: BlockItemInner::Register(
88 Register {
89 access: Access::ReadWrite,
90 bit_size: 32,
91 fieldset: Some(
92 "Apb2fzr",
93 ),
94 },
95 ),
96 },
97 BlockItem {
98 name: "apb3fzr",
99 description: Some(
100 "Debug MCU APB3 peripheral freeze register",
101 ),
102 array: None,
103 byte_offset: 0x14,
104 inner: BlockItemInner::Register(
105 Register {
106 access: Access::ReadWrite,
107 bit_size: 32,
108 fieldset: Some(
109 "Apb3fzr",
110 ),
111 },
112 ),
113 },
114 BlockItem {
115 name: "ahb1fzr",
116 description: Some(
117 "Debug MCU AHB1 peripheral freeze register",
118 ),
119 array: None,
120 byte_offset: 0x20,
121 inner: BlockItemInner::Register(
122 Register {
123 access: Access::ReadWrite,
124 bit_size: 32,
125 fieldset: Some(
126 "Ahb1fzr",
127 ),
128 },
129 ),
130 },
131 BlockItem {
132 name: "ahb3fzr",
133 description: Some(
134 "Debug MCU AHB3 peripheral freeze register",
135 ),
136 array: None,
137 byte_offset: 0x28,
138 inner: BlockItemInner::Register(
139 Register {
140 access: Access::ReadWrite,
141 bit_size: 32,
142 fieldset: Some(
143 "Ahb3fzr",
144 ),
145 },
146 ),
147 },
148 BlockItem {
149 name: "dbgmcu_sr",
150 description: Some(
151 "DBGMCU status register",
152 ),
153 array: None,
154 byte_offset: 0xfc,
155 inner: BlockItemInner::Register(
156 Register {
157 access: Access::Read,
158 bit_size: 32,
159 fieldset: Some(
160 "DbgmcuSr",
161 ),
162 },
163 ),
164 },
165 BlockItem {
166 name: "dbgmcu_dbg_auth_host",
167 description: Some(
168 "DBGMCU debug host authentication register",
169 ),
170 array: None,
171 byte_offset: 0x100,
172 inner: BlockItemInner::Register(
173 Register {
174 access: Access::Read,
175 bit_size: 32,
176 fieldset: Some(
177 "DbgmcuDbgAuthHost",
178 ),
179 },
180 ),
181 },
182 BlockItem {
183 name: "dbgmcu_dbg_auth_device",
184 description: Some(
185 "DBGMCU debug device authentication register",
186 ),
187 array: None,
188 byte_offset: 0x104,
189 inner: BlockItemInner::Register(
190 Register {
191 access: Access::Read,
192 bit_size: 32,
193 fieldset: Some(
194 "DbgmcuDbgAuthDevice",
195 ),
196 },
197 ),
198 },
199 BlockItem {
200 name: "pidr4",
201 description: Some(
202 "Debug MCU CoreSight peripheral identity register 4",
203 ),
204 array: None,
205 byte_offset: 0xfd0,
206 inner: BlockItemInner::Register(
207 Register {
208 access: Access::Read,
209 bit_size: 32,
210 fieldset: Some(
211 "Pidr4",
212 ),
213 },
214 ),
215 },
216 BlockItem {
217 name: "pidr0",
218 description: Some(
219 "Debug MCU CoreSight peripheral identity register 0",
220 ),
221 array: None,
222 byte_offset: 0xfe0,
223 inner: BlockItemInner::Register(
224 Register {
225 access: Access::Read,
226 bit_size: 32,
227 fieldset: Some(
228 "Pidr0",
229 ),
230 },
231 ),
232 },
233 BlockItem {
234 name: "pidr1",
235 description: Some(
236 "Debug MCU CoreSight peripheral identity register 1",
237 ),
238 array: None,
239 byte_offset: 0xfe4,
240 inner: BlockItemInner::Register(
241 Register {
242 access: Access::Read,
243 bit_size: 32,
244 fieldset: Some(
245 "Pidr1",
246 ),
247 },
248 ),
249 },
250 BlockItem {
251 name: "pidr2",
252 description: Some(
253 "Debug MCU CoreSight peripheral identity register 2",
254 ),
255 array: None,
256 byte_offset: 0xfe8,
257 inner: BlockItemInner::Register(
258 Register {
259 access: Access::Read,
260 bit_size: 32,
261 fieldset: Some(
262 "Pidr2",
263 ),
264 },
265 ),
266 },
267 BlockItem {
268 name: "pidr3",
269 description: Some(
270 "Debug MCU CoreSight peripheral identity register 3",
271 ),
272 array: None,
273 byte_offset: 0xfec,
274 inner: BlockItemInner::Register(
275 Register {
276 access: Access::Read,
277 bit_size: 32,
278 fieldset: Some(
279 "Pidr3",
280 ),
281 },
282 ),
283 },
284 BlockItem {
285 name: "cidr0",
286 description: Some(
287 "Debug MCU CoreSight component identity register 0",
288 ),
289 array: None,
290 byte_offset: 0xff0,
291 inner: BlockItemInner::Register(
292 Register {
293 access: Access::Read,
294 bit_size: 32,
295 fieldset: Some(
296 "Cidr0",
297 ),
298 },
299 ),
300 },
301 BlockItem {
302 name: "cidr1",
303 description: Some(
304 "Debug MCU CoreSight component identity register 1",
305 ),
306 array: None,
307 byte_offset: 0xff4,
308 inner: BlockItemInner::Register(
309 Register {
310 access: Access::Read,
311 bit_size: 32,
312 fieldset: Some(
313 "Cidr1",
314 ),
315 },
316 ),
317 },
318 BlockItem {
319 name: "cidr2",
320 description: Some(
321 "Debug MCU CoreSight component identity register 2",
322 ),
323 array: None,
324 byte_offset: 0xff8,
325 inner: BlockItemInner::Register(
326 Register {
327 access: Access::Read,
328 bit_size: 32,
329 fieldset: Some(
330 "Cidr2",
331 ),
332 },
333 ),
334 },
335 BlockItem {
336 name: "cidr3",
337 description: Some(
338 "Debug MCU CoreSight component identity register 3",
339 ),
340 array: None,
341 byte_offset: 0xffc,
342 inner: BlockItemInner::Register(
343 Register {
344 access: Access::Read,
345 bit_size: 32,
346 fieldset: Some(
347 "Cidr3",
348 ),
349 },
350 ),
351 },
352 ],
353 },
354 ],
355 fieldsets: &[
356 FieldSet {
357 name: "Ahb1fzr",
358 extends: None,
359 description: Some(
360 "Debug MCU AHB1 peripheral freeze register",
361 ),
362 bit_size: 32,
363 fields: &[
364 Field {
365 name: "dbg_gpdma0_stop",
366 description: Some(
367 "GPDMA channel 0 stop in debug",
368 ),
369 bit_offset: BitOffset::Regular(
370 RegularBitOffset {
371 offset: 0,
372 },
373 ),
374 bit_size: 1,
375 array: None,
376 enumm: None,
377 },
378 Field {
379 name: "dbg_gpdma1_stop",
380 description: Some(
381 "GPDMA channel 1 stop in debug",
382 ),
383 bit_offset: BitOffset::Regular(
384 RegularBitOffset {
385 offset: 1,
386 },
387 ),
388 bit_size: 1,
389 array: None,
390 enumm: None,
391 },
392 Field {
393 name: "dbg_gpdma2_stop",
394 description: Some(
395 "GPDMA channel 2 stop in debug",
396 ),
397 bit_offset: BitOffset::Regular(
398 RegularBitOffset {
399 offset: 2,
400 },
401 ),
402 bit_size: 1,
403 array: None,
404 enumm: None,
405 },
406 Field {
407 name: "dbg_gpdma3_stop",
408 description: Some(
409 "GPDMA channel 3 stop in debug",
410 ),
411 bit_offset: BitOffset::Regular(
412 RegularBitOffset {
413 offset: 3,
414 },
415 ),
416 bit_size: 1,
417 array: None,
418 enumm: None,
419 },
420 Field {
421 name: "dbg_gpdma4_stop",
422 description: Some(
423 "GPDMA channel 4 stop in debug",
424 ),
425 bit_offset: BitOffset::Regular(
426 RegularBitOffset {
427 offset: 4,
428 },
429 ),
430 bit_size: 1,
431 array: None,
432 enumm: None,
433 },
434 Field {
435 name: "dbg_gpdma5_stop",
436 description: Some(
437 "GPDMA channel 5 stop in debug",
438 ),
439 bit_offset: BitOffset::Regular(
440 RegularBitOffset {
441 offset: 5,
442 },
443 ),
444 bit_size: 1,
445 array: None,
446 enumm: None,
447 },
448 Field {
449 name: "dbg_gpdma6_stop",
450 description: Some(
451 "GPDMA channel 6 stop in debug",
452 ),
453 bit_offset: BitOffset::Regular(
454 RegularBitOffset {
455 offset: 6,
456 },
457 ),
458 bit_size: 1,
459 array: None,
460 enumm: None,
461 },
462 Field {
463 name: "dbg_gpdma7_stop",
464 description: Some(
465 "GPDMA channel 7 stop in debug",
466 ),
467 bit_offset: BitOffset::Regular(
468 RegularBitOffset {
469 offset: 7,
470 },
471 ),
472 bit_size: 1,
473 array: None,
474 enumm: None,
475 },
476 Field {
477 name: "dbg_gpdma8_stop",
478 description: Some(
479 "GPDMA channel 8 stop in debug",
480 ),
481 bit_offset: BitOffset::Regular(
482 RegularBitOffset {
483 offset: 8,
484 },
485 ),
486 bit_size: 1,
487 array: None,
488 enumm: None,
489 },
490 Field {
491 name: "dbg_gpdma9_stop",
492 description: Some(
493 "GPDMA channel 9 stop in debug",
494 ),
495 bit_offset: BitOffset::Regular(
496 RegularBitOffset {
497 offset: 9,
498 },
499 ),
500 bit_size: 1,
501 array: None,
502 enumm: None,
503 },
504 Field {
505 name: "dbg_gpdma10_stop",
506 description: Some(
507 "GPDMA channel 10 stop in debug",
508 ),
509 bit_offset: BitOffset::Regular(
510 RegularBitOffset {
511 offset: 10,
512 },
513 ),
514 bit_size: 1,
515 array: None,
516 enumm: None,
517 },
518 Field {
519 name: "dbg_gpdma11_stop",
520 description: Some(
521 "GPDMA channel 11 stop in debug",
522 ),
523 bit_offset: BitOffset::Regular(
524 RegularBitOffset {
525 offset: 11,
526 },
527 ),
528 bit_size: 1,
529 array: None,
530 enumm: None,
531 },
532 Field {
533 name: "dbg_gpdma12_stop",
534 description: Some(
535 "GPDMA channel 12 stop in debug",
536 ),
537 bit_offset: BitOffset::Regular(
538 RegularBitOffset {
539 offset: 12,
540 },
541 ),
542 bit_size: 1,
543 array: None,
544 enumm: None,
545 },
546 Field {
547 name: "dbg_gpdma13_stop",
548 description: Some(
549 "GPDMA channel 13 stop in debug",
550 ),
551 bit_offset: BitOffset::Regular(
552 RegularBitOffset {
553 offset: 13,
554 },
555 ),
556 bit_size: 1,
557 array: None,
558 enumm: None,
559 },
560 Field {
561 name: "dbg_gpdma14_stop",
562 description: Some(
563 "GPDMA channel 14 stop in debug",
564 ),
565 bit_offset: BitOffset::Regular(
566 RegularBitOffset {
567 offset: 14,
568 },
569 ),
570 bit_size: 1,
571 array: None,
572 enumm: None,
573 },
574 Field {
575 name: "dbg_gpdma15_stop",
576 description: Some(
577 "GPDMA channel 15 stop in debug",
578 ),
579 bit_offset: BitOffset::Regular(
580 RegularBitOffset {
581 offset: 15,
582 },
583 ),
584 bit_size: 1,
585 array: None,
586 enumm: None,
587 },
588 ],
589 },
590 FieldSet {
591 name: "Ahb3fzr",
592 extends: None,
593 description: Some(
594 "Debug MCU AHB3 peripheral freeze register",
595 ),
596 bit_size: 32,
597 fields: &[
598 Field {
599 name: "dbg_lpdma0_stop",
600 description: Some(
601 "LPDMA channel 0 stop in debug",
602 ),
603 bit_offset: BitOffset::Regular(
604 RegularBitOffset {
605 offset: 0,
606 },
607 ),
608 bit_size: 1,
609 array: None,
610 enumm: None,
611 },
612 Field {
613 name: "dbg_lpdma1_stop",
614 description: Some(
615 "LPDMA channel 1 stop in debug",
616 ),
617 bit_offset: BitOffset::Regular(
618 RegularBitOffset {
619 offset: 1,
620 },
621 ),
622 bit_size: 1,
623 array: None,
624 enumm: None,
625 },
626 Field {
627 name: "dbg_lpdma2_stop",
628 description: Some(
629 "LPDMA channel 2 stop in debug",
630 ),
631 bit_offset: BitOffset::Regular(
632 RegularBitOffset {
633 offset: 2,
634 },
635 ),
636 bit_size: 1,
637 array: None,
638 enumm: None,
639 },
640 Field {
641 name: "dbg_lpdma3_stop",
642 description: Some(
643 "LPDMA channel 3 stop in debug",
644 ),
645 bit_offset: BitOffset::Regular(
646 RegularBitOffset {
647 offset: 3,
648 },
649 ),
650 bit_size: 1,
651 array: None,
652 enumm: None,
653 },
654 ],
655 },
656 FieldSet {
657 name: "Apb1hfzr",
658 extends: None,
659 description: Some(
660 "Debug MCU APB1H peripheral freeze register",
661 ),
662 bit_size: 32,
663 fields: &[
664 Field {
665 name: "dbg_i2c4_stop",
666 description: Some(
667 "I2C4 stop in debug",
668 ),
669 bit_offset: BitOffset::Regular(
670 RegularBitOffset {
671 offset: 1,
672 },
673 ),
674 bit_size: 1,
675 array: None,
676 enumm: None,
677 },
678 Field {
679 name: "dbg_lptim2_stop",
680 description: Some(
681 "LPTIM2 stop in debug",
682 ),
683 bit_offset: BitOffset::Regular(
684 RegularBitOffset {
685 offset: 5,
686 },
687 ),
688 bit_size: 1,
689 array: None,
690 enumm: None,
691 },
692 ],
693 },
694 FieldSet {
695 name: "Apb1lfzr",
696 extends: None,
697 description: Some(
698 "Debug MCU APB1L peripheral freeze\r register",
699 ),
700 bit_size: 32,
701 fields: &[
702 Field {
703 name: "dbg_tim2_stop",
704 description: Some(
705 "TIM2 stop in debug",
706 ),
707 bit_offset: BitOffset::Regular(
708 RegularBitOffset {
709 offset: 0,
710 },
711 ),
712 bit_size: 1,
713 array: None,
714 enumm: None,
715 },
716 Field {
717 name: "dbg_tim3_stop",
718 description: Some(
719 "TIM3 stop in debug",
720 ),
721 bit_offset: BitOffset::Regular(
722 RegularBitOffset {
723 offset: 1,
724 },
725 ),
726 bit_size: 1,
727 array: None,
728 enumm: None,
729 },
730 Field {
731 name: "dbg_tim4_stop",
732 description: Some(
733 "TIM4 stop in debug",
734 ),
735 bit_offset: BitOffset::Regular(
736 RegularBitOffset {
737 offset: 2,
738 },
739 ),
740 bit_size: 1,
741 array: None,
742 enumm: None,
743 },
744 Field {
745 name: "dbg_tim5_stop",
746 description: Some(
747 "TIM5 stop in debug",
748 ),
749 bit_offset: BitOffset::Regular(
750 RegularBitOffset {
751 offset: 3,
752 },
753 ),
754 bit_size: 1,
755 array: None,
756 enumm: None,
757 },
758 Field {
759 name: "dbg_tim6_stop",
760 description: Some(
761 "TIM6 stop in debug",
762 ),
763 bit_offset: BitOffset::Regular(
764 RegularBitOffset {
765 offset: 4,
766 },
767 ),
768 bit_size: 1,
769 array: None,
770 enumm: None,
771 },
772 Field {
773 name: "dbg_tim7_stop",
774 description: Some(
775 "TIM7 stop in debug",
776 ),
777 bit_offset: BitOffset::Regular(
778 RegularBitOffset {
779 offset: 5,
780 },
781 ),
782 bit_size: 1,
783 array: None,
784 enumm: None,
785 },
786 Field {
787 name: "dbg_wwdg_stop",
788 description: Some(
789 "Window watchdog counter stop in debug",
790 ),
791 bit_offset: BitOffset::Regular(
792 RegularBitOffset {
793 offset: 11,
794 },
795 ),
796 bit_size: 1,
797 array: None,
798 enumm: None,
799 },
800 Field {
801 name: "dbg_iwdg_stop",
802 description: Some(
803 "Independent watchdog counter stop in debug",
804 ),
805 bit_offset: BitOffset::Regular(
806 RegularBitOffset {
807 offset: 12,
808 },
809 ),
810 bit_size: 1,
811 array: None,
812 enumm: None,
813 },
814 Field {
815 name: "dbg_i2c1_stop",
816 description: Some(
817 "I2C1 SMBUS timeout stop in debug",
818 ),
819 bit_offset: BitOffset::Regular(
820 RegularBitOffset {
821 offset: 21,
822 },
823 ),
824 bit_size: 1,
825 array: None,
826 enumm: None,
827 },
828 Field {
829 name: "dbg_i2c2_stop",
830 description: Some(
831 "I2C2 SMBUS timeout stop in debug",
832 ),
833 bit_offset: BitOffset::Regular(
834 RegularBitOffset {
835 offset: 22,
836 },
837 ),
838 bit_size: 1,
839 array: None,
840 enumm: None,
841 },
842 ],
843 },
844 FieldSet {
845 name: "Apb2fzr",
846 extends: None,
847 description: Some(
848 "Debug MCU APB2 peripheral freeze register",
849 ),
850 bit_size: 32,
851 fields: &[
852 Field {
853 name: "dbg_tim1_stop",
854 description: Some(
855 "TIM1 counter stopped when core is\r halted",
856 ),
857 bit_offset: BitOffset::Regular(
858 RegularBitOffset {
859 offset: 11,
860 },
861 ),
862 bit_size: 1,
863 array: None,
864 enumm: None,
865 },
866 Field {
867 name: "dbg_tim8_stop",
868 description: Some(
869 "TIM8 stop in debug",
870 ),
871 bit_offset: BitOffset::Regular(
872 RegularBitOffset {
873 offset: 13,
874 },
875 ),
876 bit_size: 1,
877 array: None,
878 enumm: None,
879 },
880 Field {
881 name: "dbg_tim15_stop",
882 description: Some(
883 "TIM15 counter stopped when core is\r halted",
884 ),
885 bit_offset: BitOffset::Regular(
886 RegularBitOffset {
887 offset: 16,
888 },
889 ),
890 bit_size: 1,
891 array: None,
892 enumm: None,
893 },
894 Field {
895 name: "dbg_tim16_stop",
896 description: Some(
897 "TIM16 counter stopped when core is\r halted",
898 ),
899 bit_offset: BitOffset::Regular(
900 RegularBitOffset {
901 offset: 17,
902 },
903 ),
904 bit_size: 1,
905 array: None,
906 enumm: None,
907 },
908 Field {
909 name: "dbg_tim17_stop",
910 description: Some(
911 "DBG_TIM17_STOP",
912 ),
913 bit_offset: BitOffset::Regular(
914 RegularBitOffset {
915 offset: 18,
916 },
917 ),
918 bit_size: 1,
919 array: None,
920 enumm: None,
921 },
922 ],
923 },
924 FieldSet {
925 name: "Apb3fzr",
926 extends: None,
927 description: Some(
928 "Debug MCU APB3 peripheral freeze register",
929 ),
930 bit_size: 32,
931 fields: &[
932 Field {
933 name: "dbg_i2c3_stop",
934 description: Some(
935 "I2C3 stop in debug",
936 ),
937 bit_offset: BitOffset::Regular(
938 RegularBitOffset {
939 offset: 10,
940 },
941 ),
942 bit_size: 1,
943 array: None,
944 enumm: None,
945 },
946 Field {
947 name: "dbg_lptim1_stop",
948 description: Some(
949 "LPTIM1 stop in debug",
950 ),
951 bit_offset: BitOffset::Regular(
952 RegularBitOffset {
953 offset: 17,
954 },
955 ),
956 bit_size: 1,
957 array: None,
958 enumm: None,
959 },
960 Field {
961 name: "dbg_lptim3_stop",
962 description: Some(
963 "LPTIM3 stop in debug",
964 ),
965 bit_offset: BitOffset::Regular(
966 RegularBitOffset {
967 offset: 18,
968 },
969 ),
970 bit_size: 1,
971 array: None,
972 enumm: None,
973 },
974 Field {
975 name: "dbg_lptim4_stop",
976 description: Some(
977 "LPTIM4 stop in debug",
978 ),
979 bit_offset: BitOffset::Regular(
980 RegularBitOffset {
981 offset: 19,
982 },
983 ),
984 bit_size: 1,
985 array: None,
986 enumm: None,
987 },
988 Field {
989 name: "dbg_rtc_stop",
990 description: Some(
991 "RTC stop in debug",
992 ),
993 bit_offset: BitOffset::Regular(
994 RegularBitOffset {
995 offset: 30,
996 },
997 ),
998 bit_size: 1,
999 array: None,
1000 enumm: None,
1001 },
1002 ],
1003 },
1004 FieldSet {
1005 name: "Cidr0",
1006 extends: None,
1007 description: Some(
1008 "Debug MCU CoreSight component identity register 0",
1009 ),
1010 bit_size: 32,
1011 fields: &[
1012 Field {
1013 name: "preamble",
1014 description: Some(
1015 "component identification bits [7:0]",
1016 ),
1017 bit_offset: BitOffset::Regular(
1018 RegularBitOffset {
1019 offset: 0,
1020 },
1021 ),
1022 bit_size: 8,
1023 array: None,
1024 enumm: None,
1025 },
1026 ],
1027 },
1028 FieldSet {
1029 name: "Cidr1",
1030 extends: None,
1031 description: Some(
1032 "Debug MCU CoreSight component identity register 1",
1033 ),
1034 bit_size: 32,
1035 fields: &[
1036 Field {
1037 name: "preamble",
1038 description: Some(
1039 "component identification bits [11:8]",
1040 ),
1041 bit_offset: BitOffset::Regular(
1042 RegularBitOffset {
1043 offset: 0,
1044 },
1045 ),
1046 bit_size: 4,
1047 array: None,
1048 enumm: None,
1049 },
1050 Field {
1051 name: "class",
1052 description: Some(
1053 "component identification bits [15:12] - component class",
1054 ),
1055 bit_offset: BitOffset::Regular(
1056 RegularBitOffset {
1057 offset: 4,
1058 },
1059 ),
1060 bit_size: 4,
1061 array: None,
1062 enumm: None,
1063 },
1064 ],
1065 },
1066 FieldSet {
1067 name: "Cidr2",
1068 extends: None,
1069 description: Some(
1070 "Debug MCU CoreSight component identity register 2",
1071 ),
1072 bit_size: 32,
1073 fields: &[
1074 Field {
1075 name: "preamble",
1076 description: Some(
1077 "component identification bits [23:16]",
1078 ),
1079 bit_offset: BitOffset::Regular(
1080 RegularBitOffset {
1081 offset: 0,
1082 },
1083 ),
1084 bit_size: 8,
1085 array: None,
1086 enumm: None,
1087 },
1088 ],
1089 },
1090 FieldSet {
1091 name: "Cidr3",
1092 extends: None,
1093 description: Some(
1094 "Debug MCU CoreSight component identity register 3",
1095 ),
1096 bit_size: 32,
1097 fields: &[
1098 Field {
1099 name: "preamble",
1100 description: Some(
1101 "component identification bits [31:24]",
1102 ),
1103 bit_offset: BitOffset::Regular(
1104 RegularBitOffset {
1105 offset: 0,
1106 },
1107 ),
1108 bit_size: 8,
1109 array: None,
1110 enumm: None,
1111 },
1112 ],
1113 },
1114 FieldSet {
1115 name: "Cr",
1116 extends: None,
1117 description: Some(
1118 "Debug MCU configuration\r register",
1119 ),
1120 bit_size: 32,
1121 fields: &[
1122 Field {
1123 name: "dbg_stop",
1124 description: Some(
1125 "Debug Stop mode",
1126 ),
1127 bit_offset: BitOffset::Regular(
1128 RegularBitOffset {
1129 offset: 1,
1130 },
1131 ),
1132 bit_size: 1,
1133 array: None,
1134 enumm: None,
1135 },
1136 Field {
1137 name: "dbg_standby",
1138 description: Some(
1139 "Debug Standby mode",
1140 ),
1141 bit_offset: BitOffset::Regular(
1142 RegularBitOffset {
1143 offset: 2,
1144 },
1145 ),
1146 bit_size: 1,
1147 array: None,
1148 enumm: None,
1149 },
1150 Field {
1151 name: "trace_ioen",
1152 description: Some(
1153 "Trace pin assignment\r control",
1154 ),
1155 bit_offset: BitOffset::Regular(
1156 RegularBitOffset {
1157 offset: 4,
1158 },
1159 ),
1160 bit_size: 1,
1161 array: None,
1162 enumm: None,
1163 },
1164 Field {
1165 name: "trace_en",
1166 description: Some(
1167 "trace port and clock\r enable",
1168 ),
1169 bit_offset: BitOffset::Regular(
1170 RegularBitOffset {
1171 offset: 5,
1172 },
1173 ),
1174 bit_size: 1,
1175 array: None,
1176 enumm: None,
1177 },
1178 Field {
1179 name: "trace_mode",
1180 description: Some(
1181 "Trace pin assignment\r control",
1182 ),
1183 bit_offset: BitOffset::Regular(
1184 RegularBitOffset {
1185 offset: 6,
1186 },
1187 ),
1188 bit_size: 2,
1189 array: None,
1190 enumm: None,
1191 },
1192 ],
1193 },
1194 FieldSet {
1195 name: "DbgmcuDbgAuthDevice",
1196 extends: None,
1197 description: Some(
1198 "DBGMCU debug device authentication register",
1199 ),
1200 bit_size: 32,
1201 fields: &[
1202 Field {
1203 name: "auth_id",
1204 description: Some(
1205 "Device specific ID\r \tDevice specific ID used for RDP regression.",
1206 ),
1207 bit_offset: BitOffset::Regular(
1208 RegularBitOffset {
1209 offset: 0,
1210 },
1211 ),
1212 bit_size: 32,
1213 array: None,
1214 enumm: None,
1215 },
1216 ],
1217 },
1218 FieldSet {
1219 name: "DbgmcuDbgAuthHost",
1220 extends: None,
1221 description: Some(
1222 "DBGMCU debug host authentication register",
1223 ),
1224 bit_size: 32,
1225 fields: &[
1226 Field {
1227 name: "auth_key",
1228 description: Some(
1229 "Device authentication key\r \tThe device specific 64-bit authentication key (OEM key) must be written to this register (in two successive 32-bit writes, least significant word first) to permit RDP regression. Writing a wrong key locks access to the device and prevent code execution from the Flash memory.",
1230 ),
1231 bit_offset: BitOffset::Regular(
1232 RegularBitOffset {
1233 offset: 0,
1234 },
1235 ),
1236 bit_size: 32,
1237 array: None,
1238 enumm: None,
1239 },
1240 ],
1241 },
1242 FieldSet {
1243 name: "DbgmcuSr",
1244 extends: None,
1245 description: Some(
1246 "DBGMCU status register",
1247 ),
1248 bit_size: 32,
1249 fields: &[
1250 Field {
1251 name: "ap_present",
1252 description: Some(
1253 "Bit n identifies whether access port AP n is present in device\r \tBit n\u{a0}=\u{a0}0: APn absent\r \tBit n\u{a0}=\u{a0}1: APn present",
1254 ),
1255 bit_offset: BitOffset::Regular(
1256 RegularBitOffset {
1257 offset: 0,
1258 },
1259 ),
1260 bit_size: 8,
1261 array: None,
1262 enumm: None,
1263 },
1264 Field {
1265 name: "ap_locked",
1266 description: Some(
1267 "DECLARATION TO BE CONFIRMED by PRODUCT OWNER! Bit n identifies whether access port AP n is open (can be accessed via the debug port) or locked (debug access to the AP is blocked)\r \tBit n\u{a0}=\u{a0}0: APn locked\r \tBit n\u{a0}=\u{a0}1: APn enabled",
1268 ),
1269 bit_offset: BitOffset::Regular(
1270 RegularBitOffset {
1271 offset: 8,
1272 },
1273 ),
1274 bit_size: 8,
1275 array: None,
1276 enumm: None,
1277 },
1278 ],
1279 },
1280 FieldSet {
1281 name: "Idcode",
1282 extends: None,
1283 description: Some(
1284 "DBGMCU_IDCODE",
1285 ),
1286 bit_size: 32,
1287 fields: &[
1288 Field {
1289 name: "dev_id",
1290 description: Some(
1291 "Device dentification",
1292 ),
1293 bit_offset: BitOffset::Regular(
1294 RegularBitOffset {
1295 offset: 0,
1296 },
1297 ),
1298 bit_size: 12,
1299 array: None,
1300 enumm: None,
1301 },
1302 Field {
1303 name: "rev_id",
1304 description: Some(
1305 "Revision",
1306 ),
1307 bit_offset: BitOffset::Regular(
1308 RegularBitOffset {
1309 offset: 16,
1310 },
1311 ),
1312 bit_size: 16,
1313 array: None,
1314 enumm: None,
1315 },
1316 ],
1317 },
1318 FieldSet {
1319 name: "Pidr0",
1320 extends: None,
1321 description: Some(
1322 "Debug MCU CoreSight peripheral identity register 0",
1323 ),
1324 bit_size: 32,
1325 fields: &[
1326 Field {
1327 name: "partnum",
1328 description: Some(
1329 "part number bits [7:0]",
1330 ),
1331 bit_offset: BitOffset::Regular(
1332 RegularBitOffset {
1333 offset: 0,
1334 },
1335 ),
1336 bit_size: 8,
1337 array: None,
1338 enumm: None,
1339 },
1340 ],
1341 },
1342 FieldSet {
1343 name: "Pidr1",
1344 extends: None,
1345 description: Some(
1346 "Debug MCU CoreSight peripheral identity register 1",
1347 ),
1348 bit_size: 32,
1349 fields: &[
1350 Field {
1351 name: "partnum",
1352 description: Some(
1353 "part number bits [11:8]",
1354 ),
1355 bit_offset: BitOffset::Regular(
1356 RegularBitOffset {
1357 offset: 0,
1358 },
1359 ),
1360 bit_size: 4,
1361 array: None,
1362 enumm: None,
1363 },
1364 Field {
1365 name: "jep106id",
1366 description: Some(
1367 "JEP106 identity code bits [3:0]",
1368 ),
1369 bit_offset: BitOffset::Regular(
1370 RegularBitOffset {
1371 offset: 4,
1372 },
1373 ),
1374 bit_size: 4,
1375 array: None,
1376 enumm: None,
1377 },
1378 ],
1379 },
1380 FieldSet {
1381 name: "Pidr2",
1382 extends: None,
1383 description: Some(
1384 "Debug MCU CoreSight peripheral identity register 2",
1385 ),
1386 bit_size: 32,
1387 fields: &[
1388 Field {
1389 name: "jep106id",
1390 description: Some(
1391 "JEP106 identity code bits [6:4]",
1392 ),
1393 bit_offset: BitOffset::Regular(
1394 RegularBitOffset {
1395 offset: 0,
1396 },
1397 ),
1398 bit_size: 3,
1399 array: None,
1400 enumm: None,
1401 },
1402 Field {
1403 name: "jedec",
1404 description: Some(
1405 "JEDEC assigned value",
1406 ),
1407 bit_offset: BitOffset::Regular(
1408 RegularBitOffset {
1409 offset: 3,
1410 },
1411 ),
1412 bit_size: 1,
1413 array: None,
1414 enumm: None,
1415 },
1416 Field {
1417 name: "revision",
1418 description: Some(
1419 "component revision number",
1420 ),
1421 bit_offset: BitOffset::Regular(
1422 RegularBitOffset {
1423 offset: 4,
1424 },
1425 ),
1426 bit_size: 4,
1427 array: None,
1428 enumm: None,
1429 },
1430 ],
1431 },
1432 FieldSet {
1433 name: "Pidr3",
1434 extends: None,
1435 description: Some(
1436 "Debug MCU CoreSight peripheral identity register 3",
1437 ),
1438 bit_size: 32,
1439 fields: &[
1440 Field {
1441 name: "cmod",
1442 description: Some(
1443 "customer modified",
1444 ),
1445 bit_offset: BitOffset::Regular(
1446 RegularBitOffset {
1447 offset: 0,
1448 },
1449 ),
1450 bit_size: 4,
1451 array: None,
1452 enumm: None,
1453 },
1454 Field {
1455 name: "revand",
1456 description: Some(
1457 "metal fix version",
1458 ),
1459 bit_offset: BitOffset::Regular(
1460 RegularBitOffset {
1461 offset: 4,
1462 },
1463 ),
1464 bit_size: 4,
1465 array: None,
1466 enumm: None,
1467 },
1468 ],
1469 },
1470 FieldSet {
1471 name: "Pidr4",
1472 extends: None,
1473 description: Some(
1474 "Debug MCU CoreSight peripheral identity register 4",
1475 ),
1476 bit_size: 32,
1477 fields: &[
1478 Field {
1479 name: "jep106con",
1480 description: Some(
1481 "JEP106 continuation code",
1482 ),
1483 bit_offset: BitOffset::Regular(
1484 RegularBitOffset {
1485 offset: 0,
1486 },
1487 ),
1488 bit_size: 4,
1489 array: None,
1490 enumm: None,
1491 },
1492 Field {
1493 name: "kcount_4",
1494 description: Some(
1495 "register file size",
1496 ),
1497 bit_offset: BitOffset::Regular(
1498 RegularBitOffset {
1499 offset: 4,
1500 },
1501 ),
1502 bit_size: 4,
1503 array: None,
1504 enumm: None,
1505 },
1506 ],
1507 },
1508 ],
1509 enums: &[],
1510};
1511