1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Dcache",
7 extends: None,
8 description: Some(
9 "Data cache.",
10 ),
11 items: &[
12 BlockItem {
13 name: "cr",
14 description: Some(
15 "DCACHE control register.",
16 ),
17 array: None,
18 byte_offset: 0x0,
19 inner: BlockItemInner::Register(
20 Register {
21 access: Access::ReadWrite,
22 bit_size: 32,
23 fieldset: Some(
24 "Cr",
25 ),
26 },
27 ),
28 },
29 BlockItem {
30 name: "sr",
31 description: Some(
32 "DCACHE status register.",
33 ),
34 array: None,
35 byte_offset: 0x4,
36 inner: BlockItemInner::Register(
37 Register {
38 access: Access::ReadWrite,
39 bit_size: 32,
40 fieldset: Some(
41 "Sr",
42 ),
43 },
44 ),
45 },
46 BlockItem {
47 name: "ier",
48 description: Some(
49 "DCACHE interrupt enable register.",
50 ),
51 array: None,
52 byte_offset: 0x8,
53 inner: BlockItemInner::Register(
54 Register {
55 access: Access::ReadWrite,
56 bit_size: 32,
57 fieldset: Some(
58 "Ier",
59 ),
60 },
61 ),
62 },
63 BlockItem {
64 name: "fcr",
65 description: Some(
66 "DCACHE flag clear register.",
67 ),
68 array: None,
69 byte_offset: 0xc,
70 inner: BlockItemInner::Register(
71 Register {
72 access: Access::ReadWrite,
73 bit_size: 32,
74 fieldset: Some(
75 "Fcr",
76 ),
77 },
78 ),
79 },
80 BlockItem {
81 name: "rhmonr",
82 description: Some(
83 "DCACHE read-hit monitor register.",
84 ),
85 array: None,
86 byte_offset: 0x10,
87 inner: BlockItemInner::Register(
88 Register {
89 access: Access::ReadWrite,
90 bit_size: 32,
91 fieldset: None,
92 },
93 ),
94 },
95 BlockItem {
96 name: "rmmonr",
97 description: Some(
98 "DCACHE read-miss monitor register.",
99 ),
100 array: None,
101 byte_offset: 0x14,
102 inner: BlockItemInner::Register(
103 Register {
104 access: Access::ReadWrite,
105 bit_size: 32,
106 fieldset: Some(
107 "Rmmonr",
108 ),
109 },
110 ),
111 },
112 BlockItem {
113 name: "whmonr",
114 description: Some(
115 "DCACHE write-hit monitor register.",
116 ),
117 array: None,
118 byte_offset: 0x20,
119 inner: BlockItemInner::Register(
120 Register {
121 access: Access::ReadWrite,
122 bit_size: 32,
123 fieldset: None,
124 },
125 ),
126 },
127 BlockItem {
128 name: "wmmonr",
129 description: Some(
130 "DCACHE write-miss monitor register.",
131 ),
132 array: None,
133 byte_offset: 0x24,
134 inner: BlockItemInner::Register(
135 Register {
136 access: Access::ReadWrite,
137 bit_size: 32,
138 fieldset: Some(
139 "Wmmonr",
140 ),
141 },
142 ),
143 },
144 BlockItem {
145 name: "cmdrsaddrr",
146 description: Some(
147 "DCACHE command range start address register.",
148 ),
149 array: None,
150 byte_offset: 0x28,
151 inner: BlockItemInner::Register(
152 Register {
153 access: Access::ReadWrite,
154 bit_size: 32,
155 fieldset: Some(
156 "Cmdrsaddrr",
157 ),
158 },
159 ),
160 },
161 BlockItem {
162 name: "cmdreaddrr",
163 description: Some(
164 "DCACHE command range end address register.",
165 ),
166 array: None,
167 byte_offset: 0x2c,
168 inner: BlockItemInner::Register(
169 Register {
170 access: Access::ReadWrite,
171 bit_size: 32,
172 fieldset: Some(
173 "Cmdreaddrr",
174 ),
175 },
176 ),
177 },
178 ],
179 },
180 ],
181 fieldsets: &[
182 FieldSet {
183 name: "Cmdreaddrr",
184 extends: None,
185 description: Some(
186 "DCACHE command range end address register.",
187 ),
188 bit_size: 32,
189 fields: &[
190 Field {
191 name: "cmdendaddr",
192 description: Some(
193 "end address of range to which the cache maintenance command specified in DCACHE_CR.CACHECMD field applies This register must be set before DCACHE_CR.CACHECMD is written.",
194 ),
195 bit_offset: BitOffset::Regular(
196 RegularBitOffset {
197 offset: 4,
198 },
199 ),
200 bit_size: 28,
201 array: None,
202 enumm: None,
203 },
204 ],
205 },
206 FieldSet {
207 name: "Cmdrsaddrr",
208 extends: None,
209 description: Some(
210 "DCACHE command range start address register.",
211 ),
212 bit_size: 32,
213 fields: &[
214 Field {
215 name: "cmdstartaddr",
216 description: Some(
217 "start address of range to which the cache maintenance command specified in DCACHE_CR.CACHECMD field applies This register must be set before DCACHE_CR.CACHECMD is written..",
218 ),
219 bit_offset: BitOffset::Regular(
220 RegularBitOffset {
221 offset: 4,
222 },
223 ),
224 bit_size: 28,
225 array: None,
226 enumm: None,
227 },
228 ],
229 },
230 FieldSet {
231 name: "Cr",
232 extends: None,
233 description: Some(
234 "DCACHE control register.",
235 ),
236 bit_size: 32,
237 fields: &[
238 Field {
239 name: "en",
240 description: Some(
241 "enable.",
242 ),
243 bit_offset: BitOffset::Regular(
244 RegularBitOffset {
245 offset: 0,
246 },
247 ),
248 bit_size: 1,
249 array: None,
250 enumm: None,
251 },
252 Field {
253 name: "cacheinv",
254 description: Some(
255 "full cache invalidation Can be set by software, only when EN = 1. Cleared by hardware when the BUSYF flag is set (during full cache invalidation operation). Writing 0 has no effect.",
256 ),
257 bit_offset: BitOffset::Regular(
258 RegularBitOffset {
259 offset: 1,
260 },
261 ),
262 bit_size: 1,
263 array: None,
264 enumm: None,
265 },
266 Field {
267 name: "cachecmd",
268 description: Some(
269 "cache command maintenance operation (cleans and/or invalidates an address range) Can be set and cleared by software, only when no maintenance command is ongoing (BUSYCMDF = 0). others: reserved.",
270 ),
271 bit_offset: BitOffset::Regular(
272 RegularBitOffset {
273 offset: 8,
274 },
275 ),
276 bit_size: 3,
277 array: None,
278 enumm: None,
279 },
280 Field {
281 name: "startcmd",
282 description: Some(
283 "starts maintenance command (maintenance operation defined in CACHECMD). Can be set by software, only when EN = 1, BUSYCMDF = 0, BUSYF = 0 and CACHECMD = 0b001, 0b010 or 0b011. Cleared by hardware when the BUSYCMDF flag is set (during cache maintenance operation). Writing 0 has no effect.",
284 ),
285 bit_offset: BitOffset::Regular(
286 RegularBitOffset {
287 offset: 11,
288 },
289 ),
290 bit_size: 1,
291 array: None,
292 enumm: None,
293 },
294 Field {
295 name: "rhitmen",
296 description: Some(
297 "read-hit monitor enable.",
298 ),
299 bit_offset: BitOffset::Regular(
300 RegularBitOffset {
301 offset: 16,
302 },
303 ),
304 bit_size: 1,
305 array: None,
306 enumm: None,
307 },
308 Field {
309 name: "rmissmen",
310 description: Some(
311 "read-miss monitor enable.",
312 ),
313 bit_offset: BitOffset::Regular(
314 RegularBitOffset {
315 offset: 17,
316 },
317 ),
318 bit_size: 1,
319 array: None,
320 enumm: None,
321 },
322 Field {
323 name: "rhitmrst",
324 description: Some(
325 "read-hit monitor reset.",
326 ),
327 bit_offset: BitOffset::Regular(
328 RegularBitOffset {
329 offset: 18,
330 },
331 ),
332 bit_size: 1,
333 array: None,
334 enumm: None,
335 },
336 Field {
337 name: "rmissmrst",
338 description: Some(
339 "read-miss monitor reset.",
340 ),
341 bit_offset: BitOffset::Regular(
342 RegularBitOffset {
343 offset: 19,
344 },
345 ),
346 bit_size: 1,
347 array: None,
348 enumm: None,
349 },
350 Field {
351 name: "whitmen",
352 description: Some(
353 "write-hit monitor enable.",
354 ),
355 bit_offset: BitOffset::Regular(
356 RegularBitOffset {
357 offset: 20,
358 },
359 ),
360 bit_size: 1,
361 array: None,
362 enumm: None,
363 },
364 Field {
365 name: "wmissmen",
366 description: Some(
367 "write-miss monitor enable.",
368 ),
369 bit_offset: BitOffset::Regular(
370 RegularBitOffset {
371 offset: 21,
372 },
373 ),
374 bit_size: 1,
375 array: None,
376 enumm: None,
377 },
378 Field {
379 name: "whitmrst",
380 description: Some(
381 "write-hit monitor reset.",
382 ),
383 bit_offset: BitOffset::Regular(
384 RegularBitOffset {
385 offset: 22,
386 },
387 ),
388 bit_size: 1,
389 array: None,
390 enumm: None,
391 },
392 Field {
393 name: "wmissmrst",
394 description: Some(
395 "write-miss monitor reset.",
396 ),
397 bit_offset: BitOffset::Regular(
398 RegularBitOffset {
399 offset: 23,
400 },
401 ),
402 bit_size: 1,
403 array: None,
404 enumm: None,
405 },
406 Field {
407 name: "hburst",
408 description: Some(
409 "output burst type for cache master port read accesses Write access is always done in INCR burst type.",
410 ),
411 bit_offset: BitOffset::Regular(
412 RegularBitOffset {
413 offset: 31,
414 },
415 ),
416 bit_size: 1,
417 array: None,
418 enumm: None,
419 },
420 ],
421 },
422 FieldSet {
423 name: "Fcr",
424 extends: None,
425 description: Some(
426 "DCACHE flag clear register.",
427 ),
428 bit_size: 32,
429 fields: &[
430 Field {
431 name: "cbsyendf",
432 description: Some(
433 "clear full invalidate busy end flag Set by software.",
434 ),
435 bit_offset: BitOffset::Regular(
436 RegularBitOffset {
437 offset: 1,
438 },
439 ),
440 bit_size: 1,
441 array: None,
442 enumm: None,
443 },
444 Field {
445 name: "cerrf",
446 description: Some(
447 "clear cache error flag Set by software.",
448 ),
449 bit_offset: BitOffset::Regular(
450 RegularBitOffset {
451 offset: 2,
452 },
453 ),
454 bit_size: 1,
455 array: None,
456 enumm: None,
457 },
458 Field {
459 name: "ccmdendf",
460 description: Some(
461 "clear command end flag Set by software.",
462 ),
463 bit_offset: BitOffset::Regular(
464 RegularBitOffset {
465 offset: 4,
466 },
467 ),
468 bit_size: 1,
469 array: None,
470 enumm: None,
471 },
472 ],
473 },
474 FieldSet {
475 name: "Ier",
476 extends: None,
477 description: Some(
478 "DCACHE interrupt enable register.",
479 ),
480 bit_size: 32,
481 fields: &[
482 Field {
483 name: "bsyendie",
484 description: Some(
485 "interrupt enable on busy end Set by SW to enable an interrupt generation at the end of a cache full invalidate operation.",
486 ),
487 bit_offset: BitOffset::Regular(
488 RegularBitOffset {
489 offset: 1,
490 },
491 ),
492 bit_size: 1,
493 array: None,
494 enumm: None,
495 },
496 Field {
497 name: "errie",
498 description: Some(
499 "interrupt enable on cache error Set by software to enable an interrupt generation in case of cache functional error (eviction or clean operation write-back error).",
500 ),
501 bit_offset: BitOffset::Regular(
502 RegularBitOffset {
503 offset: 2,
504 },
505 ),
506 bit_size: 1,
507 array: None,
508 enumm: None,
509 },
510 Field {
511 name: "cmdendie",
512 description: Some(
513 "interrupt enable on command end Set by software to enable an interrupt generation at the end of a cache command (clean and/or invalidate an address range).",
514 ),
515 bit_offset: BitOffset::Regular(
516 RegularBitOffset {
517 offset: 4,
518 },
519 ),
520 bit_size: 1,
521 array: None,
522 enumm: None,
523 },
524 ],
525 },
526 FieldSet {
527 name: "Rmmonr",
528 extends: None,
529 description: Some(
530 "DCACHE read-miss monitor register.",
531 ),
532 bit_size: 32,
533 fields: &[
534 Field {
535 name: "rmissmon",
536 description: Some(
537 "cache read-miss monitor counter.",
538 ),
539 bit_offset: BitOffset::Regular(
540 RegularBitOffset {
541 offset: 0,
542 },
543 ),
544 bit_size: 16,
545 array: None,
546 enumm: None,
547 },
548 ],
549 },
550 FieldSet {
551 name: "Sr",
552 extends: None,
553 description: Some(
554 "DCACHE status register.",
555 ),
556 bit_size: 32,
557 fields: &[
558 Field {
559 name: "busyf",
560 description: Some(
561 "full invalidate busy flag.",
562 ),
563 bit_offset: BitOffset::Regular(
564 RegularBitOffset {
565 offset: 0,
566 },
567 ),
568 bit_size: 1,
569 array: None,
570 enumm: None,
571 },
572 Field {
573 name: "bsyendf",
574 description: Some(
575 "full invalidate busy end flag Cleared by writing DCACHE_FCR.CBSYENDF = 1.",
576 ),
577 bit_offset: BitOffset::Regular(
578 RegularBitOffset {
579 offset: 1,
580 },
581 ),
582 bit_size: 1,
583 array: None,
584 enumm: None,
585 },
586 Field {
587 name: "errf",
588 description: Some(
589 "cache error flag Cleared by writing DCACHE_FCR.CERRF = 1.",
590 ),
591 bit_offset: BitOffset::Regular(
592 RegularBitOffset {
593 offset: 2,
594 },
595 ),
596 bit_size: 1,
597 array: None,
598 enumm: None,
599 },
600 Field {
601 name: "busycmdf",
602 description: Some(
603 "command busy flag.",
604 ),
605 bit_offset: BitOffset::Regular(
606 RegularBitOffset {
607 offset: 3,
608 },
609 ),
610 bit_size: 1,
611 array: None,
612 enumm: None,
613 },
614 Field {
615 name: "cmdendf",
616 description: Some(
617 "command end flag Cleared by writing DCACHE_FCR.CCMDENDF = 1.",
618 ),
619 bit_offset: BitOffset::Regular(
620 RegularBitOffset {
621 offset: 4,
622 },
623 ),
624 bit_size: 1,
625 array: None,
626 enumm: None,
627 },
628 ],
629 },
630 FieldSet {
631 name: "Wmmonr",
632 extends: None,
633 description: Some(
634 "DCACHE write-miss monitor register.",
635 ),
636 bit_size: 32,
637 fields: &[
638 Field {
639 name: "wmissmon",
640 description: Some(
641 "cache write-miss monitor counter.",
642 ),
643 bit_offset: BitOffset::Regular(
644 RegularBitOffset {
645 offset: 0,
646 },
647 ),
648 bit_size: 16,
649 array: None,
650 enumm: None,
651 },
652 ],
653 },
654 ],
655 enums: &[],
656};
657