1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[Block {
5 name: "Dcmi",
6 extends: None,
7 description: Some("Digital camera interface"),
8 items: &[
9 BlockItem {
10 name: "cr",
11 description: Some("control register 1"),
12 array: None,
13 byte_offset: 0x0,
14 inner: BlockItemInner::Register(Register {
15 access: Access::ReadWrite,
16 bit_size: 32,
17 fieldset: Some("Cr"),
18 }),
19 },
20 BlockItem {
21 name: "sr",
22 description: Some("status register"),
23 array: None,
24 byte_offset: 0x4,
25 inner: BlockItemInner::Register(Register {
26 access: Access::Read,
27 bit_size: 32,
28 fieldset: Some("Sr"),
29 }),
30 },
31 BlockItem {
32 name: "ris",
33 description: Some("raw interrupt status register"),
34 array: None,
35 byte_offset: 0x8,
36 inner: BlockItemInner::Register(Register {
37 access: Access::Read,
38 bit_size: 32,
39 fieldset: Some("Ris"),
40 }),
41 },
42 BlockItem {
43 name: "ier",
44 description: Some("interrupt enable register"),
45 array: None,
46 byte_offset: 0xc,
47 inner: BlockItemInner::Register(Register {
48 access: Access::ReadWrite,
49 bit_size: 32,
50 fieldset: Some("Ier"),
51 }),
52 },
53 BlockItem {
54 name: "mis",
55 description: Some("masked interrupt status register"),
56 array: None,
57 byte_offset: 0x10,
58 inner: BlockItemInner::Register(Register {
59 access: Access::Read,
60 bit_size: 32,
61 fieldset: Some("Mis"),
62 }),
63 },
64 BlockItem {
65 name: "icr",
66 description: Some("interrupt clear register"),
67 array: None,
68 byte_offset: 0x14,
69 inner: BlockItemInner::Register(Register {
70 access: Access::Write,
71 bit_size: 32,
72 fieldset: Some("Icr"),
73 }),
74 },
75 BlockItem {
76 name: "escr",
77 description: Some("embedded synchronization code register"),
78 array: None,
79 byte_offset: 0x18,
80 inner: BlockItemInner::Register(Register {
81 access: Access::ReadWrite,
82 bit_size: 32,
83 fieldset: Some("Escr"),
84 }),
85 },
86 BlockItem {
87 name: "esur",
88 description: Some("embedded synchronization unmask register"),
89 array: None,
90 byte_offset: 0x1c,
91 inner: BlockItemInner::Register(Register {
92 access: Access::ReadWrite,
93 bit_size: 32,
94 fieldset: Some("Esur"),
95 }),
96 },
97 BlockItem {
98 name: "cwstrt",
99 description: Some("crop window start"),
100 array: None,
101 byte_offset: 0x20,
102 inner: BlockItemInner::Register(Register {
103 access: Access::ReadWrite,
104 bit_size: 32,
105 fieldset: Some("Cwstrt"),
106 }),
107 },
108 BlockItem {
109 name: "cwsize",
110 description: Some("crop window size"),
111 array: None,
112 byte_offset: 0x24,
113 inner: BlockItemInner::Register(Register {
114 access: Access::ReadWrite,
115 bit_size: 32,
116 fieldset: Some("Cwsize"),
117 }),
118 },
119 BlockItem {
120 name: "dr",
121 description: Some("data register"),
122 array: None,
123 byte_offset: 0x28,
124 inner: BlockItemInner::Register(Register {
125 access: Access::Read,
126 bit_size: 32,
127 fieldset: Some("Dr"),
128 }),
129 },
130 ],
131 }],
132 fieldsets: &[
133 FieldSet {
134 name: "Cr",
135 extends: None,
136 description: Some("control register 1"),
137 bit_size: 32,
138 fields: &[
139 Field {
140 name: "capture",
141 description: Some("Capture enable"),
142 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
143 bit_size: 1,
144 array: None,
145 enumm: None,
146 },
147 Field {
148 name: "cm",
149 description: Some("Capture mode"),
150 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
151 bit_size: 1,
152 array: None,
153 enumm: None,
154 },
155 Field {
156 name: "crop",
157 description: Some("Crop feature"),
158 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
159 bit_size: 1,
160 array: None,
161 enumm: None,
162 },
163 Field {
164 name: "jpeg",
165 description: Some("JPEG format"),
166 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
167 bit_size: 1,
168 array: None,
169 enumm: None,
170 },
171 Field {
172 name: "ess",
173 description: Some("Embedded synchronization select"),
174 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
175 bit_size: 1,
176 array: None,
177 enumm: None,
178 },
179 Field {
180 name: "pckpol",
181 description: Some("Pixel clock polarity"),
182 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
183 bit_size: 1,
184 array: None,
185 enumm: None,
186 },
187 Field {
188 name: "hspol",
189 description: Some("Horizontal synchronization polarity"),
190 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 6 }),
191 bit_size: 1,
192 array: None,
193 enumm: None,
194 },
195 Field {
196 name: "vspol",
197 description: Some("Vertical synchronization polarity"),
198 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 7 }),
199 bit_size: 1,
200 array: None,
201 enumm: None,
202 },
203 Field {
204 name: "fcrc",
205 description: Some("Frame capture rate control"),
206 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
207 bit_size: 2,
208 array: None,
209 enumm: None,
210 },
211 Field {
212 name: "edm",
213 description: Some("Extended data mode"),
214 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 10 }),
215 bit_size: 2,
216 array: None,
217 enumm: None,
218 },
219 Field {
220 name: "enable",
221 description: Some("DCMI enable"),
222 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }),
223 bit_size: 1,
224 array: None,
225 enumm: None,
226 },
227 ],
228 },
229 FieldSet {
230 name: "Cwsize",
231 extends: None,
232 description: Some("crop window size"),
233 bit_size: 32,
234 fields: &[
235 Field {
236 name: "capcnt",
237 description: Some("Capture count"),
238 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
239 bit_size: 14,
240 array: None,
241 enumm: None,
242 },
243 Field {
244 name: "vline",
245 description: Some("Vertical line count"),
246 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
247 bit_size: 14,
248 array: None,
249 enumm: None,
250 },
251 ],
252 },
253 FieldSet {
254 name: "Cwstrt",
255 extends: None,
256 description: Some("crop window start"),
257 bit_size: 32,
258 fields: &[
259 Field {
260 name: "hoffcnt",
261 description: Some("Horizontal offset count"),
262 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
263 bit_size: 14,
264 array: None,
265 enumm: None,
266 },
267 Field {
268 name: "vst",
269 description: Some("Vertical start line count"),
270 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
271 bit_size: 13,
272 array: None,
273 enumm: None,
274 },
275 ],
276 },
277 FieldSet {
278 name: "Dr",
279 extends: None,
280 description: Some("data register"),
281 bit_size: 32,
282 fields: &[
283 Field {
284 name: "byte0",
285 description: Some("Data byte 0"),
286 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
287 bit_size: 8,
288 array: None,
289 enumm: None,
290 },
291 Field {
292 name: "byte1",
293 description: Some("Data byte 1"),
294 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
295 bit_size: 8,
296 array: None,
297 enumm: None,
298 },
299 Field {
300 name: "byte2",
301 description: Some("Data byte 2"),
302 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
303 bit_size: 8,
304 array: None,
305 enumm: None,
306 },
307 Field {
308 name: "byte3",
309 description: Some("Data byte 3"),
310 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
311 bit_size: 8,
312 array: None,
313 enumm: None,
314 },
315 ],
316 },
317 FieldSet {
318 name: "Escr",
319 extends: None,
320 description: Some("embedded synchronization code register"),
321 bit_size: 32,
322 fields: &[
323 Field {
324 name: "fsc",
325 description: Some("Frame start delimiter code"),
326 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
327 bit_size: 8,
328 array: None,
329 enumm: None,
330 },
331 Field {
332 name: "lsc",
333 description: Some("Line start delimiter code"),
334 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
335 bit_size: 8,
336 array: None,
337 enumm: None,
338 },
339 Field {
340 name: "lec",
341 description: Some("Line end delimiter code"),
342 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
343 bit_size: 8,
344 array: None,
345 enumm: None,
346 },
347 Field {
348 name: "fec",
349 description: Some("Frame end delimiter code"),
350 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
351 bit_size: 8,
352 array: None,
353 enumm: None,
354 },
355 ],
356 },
357 FieldSet {
358 name: "Esur",
359 extends: None,
360 description: Some("embedded synchronization unmask register"),
361 bit_size: 32,
362 fields: &[
363 Field {
364 name: "fsu",
365 description: Some("Frame start delimiter unmask"),
366 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
367 bit_size: 8,
368 array: None,
369 enumm: None,
370 },
371 Field {
372 name: "lsu",
373 description: Some("Line start delimiter unmask"),
374 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
375 bit_size: 8,
376 array: None,
377 enumm: None,
378 },
379 Field {
380 name: "leu",
381 description: Some("Line end delimiter unmask"),
382 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
383 bit_size: 8,
384 array: None,
385 enumm: None,
386 },
387 Field {
388 name: "feu",
389 description: Some("Frame end delimiter unmask"),
390 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
391 bit_size: 8,
392 array: None,
393 enumm: None,
394 },
395 ],
396 },
397 FieldSet {
398 name: "Icr",
399 extends: None,
400 description: Some("interrupt clear register"),
401 bit_size: 32,
402 fields: &[
403 Field {
404 name: "frame_isc",
405 description: Some("Capture complete interrupt status clear"),
406 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
407 bit_size: 1,
408 array: None,
409 enumm: None,
410 },
411 Field {
412 name: "ovr_isc",
413 description: Some("Overrun interrupt status clear"),
414 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
415 bit_size: 1,
416 array: None,
417 enumm: None,
418 },
419 Field {
420 name: "err_isc",
421 description: Some("Synchronization error interrupt status clear"),
422 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
423 bit_size: 1,
424 array: None,
425 enumm: None,
426 },
427 Field {
428 name: "vsync_isc",
429 description: Some("Vertical synch interrupt status clear"),
430 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
431 bit_size: 1,
432 array: None,
433 enumm: None,
434 },
435 Field {
436 name: "line_isc",
437 description: Some("line interrupt status clear"),
438 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
439 bit_size: 1,
440 array: None,
441 enumm: None,
442 },
443 ],
444 },
445 FieldSet {
446 name: "Ier",
447 extends: None,
448 description: Some("interrupt enable register"),
449 bit_size: 32,
450 fields: &[
451 Field {
452 name: "frame_ie",
453 description: Some("Capture complete interrupt enable"),
454 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
455 bit_size: 1,
456 array: None,
457 enumm: None,
458 },
459 Field {
460 name: "ovr_ie",
461 description: Some("Overrun interrupt enable"),
462 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
463 bit_size: 1,
464 array: None,
465 enumm: None,
466 },
467 Field {
468 name: "err_ie",
469 description: Some("Synchronization error interrupt enable"),
470 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
471 bit_size: 1,
472 array: None,
473 enumm: None,
474 },
475 Field {
476 name: "vsync_ie",
477 description: Some("VSYNC interrupt enable"),
478 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
479 bit_size: 1,
480 array: None,
481 enumm: None,
482 },
483 Field {
484 name: "line_ie",
485 description: Some("Line interrupt enable"),
486 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
487 bit_size: 1,
488 array: None,
489 enumm: None,
490 },
491 ],
492 },
493 FieldSet {
494 name: "Mis",
495 extends: None,
496 description: Some("masked interrupt status register"),
497 bit_size: 32,
498 fields: &[
499 Field {
500 name: "frame_mis",
501 description: Some("Capture complete masked interrupt status"),
502 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
503 bit_size: 1,
504 array: None,
505 enumm: None,
506 },
507 Field {
508 name: "ovr_mis",
509 description: Some("Overrun masked interrupt status"),
510 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
511 bit_size: 1,
512 array: None,
513 enumm: None,
514 },
515 Field {
516 name: "err_mis",
517 description: Some("Synchronization error masked interrupt status"),
518 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
519 bit_size: 1,
520 array: None,
521 enumm: None,
522 },
523 Field {
524 name: "vsync_mis",
525 description: Some("VSYNC masked interrupt status"),
526 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
527 bit_size: 1,
528 array: None,
529 enumm: None,
530 },
531 Field {
532 name: "line_mis",
533 description: Some("Line masked interrupt status"),
534 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
535 bit_size: 1,
536 array: None,
537 enumm: None,
538 },
539 ],
540 },
541 FieldSet {
542 name: "Ris",
543 extends: None,
544 description: Some("raw interrupt status register"),
545 bit_size: 32,
546 fields: &[
547 Field {
548 name: "frame_ris",
549 description: Some("Capture complete raw interrupt status"),
550 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
551 bit_size: 1,
552 array: None,
553 enumm: None,
554 },
555 Field {
556 name: "ovr_ris",
557 description: Some("Overrun raw interrupt status"),
558 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
559 bit_size: 1,
560 array: None,
561 enumm: None,
562 },
563 Field {
564 name: "err_ris",
565 description: Some("Synchronization error raw interrupt status"),
566 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
567 bit_size: 1,
568 array: None,
569 enumm: None,
570 },
571 Field {
572 name: "vsync_ris",
573 description: Some("VSYNC raw interrupt status"),
574 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
575 bit_size: 1,
576 array: None,
577 enumm: None,
578 },
579 Field {
580 name: "line_ris",
581 description: Some("Line raw interrupt status"),
582 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
583 bit_size: 1,
584 array: None,
585 enumm: None,
586 },
587 ],
588 },
589 FieldSet {
590 name: "Sr",
591 extends: None,
592 description: Some("status register"),
593 bit_size: 32,
594 fields: &[
595 Field {
596 name: "hsync",
597 description: Some("HSYNC"),
598 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
599 bit_size: 1,
600 array: None,
601 enumm: None,
602 },
603 Field {
604 name: "vsync",
605 description: Some("VSYNC"),
606 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
607 bit_size: 1,
608 array: None,
609 enumm: None,
610 },
611 Field {
612 name: "fne",
613 description: Some("FIFO not empty"),
614 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
615 bit_size: 1,
616 array: None,
617 enumm: None,
618 },
619 ],
620 },
621 ],
622 enums: &[],
623};
624