1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[Block {
5 name: "Dma2d",
6 extends: None,
7 description: Some("DMA2D controller"),
8 items: &[
9 BlockItem {
10 name: "cr",
11 description: Some("control register"),
12 array: None,
13 byte_offset: 0x0,
14 inner: BlockItemInner::Register(Register {
15 access: Access::ReadWrite,
16 bit_size: 32,
17 fieldset: Some("Cr"),
18 }),
19 },
20 BlockItem {
21 name: "isr",
22 description: Some("Interrupt Status Register"),
23 array: None,
24 byte_offset: 0x4,
25 inner: BlockItemInner::Register(Register {
26 access: Access::Read,
27 bit_size: 32,
28 fieldset: Some("Isr"),
29 }),
30 },
31 BlockItem {
32 name: "ifcr",
33 description: Some("interrupt flag clear register"),
34 array: None,
35 byte_offset: 0x8,
36 inner: BlockItemInner::Register(Register {
37 access: Access::ReadWrite,
38 bit_size: 32,
39 fieldset: Some("Ifcr"),
40 }),
41 },
42 BlockItem {
43 name: "fgmar",
44 description: Some("foreground memory address register"),
45 array: None,
46 byte_offset: 0xc,
47 inner: BlockItemInner::Register(Register {
48 access: Access::ReadWrite,
49 bit_size: 32,
50 fieldset: Some("Fgmar"),
51 }),
52 },
53 BlockItem {
54 name: "fgor",
55 description: Some("foreground offset register"),
56 array: None,
57 byte_offset: 0x10,
58 inner: BlockItemInner::Register(Register {
59 access: Access::ReadWrite,
60 bit_size: 32,
61 fieldset: Some("Fgor"),
62 }),
63 },
64 BlockItem {
65 name: "bgmar",
66 description: Some("background memory address register"),
67 array: None,
68 byte_offset: 0x14,
69 inner: BlockItemInner::Register(Register {
70 access: Access::ReadWrite,
71 bit_size: 32,
72 fieldset: Some("Bgmar"),
73 }),
74 },
75 BlockItem {
76 name: "bgor",
77 description: Some("background offset register"),
78 array: None,
79 byte_offset: 0x18,
80 inner: BlockItemInner::Register(Register {
81 access: Access::ReadWrite,
82 bit_size: 32,
83 fieldset: Some("Bgor"),
84 }),
85 },
86 BlockItem {
87 name: "fgpfccr",
88 description: Some("foreground PFC control register"),
89 array: None,
90 byte_offset: 0x1c,
91 inner: BlockItemInner::Register(Register {
92 access: Access::ReadWrite,
93 bit_size: 32,
94 fieldset: Some("Fgpfccr"),
95 }),
96 },
97 BlockItem {
98 name: "fgcolr",
99 description: Some("foreground color register"),
100 array: None,
101 byte_offset: 0x20,
102 inner: BlockItemInner::Register(Register {
103 access: Access::ReadWrite,
104 bit_size: 32,
105 fieldset: Some("Fgcolr"),
106 }),
107 },
108 BlockItem {
109 name: "bgpfccr",
110 description: Some("background PFC control register"),
111 array: None,
112 byte_offset: 0x24,
113 inner: BlockItemInner::Register(Register {
114 access: Access::ReadWrite,
115 bit_size: 32,
116 fieldset: Some("Bgpfccr"),
117 }),
118 },
119 BlockItem {
120 name: "bgcolr",
121 description: Some("background color register"),
122 array: None,
123 byte_offset: 0x28,
124 inner: BlockItemInner::Register(Register {
125 access: Access::ReadWrite,
126 bit_size: 32,
127 fieldset: Some("Bgcolr"),
128 }),
129 },
130 BlockItem {
131 name: "fgcmar",
132 description: Some("foreground CLUT memory address register"),
133 array: None,
134 byte_offset: 0x2c,
135 inner: BlockItemInner::Register(Register {
136 access: Access::ReadWrite,
137 bit_size: 32,
138 fieldset: Some("Fgcmar"),
139 }),
140 },
141 BlockItem {
142 name: "bgcmar",
143 description: Some("background CLUT memory address register"),
144 array: None,
145 byte_offset: 0x30,
146 inner: BlockItemInner::Register(Register {
147 access: Access::ReadWrite,
148 bit_size: 32,
149 fieldset: Some("Bgcmar"),
150 }),
151 },
152 BlockItem {
153 name: "opfccr",
154 description: Some("output PFC control register"),
155 array: None,
156 byte_offset: 0x34,
157 inner: BlockItemInner::Register(Register {
158 access: Access::ReadWrite,
159 bit_size: 32,
160 fieldset: Some("Opfccr"),
161 }),
162 },
163 BlockItem {
164 name: "ocolr",
165 description: Some("output color register"),
166 array: None,
167 byte_offset: 0x38,
168 inner: BlockItemInner::Register(Register {
169 access: Access::ReadWrite,
170 bit_size: 32,
171 fieldset: Some("Ocolr"),
172 }),
173 },
174 BlockItem {
175 name: "omar",
176 description: Some("output memory address register"),
177 array: None,
178 byte_offset: 0x3c,
179 inner: BlockItemInner::Register(Register {
180 access: Access::ReadWrite,
181 bit_size: 32,
182 fieldset: Some("Omar"),
183 }),
184 },
185 BlockItem {
186 name: "oor",
187 description: Some("output offset register"),
188 array: None,
189 byte_offset: 0x40,
190 inner: BlockItemInner::Register(Register {
191 access: Access::ReadWrite,
192 bit_size: 32,
193 fieldset: Some("Oor"),
194 }),
195 },
196 BlockItem {
197 name: "nlr",
198 description: Some("number of line register"),
199 array: None,
200 byte_offset: 0x44,
201 inner: BlockItemInner::Register(Register {
202 access: Access::ReadWrite,
203 bit_size: 32,
204 fieldset: Some("Nlr"),
205 }),
206 },
207 BlockItem {
208 name: "lwr",
209 description: Some("line watermark register"),
210 array: None,
211 byte_offset: 0x48,
212 inner: BlockItemInner::Register(Register {
213 access: Access::ReadWrite,
214 bit_size: 32,
215 fieldset: Some("Lwr"),
216 }),
217 },
218 BlockItem {
219 name: "amtcr",
220 description: Some("AHB master timer configuration register"),
221 array: None,
222 byte_offset: 0x4c,
223 inner: BlockItemInner::Register(Register {
224 access: Access::ReadWrite,
225 bit_size: 32,
226 fieldset: Some("Amtcr"),
227 }),
228 },
229 BlockItem {
230 name: "fgclut",
231 description: Some("FGCLUT"),
232 array: None,
233 byte_offset: 0x400,
234 inner: BlockItemInner::Register(Register {
235 access: Access::ReadWrite,
236 bit_size: 32,
237 fieldset: Some("Fgclut"),
238 }),
239 },
240 BlockItem {
241 name: "bgclut",
242 description: Some("BGCLUT"),
243 array: None,
244 byte_offset: 0x800,
245 inner: BlockItemInner::Register(Register {
246 access: Access::ReadWrite,
247 bit_size: 32,
248 fieldset: Some("Bgclut"),
249 }),
250 },
251 ],
252 }],
253 fieldsets: &[
254 FieldSet {
255 name: "Amtcr",
256 extends: None,
257 description: Some("AHB master timer configuration register"),
258 bit_size: 32,
259 fields: &[
260 Field {
261 name: "en",
262 description: Some("Enable"),
263 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
264 bit_size: 1,
265 array: None,
266 enumm: None,
267 },
268 Field {
269 name: "dt",
270 description: Some("Dead Time"),
271 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
272 bit_size: 8,
273 array: None,
274 enumm: None,
275 },
276 ],
277 },
278 FieldSet {
279 name: "Bgclut",
280 extends: None,
281 description: Some("BGCLUT"),
282 bit_size: 32,
283 fields: &[
284 Field {
285 name: "blue",
286 description: Some("BLUE"),
287 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
288 bit_size: 8,
289 array: None,
290 enumm: None,
291 },
292 Field {
293 name: "green",
294 description: Some("GREEN"),
295 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
296 bit_size: 8,
297 array: None,
298 enumm: None,
299 },
300 Field {
301 name: "red",
302 description: Some("RED"),
303 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
304 bit_size: 8,
305 array: None,
306 enumm: None,
307 },
308 Field {
309 name: "aplha",
310 description: Some("APLHA"),
311 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
312 bit_size: 8,
313 array: None,
314 enumm: None,
315 },
316 ],
317 },
318 FieldSet {
319 name: "Bgcmar",
320 extends: None,
321 description: Some("background CLUT memory address register"),
322 bit_size: 32,
323 fields: &[Field {
324 name: "ma",
325 description: Some("Memory address"),
326 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
327 bit_size: 32,
328 array: None,
329 enumm: None,
330 }],
331 },
332 FieldSet {
333 name: "Bgcolr",
334 extends: None,
335 description: Some("background color register"),
336 bit_size: 32,
337 fields: &[
338 Field {
339 name: "blue",
340 description: Some("Blue Value"),
341 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
342 bit_size: 8,
343 array: None,
344 enumm: None,
345 },
346 Field {
347 name: "green",
348 description: Some("Green Value"),
349 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
350 bit_size: 8,
351 array: None,
352 enumm: None,
353 },
354 Field {
355 name: "red",
356 description: Some("Red Value"),
357 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
358 bit_size: 8,
359 array: None,
360 enumm: None,
361 },
362 ],
363 },
364 FieldSet {
365 name: "Bgmar",
366 extends: None,
367 description: Some("background memory address register"),
368 bit_size: 32,
369 fields: &[Field {
370 name: "ma",
371 description: Some("Memory address"),
372 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
373 bit_size: 32,
374 array: None,
375 enumm: None,
376 }],
377 },
378 FieldSet {
379 name: "Bgor",
380 extends: None,
381 description: Some("background offset register"),
382 bit_size: 32,
383 fields: &[Field {
384 name: "lo",
385 description: Some("Line offset"),
386 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
387 bit_size: 14,
388 array: None,
389 enumm: None,
390 }],
391 },
392 FieldSet {
393 name: "Bgpfccr",
394 extends: None,
395 description: Some("background PFC control register"),
396 bit_size: 32,
397 fields: &[
398 Field {
399 name: "cm",
400 description: Some("Color mode"),
401 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
402 bit_size: 4,
403 array: None,
404 enumm: Some("BgpfccrCm"),
405 },
406 Field {
407 name: "ccm",
408 description: Some("CLUT Color mode"),
409 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
410 bit_size: 1,
411 array: None,
412 enumm: Some("BgpfccrCcm"),
413 },
414 Field {
415 name: "start",
416 description: Some("Start"),
417 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
418 bit_size: 1,
419 array: None,
420 enumm: Some("BgpfccrStart"),
421 },
422 Field {
423 name: "cs",
424 description: Some("CLUT size"),
425 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
426 bit_size: 8,
427 array: None,
428 enumm: None,
429 },
430 Field {
431 name: "am",
432 description: Some("Alpha mode"),
433 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
434 bit_size: 2,
435 array: None,
436 enumm: Some("BgpfccrAm"),
437 },
438 Field {
439 name: "alpha",
440 description: Some("Alpha value"),
441 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
442 bit_size: 8,
443 array: None,
444 enumm: None,
445 },
446 ],
447 },
448 FieldSet {
449 name: "Cr",
450 extends: None,
451 description: Some("control register"),
452 bit_size: 32,
453 fields: &[
454 Field {
455 name: "start",
456 description: Some("Start"),
457 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
458 bit_size: 1,
459 array: None,
460 enumm: Some("CrStart"),
461 },
462 Field {
463 name: "susp",
464 description: Some("Suspend"),
465 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
466 bit_size: 1,
467 array: None,
468 enumm: None,
469 },
470 Field {
471 name: "abort",
472 description: Some("Abort"),
473 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
474 bit_size: 1,
475 array: None,
476 enumm: Some("Abort"),
477 },
478 Field {
479 name: "teie",
480 description: Some("Transfer error interrupt enable"),
481 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
482 bit_size: 1,
483 array: None,
484 enumm: None,
485 },
486 Field {
487 name: "tcie",
488 description: Some("Transfer complete interrupt enable"),
489 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
490 bit_size: 1,
491 array: None,
492 enumm: None,
493 },
494 Field {
495 name: "twie",
496 description: Some("Transfer watermark interrupt enable"),
497 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 10 }),
498 bit_size: 1,
499 array: None,
500 enumm: None,
501 },
502 Field {
503 name: "caeie",
504 description: Some("CLUT access error interrupt enable"),
505 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 11 }),
506 bit_size: 1,
507 array: None,
508 enumm: None,
509 },
510 Field {
511 name: "ctcie",
512 description: Some("CLUT transfer complete interrupt enable"),
513 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
514 bit_size: 1,
515 array: None,
516 enumm: None,
517 },
518 Field {
519 name: "ceie",
520 description: Some("Configuration Error Interrupt Enable"),
521 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 13 }),
522 bit_size: 1,
523 array: None,
524 enumm: None,
525 },
526 Field {
527 name: "mode",
528 description: Some("DMA2D mode"),
529 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
530 bit_size: 2,
531 array: None,
532 enumm: Some("Mode"),
533 },
534 ],
535 },
536 FieldSet {
537 name: "Fgclut",
538 extends: None,
539 description: Some("FGCLUT"),
540 bit_size: 32,
541 fields: &[
542 Field {
543 name: "blue",
544 description: Some("BLUE"),
545 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
546 bit_size: 8,
547 array: None,
548 enumm: None,
549 },
550 Field {
551 name: "green",
552 description: Some("GREEN"),
553 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
554 bit_size: 8,
555 array: None,
556 enumm: None,
557 },
558 Field {
559 name: "red",
560 description: Some("RED"),
561 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
562 bit_size: 8,
563 array: None,
564 enumm: None,
565 },
566 Field {
567 name: "aplha",
568 description: Some("APLHA"),
569 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
570 bit_size: 8,
571 array: None,
572 enumm: None,
573 },
574 ],
575 },
576 FieldSet {
577 name: "Fgcmar",
578 extends: None,
579 description: Some("foreground CLUT memory address register"),
580 bit_size: 32,
581 fields: &[Field {
582 name: "ma",
583 description: Some("Memory Address"),
584 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
585 bit_size: 32,
586 array: None,
587 enumm: None,
588 }],
589 },
590 FieldSet {
591 name: "Fgcolr",
592 extends: None,
593 description: Some("foreground color register"),
594 bit_size: 32,
595 fields: &[
596 Field {
597 name: "blue",
598 description: Some("Blue Value"),
599 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
600 bit_size: 8,
601 array: None,
602 enumm: None,
603 },
604 Field {
605 name: "green",
606 description: Some("Green Value"),
607 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
608 bit_size: 8,
609 array: None,
610 enumm: None,
611 },
612 Field {
613 name: "red",
614 description: Some("Red Value"),
615 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
616 bit_size: 8,
617 array: None,
618 enumm: None,
619 },
620 ],
621 },
622 FieldSet {
623 name: "Fgmar",
624 extends: None,
625 description: Some("foreground memory address register"),
626 bit_size: 32,
627 fields: &[Field {
628 name: "ma",
629 description: Some("Memory address"),
630 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
631 bit_size: 32,
632 array: None,
633 enumm: None,
634 }],
635 },
636 FieldSet {
637 name: "Fgor",
638 extends: None,
639 description: Some("foreground offset register"),
640 bit_size: 32,
641 fields: &[Field {
642 name: "lo",
643 description: Some("Line offset"),
644 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
645 bit_size: 14,
646 array: None,
647 enumm: None,
648 }],
649 },
650 FieldSet {
651 name: "Fgpfccr",
652 extends: None,
653 description: Some("foreground PFC control register"),
654 bit_size: 32,
655 fields: &[
656 Field {
657 name: "cm",
658 description: Some("Color mode"),
659 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
660 bit_size: 4,
661 array: None,
662 enumm: Some("FgpfccrCm"),
663 },
664 Field {
665 name: "ccm",
666 description: Some("CLUT color mode"),
667 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
668 bit_size: 1,
669 array: None,
670 enumm: Some("FgpfccrCcm"),
671 },
672 Field {
673 name: "start",
674 description: Some("Start"),
675 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
676 bit_size: 1,
677 array: None,
678 enumm: Some("FgpfccrStart"),
679 },
680 Field {
681 name: "cs",
682 description: Some("CLUT size"),
683 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
684 bit_size: 8,
685 array: None,
686 enumm: None,
687 },
688 Field {
689 name: "am",
690 description: Some("Alpha mode"),
691 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
692 bit_size: 2,
693 array: None,
694 enumm: Some("FgpfccrAm"),
695 },
696 Field {
697 name: "alpha",
698 description: Some("Alpha value"),
699 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
700 bit_size: 8,
701 array: None,
702 enumm: None,
703 },
704 ],
705 },
706 FieldSet {
707 name: "Ifcr",
708 extends: None,
709 description: Some("interrupt flag clear register"),
710 bit_size: 32,
711 fields: &[
712 Field {
713 name: "cteif",
714 description: Some("Clear Transfer error interrupt flag"),
715 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
716 bit_size: 1,
717 array: None,
718 enumm: Some("Cteif"),
719 },
720 Field {
721 name: "ctcif",
722 description: Some("Clear transfer complete interrupt flag"),
723 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
724 bit_size: 1,
725 array: None,
726 enumm: Some("Ctcif"),
727 },
728 Field {
729 name: "ctwif",
730 description: Some("Clear transfer watermark interrupt flag"),
731 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
732 bit_size: 1,
733 array: None,
734 enumm: Some("Ctwif"),
735 },
736 Field {
737 name: "caecif",
738 description: Some("Clear CLUT access error interrupt flag"),
739 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
740 bit_size: 1,
741 array: None,
742 enumm: Some("Caecif"),
743 },
744 Field {
745 name: "cctcif",
746 description: Some("Clear CLUT transfer complete interrupt flag"),
747 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
748 bit_size: 1,
749 array: None,
750 enumm: Some("Cctcif"),
751 },
752 Field {
753 name: "cceif",
754 description: Some("Clear configuration error interrupt flag"),
755 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
756 bit_size: 1,
757 array: None,
758 enumm: Some("Cceif"),
759 },
760 ],
761 },
762 FieldSet {
763 name: "Isr",
764 extends: None,
765 description: Some("Interrupt Status Register"),
766 bit_size: 32,
767 fields: &[
768 Field {
769 name: "teif",
770 description: Some("Transfer error interrupt flag"),
771 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
772 bit_size: 1,
773 array: None,
774 enumm: None,
775 },
776 Field {
777 name: "tcif",
778 description: Some("Transfer complete interrupt flag"),
779 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
780 bit_size: 1,
781 array: None,
782 enumm: None,
783 },
784 Field {
785 name: "twif",
786 description: Some("Transfer watermark interrupt flag"),
787 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
788 bit_size: 1,
789 array: None,
790 enumm: None,
791 },
792 Field {
793 name: "caeif",
794 description: Some("CLUT access error interrupt flag"),
795 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
796 bit_size: 1,
797 array: None,
798 enumm: None,
799 },
800 Field {
801 name: "ctcif",
802 description: Some("CLUT transfer complete interrupt flag"),
803 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
804 bit_size: 1,
805 array: None,
806 enumm: None,
807 },
808 Field {
809 name: "ceif",
810 description: Some("Configuration error interrupt flag"),
811 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
812 bit_size: 1,
813 array: None,
814 enumm: None,
815 },
816 ],
817 },
818 FieldSet {
819 name: "Lwr",
820 extends: None,
821 description: Some("line watermark register"),
822 bit_size: 32,
823 fields: &[Field {
824 name: "lw",
825 description: Some("Line watermark"),
826 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
827 bit_size: 16,
828 array: None,
829 enumm: None,
830 }],
831 },
832 FieldSet {
833 name: "Nlr",
834 extends: None,
835 description: Some("number of line register"),
836 bit_size: 32,
837 fields: &[
838 Field {
839 name: "nl",
840 description: Some("Number of lines"),
841 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
842 bit_size: 16,
843 array: None,
844 enumm: None,
845 },
846 Field {
847 name: "pl",
848 description: Some("Pixel per lines"),
849 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
850 bit_size: 14,
851 array: None,
852 enumm: None,
853 },
854 ],
855 },
856 FieldSet {
857 name: "Ocolr",
858 extends: None,
859 description: Some("output color register"),
860 bit_size: 32,
861 fields: &[
862 Field {
863 name: "blue",
864 description: Some("Blue Value"),
865 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
866 bit_size: 8,
867 array: None,
868 enumm: None,
869 },
870 Field {
871 name: "green",
872 description: Some("Green Value"),
873 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
874 bit_size: 8,
875 array: None,
876 enumm: None,
877 },
878 Field {
879 name: "red",
880 description: Some("Red Value"),
881 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
882 bit_size: 8,
883 array: None,
884 enumm: None,
885 },
886 Field {
887 name: "aplha",
888 description: Some("Alpha Channel Value"),
889 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
890 bit_size: 8,
891 array: None,
892 enumm: None,
893 },
894 ],
895 },
896 FieldSet {
897 name: "Omar",
898 extends: None,
899 description: Some("output memory address register"),
900 bit_size: 32,
901 fields: &[Field {
902 name: "ma",
903 description: Some("Memory Address"),
904 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
905 bit_size: 32,
906 array: None,
907 enumm: None,
908 }],
909 },
910 FieldSet {
911 name: "Oor",
912 extends: None,
913 description: Some("output offset register"),
914 bit_size: 32,
915 fields: &[Field {
916 name: "lo",
917 description: Some("Line Offset"),
918 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
919 bit_size: 14,
920 array: None,
921 enumm: None,
922 }],
923 },
924 FieldSet {
925 name: "Opfccr",
926 extends: None,
927 description: Some("output PFC control register"),
928 bit_size: 32,
929 fields: &[Field {
930 name: "cm",
931 description: Some("Color mode"),
932 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
933 bit_size: 3,
934 array: None,
935 enumm: Some("OpfccrCm"),
936 }],
937 },
938 ],
939 enums: &[
940 Enum {
941 name: "Abort",
942 description: None,
943 bit_size: 1,
944 variants: &[EnumVariant {
945 name: "ABORT_REQUEST",
946 description: Some("Transfer abort requested"),
947 value: 1,
948 }],
949 },
950 Enum {
951 name: "BgpfccrAm",
952 description: None,
953 bit_size: 2,
954 variants: &[
955 EnumVariant {
956 name: "NO_MODIFY",
957 description: Some("No modification of alpha channel"),
958 value: 0,
959 },
960 EnumVariant {
961 name: "REPLACE",
962 description: Some("Replace with value in ALPHA[7:0]"),
963 value: 1,
964 },
965 EnumVariant {
966 name: "MULTIPLY",
967 description: Some("Multiply with value in ALPHA[7:0]"),
968 value: 2,
969 },
970 ],
971 },
972 Enum {
973 name: "BgpfccrCcm",
974 description: None,
975 bit_size: 1,
976 variants: &[
977 EnumVariant {
978 name: "ARGB8888",
979 description: Some("CLUT color format ARGB8888"),
980 value: 0,
981 },
982 EnumVariant {
983 name: "RGB888",
984 description: Some("CLUT color format RGB888"),
985 value: 1,
986 },
987 ],
988 },
989 Enum {
990 name: "BgpfccrCm",
991 description: None,
992 bit_size: 4,
993 variants: &[
994 EnumVariant {
995 name: "ARGB8888",
996 description: Some("Color mode ARGB8888"),
997 value: 0,
998 },
999 EnumVariant {
1000 name: "RGB888",
1001 description: Some("Color mode RGB888"),
1002 value: 1,
1003 },
1004 EnumVariant {
1005 name: "RGB565",
1006 description: Some("Color mode RGB565"),
1007 value: 2,
1008 },
1009 EnumVariant {
1010 name: "ARGB1555",
1011 description: Some("Color mode ARGB1555"),
1012 value: 3,
1013 },
1014 EnumVariant {
1015 name: "ARGB4444",
1016 description: Some("Color mode ARGB4444"),
1017 value: 4,
1018 },
1019 EnumVariant {
1020 name: "L8",
1021 description: Some("Color mode L8"),
1022 value: 5,
1023 },
1024 EnumVariant {
1025 name: "AL44",
1026 description: Some("Color mode AL44"),
1027 value: 6,
1028 },
1029 EnumVariant {
1030 name: "AL88",
1031 description: Some("Color mode AL88"),
1032 value: 7,
1033 },
1034 EnumVariant {
1035 name: "L4",
1036 description: Some("Color mode L4"),
1037 value: 8,
1038 },
1039 EnumVariant {
1040 name: "A8",
1041 description: Some("Color mode A8"),
1042 value: 9,
1043 },
1044 EnumVariant {
1045 name: "A4",
1046 description: Some("Color mode A4"),
1047 value: 10,
1048 },
1049 ],
1050 },
1051 Enum {
1052 name: "BgpfccrStart",
1053 description: None,
1054 bit_size: 1,
1055 variants: &[EnumVariant {
1056 name: "START",
1057 description: Some("Start the automatic loading of the CLUT"),
1058 value: 1,
1059 }],
1060 },
1061 Enum {
1062 name: "Caecif",
1063 description: None,
1064 bit_size: 1,
1065 variants: &[EnumVariant {
1066 name: "CLEAR",
1067 description: Some("Clear the CAEIF flag in the ISR register"),
1068 value: 1,
1069 }],
1070 },
1071 Enum {
1072 name: "Cceif",
1073 description: None,
1074 bit_size: 1,
1075 variants: &[EnumVariant {
1076 name: "CLEAR",
1077 description: Some("Clear the CEIF flag in the ISR register"),
1078 value: 1,
1079 }],
1080 },
1081 Enum {
1082 name: "Cctcif",
1083 description: None,
1084 bit_size: 1,
1085 variants: &[EnumVariant {
1086 name: "CLEAR",
1087 description: Some("Clear the CTCIF flag in the ISR register"),
1088 value: 1,
1089 }],
1090 },
1091 Enum {
1092 name: "CrStart",
1093 description: None,
1094 bit_size: 1,
1095 variants: &[EnumVariant {
1096 name: "START",
1097 description: Some("Launch the DMA2D"),
1098 value: 1,
1099 }],
1100 },
1101 Enum {
1102 name: "Ctcif",
1103 description: None,
1104 bit_size: 1,
1105 variants: &[EnumVariant {
1106 name: "CLEAR",
1107 description: Some("Clear the TCIF flag in the ISR register"),
1108 value: 1,
1109 }],
1110 },
1111 Enum {
1112 name: "Cteif",
1113 description: None,
1114 bit_size: 1,
1115 variants: &[EnumVariant {
1116 name: "CLEAR",
1117 description: Some("Clear the TEIF flag in the ISR register"),
1118 value: 1,
1119 }],
1120 },
1121 Enum {
1122 name: "Ctwif",
1123 description: None,
1124 bit_size: 1,
1125 variants: &[EnumVariant {
1126 name: "CLEAR",
1127 description: Some("Clear the TWIF flag in the ISR register"),
1128 value: 1,
1129 }],
1130 },
1131 Enum {
1132 name: "FgpfccrAm",
1133 description: None,
1134 bit_size: 2,
1135 variants: &[
1136 EnumVariant {
1137 name: "NO_MODIFY",
1138 description: Some("No modification of alpha channel"),
1139 value: 0,
1140 },
1141 EnumVariant {
1142 name: "REPLACE",
1143 description: Some("Replace with value in ALPHA[7:0]"),
1144 value: 1,
1145 },
1146 EnumVariant {
1147 name: "MULTIPLY",
1148 description: Some("Multiply with value in ALPHA[7:0]"),
1149 value: 2,
1150 },
1151 ],
1152 },
1153 Enum {
1154 name: "FgpfccrCcm",
1155 description: None,
1156 bit_size: 1,
1157 variants: &[
1158 EnumVariant {
1159 name: "ARGB8888",
1160 description: Some("CLUT color format ARGB8888"),
1161 value: 0,
1162 },
1163 EnumVariant {
1164 name: "RGB888",
1165 description: Some("CLUT color format RGB888"),
1166 value: 1,
1167 },
1168 ],
1169 },
1170 Enum {
1171 name: "FgpfccrCm",
1172 description: None,
1173 bit_size: 4,
1174 variants: &[
1175 EnumVariant {
1176 name: "ARGB8888",
1177 description: Some("Color mode ARGB8888"),
1178 value: 0,
1179 },
1180 EnumVariant {
1181 name: "RGB888",
1182 description: Some("Color mode RGB888"),
1183 value: 1,
1184 },
1185 EnumVariant {
1186 name: "RGB565",
1187 description: Some("Color mode RGB565"),
1188 value: 2,
1189 },
1190 EnumVariant {
1191 name: "ARGB1555",
1192 description: Some("Color mode ARGB1555"),
1193 value: 3,
1194 },
1195 EnumVariant {
1196 name: "ARGB4444",
1197 description: Some("Color mode ARGB4444"),
1198 value: 4,
1199 },
1200 EnumVariant {
1201 name: "L8",
1202 description: Some("Color mode L8"),
1203 value: 5,
1204 },
1205 EnumVariant {
1206 name: "AL44",
1207 description: Some("Color mode AL44"),
1208 value: 6,
1209 },
1210 EnumVariant {
1211 name: "AL88",
1212 description: Some("Color mode AL88"),
1213 value: 7,
1214 },
1215 EnumVariant {
1216 name: "L4",
1217 description: Some("Color mode L4"),
1218 value: 8,
1219 },
1220 EnumVariant {
1221 name: "A8",
1222 description: Some("Color mode A8"),
1223 value: 9,
1224 },
1225 EnumVariant {
1226 name: "A4",
1227 description: Some("Color mode A4"),
1228 value: 10,
1229 },
1230 ],
1231 },
1232 Enum {
1233 name: "FgpfccrStart",
1234 description: None,
1235 bit_size: 1,
1236 variants: &[EnumVariant {
1237 name: "START",
1238 description: Some("Start the automatic loading of the CLUT"),
1239 value: 1,
1240 }],
1241 },
1242 Enum {
1243 name: "Mode",
1244 description: None,
1245 bit_size: 2,
1246 variants: &[
1247 EnumVariant {
1248 name: "MEMORY_TO_MEMORY",
1249 description: Some("Memory-to-memory (FG fetch only)"),
1250 value: 0,
1251 },
1252 EnumVariant {
1253 name: "MEMORY_TO_MEMORY_PFC",
1254 description: Some("Memory-to-memory with PFC (FG fetch only with FG PFC active)"),
1255 value: 1,
1256 },
1257 EnumVariant {
1258 name: "MEMORY_TO_MEMORY_PFCBLENDING",
1259 description: Some("Memory-to-memory with blending (FG and BG fetch with PFC and blending)"),
1260 value: 2,
1261 },
1262 EnumVariant {
1263 name: "REGISTER_TO_MEMORY",
1264 description: Some("Register-to-memory"),
1265 value: 3,
1266 },
1267 ],
1268 },
1269 Enum {
1270 name: "OpfccrCm",
1271 description: None,
1272 bit_size: 3,
1273 variants: &[
1274 EnumVariant {
1275 name: "ARGB8888",
1276 description: Some("ARGB8888"),
1277 value: 0,
1278 },
1279 EnumVariant {
1280 name: "RGB888",
1281 description: Some("RGB888"),
1282 value: 1,
1283 },
1284 EnumVariant {
1285 name: "RGB565",
1286 description: Some("RGB565"),
1287 value: 2,
1288 },
1289 EnumVariant {
1290 name: "ARGB1555",
1291 description: Some("ARGB1555"),
1292 value: 3,
1293 },
1294 EnumVariant {
1295 name: "ARGB4444",
1296 description: Some("ARGB4444"),
1297 value: 4,
1298 },
1299 ],
1300 },
1301 ],
1302};
1303