dsihost_u5.rs source code [crates/stm32_metapac/src/registers/dsihost_u5.rs]

1
2	use crate::metadata::ir::*;
3	pub(crate) static REGISTERS: IR = IR {
4	blocks: &[
5	Block {
6	name: "Dsihost",
7	extends: None,
8	description: Some(
9	"DSI Host.",
10	),
11	items: &[
12	BlockItem {
13	name: "vr",
14	description: Some(
15	"DSI Host version register.",
16	),
17	array: None,
18	byte_offset: `0x0`,
19	inner: BlockItemInner::Register(
20	Register {
21	access: Access::ReadWrite,
22	bit_size: `32`,
23	fieldset: Some(
24	"Vr",
25	),
26	},
27	),
28	},
29	BlockItem {
30	name: "cr",
31	description: Some(
32	"DSI Host control register.",
33	),
34	array: None,
35	byte_offset: `0x4`,
36	inner: BlockItemInner::Register(
37	Register {
38	access: Access::ReadWrite,
39	bit_size: `32`,
40	fieldset: Some(
41	"Cr",
42	),
43	},
44	),
45	},
46	BlockItem {
47	name: "ccr",
48	description: Some(
49	"DSI Host clock control register.",
50	),
51	array: None,
52	byte_offset: `0x8`,
53	inner: BlockItemInner::Register(
54	Register {
55	access: Access::ReadWrite,
56	bit_size: `32`,
57	fieldset: Some(
58	"Ccr",
59	),
60	},
61	),
62	},
63	BlockItem {
64	name: "lvcidr",
65	description: Some(
66	"DSI Host LTDC VCID register.",
67	),
68	array: None,
69	byte_offset: `0xc`,
70	inner: BlockItemInner::Register(
71	Register {
72	access: Access::ReadWrite,
73	bit_size: `32`,
74	fieldset: Some(
75	"Lvcidr",
76	),
77	},
78	),
79	},
80	BlockItem {
81	name: "lcolcr",
82	description: Some(
83	"DSI Host LTDC color coding register.",
84	),
85	array: None,
86	byte_offset: `0x10`,
87	inner: BlockItemInner::Register(
88	Register {
89	access: Access::ReadWrite,
90	bit_size: `32`,
91	fieldset: Some(
92	"Lcolcr",
93	),
94	},
95	),
96	},
97	BlockItem {
98	name: "lpcr",
99	description: Some(
100	"DSI Host LTDC polarity configuration register.",
101	),
102	array: None,
103	byte_offset: `0x14`,
104	inner: BlockItemInner::Register(
105	Register {
106	access: Access::ReadWrite,
107	bit_size: `32`,
108	fieldset: Some(
109	"Lpcr",
110	),
111	},
112	),
113	},
114	BlockItem {
115	name: "lpmcr",
116	description: Some(
117	"DSI Host low-power mode configuration register.",
118	),
119	array: None,
120	byte_offset: `0x18`,
121	inner: BlockItemInner::Register(
122	Register {
123	access: Access::ReadWrite,
124	bit_size: `32`,
125	fieldset: Some(
126	"Lpmcr",
127	),
128	},
129	),
130	},
131	BlockItem {
132	name: "pcr",
133	description: Some(
134	"DSI Host protocol configuration register.",
135	),
136	array: None,
137	byte_offset: `0x2c`,
138	inner: BlockItemInner::Register(
139	Register {
140	access: Access::ReadWrite,
141	bit_size: `32`,
142	fieldset: Some(
143	"Pcr",
144	),
145	},
146	),
147	},
148	BlockItem {
149	name: "gvcidr",
150	description: Some(
151	"DSI Host generic VCID register.",
152	),
153	array: None,
154	byte_offset: `0x30`,
155	inner: BlockItemInner::Register(
156	Register {
157	access: Access::ReadWrite,
158	bit_size: `32`,
159	fieldset: Some(
160	"Gvcidr",
161	),
162	},
163	),
164	},
165	BlockItem {
166	name: "mcr",
167	description: Some(
168	"DSI Host mode configuration register.",
169	),
170	array: None,
171	byte_offset: `0x34`,
172	inner: BlockItemInner::Register(
173	Register {
174	access: Access::ReadWrite,
175	bit_size: `32`,
176	fieldset: Some(
177	"Mcr",
178	),
179	},
180	),
181	},
182	BlockItem {
183	name: "vmcr",
184	description: Some(
185	"DSI Host video mode configuration register.",
186	),
187	array: None,
188	byte_offset: `0x38`,
189	inner: BlockItemInner::Register(
190	Register {
191	access: Access::ReadWrite,
192	bit_size: `32`,
193	fieldset: Some(
194	"Vmcr",
195	),
196	},
197	),
198	},
199	BlockItem {
200	name: "vpcr",
201	description: Some(
202	"DSI Host video packet configuration register.",
203	),
204	array: None,
205	byte_offset: `0x3c`,
206	inner: BlockItemInner::Register(
207	Register {
208	access: Access::ReadWrite,
209	bit_size: `32`,
210	fieldset: Some(
211	"Vpcr",
212	),
213	},
214	),
215	},
216	BlockItem {
217	name: "vccr",
218	description: Some(
219	"DSI Host video chunks configuration register.",
220	),
221	array: None,
222	byte_offset: `0x40`,
223	inner: BlockItemInner::Register(
224	Register {
225	access: Access::ReadWrite,
226	bit_size: `32`,
227	fieldset: Some(
228	"Vccr",
229	),
230	},
231	),
232	},
233	BlockItem {
234	name: "vnpcr",
235	description: Some(
236	"DSI Host video null packet configuration register.",
237	),
238	array: None,
239	byte_offset: `0x44`,
240	inner: BlockItemInner::Register(
241	Register {
242	access: Access::ReadWrite,
243	bit_size: `32`,
244	fieldset: Some(
245	"Vnpcr",
246	),
247	},
248	),
249	},
250	BlockItem {
251	name: "vhsacr",
252	description: Some(
253	"DSI Host video HSA configuration register.",
254	),
255	array: None,
256	byte_offset: `0x48`,
257	inner: BlockItemInner::Register(
258	Register {
259	access: Access::ReadWrite,
260	bit_size: `32`,
261	fieldset: Some(
262	"Vhsacr",
263	),
264	},
265	),
266	},
267	BlockItem {
268	name: "vhbpcr",
269	description: Some(
270	"DSI Host video HBP configuration register.",
271	),
272	array: None,
273	byte_offset: `0x4c`,
274	inner: BlockItemInner::Register(
275	Register {
276	access: Access::ReadWrite,
277	bit_size: `32`,
278	fieldset: Some(
279	"Vhbpcr",
280	),
281	},
282	),
283	},
284	BlockItem {
285	name: "vlcr",
286	description: Some(
287	"DSI Host video line configuration register.",
288	),
289	array: None,
290	byte_offset: `0x50`,
291	inner: BlockItemInner::Register(
292	Register {
293	access: Access::ReadWrite,
294	bit_size: `32`,
295	fieldset: Some(
296	"Vlcr",
297	),
298	},
299	),
300	},
301	BlockItem {
302	name: "vvsacr",
303	description: Some(
304	"DSI Host video VSA configuration register.",
305	),
306	array: None,
307	byte_offset: `0x54`,
308	inner: BlockItemInner::Register(
309	Register {
310	access: Access::ReadWrite,
311	bit_size: `32`,
312	fieldset: Some(
313	"Vvsacr",
314	),
315	},
316	),
317	},
318	BlockItem {
319	name: "vvbpcr",
320	description: Some(
321	"DSI Host video VBP configuration register.",
322	),
323	array: None,
324	byte_offset: `0x58`,
325	inner: BlockItemInner::Register(
326	Register {
327	access: Access::ReadWrite,
328	bit_size: `32`,
329	fieldset: Some(
330	"Vvbpcr",
331	),
332	},
333	),
334	},
335	BlockItem {
336	name: "vvfpcr",
337	description: Some(
338	"DSI Host video VFP configuration register.",
339	),
340	array: None,
341	byte_offset: `0x5c`,
342	inner: BlockItemInner::Register(
343	Register {
344	access: Access::ReadWrite,
345	bit_size: `32`,
346	fieldset: Some(
347	"Vvfpcr",
348	),
349	},
350	),
351	},
352	BlockItem {
353	name: "vvacr",
354	description: Some(
355	"DSI Host video VA configuration register.",
356	),
357	array: None,
358	byte_offset: `0x60`,
359	inner: BlockItemInner::Register(
360	Register {
361	access: Access::ReadWrite,
362	bit_size: `32`,
363	fieldset: Some(
364	"Vvacr",
365	),
366	},
367	),
368	},
369	BlockItem {
370	name: "lccr",
371	description: Some(
372	"DSI Host LTDC command configuration register.",
373	),
374	array: None,
375	byte_offset: `0x64`,
376	inner: BlockItemInner::Register(
377	Register {
378	access: Access::ReadWrite,
379	bit_size: `32`,
380	fieldset: Some(
381	"Lccr",
382	),
383	},
384	),
385	},
386	BlockItem {
387	name: "cmcr",
388	description: Some(
389	"DSI Host command mode configuration register.",
390	),
391	array: None,
392	byte_offset: `0x68`,
393	inner: BlockItemInner::Register(
394	Register {
395	access: Access::ReadWrite,
396	bit_size: `32`,
397	fieldset: Some(
398	"Cmcr",
399	),
400	},
401	),
402	},
403	BlockItem {
404	name: "ghcr",
405	description: Some(
406	"DSI Host generic header configuration register.",
407	),
408	array: None,
409	byte_offset: `0x6c`,
410	inner: BlockItemInner::Register(
411	Register {
412	access: Access::ReadWrite,
413	bit_size: `32`,
414	fieldset: Some(
415	"Ghcr",
416	),
417	},
418	),
419	},
420	BlockItem {
421	name: "gpdr",
422	description: Some(
423	"DSI Host generic payload data register.",
424	),
425	array: None,
426	byte_offset: `0x70`,
427	inner: BlockItemInner::Register(
428	Register {
429	access: Access::ReadWrite,
430	bit_size: `32`,
431	fieldset: Some(
432	"Gpdr",
433	),
434	},
435	),
436	},
437	BlockItem {
438	name: "gpsr",
439	description: Some(
440	"DSI Host generic packet status register.",
441	),
442	array: None,
443	byte_offset: `0x74`,
444	inner: BlockItemInner::Register(
445	Register {
446	access: Access::ReadWrite,
447	bit_size: `32`,
448	fieldset: Some(
449	"Gpsr",
450	),
451	},
452	),
453	},
454	BlockItem {
455	name: "tccr0",
456	description: Some(
457	"DSI Host timeout counter configuration register 0.",
458	),
459	array: None,
460	byte_offset: `0x78`,
461	inner: BlockItemInner::Register(
462	Register {
463	access: Access::ReadWrite,
464	bit_size: `32`,
465	fieldset: Some(
466	"Tccr0",
467	),
468	},
469	),
470	},
471	BlockItem {
472	name: "tccr1",
473	description: Some(
474	"DSI Host timeout counter configuration register 1.",
475	),
476	array: None,
477	byte_offset: `0x7c`,
478	inner: BlockItemInner::Register(
479	Register {
480	access: Access::ReadWrite,
481	bit_size: `32`,
482	fieldset: Some(
483	"Tccr1",
484	),
485	},
486	),
487	},
488	BlockItem {
489	name: "tccr2",
490	description: Some(
491	"DSI Host timeout counter configuration register 2.",
492	),
493	array: None,
494	byte_offset: `0x80`,
495	inner: BlockItemInner::Register(
496	Register {
497	access: Access::ReadWrite,
498	bit_size: `32`,
499	fieldset: Some(
500	"Tccr2",
501	),
502	},
503	),
504	},
505	BlockItem {
506	name: "tccr3",
507	description: Some(
508	"DSI Host timeout counter configuration register 3.",
509	),
510	array: None,
511	byte_offset: `0x84`,
512	inner: BlockItemInner::Register(
513	Register {
514	access: Access::ReadWrite,
515	bit_size: `32`,
516	fieldset: Some(
517	"Tccr3",
518	),
519	},
520	),
521	},
522	BlockItem {
523	name: "tccr4",
524	description: Some(
525	"DSI Host timeout counter configuration register 4.",
526	),
527	array: None,
528	byte_offset: `0x88`,
529	inner: BlockItemInner::Register(
530	Register {
531	access: Access::ReadWrite,
532	bit_size: `32`,
533	fieldset: Some(
534	"Tccr4",
535	),
536	},
537	),
538	},
539	BlockItem {
540	name: "tccr5",
541	description: Some(
542	"DSI Host timeout counter configuration register 5.",
543	),
544	array: None,
545	byte_offset: `0x8c`,
546	inner: BlockItemInner::Register(
547	Register {
548	access: Access::ReadWrite,
549	bit_size: `32`,
550	fieldset: Some(
551	"Tccr5",
552	),
553	},
554	),
555	},
556	BlockItem {
557	name: "clcr",
558	description: Some(
559	"DSI Host clock lane configuration register.",
560	),
561	array: None,
562	byte_offset: `0x94`,
563	inner: BlockItemInner::Register(
564	Register {
565	access: Access::ReadWrite,
566	bit_size: `32`,
567	fieldset: Some(
568	"Clcr",
569	),
570	},
571	),
572	},
573	BlockItem {
574	name: "cltcr",
575	description: Some(
576	"DSI Host clock lane timer configuration register.",
577	),
578	array: None,
579	byte_offset: `0x98`,
580	inner: BlockItemInner::Register(
581	Register {
582	access: Access::ReadWrite,
583	bit_size: `32`,
584	fieldset: Some(
585	"Cltcr",
586	),
587	},
588	),
589	},
590	BlockItem {
591	name: "dltcr",
592	description: Some(
593	"DSI Host data lane timer configuration register.",
594	),
595	array: None,
596	byte_offset: `0x9c`,
597	inner: BlockItemInner::Register(
598	Register {
599	access: Access::ReadWrite,
600	bit_size: `32`,
601	fieldset: Some(
602	"Dltcr",
603	),
604	},
605	),
606	},
607	BlockItem {
608	name: "pctlr",
609	description: Some(
610	"DSI Host PHY control register.",
611	),
612	array: None,
613	byte_offset: `0xa0`,
614	inner: BlockItemInner::Register(
615	Register {
616	access: Access::ReadWrite,
617	bit_size: `32`,
618	fieldset: Some(
619	"Pctlr",
620	),
621	},
622	),
623	},
624	BlockItem {
625	name: "pconfr",
626	description: Some(
627	"DSI Host PHY configuration register.",
628	),
629	array: None,
630	byte_offset: `0xa4`,
631	inner: BlockItemInner::Register(
632	Register {
633	access: Access::ReadWrite,
634	bit_size: `32`,
635	fieldset: Some(
636	"Pconfr",
637	),
638	},
639	),
640	},
641	BlockItem {
642	name: "pucr",
643	description: Some(
644	"DSI Host PHY ULPS control register.",
645	),
646	array: None,
647	byte_offset: `0xa8`,
648	inner: BlockItemInner::Register(
649	Register {
650	access: Access::ReadWrite,
651	bit_size: `32`,
652	fieldset: Some(
653	"Pucr",
654	),
655	},
656	),
657	},
658	BlockItem {
659	name: "pttcr",
660	description: Some(
661	"DSI Host PHY TX triggers configuration register.",
662	),
663	array: None,
664	byte_offset: `0xac`,
665	inner: BlockItemInner::Register(
666	Register {
667	access: Access::ReadWrite,
668	bit_size: `32`,
669	fieldset: Some(
670	"Pttcr",
671	),
672	},
673	),
674	},
675	BlockItem {
676	name: "psr",
677	description: Some(
678	"DSI Host PHY status register.",
679	),
680	array: None,
681	byte_offset: `0xb0`,
682	inner: BlockItemInner::Register(
683	Register {
684	access: Access::ReadWrite,
685	bit_size: `32`,
686	fieldset: Some(
687	"Psr",
688	),
689	},
690	),
691	},
692	BlockItem {
693	name: "isr0",
694	description: Some(
695	"DSI Host interrupt and status register 0.",
696	),
697	array: None,
698	byte_offset: `0xbc`,
699	inner: BlockItemInner::Register(
700	Register {
701	access: Access::ReadWrite,
702	bit_size: `32`,
703	fieldset: Some(
704	"Isr0",
705	),
706	},
707	),
708	},
709	BlockItem {
710	name: "isr1",
711	description: Some(
712	"DSI Host interrupt and status register 1.",
713	),
714	array: None,
715	byte_offset: `0xc0`,
716	inner: BlockItemInner::Register(
717	Register {
718	access: Access::ReadWrite,
719	bit_size: `32`,
720	fieldset: Some(
721	"Isr1",
722	),
723	},
724	),
725	},
726	BlockItem {
727	name: "ier0",
728	description: Some(
729	"DSI Host interrupt enable register 0.",
730	),
731	array: None,
732	byte_offset: `0xc4`,
733	inner: BlockItemInner::Register(
734	Register {
735	access: Access::ReadWrite,
736	bit_size: `32`,
737	fieldset: Some(
738	"Ier0",
739	),
740	},
741	),
742	},
743	BlockItem {
744	name: "ier1",
745	description: Some(
746	"DSI Host interrupt enable register 1.",
747	),
748	array: None,
749	byte_offset: `0xc8`,
750	inner: BlockItemInner::Register(
751	Register {
752	access: Access::ReadWrite,
753	bit_size: `32`,
754	fieldset: Some(
755	"Ier1",
756	),
757	},
758	),
759	},
760	BlockItem {
761	name: "fir0",
762	description: Some(
763	"DSI Host force interrupt register 0.",
764	),
765	array: None,
766	byte_offset: `0xd8`,
767	inner: BlockItemInner::Register(
768	Register {
769	access: Access::ReadWrite,
770	bit_size: `32`,
771	fieldset: Some(
772	"Fir0",
773	),
774	},
775	),
776	},
777	BlockItem {
778	name: "fir1",
779	description: Some(
780	"DSI Host force interrupt register 1.",
781	),
782	array: None,
783	byte_offset: `0xdc`,
784	inner: BlockItemInner::Register(
785	Register {
786	access: Access::ReadWrite,
787	bit_size: `32`,
788	fieldset: Some(
789	"Fir1",
790	),
791	},
792	),
793	},
794	BlockItem {
795	name: "dltrcr",
796	description: Some(
797	"DSI Host data lane timer read configuration register.",
798	),
799	array: None,
800	byte_offset: `0xf4`,
801	inner: BlockItemInner::Register(
802	Register {
803	access: Access::ReadWrite,
804	bit_size: `32`,
805	fieldset: Some(
806	"Dltrcr",
807	),
808	},
809	),
810	},
811	BlockItem {
812	name: "vscr",
813	description: Some(
814	"DSI Host video shadow control register.",
815	),
816	array: None,
817	byte_offset: `0x100`,
818	inner: BlockItemInner::Register(
819	Register {
820	access: Access::ReadWrite,
821	bit_size: `32`,
822	fieldset: Some(
823	"Vscr",
824	),
825	},
826	),
827	},
828	BlockItem {
829	name: "lcvcidr",
830	description: Some(
831	"DSI Host LTDC current VCID register.",
832	),
833	array: None,
834	byte_offset: `0x10c`,
835	inner: BlockItemInner::Register(
836	Register {
837	access: Access::ReadWrite,
838	bit_size: `32`,
839	fieldset: Some(
840	"Lcvcidr",
841	),
842	},
843	),
844	},
845	BlockItem {
846	name: "lcccr",
847	description: Some(
848	"DSI Host LTDC current color coding register.",
849	),
850	array: None,
851	byte_offset: `0x110`,
852	inner: BlockItemInner::Register(
853	Register {
854	access: Access::ReadWrite,
855	bit_size: `32`,
856	fieldset: Some(
857	"Lcccr",
858	),
859	},
860	),
861	},
862	BlockItem {
863	name: "lpmccr",
864	description: Some(
865	"DSI Host low-power mode current configuration register.",
866	),
867	array: None,
868	byte_offset: `0x118`,
869	inner: BlockItemInner::Register(
870	Register {
871	access: Access::ReadWrite,
872	bit_size: `32`,
873	fieldset: Some(
874	"Lpmccr",
875	),
876	},
877	),
878	},
879	BlockItem {
880	name: "vmccr",
881	description: Some(
882	"DSI Host video mode current configuration register.",
883	),
884	array: None,
885	byte_offset: `0x138`,
886	inner: BlockItemInner::Register(
887	Register {
888	access: Access::ReadWrite,
889	bit_size: `32`,
890	fieldset: Some(
891	"Vmccr",
892	),
893	},
894	),
895	},
896	BlockItem {
897	name: "vpccr",
898	description: Some(
899	"DSI Host video packet current configuration register.",
900	),
901	array: None,
902	byte_offset: `0x13c`,
903	inner: BlockItemInner::Register(
904	Register {
905	access: Access::ReadWrite,
906	bit_size: `32`,
907	fieldset: Some(
908	"Vpccr",
909	),
910	},
911	),
912	},
913	BlockItem {
914	name: "vcccr",
915	description: Some(
916	"DSI Host video chunks current configuration register.",
917	),
918	array: None,
919	byte_offset: `0x140`,
920	inner: BlockItemInner::Register(
921	Register {
922	access: Access::ReadWrite,
923	bit_size: `32`,
924	fieldset: Some(
925	"Vcccr",
926	),
927	},
928	),
929	},
930	BlockItem {
931	name: "vnpccr",
932	description: Some(
933	"DSI Host video null packet current configuration register.",
934	),
935	array: None,
936	byte_offset: `0x144`,
937	inner: BlockItemInner::Register(
938	Register {
939	access: Access::ReadWrite,
940	bit_size: `32`,
941	fieldset: Some(
942	"Vnpccr",
943	),
944	},
945	),
946	},
947	BlockItem {
948	name: "vhsaccr",
949	description: Some(
950	"DSI Host video HSA current configuration register.",
951	),
952	array: None,
953	byte_offset: `0x148`,
954	inner: BlockItemInner::Register(
955	Register {
956	access: Access::ReadWrite,
957	bit_size: `32`,
958	fieldset: Some(
959	"Vhsaccr",
960	),
961	},
962	),
963	},
964	BlockItem {
965	name: "vhbpccr",
966	description: Some(
967	"DSI Host video HBP current configuration register.",
968	),
969	array: None,
970	byte_offset: `0x14c`,
971	inner: BlockItemInner::Register(
972	Register {
973	access: Access::ReadWrite,
974	bit_size: `32`,
975	fieldset: Some(
976	"Vhbpccr",
977	),
978	},
979	),
980	},
981	BlockItem {
982	name: "vlccr",
983	description: Some(
984	"DSI Host video line current configuration register.",
985	),
986	array: None,
987	byte_offset: `0x150`,
988	inner: BlockItemInner::Register(
989	Register {
990	access: Access::ReadWrite,
991	bit_size: `32`,
992	fieldset: Some(
993	"Vlccr",
994	),
995	},
996	),
997	},
998	BlockItem {
999	name: "vvsaccr",
1000	description: Some(
1001	"DSI Host video VSA current configuration register.",
1002	),
1003	array: None,
1004	byte_offset: `0x154`,
1005	inner: BlockItemInner::Register(
1006	Register {
1007	access: Access::ReadWrite,
1008	bit_size: `32`,
1009	fieldset: Some(
1010	"Vvsaccr",
1011	),
1012	},
1013	),
1014	},
1015	BlockItem {
1016	name: "vvbpccr",
1017	description: Some(
1018	"DSI Host video VBP current configuration register.",
1019	),
1020	array: None,
1021	byte_offset: `0x158`,
1022	inner: BlockItemInner::Register(
1023	Register {
1024	access: Access::ReadWrite,
1025	bit_size: `32`,
1026	fieldset: Some(
1027	"Vvbpccr",
1028	),
1029	},
1030	),
1031	},
1032	BlockItem {
1033	name: "vvfpccr",
1034	description: Some(
1035	"DSI Host video VFP current configuration register.",
1036	),
1037	array: None,
1038	byte_offset: `0x15c`,
1039	inner: BlockItemInner::Register(
1040	Register {
1041	access: Access::ReadWrite,
1042	bit_size: `32`,
1043	fieldset: Some(
1044	"Vvfpccr",
1045	),
1046	},
1047	),
1048	},
1049	BlockItem {
1050	name: "vvaccr",
1051	description: Some(
1052	"DSI Host video VA current configuration register.",
1053	),
1054	array: None,
1055	byte_offset: `0x160`,
1056	inner: BlockItemInner::Register(
1057	Register {
1058	access: Access::ReadWrite,
1059	bit_size: `32`,
1060	fieldset: Some(
1061	"Vvaccr",
1062	),
1063	},
1064	),
1065	},
1066	BlockItem {
1067	name: "fbsr",
1068	description: Some(
1069	"DSI Host FIFO and buffer status register.",
1070	),
1071	array: None,
1072	byte_offset: `0x168`,
1073	inner: BlockItemInner::Register(
1074	Register {
1075	access: Access::ReadWrite,
1076	bit_size: `32`,
1077	fieldset: Some(
1078	"Fbsr",
1079	),
1080	},
1081	),
1082	},
1083	BlockItem {
1084	name: "wcfgr",
1085	description: Some(
1086	"DSI Wrapper configuration register.",
1087	),
1088	array: None,
1089	byte_offset: `0x400`,
1090	inner: BlockItemInner::Register(
1091	Register {
1092	access: Access::ReadWrite,
1093	bit_size: `32`,
1094	fieldset: Some(
1095	"Wcfgr",
1096	),
1097	},
1098	),
1099	},
1100	BlockItem {
1101	name: "wcr",
1102	description: Some(
1103	"DSI Wrapper control register.",
1104	),
1105	array: None,
1106	byte_offset: `0x404`,
1107	inner: BlockItemInner::Register(
1108	Register {
1109	access: Access::ReadWrite,
1110	bit_size: `32`,
1111	fieldset: Some(
1112	"Wcr",
1113	),
1114	},
1115	),
1116	},
1117	BlockItem {
1118	name: "wier",
1119	description: Some(
1120	"DSI Wrapper interrupt enable register.",
1121	),
1122	array: None,
1123	byte_offset: `0x408`,
1124	inner: BlockItemInner::Register(
1125	Register {
1126	access: Access::ReadWrite,
1127	bit_size: `32`,
1128	fieldset: Some(
1129	"Wier",
1130	),
1131	},
1132	),
1133	},
1134	BlockItem {
1135	name: "wisr",
1136	description: Some(
1137	"DSI Wrapper interrupt and status register.",
1138	),
1139	array: None,
1140	byte_offset: `0x40c`,
1141	inner: BlockItemInner::Register(
1142	Register {
1143	access: Access::ReadWrite,
1144	bit_size: `32`,
1145	fieldset: Some(
1146	"Wisr",
1147	),
1148	},
1149	),
1150	},
1151	BlockItem {
1152	name: "wifcr",
1153	description: Some(
1154	"DSI Wrapper interrupt flag clear register.",
1155	),
1156	array: None,
1157	byte_offset: `0x410`,
1158	inner: BlockItemInner::Register(
1159	Register {
1160	access: Access::ReadWrite,
1161	bit_size: `32`,
1162	fieldset: Some(
1163	"Wifcr",
1164	),
1165	},
1166	),
1167	},
1168	BlockItem {
1169	name: "wpcr0",
1170	description: Some(
1171	"DSI Wrapper PHY configuration register 0.",
1172	),
1173	array: None,
1174	byte_offset: `0x418`,
1175	inner: BlockItemInner::Register(
1176	Register {
1177	access: Access::ReadWrite,
1178	bit_size: `32`,
1179	fieldset: Some(
1180	"Wpcr0",
1181	),
1182	},
1183	),
1184	},
1185	BlockItem {
1186	name: "wrpcr",
1187	description: Some(
1188	"DSI Wrapper regulator and PLL control register.",
1189	),
1190	array: None,
1191	byte_offset: `0x430`,
1192	inner: BlockItemInner::Register(
1193	Register {
1194	access: Access::ReadWrite,
1195	bit_size: `32`,
1196	fieldset: Some(
1197	"Wrpcr",
1198	),
1199	},
1200	),
1201	},
1202	BlockItem {
1203	name: "bcfgr",
1204	description: Some(
1205	"DSI bias configuration register.",
1206	),
1207	array: None,
1208	byte_offset: `0x808`,
1209	inner: BlockItemInner::Register(
1210	Register {
1211	access: Access::ReadWrite,
1212	bit_size: `32`,
1213	fieldset: Some(
1214	"Bcfgr",
1215	),
1216	},
1217	),
1218	},
1219	BlockItem {
1220	name: "dpcbcr",
1221	description: Some(
1222	"DSI D-PHY clock band control register.",
1223	),
1224	array: None,
1225	byte_offset: `0xc04`,
1226	inner: BlockItemInner::Register(
1227	Register {
1228	access: Access::ReadWrite,
1229	bit_size: `32`,
1230	fieldset: Some(
1231	"Dpcbcr",
1232	),
1233	},
1234	),
1235	},
1236	BlockItem {
1237	name: "dpcsrcr",
1238	description: Some(
1239	"DSI D-PHY clock skew rate control register.",
1240	),
1241	array: None,
1242	byte_offset: `0xc34`,
1243	inner: BlockItemInner::Register(
1244	Register {
1245	access: Access::ReadWrite,
1246	bit_size: `32`,
1247	fieldset: Some(
1248	"Dpcsrcr",
1249	),
1250	},
1251	),
1252	},
1253	BlockItem {
1254	name: "dpdl0bcr",
1255	description: Some(
1256	"DSI D-PHY data lane 0 band control register.",
1257	),
1258	array: None,
1259	byte_offset: `0xc70`,
1260	inner: BlockItemInner::Register(
1261	Register {
1262	access: Access::ReadWrite,
1263	bit_size: `32`,
1264	fieldset: Some(
1265	"Dpdl0bcr",
1266	),
1267	},
1268	),
1269	},
1270	BlockItem {
1271	name: "dpdl0srcr",
1272	description: Some(
1273	"DSI D-PHY data lane 0 skew rate control register.",
1274	),
1275	array: None,
1276	byte_offset: `0xca0`,
1277	inner: BlockItemInner::Register(
1278	Register {
1279	access: Access::ReadWrite,
1280	bit_size: `32`,
1281	fieldset: Some(
1282	"Dpdl0srcr",
1283	),
1284	},
1285	),
1286	},
1287	BlockItem {
1288	name: "dpdl1bcr",
1289	description: Some(
1290	"DSI D-PHY data lane 1 band control register.",
1291	),
1292	array: None,
1293	byte_offset: `0xd08`,
1294	inner: BlockItemInner::Register(
1295	Register {
1296	access: Access::ReadWrite,
1297	bit_size: `32`,
1298	fieldset: Some(
1299	"Dpdl1bcr",
1300	),
1301	},
1302	),
1303	},
1304	BlockItem {
1305	name: "dpdl1srcr",
1306	description: Some(
1307	"DSI D-PHY data lane 1 skew rate control register.",
1308	),
1309	array: None,
1310	byte_offset: `0xd38`,
1311	inner: BlockItemInner::Register(
1312	Register {
1313	access: Access::ReadWrite,
1314	bit_size: `32`,
1315	fieldset: Some(
1316	"Dpdl1srcr",
1317	),
1318	},
1319	),
1320	},
1321	],
1322	},
1323	],
1324	fieldsets: &[
1325	FieldSet {
1326	name: "Bcfgr",
1327	extends: None,
1328	description: Some(
1329	"DSI bias configuration register.",
1330	),
1331	bit_size: `32`,
1332	fields: &[
1333	Field {
1334	name: "pwrup",
1335	description: Some(
1336	"Power-up This bit powers-up the reference bias for the MIPI D-PHY.",
1337	),
1338	bit_offset: BitOffset::Regular(
1339	RegularBitOffset {
1340	offset: `6`,
1341	},
1342	),
1343	bit_size: `1`,
1344	array: None,
1345	enumm: None,
1346	},
1347	],
1348	},
1349	FieldSet {
1350	name: "Ccr",
1351	extends: None,
1352	description: Some(
1353	"DSI Host clock control register.",
1354	),
1355	bit_size: `32`,
1356	fields: &[
1357	Field {
1358	name: "txeckdiv",
1359	description: Some(
1360	"TX escape clock division This field indicates the division factor for the TX escape clock source (lanebyteclk). The values 0 and 1 stop the TX_ESC clock generation.",
1361	),
1362	bit_offset: BitOffset::Regular(
1363	RegularBitOffset {
1364	offset: `0`,
1365	},
1366	),
1367	bit_size: `8`,
1368	array: None,
1369	enumm: None,
1370	},
1371	Field {
1372	name: "tockdiv",
1373	description: Some(
1374	"Timeout clock division This field indicates the division factor for the timeout clock used as the timing unit in the configuration of HS to LP and LP to HS transition error.",
1375	),
1376	bit_offset: BitOffset::Regular(
1377	RegularBitOffset {
1378	offset: `8`,
1379	},
1380	),
1381	bit_size: `8`,
1382	array: None,
1383	enumm: None,
1384	},
1385	],
1386	},
1387	FieldSet {
1388	name: "Clcr",
1389	extends: None,
1390	description: Some(
1391	"DSI Host clock lane configuration register.",
1392	),
1393	bit_size: `32`,
1394	fields: &[
1395	Field {
1396	name: "dpcc",
1397	description: Some(
1398	"D-PHY clock control This bit controls the D-PHY clock state:.",
1399	),
1400	bit_offset: BitOffset::Regular(
1401	RegularBitOffset {
1402	offset: `0`,
1403	},
1404	),
1405	bit_size: `1`,
1406	array: None,
1407	enumm: None,
1408	},
1409	Field {
1410	name: "acr",
1411	description: Some(
1412	"Automatic clock lane control This bit enables the automatic mechanism to stop providing clock in the clock lane when time allows.",
1413	),
1414	bit_offset: BitOffset::Regular(
1415	RegularBitOffset {
1416	offset: `1`,
1417	},
1418	),
1419	bit_size: `1`,
1420	array: None,
1421	enumm: None,
1422	},
1423	],
1424	},
1425	FieldSet {
1426	name: "Cltcr",
1427	extends: None,
1428	description: Some(
1429	"DSI Host clock lane timer configuration register.",
1430	),
1431	bit_size: `32`,
1432	fields: &[
1433	Field {
1434	name: "lp2hs_time",
1435	description: Some(
1436	"Low-power to high-speed time This field configures the maximum time that the D-PHY clock lane takes to go from lowâ`\u{80}\u{91}`power to high-speed transmission measured in lane byte clock cycles.",
1437	),
1438	bit_offset: BitOffset::Regular(
1439	RegularBitOffset {
1440	offset: `0`,
1441	},
1442	),
1443	bit_size: `10`,
1444	array: None,
1445	enumm: None,
1446	},
1447	Field {
1448	name: "hs2lp_time",
1449	description: Some(
1450	"High-speed to low-power time This field configures the maximum time that the D-PHY clock lane takes to go from highâ`\u{80}\u{91}`speed to low-power transmission measured in lane byte clock cycles.",
1451	),
1452	bit_offset: BitOffset::Regular(
1453	RegularBitOffset {
1454	offset: `16`,
1455	},
1456	),
1457	bit_size: `10`,
1458	array: None,
1459	enumm: None,
1460	},
1461	],
1462	},
1463	FieldSet {
1464	name: "Cmcr",
1465	extends: None,
1466	description: Some(
1467	"DSI Host command mode configuration register.",
1468	),
1469	bit_size: `32`,
1470	fields: &[
1471	Field {
1472	name: "teare",
1473	description: Some(
1474	"Tearing effect acknowledge request enable This bit enables the tearing effect acknowledge request:.",
1475	),
1476	bit_offset: BitOffset::Regular(
1477	RegularBitOffset {
1478	offset: `0`,
1479	},
1480	),
1481	bit_size: `1`,
1482	array: None,
1483	enumm: None,
1484	},
1485	Field {
1486	name: "are",
1487	description: Some(
1488	"Acknowledge request enable This bit enables the acknowledge request after each packet transmission:.",
1489	),
1490	bit_offset: BitOffset::Regular(
1491	RegularBitOffset {
1492	offset: `1`,
1493	},
1494	),
1495	bit_size: `1`,
1496	array: None,
1497	enumm: None,
1498	},
1499	Field {
1500	name: "gsw0tx",
1501	description: Some(
1502	"Generic short write zero parameters transmission This bit configures the generic short write packet with zero parameters command transmission type:.",
1503	),
1504	bit_offset: BitOffset::Regular(
1505	RegularBitOffset {
1506	offset: `8`,
1507	},
1508	),
1509	bit_size: `1`,
1510	array: None,
1511	enumm: None,
1512	},
1513	Field {
1514	name: "gsw1tx",
1515	description: Some(
1516	"Generic short write one parameters transmission This bit configures the generic short write packet with one parameters command transmission type:.",
1517	),
1518	bit_offset: BitOffset::Regular(
1519	RegularBitOffset {
1520	offset: `9`,
1521	},
1522	),
1523	bit_size: `1`,
1524	array: None,
1525	enumm: None,
1526	},
1527	Field {
1528	name: "gsw2tx",
1529	description: Some(
1530	"Generic short write two parameters transmission This bit configures the generic short write packet with two parameters command transmission type:.",
1531	),
1532	bit_offset: BitOffset::Regular(
1533	RegularBitOffset {
1534	offset: `10`,
1535	},
1536	),
1537	bit_size: `1`,
1538	array: None,
1539	enumm: None,
1540	},
1541	Field {
1542	name: "gsr0tx",
1543	description: Some(
1544	"Generic short read zero parameters transmission This bit configures the generic short read packet with zero parameters command transmission type:.",
1545	),
1546	bit_offset: BitOffset::Regular(
1547	RegularBitOffset {
1548	offset: `11`,
1549	},
1550	),
1551	bit_size: `1`,
1552	array: None,
1553	enumm: None,
1554	},
1555	Field {
1556	name: "gsr1tx",
1557	description: Some(
1558	"Generic short read one parameters transmission This bit configures the generic short read packet with one parameters command transmission type:.",
1559	),
1560	bit_offset: BitOffset::Regular(
1561	RegularBitOffset {
1562	offset: `12`,
1563	},
1564	),
1565	bit_size: `1`,
1566	array: None,
1567	enumm: None,
1568	},
1569	Field {
1570	name: "gsr2tx",
1571	description: Some(
1572	"Generic short read two parameters transmission This bit configures the generic short read packet with two parameters command transmission type:.",
1573	),
1574	bit_offset: BitOffset::Regular(
1575	RegularBitOffset {
1576	offset: `13`,
1577	},
1578	),
1579	bit_size: `1`,
1580	array: None,
1581	enumm: None,
1582	},
1583	Field {
1584	name: "glwtx",
1585	description: Some(
1586	"Generic long write transmission This bit configures the generic long write packet command transmission type :.",
1587	),
1588	bit_offset: BitOffset::Regular(
1589	RegularBitOffset {
1590	offset: `14`,
1591	},
1592	),
1593	bit_size: `1`,
1594	array: None,
1595	enumm: None,
1596	},
1597	Field {
1598	name: "dsw0tx",
1599	description: Some(
1600	"DCS short write zero parameter transmission This bit configures the DCS short write packet with zero parameter command transmission type:.",
1601	),
1602	bit_offset: BitOffset::Regular(
1603	RegularBitOffset {
1604	offset: `16`,
1605	},
1606	),
1607	bit_size: `1`,
1608	array: None,
1609	enumm: None,
1610	},
1611	Field {
1612	name: "dsw1tx",
1613	description: Some(
1614	"DCS short read one parameter transmission This bit configures the DCS short read packet with one parameter command transmission type:.",
1615	),
1616	bit_offset: BitOffset::Regular(
1617	RegularBitOffset {
1618	offset: `17`,
1619	},
1620	),
1621	bit_size: `1`,
1622	array: None,
1623	enumm: None,
1624	},
1625	Field {
1626	name: "dsr0tx",
1627	description: Some(
1628	"DCS short read zero parameter transmission This bit configures the DCS short read packet with zero parameter command transmission type:.",
1629	),
1630	bit_offset: BitOffset::Regular(
1631	RegularBitOffset {
1632	offset: `18`,
1633	},
1634	),
1635	bit_size: `1`,
1636	array: None,
1637	enumm: None,
1638	},
1639	Field {
1640	name: "dlwtx",
1641	description: Some(
1642	"DCS long write transmission This bit configures the DCS long write packet command transmission type:.",
1643	),
1644	bit_offset: BitOffset::Regular(
1645	RegularBitOffset {
1646	offset: `19`,
1647	},
1648	),
1649	bit_size: `1`,
1650	array: None,
1651	enumm: None,
1652	},
1653	Field {
1654	name: "mrdps",
1655	description: Some(
1656	"Maximum read packet size This bit configures the maximum read packet size command transmission type:.",
1657	),
1658	bit_offset: BitOffset::Regular(
1659	RegularBitOffset {
1660	offset: `24`,
1661	},
1662	),
1663	bit_size: `1`,
1664	array: None,
1665	enumm: None,
1666	},
1667	],
1668	},
1669	FieldSet {
1670	name: "Cr",
1671	extends: None,
1672	description: Some(
1673	"DSI Host control register.",
1674	),
1675	bit_size: `32`,
1676	fields: &[
1677	Field {
1678	name: "en",
1679	description: Some(
1680	"Enable This bit configures the DSI Host in either power-up mode or to reset.",
1681	),
1682	bit_offset: BitOffset::Regular(
1683	RegularBitOffset {
1684	offset: `0`,
1685	},
1686	),
1687	bit_size: `1`,
1688	array: None,
1689	enumm: None,
1690	},
1691	],
1692	},
1693	FieldSet {
1694	name: "Dltcr",
1695	extends: None,
1696	description: Some(
1697	"DSI Host data lane timer configuration register.",
1698	),
1699	bit_size: `32`,
1700	fields: &[
1701	Field {
1702	name: "lp2hs_time",
1703	description: Some(
1704	"Low-power to high-speed time This field configures the maximum time that the D-PHY data lanes take to go from low-power to high-speed transmission measured in lane byte clock cycles.",
1705	),
1706	bit_offset: BitOffset::Regular(
1707	RegularBitOffset {
1708	offset: `0`,
1709	},
1710	),
1711	bit_size: `10`,
1712	array: None,
1713	enumm: None,
1714	},
1715	Field {
1716	name: "hs2lp_time",
1717	description: Some(
1718	"High-speed to low-power time This field configures the maximum time that the D-PHY data lanes take to go from high-speed to low-power transmission measured in lane byte clock cycles.",
1719	),
1720	bit_offset: BitOffset::Regular(
1721	RegularBitOffset {
1722	offset: `16`,
1723	},
1724	),
1725	bit_size: `10`,
1726	array: None,
1727	enumm: None,
1728	},
1729	],
1730	},
1731	FieldSet {
1732	name: "Dltrcr",
1733	extends: None,
1734	description: Some(
1735	"DSI Host data lane timer read configuration register.",
1736	),
1737	bit_size: `32`,
1738	fields: &[
1739	Field {
1740	name: "mrd_time",
1741	description: Some(
1742	"Maximum read time This field configures the maximum time required to perform a read command in lane byte clock cycles. This register can only be modified when no read command is in progress.",
1743	),
1744	bit_offset: BitOffset::Regular(
1745	RegularBitOffset {
1746	offset: `0`,
1747	},
1748	),
1749	bit_size: `15`,
1750	array: None,
1751	enumm: None,
1752	},
1753	],
1754	},
1755	FieldSet {
1756	name: "Dpcbcr",
1757	extends: None,
1758	description: Some(
1759	"DSI D-PHY clock band control register.",
1760	),
1761	bit_size: `32`,
1762	fields: &[
1763	Field {
1764	name: "bc",
1765	description: Some(
1766	"Band control This field selects the frequency band used by the D-PHY. Others: Reserved.",
1767	),
1768	bit_offset: BitOffset::Regular(
1769	RegularBitOffset {
1770	offset: `3`,
1771	},
1772	),
1773	bit_size: `5`,
1774	array: None,
1775	enumm: None,
1776	},
1777	],
1778	},
1779	FieldSet {
1780	name: "Dpcsrcr",
1781	extends: None,
1782	description: Some(
1783	"DSI D-PHY clock skew rate control register.",
1784	),
1785	bit_size: `32`,
1786	fields: &[
1787	Field {
1788	name: "src",
1789	description: Some(
1790	"Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved.",
1791	),
1792	bit_offset: BitOffset::Regular(
1793	RegularBitOffset {
1794	offset: `0`,
1795	},
1796	),
1797	bit_size: `8`,
1798	array: None,
1799	enumm: None,
1800	},
1801	],
1802	},
1803	FieldSet {
1804	name: "Dpdl0bcr",
1805	extends: None,
1806	description: Some(
1807	"DSI D-PHY data lane 0 band control register.",
1808	),
1809	bit_size: `32`,
1810	fields: &[
1811	Field {
1812	name: "bc",
1813	description: Some(
1814	"Band control This field selects the frequency band used by the D-PHY. Others: Reserved.",
1815	),
1816	bit_offset: BitOffset::Regular(
1817	RegularBitOffset {
1818	offset: `0`,
1819	},
1820	),
1821	bit_size: `5`,
1822	array: None,
1823	enumm: None,
1824	},
1825	],
1826	},
1827	FieldSet {
1828	name: "Dpdl0srcr",
1829	extends: None,
1830	description: Some(
1831	"DSI D-PHY data lane 0 skew rate control register.",
1832	),
1833	bit_size: `32`,
1834	fields: &[
1835	Field {
1836	name: "src",
1837	description: Some(
1838	"Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved.",
1839	),
1840	bit_offset: BitOffset::Regular(
1841	RegularBitOffset {
1842	offset: `0`,
1843	},
1844	),
1845	bit_size: `8`,
1846	array: None,
1847	enumm: None,
1848	},
1849	],
1850	},
1851	FieldSet {
1852	name: "Dpdl1bcr",
1853	extends: None,
1854	description: Some(
1855	"DSI D-PHY data lane 1 band control register.",
1856	),
1857	bit_size: `32`,
1858	fields: &[
1859	Field {
1860	name: "bc",
1861	description: Some(
1862	"Band control This field selects the frequency band used by the D-PHY. Others: Reserved.",
1863	),
1864	bit_offset: BitOffset::Regular(
1865	RegularBitOffset {
1866	offset: `0`,
1867	},
1868	),
1869	bit_size: `5`,
1870	array: None,
1871	enumm: None,
1872	},
1873	],
1874	},
1875	FieldSet {
1876	name: "Dpdl1srcr",
1877	extends: None,
1878	description: Some(
1879	"DSI D-PHY data lane 1 skew rate control register.",
1880	),
1881	bit_size: `32`,
1882	fields: &[
1883	Field {
1884	name: "src",
1885	description: Some(
1886	"Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved.",
1887	),
1888	bit_offset: BitOffset::Regular(
1889	RegularBitOffset {
1890	offset: `0`,
1891	},
1892	),
1893	bit_size: `8`,
1894	array: None,
1895	enumm: None,
1896	},
1897	],
1898	},
1899	FieldSet {
1900	name: "Fbsr",
1901	extends: None,
1902	description: Some(
1903	"DSI Host FIFO and buffer status register.",
1904	),
1905	bit_size: `32`,
1906	fields: &[
1907	Field {
1908	name: "vcwfe",
1909	description: Some(
1910	"Video mode command write FIFO empty This bit indicates the empty status of the video mode write command FIFO:.",
1911	),
1912	bit_offset: BitOffset::Regular(
1913	RegularBitOffset {
1914	offset: `0`,
1915	},
1916	),
1917	bit_size: `1`,
1918	array: None,
1919	enumm: None,
1920	},
1921	Field {
1922	name: "vcwff",
1923	description: Some(
1924	"Video mode command write FIFO full This bit indicates the full status of the video mode write command FIFO:.",
1925	),
1926	bit_offset: BitOffset::Regular(
1927	RegularBitOffset {
1928	offset: `1`,
1929	},
1930	),
1931	bit_size: `1`,
1932	array: None,
1933	enumm: None,
1934	},
1935	Field {
1936	name: "vpwfe",
1937	description: Some(
1938	"Video mode payload write FIFO empty This bit indicates the empty status of the video mode write payload FIFO:.",
1939	),
1940	bit_offset: BitOffset::Regular(
1941	RegularBitOffset {
1942	offset: `2`,
1943	},
1944	),
1945	bit_size: `1`,
1946	array: None,
1947	enumm: None,
1948	},
1949	Field {
1950	name: "vpwff",
1951	description: Some(
1952	"Video mode payload write FIFO full This bit indicates the full status of the video mode write payload FIFO:.",
1953	),
1954	bit_offset: BitOffset::Regular(
1955	RegularBitOffset {
1956	offset: `3`,
1957	},
1958	),
1959	bit_size: `1`,
1960	array: None,
1961	enumm: None,
1962	},
1963	Field {
1964	name: "acwfe",
1965	description: Some(
1966	"Adapted command mode command write FIFO empty This bit indicates the empty status of the adapted command mode write command FIFO:.",
1967	),
1968	bit_offset: BitOffset::Regular(
1969	RegularBitOffset {
1970	offset: `4`,
1971	},
1972	),
1973	bit_size: `1`,
1974	array: None,
1975	enumm: None,
1976	},
1977	Field {
1978	name: "acwff",
1979	description: Some(
1980	"Adapted command mode command write FIFO full This bit indicates the full status of the adapted command mode write command FIFO:.",
1981	),
1982	bit_offset: BitOffset::Regular(
1983	RegularBitOffset {
1984	offset: `5`,
1985	},
1986	),
1987	bit_size: `1`,
1988	array: None,
1989	enumm: None,
1990	},
1991	Field {
1992	name: "apwfe",
1993	description: Some(
1994	"Adapted command mode payload write FIFO empty This bit indicates the empty status of the adapted command mode write payload FIFO:.",
1995	),
1996	bit_offset: BitOffset::Regular(
1997	RegularBitOffset {
1998	offset: `6`,
1999	},
2000	),
2001	bit_size: `1`,
2002	array: None,
2003	enumm: None,
2004	},
2005	Field {
2006	name: "apwff",
2007	description: Some(
2008	"Adapted command mode payload write FIFO full This bit indicates the full status of the adapted command mode write payload FIFO:.",
2009	),
2010	bit_offset: BitOffset::Regular(
2011	RegularBitOffset {
2012	offset: `7`,
2013	},
2014	),
2015	bit_size: `1`,
2016	array: None,
2017	enumm: None,
2018	},
2019	Field {
2020	name: "vpbe",
2021	description: Some(
2022	"Video mode payload buffer empty This bit indicates the empty status of the video mode payload internal buffer:.",
2023	),
2024	bit_offset: BitOffset::Regular(
2025	RegularBitOffset {
2026	offset: `16`,
2027	},
2028	),
2029	bit_size: `1`,
2030	array: None,
2031	enumm: None,
2032	},
2033	Field {
2034	name: "vpbf",
2035	description: Some(
2036	"Video mode payload buffer full This bit indicates the full status of the video mode payload internal buffer:.",
2037	),
2038	bit_offset: BitOffset::Regular(
2039	RegularBitOffset {
2040	offset: `17`,
2041	},
2042	),
2043	bit_size: `1`,
2044	array: None,
2045	enumm: None,
2046	},
2047	Field {
2048	name: "acbe",
2049	description: Some(
2050	"Adapted command mode command buffer empty This bit indicates the empty status of the adapted command mode command internal buffer:.",
2051	),
2052	bit_offset: BitOffset::Regular(
2053	RegularBitOffset {
2054	offset: `20`,
2055	},
2056	),
2057	bit_size: `1`,
2058	array: None,
2059	enumm: None,
2060	},
2061	Field {
2062	name: "acbf",
2063	description: Some(
2064	"Adapted command mode command buffer full This bit indicates the full status of the adapted command mode command internal buffer:.",
2065	),
2066	bit_offset: BitOffset::Regular(
2067	RegularBitOffset {
2068	offset: `21`,
2069	},
2070	),
2071	bit_size: `1`,
2072	array: None,
2073	enumm: None,
2074	},
2075	Field {
2076	name: "apbe",
2077	description: Some(
2078	"Adapted command mode payload buffer empty This bit indicates the empty status of the adapted command mode payload internal buffer:.",
2079	),
2080	bit_offset: BitOffset::Regular(
2081	RegularBitOffset {
2082	offset: `22`,
2083	},
2084	),
2085	bit_size: `1`,
2086	array: None,
2087	enumm: None,
2088	},
2089	Field {
2090	name: "apbf",
2091	description: Some(
2092	"Adapted command mode payload buffer full This bit indicates the full status of the adapted command mode payload internal buffer:.",
2093	),
2094	bit_offset: BitOffset::Regular(
2095	RegularBitOffset {
2096	offset: `23`,
2097	},
2098	),
2099	bit_size: `1`,
2100	array: None,
2101	enumm: None,
2102	},
2103	],
2104	},
2105	FieldSet {
2106	name: "Fir0",
2107	extends: None,
2108	description: Some(
2109	"DSI Host force interrupt register 0.",
2110	),
2111	bit_size: `32`,
2112	fields: &[
2113	Field {
2114	name: "fae0",
2115	description: Some(
2116	"Force acknowledge error 0 Writing one to this bit forces an acknowledge error 0.",
2117	),
2118	bit_offset: BitOffset::Regular(
2119	RegularBitOffset {
2120	offset: `0`,
2121	},
2122	),
2123	bit_size: `1`,
2124	array: None,
2125	enumm: None,
2126	},
2127	Field {
2128	name: "fae1",
2129	description: Some(
2130	"Force acknowledge error 1 Writing one to this bit forces an acknowledge error 1.",
2131	),
2132	bit_offset: BitOffset::Regular(
2133	RegularBitOffset {
2134	offset: `1`,
2135	},
2136	),
2137	bit_size: `1`,
2138	array: None,
2139	enumm: None,
2140	},
2141	Field {
2142	name: "fae2",
2143	description: Some(
2144	"Force acknowledge error 2 Writing one to this bit forces an acknowledge error 2.",
2145	),
2146	bit_offset: BitOffset::Regular(
2147	RegularBitOffset {
2148	offset: `2`,
2149	},
2150	),
2151	bit_size: `1`,
2152	array: None,
2153	enumm: None,
2154	},
2155	Field {
2156	name: "fae3",
2157	description: Some(
2158	"Force acknowledge error 3 Writing one to this bit forces an acknowledge error 3.",
2159	),
2160	bit_offset: BitOffset::Regular(
2161	RegularBitOffset {
2162	offset: `3`,
2163	},
2164	),
2165	bit_size: `1`,
2166	array: None,
2167	enumm: None,
2168	},
2169	Field {
2170	name: "fae4",
2171	description: Some(
2172	"Force acknowledge error 4 Writing one to this bit forces an acknowledge error 4.",
2173	),
2174	bit_offset: BitOffset::Regular(
2175	RegularBitOffset {
2176	offset: `4`,
2177	},
2178	),
2179	bit_size: `1`,
2180	array: None,
2181	enumm: None,
2182	},
2183	Field {
2184	name: "fae5",
2185	description: Some(
2186	"Force acknowledge error 5 Writing one to this bit forces an acknowledge error 5.",
2187	),
2188	bit_offset: BitOffset::Regular(
2189	RegularBitOffset {
2190	offset: `5`,
2191	},
2192	),
2193	bit_size: `1`,
2194	array: None,
2195	enumm: None,
2196	},
2197	Field {
2198	name: "fae6",
2199	description: Some(
2200	"Force acknowledge error 6 Writing one to this bit forces an acknowledge error 6.",
2201	),
2202	bit_offset: BitOffset::Regular(
2203	RegularBitOffset {
2204	offset: `6`,
2205	},
2206	),
2207	bit_size: `1`,
2208	array: None,
2209	enumm: None,
2210	},
2211	Field {
2212	name: "fae7",
2213	description: Some(
2214	"Force acknowledge error 7 Writing one to this bit forces an acknowledge error 7.",
2215	),
2216	bit_offset: BitOffset::Regular(
2217	RegularBitOffset {
2218	offset: `7`,
2219	},
2220	),
2221	bit_size: `1`,
2222	array: None,
2223	enumm: None,
2224	},
2225	Field {
2226	name: "fae8",
2227	description: Some(
2228	"Force acknowledge error 8 Writing one to this bit forces an acknowledge error 8.",
2229	),
2230	bit_offset: BitOffset::Regular(
2231	RegularBitOffset {
2232	offset: `8`,
2233	},
2234	),
2235	bit_size: `1`,
2236	array: None,
2237	enumm: None,
2238	},
2239	Field {
2240	name: "fae9",
2241	description: Some(
2242	"Force acknowledge error 9 Writing one to this bit forces an acknowledge error 9.",
2243	),
2244	bit_offset: BitOffset::Regular(
2245	RegularBitOffset {
2246	offset: `9`,
2247	},
2248	),
2249	bit_size: `1`,
2250	array: None,
2251	enumm: None,
2252	},
2253	Field {
2254	name: "fae10",
2255	description: Some(
2256	"Force acknowledge error 10 Writing one to this bit forces an acknowledge error 10.",
2257	),
2258	bit_offset: BitOffset::Regular(
2259	RegularBitOffset {
2260	offset: `10`,
2261	},
2262	),
2263	bit_size: `1`,
2264	array: None,
2265	enumm: None,
2266	},
2267	Field {
2268	name: "fae11",
2269	description: Some(
2270	"Force acknowledge error 11 Writing one to this bit forces an acknowledge error 11.",
2271	),
2272	bit_offset: BitOffset::Regular(
2273	RegularBitOffset {
2274	offset: `11`,
2275	},
2276	),
2277	bit_size: `1`,
2278	array: None,
2279	enumm: None,
2280	},
2281	Field {
2282	name: "fae12",
2283	description: Some(
2284	"Force acknowledge error 12 Writing one to this bit forces an acknowledge error 12.",
2285	),
2286	bit_offset: BitOffset::Regular(
2287	RegularBitOffset {
2288	offset: `12`,
2289	},
2290	),
2291	bit_size: `1`,
2292	array: None,
2293	enumm: None,
2294	},
2295	Field {
2296	name: "fae13",
2297	description: Some(
2298	"Force acknowledge error 13 Writing one to this bit forces an acknowledge error 13.",
2299	),
2300	bit_offset: BitOffset::Regular(
2301	RegularBitOffset {
2302	offset: `13`,
2303	},
2304	),
2305	bit_size: `1`,
2306	array: None,
2307	enumm: None,
2308	},
2309	Field {
2310	name: "fae14",
2311	description: Some(
2312	"Force acknowledge error 14 Writing one to this bit forces an acknowledge error 14.",
2313	),
2314	bit_offset: BitOffset::Regular(
2315	RegularBitOffset {
2316	offset: `14`,
2317	},
2318	),
2319	bit_size: `1`,
2320	array: None,
2321	enumm: None,
2322	},
2323	Field {
2324	name: "fae15",
2325	description: Some(
2326	"Force acknowledge error 15 Writing one to this bit forces an acknowledge error 15.",
2327	),
2328	bit_offset: BitOffset::Regular(
2329	RegularBitOffset {
2330	offset: `15`,
2331	},
2332	),
2333	bit_size: `1`,
2334	array: None,
2335	enumm: None,
2336	},
2337	Field {
2338	name: "fpe0",
2339	description: Some(
2340	"Force PHY error 0 Writing one to this bit forces a PHY error 0.",
2341	),
2342	bit_offset: BitOffset::Regular(
2343	RegularBitOffset {
2344	offset: `16`,
2345	},
2346	),
2347	bit_size: `1`,
2348	array: None,
2349	enumm: None,
2350	},
2351	Field {
2352	name: "fpe1",
2353	description: Some(
2354	"Force PHY error 1 Writing one to this bit forces a PHY error 1.",
2355	),
2356	bit_offset: BitOffset::Regular(
2357	RegularBitOffset {
2358	offset: `17`,
2359	},
2360	),
2361	bit_size: `1`,
2362	array: None,
2363	enumm: None,
2364	},
2365	Field {
2366	name: "fpe2",
2367	description: Some(
2368	"Force PHY error 2 Writing one to this bit forces a PHY error 2.",
2369	),
2370	bit_offset: BitOffset::Regular(
2371	RegularBitOffset {
2372	offset: `18`,
2373	},
2374	),
2375	bit_size: `1`,
2376	array: None,
2377	enumm: None,
2378	},
2379	Field {
2380	name: "fpe3",
2381	description: Some(
2382	"Force PHY error 3 Writing one to this bit forces a PHY error 3.",
2383	),
2384	bit_offset: BitOffset::Regular(
2385	RegularBitOffset {
2386	offset: `19`,
2387	},
2388	),
2389	bit_size: `1`,
2390	array: None,
2391	enumm: None,
2392	},
2393	Field {
2394	name: "fpe4",
2395	description: Some(
2396	"Force PHY error 4 Writing one to this bit forces a PHY error 4.",
2397	),
2398	bit_offset: BitOffset::Regular(
2399	RegularBitOffset {
2400	offset: `20`,
2401	},
2402	),
2403	bit_size: `1`,
2404	array: None,
2405	enumm: None,
2406	},
2407	],
2408	},
2409	FieldSet {
2410	name: "Fir1",
2411	extends: None,
2412	description: Some(
2413	"DSI Host force interrupt register 1.",
2414	),
2415	bit_size: `32`,
2416	fields: &[
2417	Field {
2418	name: "ftohstx",
2419	description: Some(
2420	"Force timeout high-speed transmission Writing one to this bit forces a timeout high-speed transmission.",
2421	),
2422	bit_offset: BitOffset::Regular(
2423	RegularBitOffset {
2424	offset: `0`,
2425	},
2426	),
2427	bit_size: `1`,
2428	array: None,
2429	enumm: None,
2430	},
2431	Field {
2432	name: "ftolprx",
2433	description: Some(
2434	"Force timeout low-power reception Writing one to this bit forces a timeout low-power reception.",
2435	),
2436	bit_offset: BitOffset::Regular(
2437	RegularBitOffset {
2438	offset: `1`,
2439	},
2440	),
2441	bit_size: `1`,
2442	array: None,
2443	enumm: None,
2444	},
2445	Field {
2446	name: "feccse",
2447	description: Some(
2448	"Force ECC single-bit error Writing one to this bit forces a ECC single-bit error.",
2449	),
2450	bit_offset: BitOffset::Regular(
2451	RegularBitOffset {
2452	offset: `2`,
2453	},
2454	),
2455	bit_size: `1`,
2456	array: None,
2457	enumm: None,
2458	},
2459	Field {
2460	name: "feccme",
2461	description: Some(
2462	"Force ECC multi-bit error Writing one to this bit forces a ECC multi-bit error.",
2463	),
2464	bit_offset: BitOffset::Regular(
2465	RegularBitOffset {
2466	offset: `3`,
2467	},
2468	),
2469	bit_size: `1`,
2470	array: None,
2471	enumm: None,
2472	},
2473	Field {
2474	name: "fcrce",
2475	description: Some(
2476	"Force CRC error Writing one to this bit forces a CRC error.",
2477	),
2478	bit_offset: BitOffset::Regular(
2479	RegularBitOffset {
2480	offset: `4`,
2481	},
2482	),
2483	bit_size: `1`,
2484	array: None,
2485	enumm: None,
2486	},
2487	Field {
2488	name: "fpse",
2489	description: Some(
2490	"Force packet size error Writing one to this bit forces a packet size error.",
2491	),
2492	bit_offset: BitOffset::Regular(
2493	RegularBitOffset {
2494	offset: `5`,
2495	},
2496	),
2497	bit_size: `1`,
2498	array: None,
2499	enumm: None,
2500	},
2501	Field {
2502	name: "feotpe",
2503	description: Some(
2504	"Force EoTp error Writing one to this bit forces a EoTp error.",
2505	),
2506	bit_offset: BitOffset::Regular(
2507	RegularBitOffset {
2508	offset: `6`,
2509	},
2510	),
2511	bit_size: `1`,
2512	array: None,
2513	enumm: None,
2514	},
2515	Field {
2516	name: "flpwre",
2517	description: Some(
2518	"Force LTDC payload write error Writing one to this bit forces a LTDC payload write error.",
2519	),
2520	bit_offset: BitOffset::Regular(
2521	RegularBitOffset {
2522	offset: `7`,
2523	},
2524	),
2525	bit_size: `1`,
2526	array: None,
2527	enumm: None,
2528	},
2529	Field {
2530	name: "fgcwre",
2531	description: Some(
2532	"Force generic command write error Writing one to this bit forces a generic command write error.",
2533	),
2534	bit_offset: BitOffset::Regular(
2535	RegularBitOffset {
2536	offset: `8`,
2537	},
2538	),
2539	bit_size: `1`,
2540	array: None,
2541	enumm: None,
2542	},
2543	Field {
2544	name: "fgpwre",
2545	description: Some(
2546	"Force generic payload write error Writing one to this bit forces a generic payload write error.",
2547	),
2548	bit_offset: BitOffset::Regular(
2549	RegularBitOffset {
2550	offset: `9`,
2551	},
2552	),
2553	bit_size: `1`,
2554	array: None,
2555	enumm: None,
2556	},
2557	Field {
2558	name: "fgptxe",
2559	description: Some(
2560	"Force generic payload transmit error Writing one to this bit forces a generic payload transmit error.",
2561	),
2562	bit_offset: BitOffset::Regular(
2563	RegularBitOffset {
2564	offset: `10`,
2565	},
2566	),
2567	bit_size: `1`,
2568	array: None,
2569	enumm: None,
2570	},
2571	Field {
2572	name: "fgprde",
2573	description: Some(
2574	"Force generic payload read error Writing one to this bit forces a generic payload read error.",
2575	),
2576	bit_offset: BitOffset::Regular(
2577	RegularBitOffset {
2578	offset: `11`,
2579	},
2580	),
2581	bit_size: `1`,
2582	array: None,
2583	enumm: None,
2584	},
2585	Field {
2586	name: "fgprxe",
2587	description: Some(
2588	"Force generic payload receive error Writing one to this bit forces a generic payload receive error.",
2589	),
2590	bit_offset: BitOffset::Regular(
2591	RegularBitOffset {
2592	offset: `12`,
2593	},
2594	),
2595	bit_size: `1`,
2596	array: None,
2597	enumm: None,
2598	},
2599	Field {
2600	name: "fpbue",
2601	description: Some(
2602	"Force payload buffer underflow error Writing one to this bit forces a payload undrflow error.",
2603	),
2604	bit_offset: BitOffset::Regular(
2605	RegularBitOffset {
2606	offset: `19`,
2607	},
2608	),
2609	bit_size: `1`,
2610	array: None,
2611	enumm: None,
2612	},
2613	],
2614	},
2615	FieldSet {
2616	name: "Ghcr",
2617	extends: None,
2618	description: Some(
2619	"DSI Host generic header configuration register.",
2620	),
2621	bit_size: `32`,
2622	fields: &[
2623	Field {
2624	name: "dt",
2625	description: Some(
2626	"Type This field configures the packet data type of the header packet.",
2627	),
2628	bit_offset: BitOffset::Regular(
2629	RegularBitOffset {
2630	offset: `0`,
2631	},
2632	),
2633	bit_size: `6`,
2634	array: None,
2635	enumm: None,
2636	},
2637	Field {
2638	name: "vcid",
2639	description: Some(
2640	"Channel This field configures the virtual channel ID of the header packet.",
2641	),
2642	bit_offset: BitOffset::Regular(
2643	RegularBitOffset {
2644	offset: `6`,
2645	},
2646	),
2647	bit_size: `2`,
2648	array: None,
2649	enumm: None,
2650	},
2651	Field {
2652	name: "wclsb",
2653	description: Some(
2654	"WordCount LSB This field configures the less significant byte of the header packet word count for long packets, or data 0 for short packets.",
2655	),
2656	bit_offset: BitOffset::Regular(
2657	RegularBitOffset {
2658	offset: `8`,
2659	},
2660	),
2661	bit_size: `8`,
2662	array: None,
2663	enumm: None,
2664	},
2665	Field {
2666	name: "wcmsb",
2667	description: Some(
2668	"WordCount MSB This field configures the most significant byte of the header packet's word count for long packets, or data 1 for short packets.",
2669	),
2670	bit_offset: BitOffset::Regular(
2671	RegularBitOffset {
2672	offset: `16`,
2673	},
2674	),
2675	bit_size: `8`,
2676	array: None,
2677	enumm: None,
2678	},
2679	],
2680	},
2681	FieldSet {
2682	name: "Gpdr",
2683	extends: None,
2684	description: Some(
2685	"DSI Host generic payload data register.",
2686	),
2687	bit_size: `32`,
2688	fields: &[
2689	Field {
2690	name: "data1",
2691	description: Some(
2692	"Payload byte 1 This field indicates the byte 1 of the packet payload.",
2693	),
2694	bit_offset: BitOffset::Regular(
2695	RegularBitOffset {
2696	offset: `0`,
2697	},
2698	),
2699	bit_size: `8`,
2700	array: None,
2701	enumm: None,
2702	},
2703	Field {
2704	name: "data2",
2705	description: Some(
2706	"Payload byte 2 This field indicates the byte 2 of the packet payload.",
2707	),
2708	bit_offset: BitOffset::Regular(
2709	RegularBitOffset {
2710	offset: `8`,
2711	},
2712	),
2713	bit_size: `8`,
2714	array: None,
2715	enumm: None,
2716	},
2717	Field {
2718	name: "data3",
2719	description: Some(
2720	"Payload byte 3 This field indicates the byte 3 of the packet payload.",
2721	),
2722	bit_offset: BitOffset::Regular(
2723	RegularBitOffset {
2724	offset: `16`,
2725	},
2726	),
2727	bit_size: `8`,
2728	array: None,
2729	enumm: None,
2730	},
2731	Field {
2732	name: "data4",
2733	description: Some(
2734	"Payload byte 4 This field indicates the byte 4 of the packet payload.",
2735	),
2736	bit_offset: BitOffset::Regular(
2737	RegularBitOffset {
2738	offset: `24`,
2739	},
2740	),
2741	bit_size: `8`,
2742	array: None,
2743	enumm: None,
2744	},
2745	],
2746	},
2747	FieldSet {
2748	name: "Gpsr",
2749	extends: None,
2750	description: Some(
2751	"DSI Host generic packet status register.",
2752	),
2753	bit_size: `32`,
2754	fields: &[
2755	Field {
2756	name: "cmdfe",
2757	description: Some(
2758	"Command FIFO empty This bit indicates the empty status of the generic command FIFO:.",
2759	),
2760	bit_offset: BitOffset::Regular(
2761	RegularBitOffset {
2762	offset: `0`,
2763	},
2764	),
2765	bit_size: `1`,
2766	array: None,
2767	enumm: None,
2768	},
2769	Field {
2770	name: "cmdff",
2771	description: Some(
2772	"Command FIFO full This bit indicates the full status of the generic command FIFO:.",
2773	),
2774	bit_offset: BitOffset::Regular(
2775	RegularBitOffset {
2776	offset: `1`,
2777	},
2778	),
2779	bit_size: `1`,
2780	array: None,
2781	enumm: None,
2782	},
2783	Field {
2784	name: "pwrfe",
2785	description: Some(
2786	"Payload write FIFO empty This bit indicates the empty status of the generic write payload FIFO:.",
2787	),
2788	bit_offset: BitOffset::Regular(
2789	RegularBitOffset {
2790	offset: `2`,
2791	},
2792	),
2793	bit_size: `1`,
2794	array: None,
2795	enumm: None,
2796	},
2797	Field {
2798	name: "pwrff",
2799	description: Some(
2800	"Payload write FIFO full This bit indicates the full status of the generic write payload FIFO:.",
2801	),
2802	bit_offset: BitOffset::Regular(
2803	RegularBitOffset {
2804	offset: `3`,
2805	},
2806	),
2807	bit_size: `1`,
2808	array: None,
2809	enumm: None,
2810	},
2811	Field {
2812	name: "prdfe",
2813	description: Some(
2814	"Payload read FIFO empty This bit indicates the empty status of the generic read payload FIFO:.",
2815	),
2816	bit_offset: BitOffset::Regular(
2817	RegularBitOffset {
2818	offset: `4`,
2819	},
2820	),
2821	bit_size: `1`,
2822	array: None,
2823	enumm: None,
2824	},
2825	Field {
2826	name: "prdff",
2827	description: Some(
2828	"Payload read FIFO full This bit indicates the full status of the generic read payload FIFO:.",
2829	),
2830	bit_offset: BitOffset::Regular(
2831	RegularBitOffset {
2832	offset: `5`,
2833	},
2834	),
2835	bit_size: `1`,
2836	array: None,
2837	enumm: None,
2838	},
2839	Field {
2840	name: "rcb",
2841	description: Some(
2842	"Read command busy This bit is set when a read command is issued and cleared when the entire response is stored in the FIFO:.",
2843	),
2844	bit_offset: BitOffset::Regular(
2845	RegularBitOffset {
2846	offset: `6`,
2847	},
2848	),
2849	bit_size: `1`,
2850	array: None,
2851	enumm: None,
2852	},
2853	Field {
2854	name: "cmdbe",
2855	description: Some(
2856	"Command buffer empty This bit indicates the empty status of the generic payload internal buffer:.",
2857	),
2858	bit_offset: BitOffset::Regular(
2859	RegularBitOffset {
2860	offset: `16`,
2861	},
2862	),
2863	bit_size: `1`,
2864	array: None,
2865	enumm: None,
2866	},
2867	Field {
2868	name: "cmdbf",
2869	description: Some(
2870	"Command buffer full This bit indicates the full status of the generic command internal buffer:.",
2871	),
2872	bit_offset: BitOffset::Regular(
2873	RegularBitOffset {
2874	offset: `17`,
2875	},
2876	),
2877	bit_size: `1`,
2878	array: None,
2879	enumm: None,
2880	},
2881	Field {
2882	name: "pbe",
2883	description: Some(
2884	"Payload buffer empty This bit indicates the empty status of the generic payload internal buffer:.",
2885	),
2886	bit_offset: BitOffset::Regular(
2887	RegularBitOffset {
2888	offset: `18`,
2889	},
2890	),
2891	bit_size: `1`,
2892	array: None,
2893	enumm: None,
2894	},
2895	Field {
2896	name: "pbf",
2897	description: Some(
2898	"Payload buffer full This bit indicates the full status of the generic payload internal buffer:.",
2899	),
2900	bit_offset: BitOffset::Regular(
2901	RegularBitOffset {
2902	offset: `19`,
2903	},
2904	),
2905	bit_size: `1`,
2906	array: None,
2907	enumm: None,
2908	},
2909	],
2910	},
2911	FieldSet {
2912	name: "Gvcidr",
2913	extends: None,
2914	description: Some(
2915	"DSI Host generic VCID register.",
2916	),
2917	bit_size: `32`,
2918	fields: &[
2919	Field {
2920	name: "vcidrx",
2921	description: Some(
2922	"Virtual channel ID for reception This field indicates the generic interface read-back virtual channel identification.",
2923	),
2924	bit_offset: BitOffset::Regular(
2925	RegularBitOffset {
2926	offset: `0`,
2927	},
2928	),
2929	bit_size: `2`,
2930	array: None,
2931	enumm: None,
2932	},
2933	Field {
2934	name: "vcidtx",
2935	description: Some(
2936	"Virtual channel ID for transmission This field indicates the generic interface virtual channel identification where the generic packet is automatically generated and transmitted.",
2937	),
2938	bit_offset: BitOffset::Regular(
2939	RegularBitOffset {
2940	offset: `16`,
2941	},
2942	),
2943	bit_size: `2`,
2944	array: None,
2945	enumm: None,
2946	},
2947	],
2948	},
2949	FieldSet {
2950	name: "Ier0",
2951	extends: None,
2952	description: Some(
2953	"DSI Host interrupt enable register 0.",
2954	),
2955	bit_size: `32`,
2956	fields: &[
2957	Field {
2958	name: "ae0ie",
2959	description: Some(
2960	"Acknowledge error 0 interrupt enable This bit enables the interrupt generation on acknowledge error 0.",
2961	),
2962	bit_offset: BitOffset::Regular(
2963	RegularBitOffset {
2964	offset: `0`,
2965	},
2966	),
2967	bit_size: `1`,
2968	array: None,
2969	enumm: None,
2970	},
2971	Field {
2972	name: "ae1ie",
2973	description: Some(
2974	"Acknowledge error 1 interrupt enable This bit enables the interrupt generation on acknowledge error 1.",
2975	),
2976	bit_offset: BitOffset::Regular(
2977	RegularBitOffset {
2978	offset: `1`,
2979	},
2980	),
2981	bit_size: `1`,
2982	array: None,
2983	enumm: None,
2984	},
2985	Field {
2986	name: "ae2ie",
2987	description: Some(
2988	"Acknowledge error 2 interrupt enable This bit enables the interrupt generation on acknowledge error 2.",
2989	),
2990	bit_offset: BitOffset::Regular(
2991	RegularBitOffset {
2992	offset: `2`,
2993	},
2994	),
2995	bit_size: `1`,
2996	array: None,
2997	enumm: None,
2998	},
2999	Field {
3000	name: "ae3ie",
3001	description: Some(
3002	"Acknowledge error 3 interrupt enable This bit enables the interrupt generation on acknowledge error 3.",
3003	),
3004	bit_offset: BitOffset::Regular(
3005	RegularBitOffset {
3006	offset: `3`,
3007	},
3008	),
3009	bit_size: `1`,
3010	array: None,
3011	enumm: None,
3012	},
3013	Field {
3014	name: "ae4ie",
3015	description: Some(
3016	"Acknowledge error 4 interrupt enable This bit enables the interrupt generation on acknowledge error 4.",
3017	),
3018	bit_offset: BitOffset::Regular(
3019	RegularBitOffset {
3020	offset: `4`,
3021	},
3022	),
3023	bit_size: `1`,
3024	array: None,
3025	enumm: None,
3026	},
3027	Field {
3028	name: "ae5ie",
3029	description: Some(
3030	"Acknowledge error 5 interrupt enable This bit enables the interrupt generation on acknowledge error 5.",
3031	),
3032	bit_offset: BitOffset::Regular(
3033	RegularBitOffset {
3034	offset: `5`,
3035	},
3036	),
3037	bit_size: `1`,
3038	array: None,
3039	enumm: None,
3040	},
3041	Field {
3042	name: "ae6ie",
3043	description: Some(
3044	"Acknowledge error 6 interrupt enable This bit enables the interrupt generation on acknowledge error 6.",
3045	),
3046	bit_offset: BitOffset::Regular(
3047	RegularBitOffset {
3048	offset: `6`,
3049	},
3050	),
3051	bit_size: `1`,
3052	array: None,
3053	enumm: None,
3054	},
3055	Field {
3056	name: "ae7ie",
3057	description: Some(
3058	"Acknowledge error 7 interrupt enable This bit enables the interrupt generation on acknowledge error 7.",
3059	),
3060	bit_offset: BitOffset::Regular(
3061	RegularBitOffset {
3062	offset: `7`,
3063	},
3064	),
3065	bit_size: `1`,
3066	array: None,
3067	enumm: None,
3068	},
3069	Field {
3070	name: "ae8ie",
3071	description: Some(
3072	"Acknowledge error 8 interrupt enable This bit enables the interrupt generation on acknowledge error 8.",
3073	),
3074	bit_offset: BitOffset::Regular(
3075	RegularBitOffset {
3076	offset: `8`,
3077	},
3078	),
3079	bit_size: `1`,
3080	array: None,
3081	enumm: None,
3082	},
3083	Field {
3084	name: "ae9ie",
3085	description: Some(
3086	"Acknowledge error 9 interrupt enable This bit enables the interrupt generation on acknowledge error 9.",
3087	),
3088	bit_offset: BitOffset::Regular(
3089	RegularBitOffset {
3090	offset: `9`,
3091	},
3092	),
3093	bit_size: `1`,
3094	array: None,
3095	enumm: None,
3096	},
3097	Field {
3098	name: "ae10ie",
3099	description: Some(
3100	"Acknowledge error 10 interrupt enable This bit enables the interrupt generation on acknowledge error 10.",
3101	),
3102	bit_offset: BitOffset::Regular(
3103	RegularBitOffset {
3104	offset: `10`,
3105	},
3106	),
3107	bit_size: `1`,
3108	array: None,
3109	enumm: None,
3110	},
3111	Field {
3112	name: "ae11ie",
3113	description: Some(
3114	"Acknowledge error 11 interrupt enable This bit enables the interrupt generation on acknowledge error 11.",
3115	),
3116	bit_offset: BitOffset::Regular(
3117	RegularBitOffset {
3118	offset: `11`,
3119	},
3120	),
3121	bit_size: `1`,
3122	array: None,
3123	enumm: None,
3124	},
3125	Field {
3126	name: "ae12ie",
3127	description: Some(
3128	"Acknowledge error 12 interrupt enable This bit enables the interrupt generation on acknowledge error 12.",
3129	),
3130	bit_offset: BitOffset::Regular(
3131	RegularBitOffset {
3132	offset: `12`,
3133	},
3134	),
3135	bit_size: `1`,
3136	array: None,
3137	enumm: None,
3138	},
3139	Field {
3140	name: "ae13ie",
3141	description: Some(
3142	"Acknowledge error 13 interrupt enable This bit enables the interrupt generation on acknowledge error 13.",
3143	),
3144	bit_offset: BitOffset::Regular(
3145	RegularBitOffset {
3146	offset: `13`,
3147	},
3148	),
3149	bit_size: `1`,
3150	array: None,
3151	enumm: None,
3152	},
3153	Field {
3154	name: "ae14ie",
3155	description: Some(
3156	"Acknowledge error 14 interrupt enable This bit enables the interrupt generation on acknowledge error 14.",
3157	),
3158	bit_offset: BitOffset::Regular(
3159	RegularBitOffset {
3160	offset: `14`,
3161	},
3162	),
3163	bit_size: `1`,
3164	array: None,
3165	enumm: None,
3166	},
3167	Field {
3168	name: "ae15ie",
3169	description: Some(
3170	"Acknowledge error 15 interrupt enable This bit enables the interrupt generation on acknowledge error 15.",
3171	),
3172	bit_offset: BitOffset::Regular(
3173	RegularBitOffset {
3174	offset: `15`,
3175	},
3176	),
3177	bit_size: `1`,
3178	array: None,
3179	enumm: None,
3180	},
3181	Field {
3182	name: "pe0ie",
3183	description: Some(
3184	"PHY error 0 interrupt enable This bit enables the interrupt generation on PHY error 0.",
3185	),
3186	bit_offset: BitOffset::Regular(
3187	RegularBitOffset {
3188	offset: `16`,
3189	},
3190	),
3191	bit_size: `1`,
3192	array: None,
3193	enumm: None,
3194	},
3195	Field {
3196	name: "pe1ie",
3197	description: Some(
3198	"PHY error 1 interrupt enable This bit enables the interrupt generation on PHY error 1.",
3199	),
3200	bit_offset: BitOffset::Regular(
3201	RegularBitOffset {
3202	offset: `17`,
3203	},
3204	),
3205	bit_size: `1`,
3206	array: None,
3207	enumm: None,
3208	},
3209	Field {
3210	name: "pe2ie",
3211	description: Some(
3212	"PHY error 2 interrupt enable This bit enables the interrupt generation on PHY error 2.",
3213	),
3214	bit_offset: BitOffset::Regular(
3215	RegularBitOffset {
3216	offset: `18`,
3217	},
3218	),
3219	bit_size: `1`,
3220	array: None,
3221	enumm: None,
3222	},
3223	Field {
3224	name: "pe3ie",
3225	description: Some(
3226	"PHY error 3 interrupt enable This bit enables the interrupt generation on PHY error 4.",
3227	),
3228	bit_offset: BitOffset::Regular(
3229	RegularBitOffset {
3230	offset: `19`,
3231	},
3232	),
3233	bit_size: `1`,
3234	array: None,
3235	enumm: None,
3236	},
3237	Field {
3238	name: "pe4ie",
3239	description: Some(
3240	"PHY error 4 interrupt enable This bit enables the interrupt generation on PHY error 4.",
3241	),
3242	bit_offset: BitOffset::Regular(
3243	RegularBitOffset {
3244	offset: `20`,
3245	},
3246	),
3247	bit_size: `1`,
3248	array: None,
3249	enumm: None,
3250	},
3251	],
3252	},
3253	FieldSet {
3254	name: "Ier1",
3255	extends: None,
3256	description: Some(
3257	"DSI Host interrupt enable register 1.",
3258	),
3259	bit_size: `32`,
3260	fields: &[
3261	Field {
3262	name: "tohstxie",
3263	description: Some(
3264	"Timeout high-speed transmission interrupt enable This bit enables the interrupt generation on timeout high-speed transmission.",
3265	),
3266	bit_offset: BitOffset::Regular(
3267	RegularBitOffset {
3268	offset: `0`,
3269	},
3270	),
3271	bit_size: `1`,
3272	array: None,
3273	enumm: None,
3274	},
3275	Field {
3276	name: "tolprxie",
3277	description: Some(
3278	"Timeout low-power reception interrupt enable This bit enables the interrupt generation on timeout low-power reception.",
3279	),
3280	bit_offset: BitOffset::Regular(
3281	RegularBitOffset {
3282	offset: `1`,
3283	},
3284	),
3285	bit_size: `1`,
3286	array: None,
3287	enumm: None,
3288	},
3289	Field {
3290	name: "eccseie",
3291	description: Some(
3292	"ECC single-bit error interrupt enable This bit enables the interrupt generation on ECC single-bit error.",
3293	),
3294	bit_offset: BitOffset::Regular(
3295	RegularBitOffset {
3296	offset: `2`,
3297	},
3298	),
3299	bit_size: `1`,
3300	array: None,
3301	enumm: None,
3302	},
3303	Field {
3304	name: "eccmeie",
3305	description: Some(
3306	"ECC multi-bit error interrupt enable This bit enables the interrupt generation on ECC multi-bit error.",
3307	),
3308	bit_offset: BitOffset::Regular(
3309	RegularBitOffset {
3310	offset: `3`,
3311	},
3312	),
3313	bit_size: `1`,
3314	array: None,
3315	enumm: None,
3316	},
3317	Field {
3318	name: "crceie",
3319	description: Some(
3320	"CRC error interrupt enable This bit enables the interrupt generation on CRC error.",
3321	),
3322	bit_offset: BitOffset::Regular(
3323	RegularBitOffset {
3324	offset: `4`,
3325	},
3326	),
3327	bit_size: `1`,
3328	array: None,
3329	enumm: None,
3330	},
3331	Field {
3332	name: "pseie",
3333	description: Some(
3334	"Packet size error interrupt enable This bit enables the interrupt generation on packet size error.",
3335	),
3336	bit_offset: BitOffset::Regular(
3337	RegularBitOffset {
3338	offset: `5`,
3339	},
3340	),
3341	bit_size: `1`,
3342	array: None,
3343	enumm: None,
3344	},
3345	Field {
3346	name: "eotpeie",
3347	description: Some(
3348	"EoTp error interrupt enable This bit enables the interrupt generation on EoTp error.",
3349	),
3350	bit_offset: BitOffset::Regular(
3351	RegularBitOffset {
3352	offset: `6`,
3353	},
3354	),
3355	bit_size: `1`,
3356	array: None,
3357	enumm: None,
3358	},
3359	Field {
3360	name: "lpwreie",
3361	description: Some(
3362	"LTDC payload write error interrupt enable This bit enables the interrupt generation on LTDC payload write error.",
3363	),
3364	bit_offset: BitOffset::Regular(
3365	RegularBitOffset {
3366	offset: `7`,
3367	},
3368	),
3369	bit_size: `1`,
3370	array: None,
3371	enumm: None,
3372	},
3373	Field {
3374	name: "gcwreie",
3375	description: Some(
3376	"Generic command write error interrupt enable This bit enables the interrupt generation on generic command write error.",
3377	),
3378	bit_offset: BitOffset::Regular(
3379	RegularBitOffset {
3380	offset: `8`,
3381	},
3382	),
3383	bit_size: `1`,
3384	array: None,
3385	enumm: None,
3386	},
3387	Field {
3388	name: "gpwreie",
3389	description: Some(
3390	"Generic payload write error interrupt enable This bit enables the interrupt generation on generic payload write error.",
3391	),
3392	bit_offset: BitOffset::Regular(
3393	RegularBitOffset {
3394	offset: `9`,
3395	},
3396	),
3397	bit_size: `1`,
3398	array: None,
3399	enumm: None,
3400	},
3401	Field {
3402	name: "gptxeie",
3403	description: Some(
3404	"Generic payload transmit error interrupt enable This bit enables the interrupt generation on generic payload transmit error.",
3405	),
3406	bit_offset: BitOffset::Regular(
3407	RegularBitOffset {
3408	offset: `10`,
3409	},
3410	),
3411	bit_size: `1`,
3412	array: None,
3413	enumm: None,
3414	},
3415	Field {
3416	name: "gprdeie",
3417	description: Some(
3418	"Generic payload read error interrupt enable This bit enables the interrupt generation on generic payload read error.",
3419	),
3420	bit_offset: BitOffset::Regular(
3421	RegularBitOffset {
3422	offset: `11`,
3423	},
3424	),
3425	bit_size: `1`,
3426	array: None,
3427	enumm: None,
3428	},
3429	Field {
3430	name: "gprxeie",
3431	description: Some(
3432	"Generic payload receive error interrupt enable This bit enables the interrupt generation on generic payload receive error.",
3433	),
3434	bit_offset: BitOffset::Regular(
3435	RegularBitOffset {
3436	offset: `12`,
3437	},
3438	),
3439	bit_size: `1`,
3440	array: None,
3441	enumm: None,
3442	},
3443	Field {
3444	name: "pbueie",
3445	description: Some(
3446	"Payload buffer underflow error interrupt enable This bit enables the interrupt generation on payload buffer underflow error.",
3447	),
3448	bit_offset: BitOffset::Regular(
3449	RegularBitOffset {
3450	offset: `19`,
3451	},
3452	),
3453	bit_size: `1`,
3454	array: None,
3455	enumm: None,
3456	},
3457	],
3458	},
3459	FieldSet {
3460	name: "Isr0",
3461	extends: None,
3462	description: Some(
3463	"DSI Host interrupt and status register 0.",
3464	),
3465	bit_size: `32`,
3466	fields: &[
3467	Field {
3468	name: "ae0",
3469	description: Some(
3470	"Acknowledge error 0 This bit retrieves the SoT error from the acknowledge error report.",
3471	),
3472	bit_offset: BitOffset::Regular(
3473	RegularBitOffset {
3474	offset: `0`,
3475	},
3476	),
3477	bit_size: `1`,
3478	array: None,
3479	enumm: None,
3480	},
3481	Field {
3482	name: "ae1",
3483	description: Some(
3484	"Acknowledge error 1 This bit retrieves the SoT sync error from the acknowledge error report.",
3485	),
3486	bit_offset: BitOffset::Regular(
3487	RegularBitOffset {
3488	offset: `1`,
3489	},
3490	),
3491	bit_size: `1`,
3492	array: None,
3493	enumm: None,
3494	},
3495	Field {
3496	name: "ae2",
3497	description: Some(
3498	"Acknowledge error 2 This bit retrieves the EoT sync error from the acknowledge error report.",
3499	),
3500	bit_offset: BitOffset::Regular(
3501	RegularBitOffset {
3502	offset: `2`,
3503	},
3504	),
3505	bit_size: `1`,
3506	array: None,
3507	enumm: None,
3508	},
3509	Field {
3510	name: "ae3",
3511	description: Some(
3512	"Acknowledge error 3 This bit retrieves the escape mode entry command error from the acknowledge error report.",
3513	),
3514	bit_offset: BitOffset::Regular(
3515	RegularBitOffset {
3516	offset: `3`,
3517	},
3518	),
3519	bit_size: `1`,
3520	array: None,
3521	enumm: None,
3522	},
3523	Field {
3524	name: "ae4",
3525	description: Some(
3526	"Acknowledge error 4 This bit retrieves the LP transmit sync error from the acknowledge error report.",
3527	),
3528	bit_offset: BitOffset::Regular(
3529	RegularBitOffset {
3530	offset: `4`,
3531	},
3532	),
3533	bit_size: `1`,
3534	array: None,
3535	enumm: None,
3536	},
3537	Field {
3538	name: "ae5",
3539	description: Some(
3540	"Acknowledge error 5 This bit retrieves the peripheral timeout error from the acknowledge error report.",
3541	),
3542	bit_offset: BitOffset::Regular(
3543	RegularBitOffset {
3544	offset: `5`,
3545	},
3546	),
3547	bit_size: `1`,
3548	array: None,
3549	enumm: None,
3550	},
3551	Field {
3552	name: "ae6",
3553	description: Some(
3554	"Acknowledge error 6 This bit retrieves the false control error from the acknowledge error report.",
3555	),
3556	bit_offset: BitOffset::Regular(
3557	RegularBitOffset {
3558	offset: `6`,
3559	},
3560	),
3561	bit_size: `1`,
3562	array: None,
3563	enumm: None,
3564	},
3565	Field {
3566	name: "ae7",
3567	description: Some(
3568	"Acknowledge error 7 This bit retrieves the reserved (specific to the device) from the acknowledge error report.",
3569	),
3570	bit_offset: BitOffset::Regular(
3571	RegularBitOffset {
3572	offset: `7`,
3573	},
3574	),
3575	bit_size: `1`,
3576	array: None,
3577	enumm: None,
3578	},
3579	Field {
3580	name: "ae8",
3581	description: Some(
3582	"Acknowledge error 8 This bit retrieves the ECC error, single-bit (detected and corrected) from the acknowledge error report.",
3583	),
3584	bit_offset: BitOffset::Regular(
3585	RegularBitOffset {
3586	offset: `8`,
3587	},
3588	),
3589	bit_size: `1`,
3590	array: None,
3591	enumm: None,
3592	},
3593	Field {
3594	name: "ae9",
3595	description: Some(
3596	"Acknowledge error 9 This bit retrieves the ECC error, multi-bit (detected, not corrected) from the acknowledge error report.",
3597	),
3598	bit_offset: BitOffset::Regular(
3599	RegularBitOffset {
3600	offset: `9`,
3601	},
3602	),
3603	bit_size: `1`,
3604	array: None,
3605	enumm: None,
3606	},
3607	Field {
3608	name: "ae10",
3609	description: Some(
3610	"Acknowledge error 10 This bit retrieves the checksum error (long packet only) from the acknowledge error report.",
3611	),
3612	bit_offset: BitOffset::Regular(
3613	RegularBitOffset {
3614	offset: `10`,
3615	},
3616	),
3617	bit_size: `1`,
3618	array: None,
3619	enumm: None,
3620	},
3621	Field {
3622	name: "ae11",
3623	description: Some(
3624	"Acknowledge error 11 This bit retrieves the not recognized DSI data type from the acknowledge error report.",
3625	),
3626	bit_offset: BitOffset::Regular(
3627	RegularBitOffset {
3628	offset: `11`,
3629	},
3630	),
3631	bit_size: `1`,
3632	array: None,
3633	enumm: None,
3634	},
3635	Field {
3636	name: "ae12",
3637	description: Some(
3638	"Acknowledge error 12 This bit retrieves the DSI VC ID Invalid from the acknowledge error report.",
3639	),
3640	bit_offset: BitOffset::Regular(
3641	RegularBitOffset {
3642	offset: `12`,
3643	},
3644	),
3645	bit_size: `1`,
3646	array: None,
3647	enumm: None,
3648	},
3649	Field {
3650	name: "ae13",
3651	description: Some(
3652	"Acknowledge error 13 This bit retrieves the invalid transmission length from the acknowledge error report.",
3653	),
3654	bit_offset: BitOffset::Regular(
3655	RegularBitOffset {
3656	offset: `13`,
3657	},
3658	),
3659	bit_size: `1`,
3660	array: None,
3661	enumm: None,
3662	},
3663	Field {
3664	name: "ae14",
3665	description: Some(
3666	"Acknowledge error 14 This bit retrieves the reserved (specific to the device) from the acknowledge error report.",
3667	),
3668	bit_offset: BitOffset::Regular(
3669	RegularBitOffset {
3670	offset: `14`,
3671	},
3672	),
3673	bit_size: `1`,
3674	array: None,
3675	enumm: None,
3676	},
3677	Field {
3678	name: "ae15",
3679	description: Some(
3680	"Acknowledge error 15 This bit retrieves the DSI protocol violation from the acknowledge error report.",
3681	),
3682	bit_offset: BitOffset::Regular(
3683	RegularBitOffset {
3684	offset: `15`,
3685	},
3686	),
3687	bit_size: `1`,
3688	array: None,
3689	enumm: None,
3690	},
3691	Field {
3692	name: "pe0",
3693	description: Some(
3694	"PHY error 0 This bit indicates the ErrEsc escape entry error from lane 0.",
3695	),
3696	bit_offset: BitOffset::Regular(
3697	RegularBitOffset {
3698	offset: `16`,
3699	},
3700	),
3701	bit_size: `1`,
3702	array: None,
3703	enumm: None,
3704	},
3705	Field {
3706	name: "pe1",
3707	description: Some(
3708	"PHY error 1 This bit indicates the ErrSyncEsc low-power transmission synchronization error from lane 0.",
3709	),
3710	bit_offset: BitOffset::Regular(
3711	RegularBitOffset {
3712	offset: `17`,
3713	},
3714	),
3715	bit_size: `1`,
3716	array: None,
3717	enumm: None,
3718	},
3719	Field {
3720	name: "pe2",
3721	description: Some(
3722	"PHY error 2 This bit indicates the ErrControl error from lane 0.",
3723	),
3724	bit_offset: BitOffset::Regular(
3725	RegularBitOffset {
3726	offset: `18`,
3727	},
3728	),
3729	bit_size: `1`,
3730	array: None,
3731	enumm: None,
3732	},
3733	Field {
3734	name: "pe3",
3735	description: Some(
3736	"PHY error 3 This bit indicates the LP0 contention error ErrContentionLP0 from lane 0.",
3737	),
3738	bit_offset: BitOffset::Regular(
3739	RegularBitOffset {
3740	offset: `19`,
3741	},
3742	),
3743	bit_size: `1`,
3744	array: None,
3745	enumm: None,
3746	},
3747	Field {
3748	name: "pe4",
3749	description: Some(
3750	"PHY error 4 This bit indicates the LP1 contention error ErrContentionLP1 from lane 0.",
3751	),
3752	bit_offset: BitOffset::Regular(
3753	RegularBitOffset {
3754	offset: `20`,
3755	},
3756	),
3757	bit_size: `1`,
3758	array: None,
3759	enumm: None,
3760	},
3761	],
3762	},
3763	FieldSet {
3764	name: "Isr1",
3765	extends: None,
3766	description: Some(
3767	"DSI Host interrupt and status register 1.",
3768	),
3769	bit_size: `32`,
3770	fields: &[
3771	Field {
3772	name: "tohstx",
3773	description: Some(
3774	"Timeout high-speed transmission This bit indicates that the high-speed transmission timeout counter reached the end and contention is detected.",
3775	),
3776	bit_offset: BitOffset::Regular(
3777	RegularBitOffset {
3778	offset: `0`,
3779	},
3780	),
3781	bit_size: `1`,
3782	array: None,
3783	enumm: None,
3784	},
3785	Field {
3786	name: "tolprx",
3787	description: Some(
3788	"Timeout low-power reception This bit indicates that the low-power reception timeout counter reached the end and contention is detected.",
3789	),
3790	bit_offset: BitOffset::Regular(
3791	RegularBitOffset {
3792	offset: `1`,
3793	},
3794	),
3795	bit_size: `1`,
3796	array: None,
3797	enumm: None,
3798	},
3799	Field {
3800	name: "eccse",
3801	description: Some(
3802	"ECC single-bit error This bit indicates that the ECC single error is detected and corrected in a received packet.",
3803	),
3804	bit_offset: BitOffset::Regular(
3805	RegularBitOffset {
3806	offset: `2`,
3807	},
3808	),
3809	bit_size: `1`,
3810	array: None,
3811	enumm: None,
3812	},
3813	Field {
3814	name: "eccme",
3815	description: Some(
3816	"ECC multi-bit error This bit indicates that the ECC multiple error is detected in a received packet.",
3817	),
3818	bit_offset: BitOffset::Regular(
3819	RegularBitOffset {
3820	offset: `3`,
3821	},
3822	),
3823	bit_size: `1`,
3824	array: None,
3825	enumm: None,
3826	},
3827	Field {
3828	name: "crce",
3829	description: Some(
3830	"CRC error This bit indicates that the CRC error is detected in the received packet payload.",
3831	),
3832	bit_offset: BitOffset::Regular(
3833	RegularBitOffset {
3834	offset: `4`,
3835	},
3836	),
3837	bit_size: `1`,
3838	array: None,
3839	enumm: None,
3840	},
3841	Field {
3842	name: "pse",
3843	description: Some(
3844	"Packet size error This bit indicates that the packet size error is detected during the packet reception.",
3845	),
3846	bit_offset: BitOffset::Regular(
3847	RegularBitOffset {
3848	offset: `5`,
3849	},
3850	),
3851	bit_size: `1`,
3852	array: None,
3853	enumm: None,
3854	},
3855	Field {
3856	name: "eotpe",
3857	description: Some(
3858	"EoTp error This bit indicates that the EoTp packet is not received at the end of the incoming peripheral transmission.",
3859	),
3860	bit_offset: BitOffset::Regular(
3861	RegularBitOffset {
3862	offset: `6`,
3863	},
3864	),
3865	bit_size: `1`,
3866	array: None,
3867	enumm: None,
3868	},
3869	Field {
3870	name: "lpwre",
3871	description: Some(
3872	"LTDC payload write error This bit indicates that during a DPI pixel line storage, the payload FIFO becomes full and the data stored is corrupted.",
3873	),
3874	bit_offset: BitOffset::Regular(
3875	RegularBitOffset {
3876	offset: `7`,
3877	},
3878	),
3879	bit_size: `1`,
3880	array: None,
3881	enumm: None,
3882	},
3883	Field {
3884	name: "gcwre",
3885	description: Some(
3886	"Generic command write error This bit indicates that the system tried to write a command through the generic interface and the FIFO is full. Therefore, the command is not written.",
3887	),
3888	bit_offset: BitOffset::Regular(
3889	RegularBitOffset {
3890	offset: `8`,
3891	},
3892	),
3893	bit_size: `1`,
3894	array: None,
3895	enumm: None,
3896	},
3897	Field {
3898	name: "gpwre",
3899	description: Some(
3900	"Generic payload write error This bit indicates that the system tried to write a payload data through the generic interface and the FIFO is full. Therefore, the payload is not written.",
3901	),
3902	bit_offset: BitOffset::Regular(
3903	RegularBitOffset {
3904	offset: `9`,
3905	},
3906	),
3907	bit_size: `1`,
3908	array: None,
3909	enumm: None,
3910	},
3911	Field {
3912	name: "gptxe",
3913	description: Some(
3914	"Generic payload transmit error This bit indicates that during a generic interface packet build, the payload FIFO becomes empty and corrupt data is sent.",
3915	),
3916	bit_offset: BitOffset::Regular(
3917	RegularBitOffset {
3918	offset: `10`,
3919	},
3920	),
3921	bit_size: `1`,
3922	array: None,
3923	enumm: None,
3924	},
3925	Field {
3926	name: "gprde",
3927	description: Some(
3928	"Generic payload read error This bit indicates that during a DCS read data, the payload FIFO becomes empty and the data sent to the interface is corrupted.",
3929	),
3930	bit_offset: BitOffset::Regular(
3931	RegularBitOffset {
3932	offset: `11`,
3933	},
3934	),
3935	bit_size: `1`,
3936	array: None,
3937	enumm: None,
3938	},
3939	Field {
3940	name: "gprxe",
3941	description: Some(
3942	"Generic payload receive error This bit indicates that during a generic interface packet read back, the payload FIFO becomes full and the received data is corrupted.",
3943	),
3944	bit_offset: BitOffset::Regular(
3945	RegularBitOffset {
3946	offset: `12`,
3947	},
3948	),
3949	bit_size: `1`,
3950	array: None,
3951	enumm: None,
3952	},
3953	Field {
3954	name: "pbue",
3955	description: Some(
3956	"Payload buffer underflow error This bit indicates that underflow has occurred when reading payload to build DSI packet for video mode.",
3957	),
3958	bit_offset: BitOffset::Regular(
3959	RegularBitOffset {
3960	offset: `19`,
3961	},
3962	),
3963	bit_size: `1`,
3964	array: None,
3965	enumm: None,
3966	},
3967	],
3968	},
3969	FieldSet {
3970	name: "Lcccr",
3971	extends: None,
3972	description: Some(
3973	"DSI Host LTDC current color coding register.",
3974	),
3975	bit_size: `32`,
3976	fields: &[
3977	Field {
3978	name: "colc",
3979	description: Some(
3980	"Color coding This field returns the current LTDC interface color coding. 0110-1111: reserved If LTDC interface in command mode is chosen and currently works in the command mode (CMDM=1), then 0110-1111: 24-bit.",
3981	),
3982	bit_offset: BitOffset::Regular(
3983	RegularBitOffset {
3984	offset: `0`,
3985	},
3986	),
3987	bit_size: `4`,
3988	array: None,
3989	enumm: None,
3990	},
3991	Field {
3992	name: "lpe",
3993	description: Some(
3994	"Loosely packed enable This bit returns the current state of the loosely packed variant to 18-bit configurations.",
3995	),
3996	bit_offset: BitOffset::Regular(
3997	RegularBitOffset {
3998	offset: `8`,
3999	},
4000	),
4001	bit_size: `1`,
4002	array: None,
4003	enumm: None,
4004	},
4005	],
4006	},
4007	FieldSet {
4008	name: "Lccr",
4009	extends: None,
4010	description: Some(
4011	"DSI Host LTDC command configuration register.",
4012	),
4013	bit_size: `32`,
4014	fields: &[
4015	Field {
4016	name: "cmdsize",
4017	description: Some(
4018	"Command size This field configures the maximum allowed size for an LTDC write memory command, measured in pixels. Automatic partitioning of data obtained from LTDC is permanently enabled.",
4019	),
4020	bit_offset: BitOffset::Regular(
4021	RegularBitOffset {
4022	offset: `0`,
4023	},
4024	),
4025	bit_size: `16`,
4026	array: None,
4027	enumm: None,
4028	},
4029	],
4030	},
4031	FieldSet {
4032	name: "Lcolcr",
4033	extends: None,
4034	description: Some(
4035	"DSI Host LTDC color coding register.",
4036	),
4037	bit_size: `32`,
4038	fields: &[
4039	Field {
4040	name: "colc",
4041	description: Some(
4042	"Color coding This field configures the DPI color coding. Others: Reserved.",
4043	),
4044	bit_offset: BitOffset::Regular(
4045	RegularBitOffset {
4046	offset: `0`,
4047	},
4048	),
4049	bit_size: `4`,
4050	array: None,
4051	enumm: None,
4052	},
4053	Field {
4054	name: "lpe",
4055	description: Some(
4056	"Loosely packet enable This bit enables the loosely packed variant to 18-bit configuration.",
4057	),
4058	bit_offset: BitOffset::Regular(
4059	RegularBitOffset {
4060	offset: `8`,
4061	},
4062	),
4063	bit_size: `1`,
4064	array: None,
4065	enumm: None,
4066	},
4067	],
4068	},
4069	FieldSet {
4070	name: "Lcvcidr",
4071	extends: None,
4072	description: Some(
4073	"DSI Host LTDC current VCID register.",
4074	),
4075	bit_size: `32`,
4076	fields: &[
4077	Field {
4078	name: "vcid",
4079	description: Some(
4080	"Virtual channel ID This field returns the virtual channel ID for the LTDC interface.",
4081	),
4082	bit_offset: BitOffset::Regular(
4083	RegularBitOffset {
4084	offset: `0`,
4085	},
4086	),
4087	bit_size: `2`,
4088	array: None,
4089	enumm: None,
4090	},
4091	],
4092	},
4093	FieldSet {
4094	name: "Lpcr",
4095	extends: None,
4096	description: Some(
4097	"DSI Host LTDC polarity configuration register.",
4098	),
4099	bit_size: `32`,
4100	fields: &[
4101	Field {
4102	name: "dep",
4103	description: Some(
4104	"Data enable polarity This bit configures the polarity of data enable pin.",
4105	),
4106	bit_offset: BitOffset::Regular(
4107	RegularBitOffset {
4108	offset: `0`,
4109	},
4110	),
4111	bit_size: `1`,
4112	array: None,
4113	enumm: None,
4114	},
4115	Field {
4116	name: "vsp",
4117	description: Some(
4118	"VSYNC polarity This bit configures the polarity of VSYNC pin.",
4119	),
4120	bit_offset: BitOffset::Regular(
4121	RegularBitOffset {
4122	offset: `1`,
4123	},
4124	),
4125	bit_size: `1`,
4126	array: None,
4127	enumm: None,
4128	},
4129	Field {
4130	name: "hsp",
4131	description: Some(
4132	"HSYNC polarity This bit configures the polarity of HSYNC pin.",
4133	),
4134	bit_offset: BitOffset::Regular(
4135	RegularBitOffset {
4136	offset: `2`,
4137	},
4138	),
4139	bit_size: `1`,
4140	array: None,
4141	enumm: None,
4142	},
4143	],
4144	},
4145	FieldSet {
4146	name: "Lpmccr",
4147	extends: None,
4148	description: Some(
4149	"DSI Host low-power mode current configuration register.",
4150	),
4151	bit_size: `32`,
4152	fields: &[
4153	Field {
4154	name: "vlpsize",
4155	description: Some(
4156	"VACT largest packet size This field returns the current size, in bytes, of the largest packet that can fit in a line during VACT regions, for the transmission of commands in low-power mode.",
4157	),
4158	bit_offset: BitOffset::Regular(
4159	RegularBitOffset {
4160	offset: `0`,
4161	},
4162	),
4163	bit_size: `8`,
4164	array: None,
4165	enumm: None,
4166	},
4167	Field {
4168	name: "lpsize",
4169	description: Some(
4170	"Largest packet size This field is returns the current size, in bytes, of the largest packet that can fit in a line during VSA, VBP and VFP regions, for the transmission of commands in low-power mode.",
4171	),
4172	bit_offset: BitOffset::Regular(
4173	RegularBitOffset {
4174	offset: `16`,
4175	},
4176	),
4177	bit_size: `8`,
4178	array: None,
4179	enumm: None,
4180	},
4181	],
4182	},
4183	FieldSet {
4184	name: "Lpmcr",
4185	extends: None,
4186	description: Some(
4187	"DSI Host low-power mode configuration register.",
4188	),
4189	bit_size: `32`,
4190	fields: &[
4191	Field {
4192	name: "vlpsize",
4193	description: Some(
4194	"VACT largest packet size This field is used for the transmission of commands in low-power mode. It defines the size, in bytes, of the largest packet that can fit in a line during VACT regions.",
4195	),
4196	bit_offset: BitOffset::Regular(
4197	RegularBitOffset {
4198	offset: `0`,
4199	},
4200	),
4201	bit_size: `8`,
4202	array: None,
4203	enumm: None,
4204	},
4205	Field {
4206	name: "lpsize",
4207	description: Some(
4208	"Largest packet size This field is used for the transmission of commands in low-power mode. It defines the size, in bytes, of the largest packet that can fit in a line during VSA, VBP and VFP regions.",
4209	),
4210	bit_offset: BitOffset::Regular(
4211	RegularBitOffset {
4212	offset: `16`,
4213	},
4214	),
4215	bit_size: `8`,
4216	array: None,
4217	enumm: None,
4218	},
4219	],
4220	},
4221	FieldSet {
4222	name: "Lvcidr",
4223	extends: None,
4224	description: Some(
4225	"DSI Host LTDC VCID register.",
4226	),
4227	bit_size: `32`,
4228	fields: &[
4229	Field {
4230	name: "vcid",
4231	description: Some(
4232	"Virtual channel ID These bits configure the virtual channel ID for the LTDC interface traffic.",
4233	),
4234	bit_offset: BitOffset::Regular(
4235	RegularBitOffset {
4236	offset: `0`,
4237	},
4238	),
4239	bit_size: `2`,
4240	array: None,
4241	enumm: None,
4242	},
4243	],
4244	},
4245	FieldSet {
4246	name: "Mcr",
4247	extends: None,
4248	description: Some(
4249	"DSI Host mode configuration register.",
4250	),
4251	bit_size: `32`,
4252	fields: &[
4253	Field {
4254	name: "cmdm",
4255	description: Some(
4256	"Command mode This bit configures the DSI Host in either video or command mode.",
4257	),
4258	bit_offset: BitOffset::Regular(
4259	RegularBitOffset {
4260	offset: `0`,
4261	},
4262	),
4263	bit_size: `1`,
4264	array: None,
4265	enumm: None,
4266	},
4267	],
4268	},
4269	FieldSet {
4270	name: "Pconfr",
4271	extends: None,
4272	description: Some(
4273	"DSI Host PHY configuration register.",
4274	),
4275	bit_size: `32`,
4276	fields: &[
4277	Field {
4278	name: "nl",
4279	description: Some(
4280	"Number of lanes This field configures the number of active data lanes: Others: Reserved.",
4281	),
4282	bit_offset: BitOffset::Regular(
4283	RegularBitOffset {
4284	offset: `0`,
4285	},
4286	),
4287	bit_size: `2`,
4288	array: None,
4289	enumm: None,
4290	},
4291	Field {
4292	name: "sw_time",
4293	description: Some(
4294	"Stop wait time This field configures the minimum wait period to request a high-speed transmission after the Stop state.",
4295	),
4296	bit_offset: BitOffset::Regular(
4297	RegularBitOffset {
4298	offset: `8`,
4299	},
4300	),
4301	bit_size: `8`,
4302	array: None,
4303	enumm: None,
4304	},
4305	],
4306	},
4307	FieldSet {
4308	name: "Pcr",
4309	extends: None,
4310	description: Some(
4311	"DSI Host protocol configuration register.",
4312	),
4313	bit_size: `32`,
4314	fields: &[
4315	Field {
4316	name: "ettxe",
4317	description: Some(
4318	"EoTp transmission enable This bit enables the EoTP transmission.",
4319	),
4320	bit_offset: BitOffset::Regular(
4321	RegularBitOffset {
4322	offset: `0`,
4323	},
4324	),
4325	bit_size: `1`,
4326	array: None,
4327	enumm: None,
4328	},
4329	Field {
4330	name: "etrxe",
4331	description: Some(
4332	"EoTp reception enable This bit enables the EoTp reception.",
4333	),
4334	bit_offset: BitOffset::Regular(
4335	RegularBitOffset {
4336	offset: `1`,
4337	},
4338	),
4339	bit_size: `1`,
4340	array: None,
4341	enumm: None,
4342	},
4343	Field {
4344	name: "btae",
4345	description: Some(
4346	"Bus-turn-around enable This bit enables the bus-turn-around (BTA) request.",
4347	),
4348	bit_offset: BitOffset::Regular(
4349	RegularBitOffset {
4350	offset: `2`,
4351	},
4352	),
4353	bit_size: `1`,
4354	array: None,
4355	enumm: None,
4356	},
4357	Field {
4358	name: "eccrxe",
4359	description: Some(
4360	"ECC reception enable This bit enables the ECC reception, error correction and reporting.",
4361	),
4362	bit_offset: BitOffset::Regular(
4363	RegularBitOffset {
4364	offset: `3`,
4365	},
4366	),
4367	bit_size: `1`,
4368	array: None,
4369	enumm: None,
4370	},
4371	Field {
4372	name: "crcrxe",
4373	description: Some(
4374	"CRC reception enable This bit enables the CRC reception and error reporting.",
4375	),
4376	bit_offset: BitOffset::Regular(
4377	RegularBitOffset {
4378	offset: `4`,
4379	},
4380	),
4381	bit_size: `1`,
4382	array: None,
4383	enumm: None,
4384	},
4385	Field {
4386	name: "ettxlpe",
4387	description: Some(
4388	"EoTp transmission in low-power enable This bit enables the EoTP transmission in low-power.",
4389	),
4390	bit_offset: BitOffset::Regular(
4391	RegularBitOffset {
4392	offset: `5`,
4393	},
4394	),
4395	bit_size: `1`,
4396	array: None,
4397	enumm: None,
4398	},
4399	],
4400	},
4401	FieldSet {
4402	name: "Pctlr",
4403	extends: None,
4404	description: Some(
4405	"DSI Host PHY control register.",
4406	),
4407	bit_size: `32`,
4408	fields: &[
4409	Field {
4410	name: "den",
4411	description: Some(
4412	"Digital enable When set to 0, this bit places the digital section of the D-PHY in the reset state.",
4413	),
4414	bit_offset: BitOffset::Regular(
4415	RegularBitOffset {
4416	offset: `1`,
4417	},
4418	),
4419	bit_size: `1`,
4420	array: None,
4421	enumm: None,
4422	},
4423	Field {
4424	name: "cke",
4425	description: Some(
4426	"Clock enable This bit enables the D-PHY clock lane module:.",
4427	),
4428	bit_offset: BitOffset::Regular(
4429	RegularBitOffset {
4430	offset: `2`,
4431	},
4432	),
4433	bit_size: `1`,
4434	array: None,
4435	enumm: None,
4436	},
4437	],
4438	},
4439	FieldSet {
4440	name: "Psr",
4441	extends: None,
4442	description: Some(
4443	"DSI Host PHY status register.",
4444	),
4445	bit_size: `32`,
4446	fields: &[
4447	Field {
4448	name: "pd",
4449	description: Some(
4450	"PHY direction This bit indicates the status of phydirection D-PHY signal.",
4451	),
4452	bit_offset: BitOffset::Regular(
4453	RegularBitOffset {
4454	offset: `1`,
4455	},
4456	),
4457	bit_size: `1`,
4458	array: None,
4459	enumm: None,
4460	},
4461	Field {
4462	name: "pssc",
4463	description: Some(
4464	"PHY stop state clock lane This bit indicates the status of phystopstateclklane D-PHY signal.",
4465	),
4466	bit_offset: BitOffset::Regular(
4467	RegularBitOffset {
4468	offset: `2`,
4469	},
4470	),
4471	bit_size: `1`,
4472	array: None,
4473	enumm: None,
4474	},
4475	Field {
4476	name: "uanc",
4477	description: Some(
4478	"ULPS active not clock lane This bit indicates the status of ulpsactivenotclklane D-PHY signal.",
4479	),
4480	bit_offset: BitOffset::Regular(
4481	RegularBitOffset {
4482	offset: `3`,
4483	},
4484	),
4485	bit_size: `1`,
4486	array: None,
4487	enumm: None,
4488	},
4489	Field {
4490	name: "pss0",
4491	description: Some(
4492	"PHY stop state lane 0 This bit indicates the status of phystopstate0lane D-PHY signal.",
4493	),
4494	bit_offset: BitOffset::Regular(
4495	RegularBitOffset {
4496	offset: `4`,
4497	},
4498	),
4499	bit_size: `1`,
4500	array: None,
4501	enumm: None,
4502	},
4503	Field {
4504	name: "uan0",
4505	description: Some(
4506	"ULPS active not lane 1 This bit indicates the status of ulpsactivenot0lane D-PHY signal.",
4507	),
4508	bit_offset: BitOffset::Regular(
4509	RegularBitOffset {
4510	offset: `5`,
4511	},
4512	),
4513	bit_size: `1`,
4514	array: None,
4515	enumm: None,
4516	},
4517	Field {
4518	name: "rue0",
4519	description: Some(
4520	"RX ULPS escape lane 0 This bit indicates the status of rxulpsesc0lane D-PHY signal.",
4521	),
4522	bit_offset: BitOffset::Regular(
4523	RegularBitOffset {
4524	offset: `6`,
4525	},
4526	),
4527	bit_size: `1`,
4528	array: None,
4529	enumm: None,
4530	},
4531	Field {
4532	name: "pss1",
4533	description: Some(
4534	"PHY stop state lane 1 This bit indicates the status of phystopstate1lane D-PHY signal.",
4535	),
4536	bit_offset: BitOffset::Regular(
4537	RegularBitOffset {
4538	offset: `7`,
4539	},
4540	),
4541	bit_size: `1`,
4542	array: None,
4543	enumm: None,
4544	},
4545	Field {
4546	name: "uan1",
4547	description: Some(
4548	"ULPS active not lane 1 This bit indicates the status of ulpsactivenot1lane D-PHY signal.",
4549	),
4550	bit_offset: BitOffset::Regular(
4551	RegularBitOffset {
4552	offset: `8`,
4553	},
4554	),
4555	bit_size: `1`,
4556	array: None,
4557	enumm: None,
4558	},
4559	],
4560	},
4561	FieldSet {
4562	name: "Pttcr",
4563	extends: None,
4564	description: Some(
4565	"DSI Host PHY TX triggers configuration register.",
4566	),
4567	bit_size: `32`,
4568	fields: &[
4569	Field {
4570	name: "tx_trig",
4571	description: Some(
4572	"Transmission trigger Escape mode transmit trigger 0-3. Only one bit of TX_TRIG is asserted at any given time.",
4573	),
4574	bit_offset: BitOffset::Regular(
4575	RegularBitOffset {
4576	offset: `0`,
4577	},
4578	),
4579	bit_size: `4`,
4580	array: None,
4581	enumm: None,
4582	},
4583	],
4584	},
4585	FieldSet {
4586	name: "Pucr",
4587	extends: None,
4588	description: Some(
4589	"DSI Host PHY ULPS control register.",
4590	),
4591	bit_size: `32`,
4592	fields: &[
4593	Field {
4594	name: "urcl",
4595	description: Some(
4596	"ULPS request on clock lane ULPS mode request on clock lane.",
4597	),
4598	bit_offset: BitOffset::Regular(
4599	RegularBitOffset {
4600	offset: `0`,
4601	},
4602	),
4603	bit_size: `1`,
4604	array: None,
4605	enumm: None,
4606	},
4607	Field {
4608	name: "uecl",
4609	description: Some(
4610	"ULPS exit on clock lane ULPS mode exit on clock lane.",
4611	),
4612	bit_offset: BitOffset::Regular(
4613	RegularBitOffset {
4614	offset: `1`,
4615	},
4616	),
4617	bit_size: `1`,
4618	array: None,
4619	enumm: None,
4620	},
4621	Field {
4622	name: "urdl",
4623	description: Some(
4624	"ULPS request on data lane ULPS mode request on all active data lanes.",
4625	),
4626	bit_offset: BitOffset::Regular(
4627	RegularBitOffset {
4628	offset: `2`,
4629	},
4630	),
4631	bit_size: `1`,
4632	array: None,
4633	enumm: None,
4634	},
4635	Field {
4636	name: "uedl",
4637	description: Some(
4638	"ULPS exit on data lane ULPS mode exit on all active data lanes.",
4639	),
4640	bit_offset: BitOffset::Regular(
4641	RegularBitOffset {
4642	offset: `3`,
4643	},
4644	),
4645	bit_size: `1`,
4646	array: None,
4647	enumm: None,
4648	},
4649	],
4650	},
4651	FieldSet {
4652	name: "Tccr0",
4653	extends: None,
4654	description: Some(
4655	"DSI Host timeout counter configuration register 0.",
4656	),
4657	bit_size: `32`,
4658	fields: &[
4659	Field {
4660	name: "lprx_tocnt",
4661	description: Some(
4662	"Low-power reception timeout counter This field configures the timeout counter that triggers a low-power reception timeout contention detection (measured in TOCKDIV cycles).",
4663	),
4664	bit_offset: BitOffset::Regular(
4665	RegularBitOffset {
4666	offset: `0`,
4667	},
4668	),
4669	bit_size: `16`,
4670	array: None,
4671	enumm: None,
4672	},
4673	Field {
4674	name: "hstx_tocnt",
4675	description: Some(
4676	"High-speed transmission timeout counter This field configures the timeout counter that triggers a high-speed transmission timeout contention detection (measured in TOCKDIV cycles). If using the non-burst mode and there is no enough time to switch from high-speed to low-power and back in the period from one line data finishing to the next line sync start, the DSI link returns the low-power state once per frame, then configure the TOCKDIV and HSTX_TOCNT to be in accordance with: HSTX_TOCNT * lanebyteclkperiod * TOCKDIV â`\u{89}`¥ the time of one FRAME data transmission Â`\u{a0}`(1 + 10%) In burst mode, RGB pixel packets are time-compressed, leaving more time during a scan line. Therefore, if in burst mode and there is enough time to switch from high-speed to low-power and back in the period from one line data finishing to the next line sync start, the DSI link can return low-power mode and back in this time interval to save power. For this, configure the TOCKDIV and HSTX_TOCNT to be in accordance with: HSTX_TOCNT lanebyteclkperiod * TOCKDIV â`\u{89}`¥ the time of one LINE data transmission *Â`\u{a0}`(1Â`\u{a0}`+Â`\u{a0}`10%).",
4677	),
4678	bit_offset: BitOffset::Regular(
4679	RegularBitOffset {
4680	offset: `16`,
4681	},
4682	),
4683	bit_size: `16`,
4684	array: None,
4685	enumm: None,
4686	},
4687	],
4688	},
4689	FieldSet {
4690	name: "Tccr1",
4691	extends: None,
4692	description: Some(
4693	"DSI Host timeout counter configuration register 1.",
4694	),
4695	bit_size: `32`,
4696	fields: &[
4697	Field {
4698	name: "hsrd_tocnt",
4699	description: Some(
4700	"High-speed read timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a high-speed read operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts.",
4701	),
4702	bit_offset: BitOffset::Regular(
4703	RegularBitOffset {
4704	offset: `0`,
4705	},
4706	),
4707	bit_size: `16`,
4708	array: None,
4709	enumm: None,
4710	},
4711	],
4712	},
4713	FieldSet {
4714	name: "Tccr2",
4715	extends: None,
4716	description: Some(
4717	"DSI Host timeout counter configuration register 2.",
4718	),
4719	bit_size: `32`,
4720	fields: &[
4721	Field {
4722	name: "lprd_tocnt",
4723	description: Some(
4724	"Low-power read timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a low-power read operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts.",
4725	),
4726	bit_offset: BitOffset::Regular(
4727	RegularBitOffset {
4728	offset: `0`,
4729	},
4730	),
4731	bit_size: `16`,
4732	array: None,
4733	enumm: None,
4734	},
4735	],
4736	},
4737	FieldSet {
4738	name: "Tccr3",
4739	extends: None,
4740	description: Some(
4741	"DSI Host timeout counter configuration register 3.",
4742	),
4743	bit_size: `32`,
4744	fields: &[
4745	Field {
4746	name: "hswr_tocnt",
4747	description: Some(
4748	"High-speed write timeout counter This field sets a period for which the DSI Host keeps the link inactive after sending a high-speed write operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts.",
4749	),
4750	bit_offset: BitOffset::Regular(
4751	RegularBitOffset {
4752	offset: `0`,
4753	},
4754	),
4755	bit_size: `16`,
4756	array: None,
4757	enumm: None,
4758	},
4759	Field {
4760	name: "pm",
4761	description: Some(
4762	"Presp mode When set to 1, this bit ensures that the peripheral response timeout caused by HSWR_TOCNT is used only once per LTDC frame in command mode, when both the following conditions are met: dpivsync_edpiwms has risen and fallen. Packets originated from LTDC in command mode have been transmitted and its FIFO is empty again. In this scenario no non-LTDC command requests are sent to the D-PHY, even if there is traffic from generic interface ready to be sent, making it return to stop state. When it does so, PRESP_TO counter is activated and only when it finishes does the controller send any other traffic that is ready.",
4763	),
4764	bit_offset: BitOffset::Regular(
4765	RegularBitOffset {
4766	offset: `24`,
4767	},
4768	),
4769	bit_size: `1`,
4770	array: None,
4771	enumm: None,
4772	},
4773	],
4774	},
4775	FieldSet {
4776	name: "Tccr4",
4777	extends: None,
4778	description: Some(
4779	"DSI Host timeout counter configuration register 4.",
4780	),
4781	bit_size: `32`,
4782	fields: &[
4783	Field {
4784	name: "lpwr_tocnt",
4785	description: Some(
4786	"Low-power write timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a low-power write operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts.",
4787	),
4788	bit_offset: BitOffset::Regular(
4789	RegularBitOffset {
4790	offset: `0`,
4791	},
4792	),
4793	bit_size: `16`,
4794	array: None,
4795	enumm: None,
4796	},
4797	],
4798	},
4799	FieldSet {
4800	name: "Tccr5",
4801	extends: None,
4802	description: Some(
4803	"DSI Host timeout counter configuration register 5.",
4804	),
4805	bit_size: `32`,
4806	fields: &[
4807	Field {
4808	name: "bta_tocnt",
4809	description: Some(
4810	"Bus-turn-around timeout counter This field sets a period for which the DSI Host keeps the link still, after completing a bus-turn-around. This period is measured in cycles of lanebyteclk. The counting starts when the Dâ`\u{80}\u{91}`PHY enters the Stop state and causes no interrupts.",
4811	),
4812	bit_offset: BitOffset::Regular(
4813	RegularBitOffset {
4814	offset: `0`,
4815	},
4816	),
4817	bit_size: `16`,
4818	array: None,
4819	enumm: None,
4820	},
4821	],
4822	},
4823	FieldSet {
4824	name: "Vcccr",
4825	extends: None,
4826	description: Some(
4827	"DSI Host video chunks current configuration register.",
4828	),
4829	bit_size: `32`,
4830	fields: &[
4831	Field {
4832	name: "numc",
4833	description: Some(
4834	"Number of chunks This field returns the number of chunks being transmitted during a line period.",
4835	),
4836	bit_offset: BitOffset::Regular(
4837	RegularBitOffset {
4838	offset: `0`,
4839	},
4840	),
4841	bit_size: `13`,
4842	array: None,
4843	enumm: None,
4844	},
4845	],
4846	},
4847	FieldSet {
4848	name: "Vccr",
4849	extends: None,
4850	description: Some(
4851	"DSI Host video chunks configuration register.",
4852	),
4853	bit_size: `32`,
4854	fields: &[
4855	Field {
4856	name: "numc",
4857	description: Some(
4858	"Number of chunks This register configures the number of chunks to be transmitted during a line period (a chunk consists of a video packet and a null packet). If set to 0 or 1, the video line is transmitted in a single packet. If set to 1, the packet is part of a chunk, so a null packet follows it if NPSIZE > 0. Otherwise, multiple chunks are used to transmit each video line.",
4859	),
4860	bit_offset: BitOffset::Regular(
4861	RegularBitOffset {
4862	offset: `0`,
4863	},
4864	),
4865	bit_size: `13`,
4866	array: None,
4867	enumm: None,
4868	},
4869	],
4870	},
4871	FieldSet {
4872	name: "Vhbpccr",
4873	extends: None,
4874	description: Some(
4875	"DSI Host video HBP current configuration register.",
4876	),
4877	bit_size: `32`,
4878	fields: &[
4879	Field {
4880	name: "hbp",
4881	description: Some(
4882	"Horizontal back-porch duration This field returns the horizontal back-porch period in lane byte clock cycles.",
4883	),
4884	bit_offset: BitOffset::Regular(
4885	RegularBitOffset {
4886	offset: `0`,
4887	},
4888	),
4889	bit_size: `12`,
4890	array: None,
4891	enumm: None,
4892	},
4893	],
4894	},
4895	FieldSet {
4896	name: "Vhbpcr",
4897	extends: None,
4898	description: Some(
4899	"DSI Host video HBP configuration register.",
4900	),
4901	bit_size: `32`,
4902	fields: &[
4903	Field {
4904	name: "hbp",
4905	description: Some(
4906	"Horizontal back-porch duration This fields configures the horizontal back-porch period in lane byte clock cycles.",
4907	),
4908	bit_offset: BitOffset::Regular(
4909	RegularBitOffset {
4910	offset: `0`,
4911	},
4912	),
4913	bit_size: `12`,
4914	array: None,
4915	enumm: None,
4916	},
4917	],
4918	},
4919	FieldSet {
4920	name: "Vhsaccr",
4921	extends: None,
4922	description: Some(
4923	"DSI Host video HSA current configuration register.",
4924	),
4925	bit_size: `32`,
4926	fields: &[
4927	Field {
4928	name: "hsa",
4929	description: Some(
4930	"Horizontal synchronism active duration This fields returns the horizontal synchronism active period in lane byte clock cycles.",
4931	),
4932	bit_offset: BitOffset::Regular(
4933	RegularBitOffset {
4934	offset: `0`,
4935	},
4936	),
4937	bit_size: `12`,
4938	array: None,
4939	enumm: None,
4940	},
4941	],
4942	},
4943	FieldSet {
4944	name: "Vhsacr",
4945	extends: None,
4946	description: Some(
4947	"DSI Host video HSA configuration register.",
4948	),
4949	bit_size: `32`,
4950	fields: &[
4951	Field {
4952	name: "hsa",
4953	description: Some(
4954	"Horizontal synchronism active duration This fields configures the horizontal synchronism active period in lane byte clock cycles.",
4955	),
4956	bit_offset: BitOffset::Regular(
4957	RegularBitOffset {
4958	offset: `0`,
4959	},
4960	),
4961	bit_size: `12`,
4962	array: None,
4963	enumm: None,
4964	},
4965	],
4966	},
4967	FieldSet {
4968	name: "Vlccr",
4969	extends: None,
4970	description: Some(
4971	"DSI Host video line current configuration register.",
4972	),
4973	bit_size: `32`,
4974	fields: &[
4975	Field {
4976	name: "hline",
4977	description: Some(
4978	"Horizontal line duration This field returns the current total of the horizontal line period (HSA+HBP+HACT+HFP) counted in lane byte clock cycles.",
4979	),
4980	bit_offset: BitOffset::Regular(
4981	RegularBitOffset {
4982	offset: `0`,
4983	},
4984	),
4985	bit_size: `15`,
4986	array: None,
4987	enumm: None,
4988	},
4989	],
4990	},
4991	FieldSet {
4992	name: "Vlcr",
4993	extends: None,
4994	description: Some(
4995	"DSI Host video line configuration register.",
4996	),
4997	bit_size: `32`,
4998	fields: &[
4999	Field {
5000	name: "hline",
5001	description: Some(
5002	"Horizontal line duration This fields configures the total of the horizontal line period (HSA+HBP+HACT+HFP) counted in lane byte clock cycles.",
5003	),
5004	bit_offset: BitOffset::Regular(
5005	RegularBitOffset {
5006	offset: `0`,
5007	},
5008	),
5009	bit_size: `15`,
5010	array: None,
5011	enumm: None,
5012	},
5013	],
5014	},
5015	FieldSet {
5016	name: "Vmccr",
5017	extends: None,
5018	description: Some(
5019	"DSI Host video mode current configuration register.",
5020	),
5021	bit_size: `32`,
5022	fields: &[
5023	Field {
5024	name: "vmt",
5025	description: Some(
5026	"Video mode type This field returns the current video mode transmission type: 1x: Burst mode.",
5027	),
5028	bit_offset: BitOffset::Regular(
5029	RegularBitOffset {
5030	offset: `0`,
5031	},
5032	),
5033	bit_size: `2`,
5034	array: None,
5035	enumm: None,
5036	},
5037	Field {
5038	name: "lpvsae",
5039	description: Some(
5040	"Low-power vertical sync time enable This bit returns the current state of return to low-power inside the vertical sync time (VSA) period when timing allows.",
5041	),
5042	bit_offset: BitOffset::Regular(
5043	RegularBitOffset {
5044	offset: `2`,
5045	},
5046	),
5047	bit_size: `1`,
5048	array: None,
5049	enumm: None,
5050	},
5051	Field {
5052	name: "lpvbpe",
5053	description: Some(
5054	"Low-power vertical back-porch enable This bit returns the current state of return to low-power inside the vertical back-porch (VBP) period when timing allows.",
5055	),
5056	bit_offset: BitOffset::Regular(
5057	RegularBitOffset {
5058	offset: `3`,
5059	},
5060	),
5061	bit_size: `1`,
5062	array: None,
5063	enumm: None,
5064	},
5065	Field {
5066	name: "lpvfpe",
5067	description: Some(
5068	"Low-power vertical front-porch enable This bit returns the current state of return to low-power inside the vertical front-porch (VFP) period when timing allows.",
5069	),
5070	bit_offset: BitOffset::Regular(
5071	RegularBitOffset {
5072	offset: `4`,
5073	},
5074	),
5075	bit_size: `1`,
5076	array: None,
5077	enumm: None,
5078	},
5079	Field {
5080	name: "lpvae",
5081	description: Some(
5082	"Low-power vertical active enable This bit returns the current state of return to low-power inside the vertical active (VACT) period when timing allows.",
5083	),
5084	bit_offset: BitOffset::Regular(
5085	RegularBitOffset {
5086	offset: `5`,
5087	},
5088	),
5089	bit_size: `1`,
5090	array: None,
5091	enumm: None,
5092	},
5093	Field {
5094	name: "lphbpe",
5095	description: Some(
5096	"Low-power horizontal back-porch enable This bit returns the current state of return to low-power inside the horizontal back-porch (HBP) period when timing allows.",
5097	),
5098	bit_offset: BitOffset::Regular(
5099	RegularBitOffset {
5100	offset: `6`,
5101	},
5102	),
5103	bit_size: `1`,
5104	array: None,
5105	enumm: None,
5106	},
5107	Field {
5108	name: "lphfe",
5109	description: Some(
5110	"Low-power horizontal front-porch enable This bit returns the current state of return to low-power inside the horizontal front-porch (HFP) period when timing allows.",
5111	),
5112	bit_offset: BitOffset::Regular(
5113	RegularBitOffset {
5114	offset: `7`,
5115	},
5116	),
5117	bit_size: `1`,
5118	array: None,
5119	enumm: None,
5120	},
5121	Field {
5122	name: "fbtaae",
5123	description: Some(
5124	"Frame BTA acknowledge enable This bit returns the current state of request for an acknowledge response at the end of a frame.",
5125	),
5126	bit_offset: BitOffset::Regular(
5127	RegularBitOffset {
5128	offset: `8`,
5129	},
5130	),
5131	bit_size: `1`,
5132	array: None,
5133	enumm: None,
5134	},
5135	Field {
5136	name: "lpce",
5137	description: Some(
5138	"Low-power command enable This bit returns the current command transmission state in low-power mode.",
5139	),
5140	bit_offset: BitOffset::Regular(
5141	RegularBitOffset {
5142	offset: `9`,
5143	},
5144	),
5145	bit_size: `1`,
5146	array: None,
5147	enumm: None,
5148	},
5149	],
5150	},
5151	FieldSet {
5152	name: "Vmcr",
5153	extends: None,
5154	description: Some(
5155	"DSI Host video mode configuration register.",
5156	),
5157	bit_size: `32`,
5158	fields: &[
5159	Field {
5160	name: "vmt",
5161	description: Some(
5162	"Video mode type This field configures the video mode transmission type : 1x: Burst mode.",
5163	),
5164	bit_offset: BitOffset::Regular(
5165	RegularBitOffset {
5166	offset: `0`,
5167	},
5168	),
5169	bit_size: `2`,
5170	array: None,
5171	enumm: None,
5172	},
5173	Field {
5174	name: "lpvsae",
5175	description: Some(
5176	"Low-power vertical sync active enable This bit enables to return to low-power inside the vertical sync time (VSA) period when timing allows.",
5177	),
5178	bit_offset: BitOffset::Regular(
5179	RegularBitOffset {
5180	offset: `8`,
5181	},
5182	),
5183	bit_size: `1`,
5184	array: None,
5185	enumm: None,
5186	},
5187	Field {
5188	name: "lpvbpe",
5189	description: Some(
5190	"Low-power vertical back-porch enable This bit enables to return to low-power inside the vertical back-porch (VBP) period when timing allows.",
5191	),
5192	bit_offset: BitOffset::Regular(
5193	RegularBitOffset {
5194	offset: `9`,
5195	},
5196	),
5197	bit_size: `1`,
5198	array: None,
5199	enumm: None,
5200	},
5201	Field {
5202	name: "lpvfpe",
5203	description: Some(
5204	"Low-power vertical front-porch enable This bit enables to return to low-power inside the vertical front-porch (VFP) period when timing allows.",
5205	),
5206	bit_offset: BitOffset::Regular(
5207	RegularBitOffset {
5208	offset: `10`,
5209	},
5210	),
5211	bit_size: `1`,
5212	array: None,
5213	enumm: None,
5214	},
5215	Field {
5216	name: "lpvae",
5217	description: Some(
5218	"Low-power vertical active enable This bit enables to return to low-power inside the vertical active (VACT) period when timing allows.",
5219	),
5220	bit_offset: BitOffset::Regular(
5221	RegularBitOffset {
5222	offset: `11`,
5223	},
5224	),
5225	bit_size: `1`,
5226	array: None,
5227	enumm: None,
5228	},
5229	Field {
5230	name: "lphbpe",
5231	description: Some(
5232	"Low-power horizontal back-porch enable This bit enables the return to low-power inside the horizontal back-porch (HBP) period when timing allows.",
5233	),
5234	bit_offset: BitOffset::Regular(
5235	RegularBitOffset {
5236	offset: `12`,
5237	},
5238	),
5239	bit_size: `1`,
5240	array: None,
5241	enumm: None,
5242	},
5243	Field {
5244	name: "lphfpe",
5245	description: Some(
5246	"Low-power horizontal front-porch enable This bit enables the return to low-power inside the horizontal front-porch (HFP) period when timing allows.",
5247	),
5248	bit_offset: BitOffset::Regular(
5249	RegularBitOffset {
5250	offset: `13`,
5251	},
5252	),
5253	bit_size: `1`,
5254	array: None,
5255	enumm: None,
5256	},
5257	Field {
5258	name: "fbtaae",
5259	description: Some(
5260	"Frame bus-turn-around acknowledge enable This bit enables the request for an acknowledge response at the end of a frame.",
5261	),
5262	bit_offset: BitOffset::Regular(
5263	RegularBitOffset {
5264	offset: `14`,
5265	},
5266	),
5267	bit_size: `1`,
5268	array: None,
5269	enumm: None,
5270	},
5271	Field {
5272	name: "lpce",
5273	description: Some(
5274	"Low-power command enable This bit enables the command transmission only in low-power mode.",
5275	),
5276	bit_offset: BitOffset::Regular(
5277	RegularBitOffset {
5278	offset: `15`,
5279	},
5280	),
5281	bit_size: `1`,
5282	array: None,
5283	enumm: None,
5284	},
5285	Field {
5286	name: "pge",
5287	description: Some(
5288	"Pattern generator enable This bit enables the video mode pattern generator.",
5289	),
5290	bit_offset: BitOffset::Regular(
5291	RegularBitOffset {
5292	offset: `16`,
5293	},
5294	),
5295	bit_size: `1`,
5296	array: None,
5297	enumm: None,
5298	},
5299	Field {
5300	name: "pgm",
5301	description: Some(
5302	"Pattern generator mode This bit configures the pattern generator mode.",
5303	),
5304	bit_offset: BitOffset::Regular(
5305	RegularBitOffset {
5306	offset: `20`,
5307	},
5308	),
5309	bit_size: `1`,
5310	array: None,
5311	enumm: None,
5312	},
5313	Field {
5314	name: "pgo",
5315	description: Some(
5316	"Pattern generator orientation This bit configures the color bar orientation.",
5317	),
5318	bit_offset: BitOffset::Regular(
5319	RegularBitOffset {
5320	offset: `24`,
5321	},
5322	),
5323	bit_size: `1`,
5324	array: None,
5325	enumm: None,
5326	},
5327	],
5328	},
5329	FieldSet {
5330	name: "Vnpccr",
5331	extends: None,
5332	description: Some(
5333	"DSI Host video null packet current configuration register.",
5334	),
5335	bit_size: `32`,
5336	fields: &[
5337	Field {
5338	name: "npsize",
5339	description: Some(
5340	"Null packet size This field returns the number of bytes inside a null packet.",
5341	),
5342	bit_offset: BitOffset::Regular(
5343	RegularBitOffset {
5344	offset: `0`,
5345	},
5346	),
5347	bit_size: `13`,
5348	array: None,
5349	enumm: None,
5350	},
5351	],
5352	},
5353	FieldSet {
5354	name: "Vnpcr",
5355	extends: None,
5356	description: Some(
5357	"DSI Host video null packet configuration register.",
5358	),
5359	bit_size: `32`,
5360	fields: &[
5361	Field {
5362	name: "npsize",
5363	description: Some(
5364	"Null packet size This field configures the number of bytes inside a null packet. Setting to 0 disables the null packets.",
5365	),
5366	bit_offset: BitOffset::Regular(
5367	RegularBitOffset {
5368	offset: `0`,
5369	},
5370	),
5371	bit_size: `13`,
5372	array: None,
5373	enumm: None,
5374	},
5375	],
5376	},
5377	FieldSet {
5378	name: "Vpccr",
5379	extends: None,
5380	description: Some(
5381	"DSI Host video packet current configuration register.",
5382	),
5383	bit_size: `32`,
5384	fields: &[
5385	Field {
5386	name: "vpsize",
5387	description: Some(
5388	"Video packet size This field returns the number of pixels in a single video packet.",
5389	),
5390	bit_offset: BitOffset::Regular(
5391	RegularBitOffset {
5392	offset: `0`,
5393	},
5394	),
5395	bit_size: `14`,
5396	array: None,
5397	enumm: None,
5398	},
5399	],
5400	},
5401	FieldSet {
5402	name: "Vpcr",
5403	extends: None,
5404	description: Some(
5405	"DSI Host video packet configuration register.",
5406	),
5407	bit_size: `32`,
5408	fields: &[
5409	Field {
5410	name: "vpsize",
5411	description: Some(
5412	"Video packet size This field configures the number of pixels in a single video packet. For 18-bit not loosely packed data types, this number must be a multiple of 4. For YCbCr data types, it must be a multiple of 2 as described in the DSI specification.",
5413	),
5414	bit_offset: BitOffset::Regular(
5415	RegularBitOffset {
5416	offset: `0`,
5417	},
5418	),
5419	bit_size: `14`,
5420	array: None,
5421	enumm: None,
5422	},
5423	],
5424	},
5425	FieldSet {
5426	name: "Vr",
5427	extends: None,
5428	description: Some(
5429	"DSI Host version register.",
5430	),
5431	bit_size: `32`,
5432	fields: &[
5433	Field {
5434	name: "version",
5435	description: Some(
5436	"Version of the DSI Host This read-only register contains the version of the DSI Host.",
5437	),
5438	bit_offset: BitOffset::Regular(
5439	RegularBitOffset {
5440	offset: `0`,
5441	},
5442	),
5443	bit_size: `32`,
5444	array: None,
5445	enumm: None,
5446	},
5447	],
5448	},
5449	FieldSet {
5450	name: "Vscr",
5451	extends: None,
5452	description: Some(
5453	"DSI Host video shadow control register.",
5454	),
5455	bit_size: `32`,
5456	fields: &[
5457	Field {
5458	name: "en",
5459	description: Some(
5460	"Enable When set to 1, DSI Host LTDC interface receives the active configuration from the auxiliary registers. When this bit is set along with the UR bit, the auxiliary registers are automatically updated.",
5461	),
5462	bit_offset: BitOffset::Regular(
5463	RegularBitOffset {
5464	offset: `0`,
5465	},
5466	),
5467	bit_size: `1`,
5468	array: None,
5469	enumm: None,
5470	},
5471	Field {
5472	name: "ur",
5473	description: Some(
5474	"Update register When set to 1, the LTDC registers are copied to the auxiliary registers. After copying, this bit is auto cleared.",
5475	),
5476	bit_offset: BitOffset::Regular(
5477	RegularBitOffset {
5478	offset: `8`,
5479	},
5480	),
5481	bit_size: `1`,
5482	array: None,
5483	enumm: None,
5484	},
5485	],
5486	},
5487	FieldSet {
5488	name: "Vvaccr",
5489	extends: None,
5490	description: Some(
5491	"DSI Host video VA current configuration register.",
5492	),
5493	bit_size: `32`,
5494	fields: &[
5495	Field {
5496	name: "va",
5497	description: Some(
5498	"Vertical active duration This field returns the current vertical active period measured in number of horizontal lines.",
5499	),
5500	bit_offset: BitOffset::Regular(
5501	RegularBitOffset {
5502	offset: `0`,
5503	},
5504	),
5505	bit_size: `14`,
5506	array: None,
5507	enumm: None,
5508	},
5509	],
5510	},
5511	FieldSet {
5512	name: "Vvacr",
5513	extends: None,
5514	description: Some(
5515	"DSI Host video VA configuration register.",
5516	),
5517	bit_size: `32`,
5518	fields: &[
5519	Field {
5520	name: "va",
5521	description: Some(
5522	"Vertical active duration This fields configures the vertical active period measured in number of horizontal lines.",
5523	),
5524	bit_offset: BitOffset::Regular(
5525	RegularBitOffset {
5526	offset: `0`,
5527	},
5528	),
5529	bit_size: `14`,
5530	array: None,
5531	enumm: None,
5532	},
5533	],
5534	},
5535	FieldSet {
5536	name: "Vvbpccr",
5537	extends: None,
5538	description: Some(
5539	"DSI Host video VBP current configuration register.",
5540	),
5541	bit_size: `32`,
5542	fields: &[
5543	Field {
5544	name: "vbp",
5545	description: Some(
5546	"Vertical back-porch duration This field returns the current vertical back-porch period measured in number of horizontal lines.",
5547	),
5548	bit_offset: BitOffset::Regular(
5549	RegularBitOffset {
5550	offset: `0`,
5551	},
5552	),
5553	bit_size: `10`,
5554	array: None,
5555	enumm: None,
5556	},
5557	],
5558	},
5559	FieldSet {
5560	name: "Vvbpcr",
5561	extends: None,
5562	description: Some(
5563	"DSI Host video VBP configuration register.",
5564	),
5565	bit_size: `32`,
5566	fields: &[
5567	Field {
5568	name: "vbp",
5569	description: Some(
5570	"Vertical back-porch duration This fields configures the vertical back-porch period measured in number of horizontal lines.",
5571	),
5572	bit_offset: BitOffset::Regular(
5573	RegularBitOffset {
5574	offset: `0`,
5575	},
5576	),
5577	bit_size: `10`,
5578	array: None,
5579	enumm: None,
5580	},
5581	],
5582	},
5583	FieldSet {
5584	name: "Vvfpccr",
5585	extends: None,
5586	description: Some(
5587	"DSI Host video VFP current configuration register.",
5588	),
5589	bit_size: `32`,
5590	fields: &[
5591	Field {
5592	name: "vfp",
5593	description: Some(
5594	"Vertical front-porch duration This field returns the current vertical front-porch period measured in number of horizontal lines.",
5595	),
5596	bit_offset: BitOffset::Regular(
5597	RegularBitOffset {
5598	offset: `0`,
5599	},
5600	),
5601	bit_size: `10`,
5602	array: None,
5603	enumm: None,
5604	},
5605	],
5606	},
5607	FieldSet {
5608	name: "Vvfpcr",
5609	extends: None,
5610	description: Some(
5611	"DSI Host video VFP configuration register.",
5612	),
5613	bit_size: `32`,
5614	fields: &[
5615	Field {
5616	name: "vfp",
5617	description: Some(
5618	"Vertical front-porch duration This fields configures the vertical front-porch period measured in number of horizontal lines.",
5619	),
5620	bit_offset: BitOffset::Regular(
5621	RegularBitOffset {
5622	offset: `0`,
5623	},
5624	),
5625	bit_size: `10`,
5626	array: None,
5627	enumm: None,
5628	},
5629	],
5630	},
5631	FieldSet {
5632	name: "Vvsaccr",
5633	extends: None,
5634	description: Some(
5635	"DSI Host video VSA current configuration register.",
5636	),
5637	bit_size: `32`,
5638	fields: &[
5639	Field {
5640	name: "vsa",
5641	description: Some(
5642	"Vertical synchronism active duration This field returns the current vertical synchronism active period measured in number of horizontal lines.",
5643	),
5644	bit_offset: BitOffset::Regular(
5645	RegularBitOffset {
5646	offset: `0`,
5647	},
5648	),
5649	bit_size: `10`,
5650	array: None,
5651	enumm: None,
5652	},
5653	],
5654	},
5655	FieldSet {
5656	name: "Vvsacr",
5657	extends: None,
5658	description: Some(
5659	"DSI Host video VSA configuration register.",
5660	),
5661	bit_size: `32`,
5662	fields: &[
5663	Field {
5664	name: "vsa",
5665	description: Some(
5666	"Vertical synchronism active duration This fields configures the vertical synchronism active period measured in number of horizontal lines.",
5667	),
5668	bit_offset: BitOffset::Regular(
5669	RegularBitOffset {
5670	offset: `0`,
5671	},
5672	),
5673	bit_size: `10`,
5674	array: None,
5675	enumm: None,
5676	},
5677	],
5678	},
5679	FieldSet {
5680	name: "Wcfgr",
5681	extends: None,
5682	description: Some(
5683	"DSI Wrapper configuration register.",
5684	),
5685	bit_size: `32`,
5686	fields: &[
5687	Field {
5688	name: "dsim",
5689	description: Some(
5690	"DSI mode This bit selects the mode for the video transmission. This bit must only be changed when DSI Host is stopped (CR.EN = 0).",
5691	),
5692	bit_offset: BitOffset::Regular(
5693	RegularBitOffset {
5694	offset: `0`,
5695	},
5696	),
5697	bit_size: `1`,
5698	array: None,
5699	enumm: None,
5700	},
5701	Field {
5702	name: "colmux",
5703	description: Some(
5704	"Color multiplexing This bit selects the color multiplexing used by DSI Host. This field must only be changed when DSI is stopped (WCR.DSIEN = 0 and CR.ENÂ`\u{a0}`=Â`\u{a0}`0).",
5705	),
5706	bit_offset: BitOffset::Regular(
5707	RegularBitOffset {
5708	offset: `1`,
5709	},
5710	),
5711	bit_size: `3`,
5712	array: None,
5713	enumm: None,
5714	},
5715	Field {
5716	name: "tesrc",
5717	description: Some(
5718	"TE source This bit selects the tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (CR.EN = 0).",
5719	),
5720	bit_offset: BitOffset::Regular(
5721	RegularBitOffset {
5722	offset: `4`,
5723	},
5724	),
5725	bit_size: `1`,
5726	array: None,
5727	enumm: None,
5728	},
5729	Field {
5730	name: "tepol",
5731	description: Some(
5732	"TE polarity This bit selects the polarity of the external pin tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (CR.EN = 0).",
5733	),
5734	bit_offset: BitOffset::Regular(
5735	RegularBitOffset {
5736	offset: `5`,
5737	},
5738	),
5739	bit_size: `1`,
5740	array: None,
5741	enumm: None,
5742	},
5743	Field {
5744	name: "ar",
5745	description: Some(
5746	"Automatic refresh This bit selects the refresh mode in DBI mode. This bit must only be changed when DSI Host is stopped (CR.EN = 0).",
5747	),
5748	bit_offset: BitOffset::Regular(
5749	RegularBitOffset {
5750	offset: `6`,
5751	},
5752	),
5753	bit_size: `1`,
5754	array: None,
5755	enumm: None,
5756	},
5757	Field {
5758	name: "vspol",
5759	description: Some(
5760	"VSync polarity This bit selects the VSync edge on which the LTDC is halted. This bit must only be changed when DSI is stopped (WCR.DSIEN = 0 and CR.ENÂ`\u{a0}`=Â`\u{a0}`0).",
5761	),
5762	bit_offset: BitOffset::Regular(
5763	RegularBitOffset {
5764	offset: `7`,
5765	},
5766	),
5767	bit_size: `1`,
5768	array: None,
5769	enumm: None,
5770	},
5771	],
5772	},
5773	FieldSet {
5774	name: "Wcr",
5775	extends: None,
5776	description: Some(
5777	"DSI Wrapper control register.",
5778	),
5779	bit_size: `32`,
5780	fields: &[
5781	Field {
5782	name: "colm",
5783	description: Some(
5784	"Color mode This bit controls the display color mode in video mode.",
5785	),
5786	bit_offset: BitOffset::Regular(
5787	RegularBitOffset {
5788	offset: `0`,
5789	},
5790	),
5791	bit_size: `1`,
5792	array: None,
5793	enumm: None,
5794	},
5795	Field {
5796	name: "shtdn",
5797	description: Some(
5798	"Shutdown This bit controls the display shutdown in video mode.",
5799	),
5800	bit_offset: BitOffset::Regular(
5801	RegularBitOffset {
5802	offset: `1`,
5803	},
5804	),
5805	bit_size: `1`,
5806	array: None,
5807	enumm: None,
5808	},
5809	Field {
5810	name: "ltdcen",
5811	description: Some(
5812	"LTDC enable This bit enables the LTDC for a frame transfer in adapted command mode.",
5813	),
5814	bit_offset: BitOffset::Regular(
5815	RegularBitOffset {
5816	offset: `2`,
5817	},
5818	),
5819	bit_size: `1`,
5820	array: None,
5821	enumm: None,
5822	},
5823	Field {
5824	name: "dsien",
5825	description: Some(
5826	"DSI enable This bit enables the DSI Wrapper.",
5827	),
5828	bit_offset: BitOffset::Regular(
5829	RegularBitOffset {
5830	offset: `3`,
5831	},
5832	),
5833	bit_size: `1`,
5834	array: None,
5835	enumm: None,
5836	},
5837	],
5838	},
5839	FieldSet {
5840	name: "Wier",
5841	extends: None,
5842	description: Some(
5843	"DSI Wrapper interrupt enable register.",
5844	),
5845	bit_size: `32`,
5846	fields: &[
5847	Field {
5848	name: "teie",
5849	description: Some(
5850	"Tearing effect interrupt enable This bit enables the tearing effect interrupt.",
5851	),
5852	bit_offset: BitOffset::Regular(
5853	RegularBitOffset {
5854	offset: `0`,
5855	},
5856	),
5857	bit_size: `1`,
5858	array: None,
5859	enumm: None,
5860	},
5861	Field {
5862	name: "erie",
5863	description: Some(
5864	"End of refresh interrupt enable This bit enables the end of refresh interrupt.",
5865	),
5866	bit_offset: BitOffset::Regular(
5867	RegularBitOffset {
5868	offset: `1`,
5869	},
5870	),
5871	bit_size: `1`,
5872	array: None,
5873	enumm: None,
5874	},
5875	Field {
5876	name: "plllie",
5877	description: Some(
5878	"PLL lock interrupt enable This bit enables the PLL lock interrupt.",
5879	),
5880	bit_offset: BitOffset::Regular(
5881	RegularBitOffset {
5882	offset: `9`,
5883	},
5884	),
5885	bit_size: `1`,
5886	array: None,
5887	enumm: None,
5888	},
5889	Field {
5890	name: "plluie",
5891	description: Some(
5892	"PLL unlock interrupt enable This bit enables the PLL unlock interrupt.",
5893	),
5894	bit_offset: BitOffset::Regular(
5895	RegularBitOffset {
5896	offset: `10`,
5897	},
5898	),
5899	bit_size: `1`,
5900	array: None,
5901	enumm: None,
5902	},
5903	],
5904	},
5905	FieldSet {
5906	name: "Wifcr",
5907	extends: None,
5908	description: Some(
5909	"DSI Wrapper interrupt flag clear register.",
5910	),
5911	bit_size: `32`,
5912	fields: &[
5913	Field {
5914	name: "cteif",
5915	description: Some(
5916	"Clear tearing effect interrupt flag Write 1 clears the TEIF flag in the WSR register.",
5917	),
5918	bit_offset: BitOffset::Regular(
5919	RegularBitOffset {
5920	offset: `0`,
5921	},
5922	),
5923	bit_size: `1`,
5924	array: None,
5925	enumm: None,
5926	},
5927	Field {
5928	name: "cerif",
5929	description: Some(
5930	"Clear end of refresh interrupt flag Write 1 clears the ERIF flag in the WSR register.",
5931	),
5932	bit_offset: BitOffset::Regular(
5933	RegularBitOffset {
5934	offset: `1`,
5935	},
5936	),
5937	bit_size: `1`,
5938	array: None,
5939	enumm: None,
5940	},
5941	Field {
5942	name: "cplllif",
5943	description: Some(
5944	"Clear PLL lock interrupt flag Write 1 clears the PLLLIF flag in the WSR register.",
5945	),
5946	bit_offset: BitOffset::Regular(
5947	RegularBitOffset {
5948	offset: `9`,
5949	},
5950	),
5951	bit_size: `1`,
5952	array: None,
5953	enumm: None,
5954	},
5955	Field {
5956	name: "cplluif",
5957	description: Some(
5958	"Clear PLL unlock interrupt flag Write 1 clears the PLLUIF flag in the WSR register.",
5959	),
5960	bit_offset: BitOffset::Regular(
5961	RegularBitOffset {
5962	offset: `10`,
5963	},
5964	),
5965	bit_size: `1`,
5966	array: None,
5967	enumm: None,
5968	},
5969	],
5970	},
5971	FieldSet {
5972	name: "Wisr",
5973	extends: None,
5974	description: Some(
5975	"DSI Wrapper interrupt and status register.",
5976	),
5977	bit_size: `32`,
5978	fields: &[
5979	Field {
5980	name: "teif",
5981	description: Some(
5982	"Tearing effect interrupt flag This bit is set when a tearing effect event occurs.",
5983	),
5984	bit_offset: BitOffset::Regular(
5985	RegularBitOffset {
5986	offset: `0`,
5987	},
5988	),
5989	bit_size: `1`,
5990	array: None,
5991	enumm: None,
5992	},
5993	Field {
5994	name: "erif",
5995	description: Some(
5996	"End of refresh interrupt flag This bit is set when the transfer of a frame in adapted command mode is finished.",
5997	),
5998	bit_offset: BitOffset::Regular(
5999	RegularBitOffset {
6000	offset: `1`,
6001	},
6002	),
6003	bit_size: `1`,
6004	array: None,
6005	enumm: None,
6006	},
6007	Field {
6008	name: "busy",
6009	description: Some(
6010	"Busy flag This bit is set when the transfer of a frame in adapted command mode is ongoing.",
6011	),
6012	bit_offset: BitOffset::Regular(
6013	RegularBitOffset {
6014	offset: `2`,
6015	},
6016	),
6017	bit_size: `1`,
6018	array: None,
6019	enumm: None,
6020	},
6021	Field {
6022	name: "pllls",
6023	description: Some(
6024	"PLL lock status This bit is set when the PLL is locked and cleared when it is unlocked.",
6025	),
6026	bit_offset: BitOffset::Regular(
6027	RegularBitOffset {
6028	offset: `8`,
6029	},
6030	),
6031	bit_size: `1`,
6032	array: None,
6033	enumm: None,
6034	},
6035	Field {
6036	name: "plllif",
6037	description: Some(
6038	"PLL lock interrupt flag This bit is set when the PLL becomes locked.",
6039	),
6040	bit_offset: BitOffset::Regular(
6041	RegularBitOffset {
6042	offset: `9`,
6043	},
6044	),
6045	bit_size: `1`,
6046	array: None,
6047	enumm: None,
6048	},
6049	Field {
6050	name: "plluif",
6051	description: Some(
6052	"PLL unlock interrupt flag This bit is set when the PLL becomes unlocked.",
6053	),
6054	bit_offset: BitOffset::Regular(
6055	RegularBitOffset {
6056	offset: `10`,
6057	},
6058	),
6059	bit_size: `1`,
6060	array: None,
6061	enumm: None,
6062	},
6063	],
6064	},
6065	FieldSet {
6066	name: "Wpcr0",
6067	extends: None,
6068	description: Some(
6069	"DSI Wrapper PHY configuration register 0.",
6070	),
6071	bit_size: `32`,
6072	fields: &[
6073	Field {
6074	name: "swcl",
6075	description: Some(
6076	"Swap clock lane pins This bit swaps the pins on clock lane.",
6077	),
6078	bit_offset: BitOffset::Regular(
6079	RegularBitOffset {
6080	offset: `6`,
6081	},
6082	),
6083	bit_size: `1`,
6084	array: None,
6085	enumm: None,
6086	},
6087	Field {
6088	name: "swdl0",
6089	description: Some(
6090	"Swap data lane 0 pins This bit swaps the pins on data lane 0.",
6091	),
6092	bit_offset: BitOffset::Regular(
6093	RegularBitOffset {
6094	offset: `7`,
6095	},
6096	),
6097	bit_size: `1`,
6098	array: None,
6099	enumm: None,
6100	},
6101	Field {
6102	name: "swdl1",
6103	description: Some(
6104	"Swap data lane 1 pins This bit swaps the pins on clock lane.",
6105	),
6106	bit_offset: BitOffset::Regular(
6107	RegularBitOffset {
6108	offset: `8`,
6109	},
6110	),
6111	bit_size: `1`,
6112	array: None,
6113	enumm: None,
6114	},
6115	Field {
6116	name: "ftxsmcl",
6117	description: Some(
6118	"Force in TX Stop mode the clock lane This bit forces the clock lane in TX stop mode. It is used to initialize a lane module in transmit mode. It causes the lane module to immediately jump to transmit control mode and to begin transmitting a stop state (LP-11). It can be used to go back in TX mode after a wrong BTA sequence.",
6119	),
6120	bit_offset: BitOffset::Regular(
6121	RegularBitOffset {
6122	offset: `12`,
6123	},
6124	),
6125	bit_size: `1`,
6126	array: None,
6127	enumm: None,
6128	},
6129	Field {
6130	name: "ftxsmdl",
6131	description: Some(
6132	"Force in TX Stop mode the data lanes This bit forces the data lanes in TX stop mode. It is used to initialize a lane module in transmit mode. It causes the lane module to immediately jump to transmit control mode and to begin transmitting a stop state (LP-11). It can be used to go back in TX mode after a wrong BTA sequence.",
6133	),
6134	bit_offset: BitOffset::Regular(
6135	RegularBitOffset {
6136	offset: `13`,
6137	},
6138	),
6139	bit_size: `1`,
6140	array: None,
6141	enumm: None,
6142	},
6143	],
6144	},
6145	FieldSet {
6146	name: "Wrpcr",
6147	extends: None,
6148	description: Some(
6149	"DSI Wrapper regulator and PLL control register.",
6150	),
6151	bit_size: `32`,
6152	fields: &[
6153	Field {
6154	name: "pllen",
6155	description: Some(
6156	"PLL enable This bit enables the D-PHY PLL.",
6157	),
6158	bit_offset: BitOffset::Regular(
6159	RegularBitOffset {
6160	offset: `0`,
6161	},
6162	),
6163	bit_size: `1`,
6164	array: None,
6165	enumm: None,
6166	},
6167	Field {
6168	name: "ndiv",
6169	description: Some(
6170	"PLL loop division factor This field configures the PLL loop division factor. 2: PLL loop divided by 2x2 ... 511: PLL loop divided by 511x2.",
6171	),
6172	bit_offset: BitOffset::Regular(
6173	RegularBitOffset {
6174	offset: `2`,
6175	},
6176	),
6177	bit_size: `9`,
6178	array: None,
6179	enumm: None,
6180	},
6181	Field {
6182	name: "idf",
6183	description: Some(
6184	"PLL input division factor This field configures the PLL input division factor. 2: PLL input divided by 2 ... 511: PLL input divided by 511.",
6185	),
6186	bit_offset: BitOffset::Regular(
6187	RegularBitOffset {
6188	offset: `11`,
6189	},
6190	),
6191	bit_size: `9`,
6192	array: None,
6193	enumm: None,
6194	},
6195	Field {
6196	name: "odf",
6197	description: Some(
6198	"PLL output division factor This field configures the PLL output division factor. 2: PLL output divided by 2 ... 511: PLL output divided by 511.",
6199	),
6200	bit_offset: BitOffset::Regular(
6201	RegularBitOffset {
6202	offset: `20`,
6203	},
6204	),
6205	bit_size: `9`,
6206	array: None,
6207	enumm: None,
6208	},
6209	],
6210	},
6211	],
6212	enums: &[],
6213	};
6214