1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Gfxmmu",
7 extends: None,
8 description: Some(
9 "GFXMMU.",
10 ),
11 items: &[
12 BlockItem {
13 name: "cr",
14 description: Some(
15 "GFXMMU configuration register.",
16 ),
17 array: None,
18 byte_offset: 0x0,
19 inner: BlockItemInner::Register(
20 Register {
21 access: Access::ReadWrite,
22 bit_size: 32,
23 fieldset: Some(
24 "Cr",
25 ),
26 },
27 ),
28 },
29 BlockItem {
30 name: "sr",
31 description: Some(
32 "GFXMMU status register.",
33 ),
34 array: None,
35 byte_offset: 0x4,
36 inner: BlockItemInner::Register(
37 Register {
38 access: Access::Read,
39 bit_size: 32,
40 fieldset: Some(
41 "Sr",
42 ),
43 },
44 ),
45 },
46 BlockItem {
47 name: "fcr",
48 description: Some(
49 "GFXMMU flag clear register.",
50 ),
51 array: None,
52 byte_offset: 0x8,
53 inner: BlockItemInner::Register(
54 Register {
55 access: Access::Write,
56 bit_size: 32,
57 fieldset: Some(
58 "Fcr",
59 ),
60 },
61 ),
62 },
63 BlockItem {
64 name: "ccr",
65 description: Some(
66 "GFXMMU cache control register.",
67 ),
68 array: None,
69 byte_offset: 0xc,
70 inner: BlockItemInner::Register(
71 Register {
72 access: Access::ReadWrite,
73 bit_size: 32,
74 fieldset: Some(
75 "Ccr",
76 ),
77 },
78 ),
79 },
80 BlockItem {
81 name: "dvr",
82 description: Some(
83 "GFXMMU default value register.",
84 ),
85 array: None,
86 byte_offset: 0x10,
87 inner: BlockItemInner::Register(
88 Register {
89 access: Access::ReadWrite,
90 bit_size: 32,
91 fieldset: Some(
92 "Dvr",
93 ),
94 },
95 ),
96 },
97 BlockItem {
98 name: "bcr",
99 description: Some(
100 "GFXMMU buffer 0 configuration register.",
101 ),
102 array: Some(
103 Array::Regular(
104 RegularArray {
105 len: 4,
106 stride: 4,
107 },
108 ),
109 ),
110 byte_offset: 0x20,
111 inner: BlockItemInner::Register(
112 Register {
113 access: Access::ReadWrite,
114 bit_size: 32,
115 fieldset: Some(
116 "Bcr",
117 ),
118 },
119 ),
120 },
121 BlockItem {
122 name: "lutl",
123 description: Some(
124 "GFXMMU LUT entry 0 low.",
125 ),
126 array: Some(
127 Array::Regular(
128 RegularArray {
129 len: 1024,
130 stride: 8,
131 },
132 ),
133 ),
134 byte_offset: 0x1000,
135 inner: BlockItemInner::Register(
136 Register {
137 access: Access::ReadWrite,
138 bit_size: 32,
139 fieldset: Some(
140 "Lutl",
141 ),
142 },
143 ),
144 },
145 BlockItem {
146 name: "luth",
147 description: Some(
148 "GFXMMU LUT entry 0 high.",
149 ),
150 array: Some(
151 Array::Regular(
152 RegularArray {
153 len: 1024,
154 stride: 8,
155 },
156 ),
157 ),
158 byte_offset: 0x1004,
159 inner: BlockItemInner::Register(
160 Register {
161 access: Access::ReadWrite,
162 bit_size: 32,
163 fieldset: Some(
164 "Luth",
165 ),
166 },
167 ),
168 },
169 ],
170 },
171 ],
172 fieldsets: &[
173 FieldSet {
174 name: "Bcr",
175 extends: None,
176 description: Some(
177 "GFXMMU buffer configuration register.",
178 ),
179 bit_size: 32,
180 fields: &[
181 Field {
182 name: "pbo",
183 description: Some(
184 "Physical buffer offset. Offset of the physical buffer.",
185 ),
186 bit_offset: BitOffset::Regular(
187 RegularBitOffset {
188 offset: 4,
189 },
190 ),
191 bit_size: 19,
192 array: None,
193 enumm: None,
194 },
195 Field {
196 name: "pbba",
197 description: Some(
198 "Physical buffer base address. Base address MSB of the physical buffer.",
199 ),
200 bit_offset: BitOffset::Regular(
201 RegularBitOffset {
202 offset: 23,
203 },
204 ),
205 bit_size: 9,
206 array: None,
207 enumm: None,
208 },
209 ],
210 },
211 FieldSet {
212 name: "Ccr",
213 extends: None,
214 description: Some(
215 "GFXMMU cache control register.",
216 ),
217 bit_size: 32,
218 fields: &[
219 Field {
220 name: "ff",
221 description: Some(
222 "Force flush. When set, the cache entries are flushed. This bit is reset by hardware when the flushing is complete. Write 0 has no effect.",
223 ),
224 bit_offset: BitOffset::Regular(
225 RegularBitOffset {
226 offset: 0,
227 },
228 ),
229 bit_size: 1,
230 array: None,
231 enumm: None,
232 },
233 Field {
234 name: "fi",
235 description: Some(
236 "Force invalidate. When set, the cache entries are invalidated. This bit is reset by hardware when the invalidation is complete. Write 0 has no effect.",
237 ),
238 bit_offset: BitOffset::Regular(
239 RegularBitOffset {
240 offset: 1,
241 },
242 ),
243 bit_size: 1,
244 array: None,
245 enumm: None,
246 },
247 ],
248 },
249 FieldSet {
250 name: "Cr",
251 extends: None,
252 description: Some(
253 "GFXMMU configuration register.",
254 ),
255 bit_size: 32,
256 fields: &[
257 Field {
258 name: "boie",
259 description: Some(
260 "Buffer overflow interrupt enable. This bit enables the buffer 0 overflow interrupt.",
261 ),
262 bit_offset: BitOffset::Regular(
263 RegularBitOffset {
264 offset: 0,
265 },
266 ),
267 bit_size: 1,
268 array: Some(
269 Array::Regular(
270 RegularArray {
271 len: 4,
272 stride: 1,
273 },
274 ),
275 ),
276 enumm: None,
277 },
278 Field {
279 name: "ameie",
280 description: Some(
281 "AHB master error interrupt enable. This bit enables the AHB master error interrupt.",
282 ),
283 bit_offset: BitOffset::Regular(
284 RegularBitOffset {
285 offset: 4,
286 },
287 ),
288 bit_size: 1,
289 array: None,
290 enumm: None,
291 },
292 Field {
293 name: "bm",
294 description: Some(
295 "192 Block mode. This bit defines the number of blocks per line.",
296 ),
297 bit_offset: BitOffset::Regular(
298 RegularBitOffset {
299 offset: 6,
300 },
301 ),
302 bit_size: 1,
303 array: Some(
304 Array::Regular(
305 RegularArray {
306 len: 1,
307 stride: 0,
308 },
309 ),
310 ),
311 enumm: Some(
312 "Bm192",
313 ),
314 },
315 Field {
316 name: "ce",
317 description: Some(
318 "Cache enable. This bit enables the cache unit.",
319 ),
320 bit_offset: BitOffset::Regular(
321 RegularBitOffset {
322 offset: 7,
323 },
324 ),
325 bit_size: 1,
326 array: None,
327 enumm: None,
328 },
329 Field {
330 name: "cl",
331 description: Some(
332 "Cache lock. This bit lock the cache onto the buffer defined in the CLB field.",
333 ),
334 bit_offset: BitOffset::Regular(
335 RegularBitOffset {
336 offset: 8,
337 },
338 ),
339 bit_size: 1,
340 array: None,
341 enumm: None,
342 },
343 Field {
344 name: "clb",
345 description: Some(
346 "Cache lock buffer. This field select the buffer on which the cache is locked.",
347 ),
348 bit_offset: BitOffset::Regular(
349 RegularBitOffset {
350 offset: 9,
351 },
352 ),
353 bit_size: 2,
354 array: None,
355 enumm: Some(
356 "Clb",
357 ),
358 },
359 Field {
360 name: "fc",
361 description: Some(
362 "Force caching. This bit force the caching into the cache regardless of the MPU attributes. The cache must be enable (CE bit set).",
363 ),
364 bit_offset: BitOffset::Regular(
365 RegularBitOffset {
366 offset: 11,
367 },
368 ),
369 bit_size: 1,
370 array: None,
371 enumm: None,
372 },
373 Field {
374 name: "pd",
375 description: Some(
376 "Prefetch disable. This bit disables the prefetch of the cache.",
377 ),
378 bit_offset: BitOffset::Regular(
379 RegularBitOffset {
380 offset: 12,
381 },
382 ),
383 bit_size: 1,
384 array: None,
385 enumm: None,
386 },
387 Field {
388 name: "oc",
389 description: Some(
390 "Outter cachability. This bit configure the cachability of an access generated by the GFXMMU cache.",
391 ),
392 bit_offset: BitOffset::Regular(
393 RegularBitOffset {
394 offset: 16,
395 },
396 ),
397 bit_size: 1,
398 array: None,
399 enumm: None,
400 },
401 Field {
402 name: "ob",
403 description: Some(
404 "Outter bufferability. This bit configure the bufferability of an access generated by the GFXMMU cache.",
405 ),
406 bit_offset: BitOffset::Regular(
407 RegularBitOffset {
408 offset: 17,
409 },
410 ),
411 bit_size: 1,
412 array: None,
413 enumm: None,
414 },
415 ],
416 },
417 FieldSet {
418 name: "Dvr",
419 extends: None,
420 description: Some(
421 "GFXMMU default value register.",
422 ),
423 bit_size: 32,
424 fields: &[
425 Field {
426 name: "dv",
427 description: Some(
428 "Default value. This field indicates the default 32-bit value which is returned when a master accesses a virtual memory location not physically mapped.",
429 ),
430 bit_offset: BitOffset::Regular(
431 RegularBitOffset {
432 offset: 0,
433 },
434 ),
435 bit_size: 32,
436 array: None,
437 enumm: None,
438 },
439 ],
440 },
441 FieldSet {
442 name: "Fcr",
443 extends: None,
444 description: Some(
445 "GFXMMU flag clear register.",
446 ),
447 bit_size: 32,
448 fields: &[
449 Field {
450 name: "cbof",
451 description: Some(
452 "Clear buffer overflow flag. Writing 1 clears the buffer 0 overflow flag in the GFXMMU_SR register.",
453 ),
454 bit_offset: BitOffset::Regular(
455 RegularBitOffset {
456 offset: 0,
457 },
458 ),
459 bit_size: 1,
460 array: Some(
461 Array::Regular(
462 RegularArray {
463 len: 4,
464 stride: 1,
465 },
466 ),
467 ),
468 enumm: None,
469 },
470 Field {
471 name: "camef",
472 description: Some(
473 "Clear AHB master error flag. Writing 1 clears the AHB master error flag in the GFXMMU_SR register.",
474 ),
475 bit_offset: BitOffset::Regular(
476 RegularBitOffset {
477 offset: 4,
478 },
479 ),
480 bit_size: 1,
481 array: None,
482 enumm: None,
483 },
484 ],
485 },
486 FieldSet {
487 name: "Luth",
488 extends: None,
489 description: Some(
490 "GFXMMU LUT entry high.",
491 ),
492 bit_size: 32,
493 fields: &[
494 Field {
495 name: "lo",
496 description: Some(
497 "Line offset. Line offset of line number x (i.e. offset of block 0 of line x).",
498 ),
499 bit_offset: BitOffset::Regular(
500 RegularBitOffset {
501 offset: 4,
502 },
503 ),
504 bit_size: 18,
505 array: None,
506 enumm: None,
507 },
508 ],
509 },
510 FieldSet {
511 name: "Lutl",
512 extends: None,
513 description: Some(
514 "GFXMMU LUT entry low.",
515 ),
516 bit_size: 32,
517 fields: &[
518 Field {
519 name: "en",
520 description: Some(
521 "Line enable.",
522 ),
523 bit_offset: BitOffset::Regular(
524 RegularBitOffset {
525 offset: 0,
526 },
527 ),
528 bit_size: 1,
529 array: None,
530 enumm: None,
531 },
532 Field {
533 name: "fvb",
534 description: Some(
535 "First Valid Block. Number of the first valid block of line number x.",
536 ),
537 bit_offset: BitOffset::Regular(
538 RegularBitOffset {
539 offset: 8,
540 },
541 ),
542 bit_size: 8,
543 array: None,
544 enumm: None,
545 },
546 Field {
547 name: "lvb",
548 description: Some(
549 "Last Valid Block. Number of the last valid block of line number X.",
550 ),
551 bit_offset: BitOffset::Regular(
552 RegularBitOffset {
553 offset: 16,
554 },
555 ),
556 bit_size: 8,
557 array: None,
558 enumm: None,
559 },
560 ],
561 },
562 FieldSet {
563 name: "Sr",
564 extends: None,
565 description: Some(
566 "GFXMMU status register.",
567 ),
568 bit_size: 32,
569 fields: &[
570 Field {
571 name: "bof",
572 description: Some(
573 "Buffer overflow flag. This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is cleared by writing 1 to CB0OF.",
574 ),
575 bit_offset: BitOffset::Regular(
576 RegularBitOffset {
577 offset: 0,
578 },
579 ),
580 bit_size: 1,
581 array: Some(
582 Array::Regular(
583 RegularArray {
584 len: 4,
585 stride: 1,
586 },
587 ),
588 ),
589 enumm: None,
590 },
591 Field {
592 name: "amef",
593 description: Some(
594 "AHB master error flag. This bit is set when an AHB error happens during a transaction. It is cleared by writing 1 to CAMEF.",
595 ),
596 bit_offset: BitOffset::Regular(
597 RegularBitOffset {
598 offset: 4,
599 },
600 ),
601 bit_size: 1,
602 array: None,
603 enumm: None,
604 },
605 ],
606 },
607 ],
608 enums: &[
609 Enum {
610 name: "Bm192",
611 description: None,
612 bit_size: 1,
613 variants: &[
614 EnumVariant {
615 name: "_256BLOCKS_PER_LINE",
616 description: Some(
617 "256 blocks per line.",
618 ),
619 value: 0,
620 },
621 EnumVariant {
622 name: "_192BLOCKS_PER_LINE",
623 description: Some(
624 "192 blocks per line.",
625 ),
626 value: 1,
627 },
628 ],
629 },
630 Enum {
631 name: "Clb",
632 description: None,
633 bit_size: 2,
634 variants: &[
635 EnumVariant {
636 name: "LOCKED_ON_BUFFER0",
637 description: Some(
638 "Cache locked on buffer 0.",
639 ),
640 value: 0,
641 },
642 EnumVariant {
643 name: "LOCKED_ON_BUFFER1",
644 description: Some(
645 "Cache locked on buffer 1.",
646 ),
647 value: 1,
648 },
649 EnumVariant {
650 name: "LOCKED_ON_BUFFER2",
651 description: Some(
652 "Cache locked on buffer 2.",
653 ),
654 value: 2,
655 },
656 EnumVariant {
657 name: "LOCKED_ON_BUFFER3",
658 description: Some(
659 "Cache locked on buffer 3.",
660 ),
661 value: 3,
662 },
663 ],
664 },
665 ],
666};
667