1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Channel",
7 extends: None,
8 description: None,
9 items: &[
10 BlockItem {
11 name: "lbar",
12 description: Some(
13 "GPDMA channel 15 linked-list base address register",
14 ),
15 array: None,
16 byte_offset: 0x0,
17 inner: BlockItemInner::Register(
18 Register {
19 access: Access::ReadWrite,
20 bit_size: 32,
21 fieldset: Some(
22 "ChLbar",
23 ),
24 },
25 ),
26 },
27 BlockItem {
28 name: "fcr",
29 description: Some(
30 "GPDMA channel 15 flag clear register",
31 ),
32 array: None,
33 byte_offset: 0xc,
34 inner: BlockItemInner::Register(
35 Register {
36 access: Access::ReadWrite,
37 bit_size: 32,
38 fieldset: Some(
39 "ChFcr",
40 ),
41 },
42 ),
43 },
44 BlockItem {
45 name: "sr",
46 description: Some(
47 "GPDMA channel 15 status register",
48 ),
49 array: None,
50 byte_offset: 0x10,
51 inner: BlockItemInner::Register(
52 Register {
53 access: Access::ReadWrite,
54 bit_size: 32,
55 fieldset: Some(
56 "ChSr",
57 ),
58 },
59 ),
60 },
61 BlockItem {
62 name: "cr",
63 description: Some(
64 "GPDMA channel 15 control register",
65 ),
66 array: None,
67 byte_offset: 0x14,
68 inner: BlockItemInner::Register(
69 Register {
70 access: Access::ReadWrite,
71 bit_size: 32,
72 fieldset: Some(
73 "ChCr",
74 ),
75 },
76 ),
77 },
78 BlockItem {
79 name: "tr1",
80 description: Some(
81 "GPDMA channel 15 transfer register 1",
82 ),
83 array: None,
84 byte_offset: 0x40,
85 inner: BlockItemInner::Register(
86 Register {
87 access: Access::ReadWrite,
88 bit_size: 32,
89 fieldset: Some(
90 "ChTr1",
91 ),
92 },
93 ),
94 },
95 BlockItem {
96 name: "tr2",
97 description: Some(
98 "GPDMA channel 15 transfer register 2",
99 ),
100 array: None,
101 byte_offset: 0x44,
102 inner: BlockItemInner::Register(
103 Register {
104 access: Access::ReadWrite,
105 bit_size: 32,
106 fieldset: Some(
107 "ChTr2",
108 ),
109 },
110 ),
111 },
112 BlockItem {
113 name: "br1",
114 description: Some(
115 "GPDMA channel 15 alternate block register 1",
116 ),
117 array: None,
118 byte_offset: 0x48,
119 inner: BlockItemInner::Register(
120 Register {
121 access: Access::ReadWrite,
122 bit_size: 32,
123 fieldset: Some(
124 "ChBr1",
125 ),
126 },
127 ),
128 },
129 BlockItem {
130 name: "sar",
131 description: Some(
132 "GPDMA channel 15 source address register",
133 ),
134 array: None,
135 byte_offset: 0x4c,
136 inner: BlockItemInner::Register(
137 Register {
138 access: Access::ReadWrite,
139 bit_size: 32,
140 fieldset: None,
141 },
142 ),
143 },
144 BlockItem {
145 name: "dar",
146 description: Some(
147 "GPDMA channel 15 destination address register",
148 ),
149 array: None,
150 byte_offset: 0x50,
151 inner: BlockItemInner::Register(
152 Register {
153 access: Access::ReadWrite,
154 bit_size: 32,
155 fieldset: None,
156 },
157 ),
158 },
159 BlockItem {
160 name: "tr3",
161 description: Some(
162 "GPDMA channel 15 transfer register 3",
163 ),
164 array: None,
165 byte_offset: 0x54,
166 inner: BlockItemInner::Register(
167 Register {
168 access: Access::ReadWrite,
169 bit_size: 32,
170 fieldset: Some(
171 "ChTr3",
172 ),
173 },
174 ),
175 },
176 BlockItem {
177 name: "br2",
178 description: Some(
179 "GPDMA channel 15 block register 2",
180 ),
181 array: None,
182 byte_offset: 0x58,
183 inner: BlockItemInner::Register(
184 Register {
185 access: Access::ReadWrite,
186 bit_size: 32,
187 fieldset: Some(
188 "ChBr2",
189 ),
190 },
191 ),
192 },
193 BlockItem {
194 name: "llr",
195 description: Some(
196 "GPDMA channel 15 alternate linked-list address register",
197 ),
198 array: None,
199 byte_offset: 0x7c,
200 inner: BlockItemInner::Register(
201 Register {
202 access: Access::ReadWrite,
203 bit_size: 32,
204 fieldset: Some(
205 "ChLlr",
206 ),
207 },
208 ),
209 },
210 ],
211 },
212 Block {
213 name: "Gpdma",
214 extends: None,
215 description: Some(
216 "GPDMA",
217 ),
218 items: &[
219 BlockItem {
220 name: "seccfgr",
221 description: Some(
222 "GPDMA secure configuration register",
223 ),
224 array: None,
225 byte_offset: 0x0,
226 inner: BlockItemInner::Register(
227 Register {
228 access: Access::ReadWrite,
229 bit_size: 32,
230 fieldset: Some(
231 "Seccfgr",
232 ),
233 },
234 ),
235 },
236 BlockItem {
237 name: "privcfgr",
238 description: Some(
239 "GPDMA privileged configuration register",
240 ),
241 array: None,
242 byte_offset: 0x4,
243 inner: BlockItemInner::Register(
244 Register {
245 access: Access::ReadWrite,
246 bit_size: 32,
247 fieldset: Some(
248 "Privcfgr",
249 ),
250 },
251 ),
252 },
253 BlockItem {
254 name: "rcfglockr",
255 description: Some(
256 "GPDMA configuration lock register",
257 ),
258 array: None,
259 byte_offset: 0x8,
260 inner: BlockItemInner::Register(
261 Register {
262 access: Access::ReadWrite,
263 bit_size: 32,
264 fieldset: Some(
265 "Rcfglockr",
266 ),
267 },
268 ),
269 },
270 BlockItem {
271 name: "misr",
272 description: Some(
273 "GPDMA non-secure masked interrupt status register",
274 ),
275 array: None,
276 byte_offset: 0xc,
277 inner: BlockItemInner::Register(
278 Register {
279 access: Access::ReadWrite,
280 bit_size: 32,
281 fieldset: Some(
282 "Misr",
283 ),
284 },
285 ),
286 },
287 BlockItem {
288 name: "smisr",
289 description: Some(
290 "GPDMA secure masked interrupt status register",
291 ),
292 array: None,
293 byte_offset: 0x10,
294 inner: BlockItemInner::Register(
295 Register {
296 access: Access::ReadWrite,
297 bit_size: 32,
298 fieldset: Some(
299 "Misr",
300 ),
301 },
302 ),
303 },
304 BlockItem {
305 name: "ch",
306 description: None,
307 array: Some(
308 Array::Regular(
309 RegularArray {
310 len: 16,
311 stride: 128,
312 },
313 ),
314 ),
315 byte_offset: 0x50,
316 inner: BlockItemInner::Block(
317 BlockItemBlock {
318 block: "Channel",
319 },
320 ),
321 },
322 ],
323 },
324 ],
325 fieldsets: &[
326 FieldSet {
327 name: "ChBr1",
328 extends: None,
329 description: Some(
330 "GPDMA channel 15 alternate block register 1",
331 ),
332 bit_size: 32,
333 fields: &[
334 Field {
335 name: "bndt",
336 description: Some(
337 "block number of data bytes to transfer from the source. Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if CH[x].LLR.UB1 = 1, this field is updated by the LLI in the memory. - if CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. - if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if CH[x].LLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. When configured in packing mode (CH[x].TR1.PAM[1]=1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued.",
338 ),
339 bit_offset: BitOffset::Regular(
340 RegularBitOffset {
341 offset: 0,
342 },
343 ),
344 bit_size: 16,
345 array: None,
346 enumm: None,
347 },
348 Field {
349 name: "brc",
350 description: Some(
351 "Block repeat counter. This field contains the number of repetitions of the current block (0 to 2047). When the channel is enabled, this field becomes read-only. After decrements, this field indicates the remaining number of blocks, excluding the current one. This counter is hardware decremented for each completed block transfer. Once the last block transfer is completed (BRC[10:0] = BNDT[15:0] = 0): If CH[x].LLR.UB1 = 1, all CH[x].BR1 fields are updated by the next LLI in the memory. If CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). if CH[x].LLR = 0, this field is kept as zero following the last LLI and data transfer.",
352 ),
353 bit_offset: BitOffset::Regular(
354 RegularBitOffset {
355 offset: 16,
356 },
357 ),
358 bit_size: 11,
359 array: None,
360 enumm: None,
361 },
362 Field {
363 name: "sdec",
364 description: Some(
365 "source address decrement",
366 ),
367 bit_offset: BitOffset::Regular(
368 RegularBitOffset {
369 offset: 28,
370 },
371 ),
372 bit_size: 1,
373 array: None,
374 enumm: Some(
375 "Dec",
376 ),
377 },
378 Field {
379 name: "ddec",
380 description: Some(
381 "destination address decrement",
382 ),
383 bit_offset: BitOffset::Regular(
384 RegularBitOffset {
385 offset: 29,
386 },
387 ),
388 bit_size: 1,
389 array: None,
390 enumm: Some(
391 "Dec",
392 ),
393 },
394 Field {
395 name: "brsdec",
396 description: Some(
397 "Block repeat source address decrement. Note: On top of this increment/decrement (depending on BRSDEC), CH[x].SAR is in the same time also updated by the increment/decrement (depending on SDEC) of the CH[x].TR3.SAO value, as it is done after any programmed burst transfer.",
398 ),
399 bit_offset: BitOffset::Regular(
400 RegularBitOffset {
401 offset: 30,
402 },
403 ),
404 bit_size: 1,
405 array: None,
406 enumm: Some(
407 "Dec",
408 ),
409 },
410 Field {
411 name: "brddec",
412 description: Some(
413 "Block repeat destination address decrement. Note: On top of this increment/decrement (depending on BRDDEC), CH[x].DAR is in the same time also updated by the increment/decrement (depending on DDEC) of the CH[x].TR3.DAO value, as it is usually done at the end of each programmed burst transfer.",
414 ),
415 bit_offset: BitOffset::Regular(
416 RegularBitOffset {
417 offset: 31,
418 },
419 ),
420 bit_size: 1,
421 array: None,
422 enumm: Some(
423 "Dec",
424 ),
425 },
426 ],
427 },
428 FieldSet {
429 name: "ChBr2",
430 extends: None,
431 description: Some(
432 "GPDMA channel 12 block register 2",
433 ),
434 bit_size: 32,
435 fields: &[
436 Field {
437 name: "brsao",
438 description: Some(
439 "Block repeated source address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRSDEC) the current source address (CH[x].SAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (BRSAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued.",
440 ),
441 bit_offset: BitOffset::Regular(
442 RegularBitOffset {
443 offset: 0,
444 },
445 ),
446 bit_size: 16,
447 array: None,
448 enumm: None,
449 },
450 Field {
451 name: "brdao",
452 description: Some(
453 "Block repeated destination address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRDDEC) the current destination address (CH[x].DAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (BRDAO[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued.",
454 ),
455 bit_offset: BitOffset::Regular(
456 RegularBitOffset {
457 offset: 16,
458 },
459 ),
460 bit_size: 16,
461 array: None,
462 enumm: None,
463 },
464 ],
465 },
466 FieldSet {
467 name: "ChCr",
468 extends: None,
469 description: Some(
470 "GPDMA channel 11 control register",
471 ),
472 bit_size: 32,
473 fields: &[
474 Field {
475 name: "en",
476 description: Some(
477 "enable. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored.",
478 ),
479 bit_offset: BitOffset::Regular(
480 RegularBitOffset {
481 offset: 0,
482 },
483 ),
484 bit_size: 1,
485 array: None,
486 enumm: None,
487 },
488 Field {
489 name: "reset",
490 description: Some(
491 "reset. This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the FIFO, the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (CH[x].SR.SUSPF = 1 and CH[x].SR.IDLEF = CH[x].CR.EN = 1). - channel in disabled state (CH[x].SR.IDLEF = 1 and CH[x].CR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (CH[x].BR1, CH[x].SAR and CH[x].DAR) before enabling again the channel (see the programming sequence in ).",
492 ),
493 bit_offset: BitOffset::Regular(
494 RegularBitOffset {
495 offset: 1,
496 },
497 ),
498 bit_size: 1,
499 array: None,
500 enumm: None,
501 },
502 Field {
503 name: "susp",
504 description: Some(
505 "suspend. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going GPDMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in .",
506 ),
507 bit_offset: BitOffset::Regular(
508 RegularBitOffset {
509 offset: 2,
510 },
511 ),
512 bit_size: 1,
513 array: None,
514 enumm: None,
515 },
516 Field {
517 name: "tcie",
518 description: Some(
519 "transfer complete interrupt enable",
520 ),
521 bit_offset: BitOffset::Regular(
522 RegularBitOffset {
523 offset: 8,
524 },
525 ),
526 bit_size: 1,
527 array: None,
528 enumm: None,
529 },
530 Field {
531 name: "htie",
532 description: Some(
533 "half transfer complete interrupt enable",
534 ),
535 bit_offset: BitOffset::Regular(
536 RegularBitOffset {
537 offset: 9,
538 },
539 ),
540 bit_size: 1,
541 array: None,
542 enumm: None,
543 },
544 Field {
545 name: "dteie",
546 description: Some(
547 "data transfer error interrupt enable",
548 ),
549 bit_offset: BitOffset::Regular(
550 RegularBitOffset {
551 offset: 10,
552 },
553 ),
554 bit_size: 1,
555 array: None,
556 enumm: None,
557 },
558 Field {
559 name: "uleie",
560 description: Some(
561 "update link transfer error interrupt enable",
562 ),
563 bit_offset: BitOffset::Regular(
564 RegularBitOffset {
565 offset: 11,
566 },
567 ),
568 bit_size: 1,
569 array: None,
570 enumm: None,
571 },
572 Field {
573 name: "useie",
574 description: Some(
575 "user setting error interrupt enable",
576 ),
577 bit_offset: BitOffset::Regular(
578 RegularBitOffset {
579 offset: 12,
580 },
581 ),
582 bit_size: 1,
583 array: None,
584 enumm: None,
585 },
586 Field {
587 name: "suspie",
588 description: Some(
589 "completed suspension interrupt enable",
590 ),
591 bit_offset: BitOffset::Regular(
592 RegularBitOffset {
593 offset: 13,
594 },
595 ),
596 bit_size: 1,
597 array: None,
598 enumm: None,
599 },
600 Field {
601 name: "toie",
602 description: Some(
603 "trigger overrun interrupt enable",
604 ),
605 bit_offset: BitOffset::Regular(
606 RegularBitOffset {
607 offset: 14,
608 },
609 ),
610 bit_size: 1,
611 array: None,
612 enumm: None,
613 },
614 Field {
615 name: "lsm",
616 description: Some(
617 "Link step mode. First the (possible 1D/repeated) block transfer is executed as defined by the current internal register file until CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present. Secondly the next linked-list data structure is conditionally uploaded from memory as defined by CH[x].LLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1.",
618 ),
619 bit_offset: BitOffset::Regular(
620 RegularBitOffset {
621 offset: 16,
622 },
623 ),
624 bit_size: 1,
625 array: None,
626 enumm: Some(
627 "Lsm",
628 ),
629 },
630 Field {
631 name: "lap",
632 description: Some(
633 "linked-list allocated port. This bit is used to allocate the master port for the update of the GPDMA linked-list registers from the memory. Note: This bit must be written when EN=0. This bit is read-only when EN=1.",
634 ),
635 bit_offset: BitOffset::Regular(
636 RegularBitOffset {
637 offset: 17,
638 },
639 ),
640 bit_size: 1,
641 array: None,
642 enumm: Some(
643 "Ap",
644 ),
645 },
646 Field {
647 name: "prio",
648 description: Some(
649 "priority level of the channel x GPDMA transfer versus others. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.",
650 ),
651 bit_offset: BitOffset::Regular(
652 RegularBitOffset {
653 offset: 22,
654 },
655 ),
656 bit_size: 2,
657 array: None,
658 enumm: Some(
659 "Prio",
660 ),
661 },
662 ],
663 },
664 FieldSet {
665 name: "ChFcr",
666 extends: None,
667 description: Some(
668 "GPDMA channel 7 flag clear register",
669 ),
670 bit_size: 32,
671 fields: &[
672 Field {
673 name: "tcf",
674 description: Some(
675 "transfer complete flag clear",
676 ),
677 bit_offset: BitOffset::Regular(
678 RegularBitOffset {
679 offset: 8,
680 },
681 ),
682 bit_size: 1,
683 array: None,
684 enumm: None,
685 },
686 Field {
687 name: "htf",
688 description: Some(
689 "half transfer flag clear",
690 ),
691 bit_offset: BitOffset::Regular(
692 RegularBitOffset {
693 offset: 9,
694 },
695 ),
696 bit_size: 1,
697 array: None,
698 enumm: None,
699 },
700 Field {
701 name: "dtef",
702 description: Some(
703 "data transfer error flag clear",
704 ),
705 bit_offset: BitOffset::Regular(
706 RegularBitOffset {
707 offset: 10,
708 },
709 ),
710 bit_size: 1,
711 array: None,
712 enumm: None,
713 },
714 Field {
715 name: "ulef",
716 description: Some(
717 "update link transfer error flag clear",
718 ),
719 bit_offset: BitOffset::Regular(
720 RegularBitOffset {
721 offset: 11,
722 },
723 ),
724 bit_size: 1,
725 array: None,
726 enumm: None,
727 },
728 Field {
729 name: "usef",
730 description: Some(
731 "user setting error flag clear",
732 ),
733 bit_offset: BitOffset::Regular(
734 RegularBitOffset {
735 offset: 12,
736 },
737 ),
738 bit_size: 1,
739 array: None,
740 enumm: None,
741 },
742 Field {
743 name: "suspf",
744 description: Some(
745 "completed suspension flag clear",
746 ),
747 bit_offset: BitOffset::Regular(
748 RegularBitOffset {
749 offset: 13,
750 },
751 ),
752 bit_size: 1,
753 array: None,
754 enumm: None,
755 },
756 Field {
757 name: "tof",
758 description: Some(
759 "trigger overrun flag clear",
760 ),
761 bit_offset: BitOffset::Regular(
762 RegularBitOffset {
763 offset: 14,
764 },
765 ),
766 bit_size: 1,
767 array: None,
768 enumm: None,
769 },
770 ],
771 },
772 FieldSet {
773 name: "ChLbar",
774 extends: None,
775 description: Some(
776 "GPDMA channel 14 linked-list base address register",
777 ),
778 bit_size: 32,
779 fields: &[
780 Field {
781 name: "lba",
782 description: Some(
783 "linked-list base address of GPDMA channel x",
784 ),
785 bit_offset: BitOffset::Regular(
786 RegularBitOffset {
787 offset: 16,
788 },
789 ),
790 bit_size: 16,
791 array: None,
792 enumm: None,
793 },
794 ],
795 },
796 FieldSet {
797 name: "ChLlr",
798 extends: None,
799 description: Some(
800 "GPDMA channel 15 alternate linked-list address register",
801 ),
802 bit_size: 32,
803 fields: &[
804 Field {
805 name: "la",
806 description: Some(
807 "pointer (16-bit low-significant address) to the next linked-list data structure. If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list GPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list GPDMA internal register file (CH[x].CTR1, CH[x].TR2, CH[x].BR1, CH[x].SAR, CH[x].DAR and CH[x].LLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored.",
808 ),
809 bit_offset: BitOffset::Regular(
810 RegularBitOffset {
811 offset: 2,
812 },
813 ),
814 bit_size: 14,
815 array: None,
816 enumm: None,
817 },
818 Field {
819 name: "ull",
820 description: Some(
821 "Update CH[x].LLR register from memory. This bit is used to control the update of CH[x].LLR from the memory during the link transfer.",
822 ),
823 bit_offset: BitOffset::Regular(
824 RegularBitOffset {
825 offset: 16,
826 },
827 ),
828 bit_size: 1,
829 array: None,
830 enumm: None,
831 },
832 Field {
833 name: "ub2",
834 description: Some(
835 "Update CH[x].BR2 from memory. This bit controls the update of CH[x].BR2 from the memory during the link transfer.",
836 ),
837 bit_offset: BitOffset::Regular(
838 RegularBitOffset {
839 offset: 25,
840 },
841 ),
842 bit_size: 1,
843 array: None,
844 enumm: None,
845 },
846 Field {
847 name: "ut3",
848 description: Some(
849 "Update CH[x].TR3 from memory. This bit controls the update of CH[x].TR3 from the memory during the link transfer.",
850 ),
851 bit_offset: BitOffset::Regular(
852 RegularBitOffset {
853 offset: 26,
854 },
855 ),
856 bit_size: 1,
857 array: None,
858 enumm: None,
859 },
860 Field {
861 name: "uda",
862 description: Some(
863 "Update CH[x].DAR register from memory. This bit is used to control the update of CH[x].DAR from the memory during the link transfer.",
864 ),
865 bit_offset: BitOffset::Regular(
866 RegularBitOffset {
867 offset: 27,
868 },
869 ),
870 bit_size: 1,
871 array: None,
872 enumm: None,
873 },
874 Field {
875 name: "usa",
876 description: Some(
877 "update CH[x].SAR from memory. This bit controls the update of CH[x].SAR from the memory during the link transfer.",
878 ),
879 bit_offset: BitOffset::Regular(
880 RegularBitOffset {
881 offset: 28,
882 },
883 ),
884 bit_size: 1,
885 array: None,
886 enumm: None,
887 },
888 Field {
889 name: "ub1",
890 description: Some(
891 "Update CH[x].BR1 from memory. This bit controls the update of CH[x].BR1 from the memory during the link transfer. If UB1 = 0 and if CH[x].LLR ≠ 0, the linked-list is not completed. CH[x].BR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer.",
892 ),
893 bit_offset: BitOffset::Regular(
894 RegularBitOffset {
895 offset: 29,
896 },
897 ),
898 bit_size: 1,
899 array: None,
900 enumm: None,
901 },
902 Field {
903 name: "ut2",
904 description: Some(
905 "Update CH[x].TR2 from memory. This bit controls the update of CH[x].TR2 from the memory during the link transfer.",
906 ),
907 bit_offset: BitOffset::Regular(
908 RegularBitOffset {
909 offset: 30,
910 },
911 ),
912 bit_size: 1,
913 array: None,
914 enumm: None,
915 },
916 Field {
917 name: "ut1",
918 description: Some(
919 "Update CH[x].TR1 from memory. This bit controls the update of CH[x].TR1 from the memory during the link transfer.",
920 ),
921 bit_offset: BitOffset::Regular(
922 RegularBitOffset {
923 offset: 31,
924 },
925 ),
926 bit_size: 1,
927 array: None,
928 enumm: None,
929 },
930 ],
931 },
932 FieldSet {
933 name: "ChSr",
934 extends: None,
935 description: Some(
936 "GPDMA channel 15 status register",
937 ),
938 bit_size: 32,
939 fields: &[
940 Field {
941 name: "idlef",
942 description: Some(
943 "idle flag. This idle flag is de-asserted by hardware when the channel is enabled (CH[x].CR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state).",
944 ),
945 bit_offset: BitOffset::Regular(
946 RegularBitOffset {
947 offset: 0,
948 },
949 ),
950 bit_size: 1,
951 array: None,
952 enumm: None,
953 },
954 Field {
955 name: "tcf",
956 description: Some(
957 "transfer complete flag. A transfer complete event is either a block transfer complete, a 2D/repeated block transfer complete, a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0]).",
958 ),
959 bit_offset: BitOffset::Regular(
960 RegularBitOffset {
961 offset: 8,
962 },
963 ),
964 bit_size: 1,
965 array: None,
966 enumm: None,
967 },
968 Field {
969 name: "htf",
970 description: Some(
971 "half transfer flag. An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0]). An half block transfer occurs when half of the bytes of the source block size (rounded up integer of CH[x].BR1.BNDT[15:0]/2) has been transferred to the destination. An half 2D/repeated block transfer occurs when half of the repeated blocks (rounded up integer of (CH[x].BR1.BRC[10:0]+1)/2)) has been transferred to the destination.",
972 ),
973 bit_offset: BitOffset::Regular(
974 RegularBitOffset {
975 offset: 9,
976 },
977 ),
978 bit_size: 1,
979 array: None,
980 enumm: None,
981 },
982 Field {
983 name: "dtef",
984 description: Some(
985 "data transfer error flag",
986 ),
987 bit_offset: BitOffset::Regular(
988 RegularBitOffset {
989 offset: 10,
990 },
991 ),
992 bit_size: 1,
993 array: None,
994 enumm: None,
995 },
996 Field {
997 name: "ulef",
998 description: Some(
999 "update link transfer error flag",
1000 ),
1001 bit_offset: BitOffset::Regular(
1002 RegularBitOffset {
1003 offset: 11,
1004 },
1005 ),
1006 bit_size: 1,
1007 array: None,
1008 enumm: None,
1009 },
1010 Field {
1011 name: "usef",
1012 description: Some(
1013 "user setting error flag",
1014 ),
1015 bit_offset: BitOffset::Regular(
1016 RegularBitOffset {
1017 offset: 12,
1018 },
1019 ),
1020 bit_size: 1,
1021 array: None,
1022 enumm: None,
1023 },
1024 Field {
1025 name: "suspf",
1026 description: Some(
1027 "completed suspension flag",
1028 ),
1029 bit_offset: BitOffset::Regular(
1030 RegularBitOffset {
1031 offset: 13,
1032 },
1033 ),
1034 bit_size: 1,
1035 array: None,
1036 enumm: None,
1037 },
1038 Field {
1039 name: "tof",
1040 description: Some(
1041 "trigger overrun flag",
1042 ),
1043 bit_offset: BitOffset::Regular(
1044 RegularBitOffset {
1045 offset: 14,
1046 },
1047 ),
1048 bit_size: 1,
1049 array: None,
1050 enumm: None,
1051 },
1052 Field {
1053 name: "fifol",
1054 description: Some(
1055 "monitored FIFO level. Number of available write beats in the FIFO, in units of the programmed destination data width (see CH[x].TR1.DDW[1:0], in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to CH[x].BR1.BDNT[15:0] and CH[x].BR1.BRC[10:0], to know how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be suspended (CH[x].SR.SUSPF = 1).",
1056 ),
1057 bit_offset: BitOffset::Regular(
1058 RegularBitOffset {
1059 offset: 16,
1060 },
1061 ),
1062 bit_size: 8,
1063 array: None,
1064 enumm: None,
1065 },
1066 ],
1067 },
1068 FieldSet {
1069 name: "ChTr1",
1070 extends: None,
1071 description: Some(
1072 "GPDMA channel 8 transfer register 1",
1073 ),
1074 bit_size: 32,
1075 fields: &[
1076 Field {
1077 name: "sdw",
1078 description: Some(
1079 "binary logarithm of the source data width of a burst in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and no transfer is issued. A source block size must be a multiple of the source data width (CH[x].BR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address CH[x].SAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued.",
1080 ),
1081 bit_offset: BitOffset::Regular(
1082 RegularBitOffset {
1083 offset: 0,
1084 },
1085 ),
1086 bit_size: 2,
1087 array: None,
1088 enumm: Some(
1089 "Dw",
1090 ),
1091 },
1092 Field {
1093 name: "sinc",
1094 description: Some(
1095 "source incrementing burst. The source address, pointed by CH[x].SAR, is kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer.",
1096 ),
1097 bit_offset: BitOffset::Regular(
1098 RegularBitOffset {
1099 offset: 3,
1100 },
1101 ),
1102 bit_size: 1,
1103 array: None,
1104 enumm: None,
1105 },
1106 Field {
1107 name: "sbl_1",
1108 description: Some(
1109 "source burst length minus 1, between 0 and 63. The burst length unit is one data named beat within a burst. If SBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width SDW_LOG2[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed.",
1110 ),
1111 bit_offset: BitOffset::Regular(
1112 RegularBitOffset {
1113 offset: 4,
1114 },
1115 ),
1116 bit_size: 6,
1117 array: None,
1118 enumm: None,
1119 },
1120 Field {
1121 name: "pam",
1122 description: Some(
1123 "padding/alignment mode. If DDW[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination transfer is equal to the data width of a burst source transfer, these bits are ignored. Else: - Case 1: If destination data width > source data width. 1x: successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer. - Case 2: If destination data width < source data width. 1x: source data is FIFO queued and unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination. Note:",
1124 ),
1125 bit_offset: BitOffset::Regular(
1126 RegularBitOffset {
1127 offset: 11,
1128 },
1129 ),
1130 bit_size: 2,
1131 array: None,
1132 enumm: Some(
1133 "Pam",
1134 ),
1135 },
1136 Field {
1137 name: "sbx",
1138 description: Some(
1139 "source byte exchange within the unaligned half-word of each source word. If set, the two consecutive bytes within the unaligned half-word of each source word are exchanged. If the source data width is shorter than a word, this bit is ignored.",
1140 ),
1141 bit_offset: BitOffset::Regular(
1142 RegularBitOffset {
1143 offset: 13,
1144 },
1145 ),
1146 bit_size: 1,
1147 array: None,
1148 enumm: None,
1149 },
1150 Field {
1151 name: "sap",
1152 description: Some(
1153 "source allocated port. This bit is used to allocate the master port for the source transfer. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.",
1154 ),
1155 bit_offset: BitOffset::Regular(
1156 RegularBitOffset {
1157 offset: 14,
1158 },
1159 ),
1160 bit_size: 1,
1161 array: None,
1162 enumm: Some(
1163 "Ap",
1164 ),
1165 },
1166 Field {
1167 name: "ssec",
1168 description: Some(
1169 "security attribute of the GPDMA transfer from the source. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx =1 . A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer from the source is non-secure.",
1170 ),
1171 bit_offset: BitOffset::Regular(
1172 RegularBitOffset {
1173 offset: 15,
1174 },
1175 ),
1176 bit_size: 1,
1177 array: None,
1178 enumm: None,
1179 },
1180 Field {
1181 name: "ddw",
1182 description: Some(
1183 "binary logarithm of the destination data width of a burst, in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination burst transfer must have an aligned address with its data width (start address CH[x].DAR[2:0] and address offset CH[x].TR3.DAO[2:0], versus DDW[1:0]). Otherwise a user setting error is reported and no transfer is issued.",
1184 ),
1185 bit_offset: BitOffset::Regular(
1186 RegularBitOffset {
1187 offset: 16,
1188 },
1189 ),
1190 bit_size: 2,
1191 array: None,
1192 enumm: Some(
1193 "Dw",
1194 ),
1195 },
1196 Field {
1197 name: "dinc",
1198 description: Some(
1199 "destination incrementing burst. The destination address, pointed by CH[x].DAR, is kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer.",
1200 ),
1201 bit_offset: BitOffset::Regular(
1202 RegularBitOffset {
1203 offset: 19,
1204 },
1205 ),
1206 bit_size: 1,
1207 array: None,
1208 enumm: None,
1209 },
1210 Field {
1211 name: "dbl_1",
1212 description: Some(
1213 "destination burst length minus 1, between 0 and 63. The burst length unit is one data named beat within a burst. If DBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width DDW[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed.",
1214 ),
1215 bit_offset: BitOffset::Regular(
1216 RegularBitOffset {
1217 offset: 20,
1218 },
1219 ),
1220 bit_size: 6,
1221 array: None,
1222 enumm: None,
1223 },
1224 Field {
1225 name: "dbx",
1226 description: Some(
1227 "destination byte exchange. IF set, the two consecutive (post PAM) bytes are exchanged in each destination half-word. If the destination data size is a byte, this bit is ignored.",
1228 ),
1229 bit_offset: BitOffset::Regular(
1230 RegularBitOffset {
1231 offset: 26,
1232 },
1233 ),
1234 bit_size: 1,
1235 array: None,
1236 enumm: None,
1237 },
1238 Field {
1239 name: "dhx",
1240 description: Some(
1241 "destination half-word exchange. If set, e two consecutive (post PAM) half-words are exchanged in each destination word. If the destination data size is shorter than a word, this bit is ignored.",
1242 ),
1243 bit_offset: BitOffset::Regular(
1244 RegularBitOffset {
1245 offset: 27,
1246 },
1247 ),
1248 bit_size: 1,
1249 array: None,
1250 enumm: None,
1251 },
1252 Field {
1253 name: "dap",
1254 description: Some(
1255 "destination allocated port. This bit is used to allocate the master port for the destination transfer. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.",
1256 ),
1257 bit_offset: BitOffset::Regular(
1258 RegularBitOffset {
1259 offset: 30,
1260 },
1261 ),
1262 bit_size: 1,
1263 array: None,
1264 enumm: Some(
1265 "Ap",
1266 ),
1267 },
1268 Field {
1269 name: "dsec",
1270 description: Some(
1271 "security attribute of the GPDMA transfer to the destination. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx = 1. A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer to the destination is non-secure.",
1272 ),
1273 bit_offset: BitOffset::Regular(
1274 RegularBitOffset {
1275 offset: 31,
1276 },
1277 ),
1278 bit_size: 1,
1279 array: None,
1280 enumm: None,
1281 },
1282 ],
1283 },
1284 FieldSet {
1285 name: "ChTr2",
1286 extends: None,
1287 description: Some(
1288 "GPDMA channel 10 transfer register 2",
1289 ),
1290 bit_size: 32,
1291 fields: &[
1292 Field {
1293 name: "reqsel",
1294 description: Some(
1295 "GPDMA hardware request selection. These bits are ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per . The user must not assign a same input hardware request (same REQSEL[6:0] value) to different active GPDMA channels (CH[x].CR.EN = 1 and CH[x].TR2.SWREQ = 0 for these channels). GPDMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting.",
1296 ),
1297 bit_offset: BitOffset::Regular(
1298 RegularBitOffset {
1299 offset: 0,
1300 },
1301 ),
1302 bit_size: 7,
1303 array: None,
1304 enumm: None,
1305 },
1306 Field {
1307 name: "swreq",
1308 description: Some(
1309 "software request. This bit is internally taken into account when CH[x].CR.EN is asserted.",
1310 ),
1311 bit_offset: BitOffset::Regular(
1312 RegularBitOffset {
1313 offset: 9,
1314 },
1315 ),
1316 bit_size: 1,
1317 array: None,
1318 enumm: Some(
1319 "Swreq",
1320 ),
1321 },
1322 Field {
1323 name: "dreq",
1324 description: Some(
1325 "destination hardware request. This bit is ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else: Note:",
1326 ),
1327 bit_offset: BitOffset::Regular(
1328 RegularBitOffset {
1329 offset: 10,
1330 },
1331 ),
1332 bit_size: 1,
1333 array: None,
1334 enumm: Some(
1335 "Dreq",
1336 ),
1337 },
1338 Field {
1339 name: "breq",
1340 description: Some(
1341 "Block hardware request. If the channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else:",
1342 ),
1343 bit_offset: BitOffset::Regular(
1344 RegularBitOffset {
1345 offset: 11,
1346 },
1347 ),
1348 bit_size: 1,
1349 array: None,
1350 enumm: Some(
1351 "Breq",
1352 ),
1353 },
1354 Field {
1355 name: "trigm",
1356 description: Some(
1357 "trigger mode. These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (CH[x].CR.EN asserted) with TRIGPOL[1:0] = 00 or 11, these TRIGM[1:0] bits are ignored. Else, a GPDMA transfer is conditioned by at least one trigger hit: first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. – If the peripheral is programmed as a source (DREQ = 0) of the LLI data transfer, each programmed burst read is conditioned. – If the peripheral is programmed as a destination (DREQ = 1) of the LLI data transfer, each programmed burst write is conditioned. The first memory burst read of a (possibly 2D/repeated) block, also named as the first ready FIFO-based source burst, is gated by the occurrence of both the hardware request and the first trigger hit. The GPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 01 or respectively TRIGPOL[1:0] = 10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[5:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the CH[x].TR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized.memorized. A trigger overrun flag is reported (CH[x].SR.TOF =1 ), and an interrupt is generated if enabled (CH[x].CR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0] = 11 and (SWREQ =1 or (SWREQ = 0 and DREQ =0 )), the shortened burst transfer (by singles or/and by bursts of lower length) is conditioned once by the trigger. When the programmed destination burst is internally shortened by singles or/and by bursts of lower length (versus FIFO size, versus block size, 1-Kbyte boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0] = 11 and SWREQ = 0 and DREQ = 1), this shortened destination burst transfer is conditioned once by the trigger.",
1358 ),
1359 bit_offset: BitOffset::Regular(
1360 RegularBitOffset {
1361 offset: 14,
1362 },
1363 ),
1364 bit_size: 2,
1365 array: None,
1366 enumm: Some(
1367 "Trigm",
1368 ),
1369 },
1370 Field {
1371 name: "trigsel",
1372 description: Some(
1373 "trigger event input selection. These bits select the trigger event input of the GPDMA transfer (as per ), with an active trigger event if TRIGPOL[1:0] ≠ 00.",
1374 ),
1375 bit_offset: BitOffset::Regular(
1376 RegularBitOffset {
1377 offset: 16,
1378 },
1379 ),
1380 bit_size: 6,
1381 array: None,
1382 enumm: None,
1383 },
1384 Field {
1385 name: "trigpol",
1386 description: Some(
1387 "trigger event polarity. These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0].",
1388 ),
1389 bit_offset: BitOffset::Regular(
1390 RegularBitOffset {
1391 offset: 24,
1392 },
1393 ),
1394 bit_size: 2,
1395 array: None,
1396 enumm: Some(
1397 "Trigpol",
1398 ),
1399 },
1400 Field {
1401 name: "tcem",
1402 description: Some(
1403 "transfer complete event mode. These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1.",
1404 ),
1405 bit_offset: BitOffset::Regular(
1406 RegularBitOffset {
1407 offset: 30,
1408 },
1409 ),
1410 bit_size: 2,
1411 array: None,
1412 enumm: Some(
1413 "Tcem",
1414 ),
1415 },
1416 ],
1417 },
1418 FieldSet {
1419 name: "ChTr3",
1420 extends: None,
1421 description: Some(
1422 "GPDMA channel 14 transfer register 3",
1423 ),
1424 bit_size: 32,
1425 fields: &[
1426 Field {
1427 name: "sao",
1428 description: Some(
1429 "source address offset increment. The source address, pointed by CH[x].SAR, is incremented or decremented (depending on CH[x].BR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.SINC = 1). Note: A source address offset must be aligned with the programmed data width of a source burst (SAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional CH[x].TR3.SAO[12:0] is not applied.",
1430 ),
1431 bit_offset: BitOffset::Regular(
1432 RegularBitOffset {
1433 offset: 0,
1434 },
1435 ),
1436 bit_size: 13,
1437 array: None,
1438 enumm: None,
1439 },
1440 Field {
1441 name: "dao",
1442 description: Some(
1443 "destination address offset increment. The destination address, pointed by CH[x].DAR, is incremented or decremented (depending on CH[x].BR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.DINC = 1). Note: A destination address offset must be aligned with the programmed data width of a destination burst (DAO[2:0] versus CH[x].TR1.DDW[1:0]). Else, a user setting error is reported and no transfer is issued.",
1444 ),
1445 bit_offset: BitOffset::Regular(
1446 RegularBitOffset {
1447 offset: 16,
1448 },
1449 ),
1450 bit_size: 13,
1451 array: None,
1452 enumm: None,
1453 },
1454 ],
1455 },
1456 FieldSet {
1457 name: "Misr",
1458 extends: None,
1459 description: Some(
1460 "GPDMA secure masked interrupt status register",
1461 ),
1462 bit_size: 32,
1463 fields: &[
1464 Field {
1465 name: "mis",
1466 description: Some(
1467 "MIS0",
1468 ),
1469 bit_offset: BitOffset::Regular(
1470 RegularBitOffset {
1471 offset: 0,
1472 },
1473 ),
1474 bit_size: 1,
1475 array: Some(
1476 Array::Regular(
1477 RegularArray {
1478 len: 16,
1479 stride: 1,
1480 },
1481 ),
1482 ),
1483 enumm: None,
1484 },
1485 ],
1486 },
1487 FieldSet {
1488 name: "Privcfgr",
1489 extends: None,
1490 description: Some(
1491 "GPDMA privileged configuration register",
1492 ),
1493 bit_size: 32,
1494 fields: &[
1495 Field {
1496 name: "priv_",
1497 description: Some(
1498 "PRIV0",
1499 ),
1500 bit_offset: BitOffset::Regular(
1501 RegularBitOffset {
1502 offset: 0,
1503 },
1504 ),
1505 bit_size: 1,
1506 array: Some(
1507 Array::Regular(
1508 RegularArray {
1509 len: 16,
1510 stride: 1,
1511 },
1512 ),
1513 ),
1514 enumm: None,
1515 },
1516 ],
1517 },
1518 FieldSet {
1519 name: "Rcfglockr",
1520 extends: None,
1521 description: Some(
1522 "GPDMA configuration lock register",
1523 ),
1524 bit_size: 32,
1525 fields: &[
1526 Field {
1527 name: "lock",
1528 description: Some(
1529 "LOCK0",
1530 ),
1531 bit_offset: BitOffset::Regular(
1532 RegularBitOffset {
1533 offset: 0,
1534 },
1535 ),
1536 bit_size: 1,
1537 array: Some(
1538 Array::Regular(
1539 RegularArray {
1540 len: 16,
1541 stride: 1,
1542 },
1543 ),
1544 ),
1545 enumm: None,
1546 },
1547 ],
1548 },
1549 FieldSet {
1550 name: "Seccfgr",
1551 extends: None,
1552 description: Some(
1553 "GPDMA secure configuration register",
1554 ),
1555 bit_size: 32,
1556 fields: &[
1557 Field {
1558 name: "sec",
1559 description: Some(
1560 "SEC0",
1561 ),
1562 bit_offset: BitOffset::Regular(
1563 RegularBitOffset {
1564 offset: 0,
1565 },
1566 ),
1567 bit_size: 1,
1568 array: Some(
1569 Array::Regular(
1570 RegularArray {
1571 len: 16,
1572 stride: 1,
1573 },
1574 ),
1575 ),
1576 enumm: None,
1577 },
1578 ],
1579 },
1580 ],
1581 enums: &[
1582 Enum {
1583 name: "Ap",
1584 description: None,
1585 bit_size: 1,
1586 variants: &[
1587 EnumVariant {
1588 name: "PORT0",
1589 description: Some(
1590 "port 0 (AHB) allocated",
1591 ),
1592 value: 0,
1593 },
1594 EnumVariant {
1595 name: "PORT1",
1596 description: Some(
1597 "port 1 (AHB) allocated",
1598 ),
1599 value: 1,
1600 },
1601 ],
1602 },
1603 Enum {
1604 name: "Breq",
1605 description: None,
1606 bit_size: 1,
1607 variants: &[
1608 EnumVariant {
1609 name: "BURST",
1610 description: Some(
1611 "the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level.",
1612 ),
1613 value: 0,
1614 },
1615 EnumVariant {
1616 name: "BLOCK",
1617 description: Some(
1618 "the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ).",
1619 ),
1620 value: 1,
1621 },
1622 ],
1623 },
1624 Enum {
1625 name: "Dec",
1626 description: None,
1627 bit_size: 1,
1628 variants: &[
1629 EnumVariant {
1630 name: "ADD",
1631 description: Some(
1632 "The address is incremented by the programmed offset.",
1633 ),
1634 value: 0,
1635 },
1636 EnumVariant {
1637 name: "SUBTRACT",
1638 description: Some(
1639 "The address is decremented by the programmed offset.",
1640 ),
1641 value: 1,
1642 },
1643 ],
1644 },
1645 Enum {
1646 name: "Dreq",
1647 description: None,
1648 bit_size: 1,
1649 variants: &[
1650 EnumVariant {
1651 name: "SOURCE_PERIPHERAL",
1652 description: Some(
1653 "selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port)",
1654 ),
1655 value: 0,
1656 },
1657 EnumVariant {
1658 name: "DESTINATION_PERIPHERAL",
1659 description: Some(
1660 "selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port)",
1661 ),
1662 value: 1,
1663 },
1664 ],
1665 },
1666 Enum {
1667 name: "Dw",
1668 description: None,
1669 bit_size: 2,
1670 variants: &[
1671 EnumVariant {
1672 name: "BYTE",
1673 description: Some(
1674 "byte",
1675 ),
1676 value: 0,
1677 },
1678 EnumVariant {
1679 name: "HALF_WORD",
1680 description: Some(
1681 "half-word (2 bytes)",
1682 ),
1683 value: 1,
1684 },
1685 EnumVariant {
1686 name: "WORD",
1687 description: Some(
1688 "word (4 bytes)",
1689 ),
1690 value: 2,
1691 },
1692 ],
1693 },
1694 Enum {
1695 name: "Lsm",
1696 description: None,
1697 bit_size: 1,
1698 variants: &[
1699 EnumVariant {
1700 name: "RUN_TO_COMPLETION",
1701 description: Some(
1702 "channel executed for the full linked-list and completed at the end of the last LLI (CH[x].LLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 =UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present.",
1703 ),
1704 value: 0,
1705 },
1706 EnumVariant {
1707 name: "LINK_STEP",
1708 description: Some(
1709 "channel executed once for the current LLI",
1710 ),
1711 value: 1,
1712 },
1713 ],
1714 },
1715 Enum {
1716 name: "Pam",
1717 description: None,
1718 bit_size: 2,
1719 variants: &[
1720 EnumVariant {
1721 name: "ZERO_EXTEND_OR_LEFT_TRUNCATE",
1722 description: Some(
1723 "If destination is wider: source data is transferred as right aligned, padded with 0s up to the destination data width\nIf source is wider: source data is transferred as right aligned, left-truncated down to the destination data width",
1724 ),
1725 value: 0,
1726 },
1727 EnumVariant {
1728 name: "SIGN_EXTEND_OR_RIGHT_TRUNCATE",
1729 description: Some(
1730 "If destination is wider: source data is transferred as right aligned, sign extended up to the destination data width\nIf source is wider: source data is transferred as left-aligned, right-truncated down to the destination data width",
1731 ),
1732 value: 1,
1733 },
1734 EnumVariant {
1735 name: "PACK",
1736 description: Some(
1737 "source data is FIFO queued and packed/unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination",
1738 ),
1739 value: 2,
1740 },
1741 ],
1742 },
1743 Enum {
1744 name: "Prio",
1745 description: None,
1746 bit_size: 2,
1747 variants: &[
1748 EnumVariant {
1749 name: "LOW_WITH_LOWH_WEIGHT",
1750 description: Some(
1751 "low priority, low weight",
1752 ),
1753 value: 0,
1754 },
1755 EnumVariant {
1756 name: "LOW_WITH_MID_WEIGHT",
1757 description: Some(
1758 "low priority, mid weight",
1759 ),
1760 value: 1,
1761 },
1762 EnumVariant {
1763 name: "LOW_WITH_HIGH_WEIGHT",
1764 description: Some(
1765 "low priority, high weight",
1766 ),
1767 value: 2,
1768 },
1769 EnumVariant {
1770 name: "HIGH",
1771 description: Some(
1772 "high priority",
1773 ),
1774 value: 3,
1775 },
1776 ],
1777 },
1778 Enum {
1779 name: "Swreq",
1780 description: None,
1781 bit_size: 1,
1782 variants: &[
1783 EnumVariant {
1784 name: "HARDWARE",
1785 description: Some(
1786 "no software request. The selected hardware request REQSEL[6:0] is taken into account.",
1787 ),
1788 value: 0,
1789 },
1790 EnumVariant {
1791 name: "SOFTWARE",
1792 description: Some(
1793 "software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored.",
1794 ),
1795 value: 1,
1796 },
1797 ],
1798 },
1799 Enum {
1800 name: "Tcem",
1801 description: None,
1802 bit_size: 2,
1803 variants: &[
1804 EnumVariant {
1805 name: "EACH_BLOCK",
1806 description: Some(
1807 "at block level (when CH[x].BR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block.",
1808 ),
1809 value: 0,
1810 },
1811 EnumVariant {
1812 name: "EACH2DBLOCK",
1813 description: Some(
1814 "channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when CH[x].BR1.BRC[10:0] = 0 and CH[x].BR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block.",
1815 ),
1816 value: 1,
1817 },
1818 EnumVariant {
1819 name: "EACH_LINKED_LIST_ITEM",
1820 description: Some(
1821 "at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer.",
1822 ),
1823 value: 2,
1824 },
1825 EnumVariant {
1826 name: "LAST_LINKED_LIST_ITEM",
1827 description: Some(
1828 "at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address CH[x].LLR.LA[15:2] to zero and clears all the CH[x].LLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated.",
1829 ),
1830 value: 3,
1831 },
1832 ],
1833 },
1834 Enum {
1835 name: "Trigm",
1836 description: None,
1837 bit_size: 2,
1838 variants: &[
1839 EnumVariant {
1840 name: "BLOCK",
1841 description: Some(
1842 "at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with CH[x].BR1.BRC[10:0] ≠ 0).",
1843 ),
1844 value: 0,
1845 },
1846 EnumVariant {
1847 name: "_2DBLOCK",
1848 description: Some(
1849 "channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the",
1850 ),
1851 value: 1,
1852 },
1853 EnumVariant {
1854 name: "LINKED_LIST_ITEM",
1855 description: Some(
1856 "at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned.",
1857 ),
1858 value: 2,
1859 },
1860 EnumVariant {
1861 name: "BURST",
1862 description: Some(
1863 "at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger.",
1864 ),
1865 value: 3,
1866 },
1867 ],
1868 },
1869 Enum {
1870 name: "Trigpol",
1871 description: None,
1872 bit_size: 2,
1873 variants: &[
1874 EnumVariant {
1875 name: "NONE",
1876 description: Some(
1877 "no trigger (masked trigger event)",
1878 ),
1879 value: 0,
1880 },
1881 EnumVariant {
1882 name: "RISING_EDGE",
1883 description: Some(
1884 "trigger on the rising edge",
1885 ),
1886 value: 1,
1887 },
1888 EnumVariant {
1889 name: "FALLING_EDGE",
1890 description: Some(
1891 "trigger on the falling edge",
1892 ),
1893 value: 2,
1894 },
1895 EnumVariant {
1896 name: "NONE_ALT",
1897 description: Some(
1898 "same as 00",
1899 ),
1900 value: 3,
1901 },
1902 ],
1903 },
1904 ],
1905};
1906