1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Gpio",
7 extends: None,
8 description: Some(
9 "General-purpose I/Os",
10 ),
11 items: &[
12 BlockItem {
13 name: "moder",
14 description: Some(
15 "GPIO port mode register",
16 ),
17 array: None,
18 byte_offset: 0x0,
19 inner: BlockItemInner::Register(
20 Register {
21 access: Access::ReadWrite,
22 bit_size: 32,
23 fieldset: Some(
24 "Moder",
25 ),
26 },
27 ),
28 },
29 BlockItem {
30 name: "otyper",
31 description: Some(
32 "GPIO port output type register",
33 ),
34 array: None,
35 byte_offset: 0x4,
36 inner: BlockItemInner::Register(
37 Register {
38 access: Access::ReadWrite,
39 bit_size: 32,
40 fieldset: Some(
41 "Otyper",
42 ),
43 },
44 ),
45 },
46 BlockItem {
47 name: "ospeedr",
48 description: Some(
49 "GPIO port output speed register",
50 ),
51 array: None,
52 byte_offset: 0x8,
53 inner: BlockItemInner::Register(
54 Register {
55 access: Access::ReadWrite,
56 bit_size: 32,
57 fieldset: Some(
58 "Ospeedr",
59 ),
60 },
61 ),
62 },
63 BlockItem {
64 name: "pupdr",
65 description: Some(
66 "GPIO port pull-up/pull-down register",
67 ),
68 array: None,
69 byte_offset: 0xc,
70 inner: BlockItemInner::Register(
71 Register {
72 access: Access::ReadWrite,
73 bit_size: 32,
74 fieldset: Some(
75 "Pupdr",
76 ),
77 },
78 ),
79 },
80 BlockItem {
81 name: "idr",
82 description: Some(
83 "GPIO port input data register",
84 ),
85 array: None,
86 byte_offset: 0x10,
87 inner: BlockItemInner::Register(
88 Register {
89 access: Access::Read,
90 bit_size: 32,
91 fieldset: Some(
92 "Idr",
93 ),
94 },
95 ),
96 },
97 BlockItem {
98 name: "odr",
99 description: Some(
100 "GPIO port output data register",
101 ),
102 array: None,
103 byte_offset: 0x14,
104 inner: BlockItemInner::Register(
105 Register {
106 access: Access::ReadWrite,
107 bit_size: 32,
108 fieldset: Some(
109 "Odr",
110 ),
111 },
112 ),
113 },
114 BlockItem {
115 name: "bsrr",
116 description: Some(
117 "GPIO port bit set/reset register",
118 ),
119 array: None,
120 byte_offset: 0x18,
121 inner: BlockItemInner::Register(
122 Register {
123 access: Access::Write,
124 bit_size: 32,
125 fieldset: Some(
126 "Bsrr",
127 ),
128 },
129 ),
130 },
131 BlockItem {
132 name: "lckr",
133 description: Some(
134 "GPIO port configuration lock register",
135 ),
136 array: None,
137 byte_offset: 0x1c,
138 inner: BlockItemInner::Register(
139 Register {
140 access: Access::ReadWrite,
141 bit_size: 32,
142 fieldset: Some(
143 "Lckr",
144 ),
145 },
146 ),
147 },
148 BlockItem {
149 name: "afr",
150 description: Some(
151 "GPIO alternate function registers. The register described in the datasheet as AFRL is index 0 in this array, and AFRH is index 1. Note that when operating on AFRH, you need to subtract 8 from any operations on the field array it contains -- the alternate function for pin 9 is at index 1, for instance.",
152 ),
153 array: Some(
154 Array::Regular(
155 RegularArray {
156 len: 2,
157 stride: 4,
158 },
159 ),
160 ),
161 byte_offset: 0x20,
162 inner: BlockItemInner::Register(
163 Register {
164 access: Access::ReadWrite,
165 bit_size: 32,
166 fieldset: Some(
167 "Afr",
168 ),
169 },
170 ),
171 },
172 ],
173 },
174 ],
175 fieldsets: &[
176 FieldSet {
177 name: "Afr",
178 extends: None,
179 description: Some(
180 "GPIO alternate function register. This contains an array of 8 fields, which correspond to pins 0-7 of the port (for AFRL) or pins 8-15 of the port (for AFRH).",
181 ),
182 bit_size: 32,
183 fields: &[
184 Field {
185 name: "afr",
186 description: Some(
187 "Alternate function selection for one of the pins controlled by this register (0-7).",
188 ),
189 bit_offset: BitOffset::Regular(
190 RegularBitOffset {
191 offset: 0,
192 },
193 ),
194 bit_size: 4,
195 array: Some(
196 Array::Regular(
197 RegularArray {
198 len: 8,
199 stride: 4,
200 },
201 ),
202 ),
203 enumm: None,
204 },
205 ],
206 },
207 FieldSet {
208 name: "Bsrr",
209 extends: None,
210 description: Some(
211 "GPIO port bit set/reset register",
212 ),
213 bit_size: 32,
214 fields: &[
215 Field {
216 name: "bs",
217 description: Some(
218 "Port x set bit y (y= 0..15)",
219 ),
220 bit_offset: BitOffset::Regular(
221 RegularBitOffset {
222 offset: 0,
223 },
224 ),
225 bit_size: 1,
226 array: Some(
227 Array::Regular(
228 RegularArray {
229 len: 16,
230 stride: 1,
231 },
232 ),
233 ),
234 enumm: None,
235 },
236 Field {
237 name: "br",
238 description: Some(
239 "Port x set bit y (y= 0..15)",
240 ),
241 bit_offset: BitOffset::Regular(
242 RegularBitOffset {
243 offset: 16,
244 },
245 ),
246 bit_size: 1,
247 array: Some(
248 Array::Regular(
249 RegularArray {
250 len: 16,
251 stride: 1,
252 },
253 ),
254 ),
255 enumm: None,
256 },
257 ],
258 },
259 FieldSet {
260 name: "Idr",
261 extends: None,
262 description: Some(
263 "GPIO port input data register",
264 ),
265 bit_size: 32,
266 fields: &[
267 Field {
268 name: "idr",
269 description: Some(
270 "Port input data (y = 0..15)",
271 ),
272 bit_offset: BitOffset::Regular(
273 RegularBitOffset {
274 offset: 0,
275 },
276 ),
277 bit_size: 1,
278 array: Some(
279 Array::Regular(
280 RegularArray {
281 len: 16,
282 stride: 1,
283 },
284 ),
285 ),
286 enumm: Some(
287 "Idr",
288 ),
289 },
290 ],
291 },
292 FieldSet {
293 name: "Lckr",
294 extends: None,
295 description: Some(
296 "GPIO port configuration lock register",
297 ),
298 bit_size: 32,
299 fields: &[
300 Field {
301 name: "lck",
302 description: Some(
303 "Port configuration locked",
304 ),
305 bit_offset: BitOffset::Regular(
306 RegularBitOffset {
307 offset: 0,
308 },
309 ),
310 bit_size: 1,
311 array: Some(
312 Array::Regular(
313 RegularArray {
314 len: 16,
315 stride: 1,
316 },
317 ),
318 ),
319 enumm: None,
320 },
321 Field {
322 name: "lckk",
323 description: Some(
324 "Port configuration lock key active",
325 ),
326 bit_offset: BitOffset::Regular(
327 RegularBitOffset {
328 offset: 16,
329 },
330 ),
331 bit_size: 1,
332 array: None,
333 enumm: None,
334 },
335 ],
336 },
337 FieldSet {
338 name: "Moder",
339 extends: None,
340 description: Some(
341 "GPIO port mode register",
342 ),
343 bit_size: 32,
344 fields: &[
345 Field {
346 name: "moder",
347 description: Some(
348 "Port x configuration bits (y = 0..15)",
349 ),
350 bit_offset: BitOffset::Regular(
351 RegularBitOffset {
352 offset: 0,
353 },
354 ),
355 bit_size: 2,
356 array: Some(
357 Array::Regular(
358 RegularArray {
359 len: 16,
360 stride: 2,
361 },
362 ),
363 ),
364 enumm: Some(
365 "Moder",
366 ),
367 },
368 ],
369 },
370 FieldSet {
371 name: "Odr",
372 extends: None,
373 description: Some(
374 "GPIO port output data register",
375 ),
376 bit_size: 32,
377 fields: &[
378 Field {
379 name: "odr",
380 description: Some(
381 "Port output data (y = 0..15)",
382 ),
383 bit_offset: BitOffset::Regular(
384 RegularBitOffset {
385 offset: 0,
386 },
387 ),
388 bit_size: 1,
389 array: Some(
390 Array::Regular(
391 RegularArray {
392 len: 16,
393 stride: 1,
394 },
395 ),
396 ),
397 enumm: Some(
398 "Odr",
399 ),
400 },
401 ],
402 },
403 FieldSet {
404 name: "Ospeedr",
405 extends: None,
406 description: Some(
407 "GPIO port output speed register",
408 ),
409 bit_size: 32,
410 fields: &[
411 Field {
412 name: "ospeedr",
413 description: Some(
414 "Port x configuration bits (y = 0..15)",
415 ),
416 bit_offset: BitOffset::Regular(
417 RegularBitOffset {
418 offset: 0,
419 },
420 ),
421 bit_size: 2,
422 array: Some(
423 Array::Regular(
424 RegularArray {
425 len: 16,
426 stride: 2,
427 },
428 ),
429 ),
430 enumm: Some(
431 "Ospeedr",
432 ),
433 },
434 ],
435 },
436 FieldSet {
437 name: "Otyper",
438 extends: None,
439 description: Some(
440 "GPIO port output type register",
441 ),
442 bit_size: 32,
443 fields: &[
444 Field {
445 name: "ot",
446 description: Some(
447 "Port x configuration bits (y = 0..15)",
448 ),
449 bit_offset: BitOffset::Regular(
450 RegularBitOffset {
451 offset: 0,
452 },
453 ),
454 bit_size: 1,
455 array: Some(
456 Array::Regular(
457 RegularArray {
458 len: 16,
459 stride: 1,
460 },
461 ),
462 ),
463 enumm: Some(
464 "Ot",
465 ),
466 },
467 ],
468 },
469 FieldSet {
470 name: "Pupdr",
471 extends: None,
472 description: Some(
473 "GPIO port pull-up/pull-down register",
474 ),
475 bit_size: 32,
476 fields: &[
477 Field {
478 name: "pupdr",
479 description: Some(
480 "Port x configuration bits (y = 0..15)",
481 ),
482 bit_offset: BitOffset::Regular(
483 RegularBitOffset {
484 offset: 0,
485 },
486 ),
487 bit_size: 2,
488 array: Some(
489 Array::Regular(
490 RegularArray {
491 len: 16,
492 stride: 2,
493 },
494 ),
495 ),
496 enumm: Some(
497 "Pupdr",
498 ),
499 },
500 ],
501 },
502 ],
503 enums: &[
504 Enum {
505 name: "Idr",
506 description: None,
507 bit_size: 1,
508 variants: &[
509 EnumVariant {
510 name: "LOW",
511 description: Some(
512 "Input is logic low",
513 ),
514 value: 0,
515 },
516 EnumVariant {
517 name: "HIGH",
518 description: Some(
519 "Input is logic high",
520 ),
521 value: 1,
522 },
523 ],
524 },
525 Enum {
526 name: "Moder",
527 description: None,
528 bit_size: 2,
529 variants: &[
530 EnumVariant {
531 name: "INPUT",
532 description: Some(
533 "Input mode (reset state)",
534 ),
535 value: 0,
536 },
537 EnumVariant {
538 name: "OUTPUT",
539 description: Some(
540 "General purpose output mode",
541 ),
542 value: 1,
543 },
544 EnumVariant {
545 name: "ALTERNATE",
546 description: Some(
547 "Alternate function mode",
548 ),
549 value: 2,
550 },
551 EnumVariant {
552 name: "ANALOG",
553 description: Some(
554 "Analog mode",
555 ),
556 value: 3,
557 },
558 ],
559 },
560 Enum {
561 name: "Odr",
562 description: None,
563 bit_size: 1,
564 variants: &[
565 EnumVariant {
566 name: "LOW",
567 description: Some(
568 "Set output to logic low",
569 ),
570 value: 0,
571 },
572 EnumVariant {
573 name: "HIGH",
574 description: Some(
575 "Set output to logic high",
576 ),
577 value: 1,
578 },
579 ],
580 },
581 Enum {
582 name: "Ospeedr",
583 description: None,
584 bit_size: 2,
585 variants: &[
586 EnumVariant {
587 name: "LOW_SPEED",
588 description: Some(
589 "Low speed",
590 ),
591 value: 0,
592 },
593 EnumVariant {
594 name: "MEDIUM_SPEED",
595 description: Some(
596 "Medium speed",
597 ),
598 value: 1,
599 },
600 EnumVariant {
601 name: "HIGH_SPEED",
602 description: Some(
603 "High speed",
604 ),
605 value: 2,
606 },
607 EnumVariant {
608 name: "VERY_HIGH_SPEED",
609 description: Some(
610 "Very high speed",
611 ),
612 value: 3,
613 },
614 ],
615 },
616 Enum {
617 name: "Ot",
618 description: None,
619 bit_size: 1,
620 variants: &[
621 EnumVariant {
622 name: "PUSH_PULL",
623 description: Some(
624 "Output push-pull (reset state)",
625 ),
626 value: 0,
627 },
628 EnumVariant {
629 name: "OPEN_DRAIN",
630 description: Some(
631 "Output open-drain",
632 ),
633 value: 1,
634 },
635 ],
636 },
637 Enum {
638 name: "Pupdr",
639 description: None,
640 bit_size: 2,
641 variants: &[
642 EnumVariant {
643 name: "FLOATING",
644 description: Some(
645 "No pull-up, pull-down",
646 ),
647 value: 0,
648 },
649 EnumVariant {
650 name: "PULL_UP",
651 description: Some(
652 "Pull-up",
653 ),
654 value: 1,
655 },
656 EnumVariant {
657 name: "PULL_DOWN",
658 description: Some(
659 "Pull-down",
660 ),
661 value: 2,
662 },
663 ],
664 },
665 ],
666};
667