1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[Block {
5 name: "Hash",
6 extends: None,
7 description: Some("Hash processor."),
8 items: &[
9 BlockItem {
10 name: "cr",
11 description: Some("control register."),
12 array: None,
13 byte_offset: 0x0,
14 inner: BlockItemInner::Register(Register {
15 access: Access::ReadWrite,
16 bit_size: 32,
17 fieldset: Some("Cr"),
18 }),
19 },
20 BlockItem {
21 name: "din",
22 description: Some("data input register."),
23 array: None,
24 byte_offset: 0x4,
25 inner: BlockItemInner::Register(Register {
26 access: Access::Write,
27 bit_size: 32,
28 fieldset: None,
29 }),
30 },
31 BlockItem {
32 name: "str",
33 description: Some("start register."),
34 array: None,
35 byte_offset: 0x8,
36 inner: BlockItemInner::Register(Register {
37 access: Access::ReadWrite,
38 bit_size: 32,
39 fieldset: Some("Str"),
40 }),
41 },
42 BlockItem {
43 name: "hra",
44 description: Some("digest registers."),
45 array: Some(Array::Regular(RegularArray { len: 5, stride: 4 })),
46 byte_offset: 0xc,
47 inner: BlockItemInner::Register(Register {
48 access: Access::ReadWrite,
49 bit_size: 32,
50 fieldset: None,
51 }),
52 },
53 BlockItem {
54 name: "imr",
55 description: Some("interrupt enable register."),
56 array: None,
57 byte_offset: 0x20,
58 inner: BlockItemInner::Register(Register {
59 access: Access::ReadWrite,
60 bit_size: 32,
61 fieldset: Some("Imr"),
62 }),
63 },
64 BlockItem {
65 name: "sr",
66 description: Some("status register."),
67 array: None,
68 byte_offset: 0x24,
69 inner: BlockItemInner::Register(Register {
70 access: Access::ReadWrite,
71 bit_size: 32,
72 fieldset: Some("Sr"),
73 }),
74 },
75 BlockItem {
76 name: "csr",
77 description: Some("context swap registers."),
78 array: Some(Array::Regular(RegularArray { len: 54, stride: 4 })),
79 byte_offset: 0xf8,
80 inner: BlockItemInner::Register(Register {
81 access: Access::ReadWrite,
82 bit_size: 32,
83 fieldset: None,
84 }),
85 },
86 BlockItem {
87 name: "hr",
88 description: Some("HASH digest register."),
89 array: Some(Array::Regular(RegularArray { len: 8, stride: 4 })),
90 byte_offset: 0x310,
91 inner: BlockItemInner::Register(Register {
92 access: Access::Read,
93 bit_size: 32,
94 fieldset: None,
95 }),
96 },
97 ],
98 }],
99 fieldsets: &[
100 FieldSet {
101 name: "Cr",
102 extends: None,
103 description: Some("control register."),
104 bit_size: 32,
105 fields: &[
106 Field {
107 name: "init",
108 description: Some("Initialize message digest calculation."),
109 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
110 bit_size: 1,
111 array: None,
112 enumm: None,
113 },
114 Field {
115 name: "dmae",
116 description: Some("DMA enable."),
117 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
118 bit_size: 1,
119 array: None,
120 enumm: None,
121 },
122 Field {
123 name: "datatype",
124 description: Some("Data type selection."),
125 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
126 bit_size: 2,
127 array: None,
128 enumm: None,
129 },
130 Field {
131 name: "mode",
132 description: Some("Mode selection."),
133 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 6 }),
134 bit_size: 1,
135 array: None,
136 enumm: None,
137 },
138 Field {
139 name: "nbw",
140 description: Some("Number of words already pushed."),
141 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
142 bit_size: 4,
143 array: None,
144 enumm: None,
145 },
146 Field {
147 name: "dinne",
148 description: Some("DIN not empty."),
149 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
150 bit_size: 1,
151 array: None,
152 enumm: None,
153 },
154 Field {
155 name: "mdmat",
156 description: Some("Multiple DMA Transfers."),
157 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 13 }),
158 bit_size: 1,
159 array: None,
160 enumm: None,
161 },
162 Field {
163 name: "lkey",
164 description: Some("Long key selection."),
165 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
166 bit_size: 1,
167 array: None,
168 enumm: None,
169 },
170 Field {
171 name: "algo",
172 description: Some("Algorithm selection."),
173 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 17 }),
174 bit_size: 2,
175 array: None,
176 enumm: None,
177 },
178 ],
179 },
180 FieldSet {
181 name: "Imr",
182 extends: None,
183 description: Some("interrupt enable register."),
184 bit_size: 32,
185 fields: &[
186 Field {
187 name: "dinie",
188 description: Some("Data input interrupt enable."),
189 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
190 bit_size: 1,
191 array: None,
192 enumm: None,
193 },
194 Field {
195 name: "dcie",
196 description: Some("Digest calculation completion interrupt enable."),
197 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
198 bit_size: 1,
199 array: None,
200 enumm: None,
201 },
202 ],
203 },
204 FieldSet {
205 name: "Sr",
206 extends: None,
207 description: Some("status register."),
208 bit_size: 32,
209 fields: &[
210 Field {
211 name: "dinis",
212 description: Some("Data input interrupt status."),
213 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
214 bit_size: 1,
215 array: None,
216 enumm: None,
217 },
218 Field {
219 name: "dcis",
220 description: Some("Digest calculation completion interrupt status."),
221 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
222 bit_size: 1,
223 array: None,
224 enumm: None,
225 },
226 Field {
227 name: "dmas",
228 description: Some("DMA Status."),
229 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
230 bit_size: 1,
231 array: None,
232 enumm: None,
233 },
234 Field {
235 name: "busy",
236 description: Some("Busy bit."),
237 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
238 bit_size: 1,
239 array: None,
240 enumm: None,
241 },
242 Field {
243 name: "nbwp",
244 description: Some("Number of words already pushed."),
245 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
246 bit_size: 5,
247 array: None,
248 enumm: None,
249 },
250 Field {
251 name: "dinne",
252 description: Some("DIN not empty."),
253 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 15 }),
254 bit_size: 1,
255 array: None,
256 enumm: None,
257 },
258 Field {
259 name: "nbwe",
260 description: Some("Number of words expected."),
261 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
262 bit_size: 5,
263 array: None,
264 enumm: None,
265 },
266 ],
267 },
268 FieldSet {
269 name: "Str",
270 extends: None,
271 description: Some("start register."),
272 bit_size: 32,
273 fields: &[
274 Field {
275 name: "nblw",
276 description: Some("Number of valid bits in the last word of the message."),
277 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
278 bit_size: 5,
279 array: None,
280 enumm: None,
281 },
282 Field {
283 name: "dcal",
284 description: Some("Digest calculation."),
285 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
286 bit_size: 1,
287 array: None,
288 enumm: None,
289 },
290 ],
291 },
292 ],
293 enums: &[],
294};
295