1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Hspi",
7 extends: None,
8 description: Some(
9 "HSPI.",
10 ),
11 items: &[
12 BlockItem {
13 name: "cr",
14 description: Some(
15 "HSPI control register.",
16 ),
17 array: None,
18 byte_offset: 0x0,
19 inner: BlockItemInner::Register(
20 Register {
21 access: Access::ReadWrite,
22 bit_size: 32,
23 fieldset: Some(
24 "Cr",
25 ),
26 },
27 ),
28 },
29 BlockItem {
30 name: "dcr1",
31 description: Some(
32 "HSPI device configuration register 1.",
33 ),
34 array: None,
35 byte_offset: 0x8,
36 inner: BlockItemInner::Register(
37 Register {
38 access: Access::ReadWrite,
39 bit_size: 32,
40 fieldset: Some(
41 "Dcr1",
42 ),
43 },
44 ),
45 },
46 BlockItem {
47 name: "dcr2",
48 description: Some(
49 "HSPI device configuration register 2.",
50 ),
51 array: None,
52 byte_offset: 0xc,
53 inner: BlockItemInner::Register(
54 Register {
55 access: Access::ReadWrite,
56 bit_size: 32,
57 fieldset: Some(
58 "Dcr2",
59 ),
60 },
61 ),
62 },
63 BlockItem {
64 name: "dcr3",
65 description: Some(
66 "HSPI device configuration register 3.",
67 ),
68 array: None,
69 byte_offset: 0x10,
70 inner: BlockItemInner::Register(
71 Register {
72 access: Access::ReadWrite,
73 bit_size: 32,
74 fieldset: Some(
75 "Dcr3",
76 ),
77 },
78 ),
79 },
80 BlockItem {
81 name: "dcr4",
82 description: Some(
83 "HSPI device configuration register 4.",
84 ),
85 array: None,
86 byte_offset: 0x14,
87 inner: BlockItemInner::Register(
88 Register {
89 access: Access::ReadWrite,
90 bit_size: 32,
91 fieldset: Some(
92 "Dcr4",
93 ),
94 },
95 ),
96 },
97 BlockItem {
98 name: "sr",
99 description: None,
100 array: None,
101 byte_offset: 0x20,
102 inner: BlockItemInner::Register(
103 Register {
104 access: Access::ReadWrite,
105 bit_size: 32,
106 fieldset: Some(
107 "Sr",
108 ),
109 },
110 ),
111 },
112 BlockItem {
113 name: "fcr",
114 description: None,
115 array: None,
116 byte_offset: 0x24,
117 inner: BlockItemInner::Register(
118 Register {
119 access: Access::ReadWrite,
120 bit_size: 32,
121 fieldset: Some(
122 "Fcr",
123 ),
124 },
125 ),
126 },
127 BlockItem {
128 name: "dlr",
129 description: Some(
130 "HSPI data length register.",
131 ),
132 array: None,
133 byte_offset: 0x40,
134 inner: BlockItemInner::Register(
135 Register {
136 access: Access::ReadWrite,
137 bit_size: 32,
138 fieldset: Some(
139 "Dlr",
140 ),
141 },
142 ),
143 },
144 BlockItem {
145 name: "ar",
146 description: None,
147 array: None,
148 byte_offset: 0x48,
149 inner: BlockItemInner::Register(
150 Register {
151 access: Access::ReadWrite,
152 bit_size: 32,
153 fieldset: Some(
154 "Ar",
155 ),
156 },
157 ),
158 },
159 BlockItem {
160 name: "dr",
161 description: None,
162 array: None,
163 byte_offset: 0x50,
164 inner: BlockItemInner::Register(
165 Register {
166 access: Access::ReadWrite,
167 bit_size: 32,
168 fieldset: Some(
169 "Dr",
170 ),
171 },
172 ),
173 },
174 BlockItem {
175 name: "psmkr",
176 description: Some(
177 "HSPI polling status mask register.",
178 ),
179 array: None,
180 byte_offset: 0x80,
181 inner: BlockItemInner::Register(
182 Register {
183 access: Access::ReadWrite,
184 bit_size: 32,
185 fieldset: Some(
186 "Psmkr",
187 ),
188 },
189 ),
190 },
191 BlockItem {
192 name: "psmar",
193 description: Some(
194 "HSPI polling status match register.",
195 ),
196 array: None,
197 byte_offset: 0x88,
198 inner: BlockItemInner::Register(
199 Register {
200 access: Access::ReadWrite,
201 bit_size: 32,
202 fieldset: Some(
203 "Psmar",
204 ),
205 },
206 ),
207 },
208 BlockItem {
209 name: "pir",
210 description: Some(
211 "HSPI polling interval register.",
212 ),
213 array: None,
214 byte_offset: 0x90,
215 inner: BlockItemInner::Register(
216 Register {
217 access: Access::ReadWrite,
218 bit_size: 32,
219 fieldset: Some(
220 "Pir",
221 ),
222 },
223 ),
224 },
225 BlockItem {
226 name: "ccr",
227 description: Some(
228 "HSPI communication configuration register.",
229 ),
230 array: None,
231 byte_offset: 0x100,
232 inner: BlockItemInner::Register(
233 Register {
234 access: Access::ReadWrite,
235 bit_size: 32,
236 fieldset: Some(
237 "Ccr",
238 ),
239 },
240 ),
241 },
242 BlockItem {
243 name: "tcr",
244 description: Some(
245 "HSPI timing configuration register.",
246 ),
247 array: None,
248 byte_offset: 0x108,
249 inner: BlockItemInner::Register(
250 Register {
251 access: Access::ReadWrite,
252 bit_size: 32,
253 fieldset: Some(
254 "Tcr",
255 ),
256 },
257 ),
258 },
259 BlockItem {
260 name: "ir",
261 description: Some(
262 "HSPI instruction register.",
263 ),
264 array: None,
265 byte_offset: 0x110,
266 inner: BlockItemInner::Register(
267 Register {
268 access: Access::ReadWrite,
269 bit_size: 32,
270 fieldset: Some(
271 "Ir",
272 ),
273 },
274 ),
275 },
276 BlockItem {
277 name: "abr",
278 description: Some(
279 "HSPI alternate bytes register.",
280 ),
281 array: None,
282 byte_offset: 0x120,
283 inner: BlockItemInner::Register(
284 Register {
285 access: Access::ReadWrite,
286 bit_size: 32,
287 fieldset: Some(
288 "Abr",
289 ),
290 },
291 ),
292 },
293 BlockItem {
294 name: "lptr",
295 description: Some(
296 "HSPI low-power timeout register.",
297 ),
298 array: None,
299 byte_offset: 0x130,
300 inner: BlockItemInner::Register(
301 Register {
302 access: Access::ReadWrite,
303 bit_size: 32,
304 fieldset: Some(
305 "Lptr",
306 ),
307 },
308 ),
309 },
310 BlockItem {
311 name: "wpccr",
312 description: Some(
313 "HSPI wrap communication configuration register.",
314 ),
315 array: None,
316 byte_offset: 0x140,
317 inner: BlockItemInner::Register(
318 Register {
319 access: Access::ReadWrite,
320 bit_size: 32,
321 fieldset: Some(
322 "Wpccr",
323 ),
324 },
325 ),
326 },
327 BlockItem {
328 name: "wptcr",
329 description: Some(
330 "HSPI wrap timing configuration register.",
331 ),
332 array: None,
333 byte_offset: 0x148,
334 inner: BlockItemInner::Register(
335 Register {
336 access: Access::ReadWrite,
337 bit_size: 32,
338 fieldset: Some(
339 "Wptcr",
340 ),
341 },
342 ),
343 },
344 BlockItem {
345 name: "wpir",
346 description: Some(
347 "HSPI wrap instruction register.",
348 ),
349 array: None,
350 byte_offset: 0x150,
351 inner: BlockItemInner::Register(
352 Register {
353 access: Access::ReadWrite,
354 bit_size: 32,
355 fieldset: Some(
356 "Wpir",
357 ),
358 },
359 ),
360 },
361 BlockItem {
362 name: "wpabr",
363 description: Some(
364 "HSPI wrap alternate bytes register.",
365 ),
366 array: None,
367 byte_offset: 0x160,
368 inner: BlockItemInner::Register(
369 Register {
370 access: Access::ReadWrite,
371 bit_size: 32,
372 fieldset: Some(
373 "Wpabr",
374 ),
375 },
376 ),
377 },
378 BlockItem {
379 name: "wccr",
380 description: Some(
381 "HSPI write communication configuration register.",
382 ),
383 array: None,
384 byte_offset: 0x180,
385 inner: BlockItemInner::Register(
386 Register {
387 access: Access::ReadWrite,
388 bit_size: 32,
389 fieldset: Some(
390 "Wccr",
391 ),
392 },
393 ),
394 },
395 BlockItem {
396 name: "wtcr",
397 description: Some(
398 "HSPI write timing configuration register.",
399 ),
400 array: None,
401 byte_offset: 0x188,
402 inner: BlockItemInner::Register(
403 Register {
404 access: Access::ReadWrite,
405 bit_size: 32,
406 fieldset: Some(
407 "Wtcr",
408 ),
409 },
410 ),
411 },
412 BlockItem {
413 name: "wir",
414 description: Some(
415 "HSPI write instruction register.",
416 ),
417 array: None,
418 byte_offset: 0x190,
419 inner: BlockItemInner::Register(
420 Register {
421 access: Access::ReadWrite,
422 bit_size: 32,
423 fieldset: Some(
424 "Wir",
425 ),
426 },
427 ),
428 },
429 BlockItem {
430 name: "wabr",
431 description: Some(
432 "HSPI write alternate bytes register.",
433 ),
434 array: None,
435 byte_offset: 0x1a0,
436 inner: BlockItemInner::Register(
437 Register {
438 access: Access::ReadWrite,
439 bit_size: 32,
440 fieldset: Some(
441 "Wabr",
442 ),
443 },
444 ),
445 },
446 BlockItem {
447 name: "hlcr",
448 description: Some(
449 "HSPI HyperBus latency configuration register.",
450 ),
451 array: None,
452 byte_offset: 0x200,
453 inner: BlockItemInner::Register(
454 Register {
455 access: Access::ReadWrite,
456 bit_size: 32,
457 fieldset: Some(
458 "Hlcr",
459 ),
460 },
461 ),
462 },
463 BlockItem {
464 name: "calfcr",
465 description: Some(
466 "HSPI full-cycle calibration configuration.",
467 ),
468 array: None,
469 byte_offset: 0x210,
470 inner: BlockItemInner::Register(
471 Register {
472 access: Access::ReadWrite,
473 bit_size: 32,
474 fieldset: Some(
475 "Calfcr",
476 ),
477 },
478 ),
479 },
480 BlockItem {
481 name: "calmr",
482 description: Some(
483 "HSPI DLL master calibration configuration.",
484 ),
485 array: None,
486 byte_offset: 0x218,
487 inner: BlockItemInner::Register(
488 Register {
489 access: Access::ReadWrite,
490 bit_size: 32,
491 fieldset: Some(
492 "Calmr",
493 ),
494 },
495 ),
496 },
497 BlockItem {
498 name: "calsor",
499 description: Some(
500 "HSPI DLL slave output calibration configuration.",
501 ),
502 array: None,
503 byte_offset: 0x220,
504 inner: BlockItemInner::Register(
505 Register {
506 access: Access::ReadWrite,
507 bit_size: 32,
508 fieldset: Some(
509 "Calsor",
510 ),
511 },
512 ),
513 },
514 BlockItem {
515 name: "calsir",
516 description: Some(
517 "HSPI DLL slave input calibration configuration.",
518 ),
519 array: None,
520 byte_offset: 0x228,
521 inner: BlockItemInner::Register(
522 Register {
523 access: Access::ReadWrite,
524 bit_size: 32,
525 fieldset: Some(
526 "Calsir",
527 ),
528 },
529 ),
530 },
531 ],
532 },
533 ],
534 fieldsets: &[
535 FieldSet {
536 name: "Abr",
537 extends: None,
538 description: Some(
539 "HSPI alternate bytes register.",
540 ),
541 bit_size: 32,
542 fields: &[
543 Field {
544 name: "alternate",
545 description: Some(
546 "[31: 0]: Alternate bytes Optional data to be send to the external SPI device right after the address.",
547 ),
548 bit_offset: BitOffset::Regular(
549 RegularBitOffset {
550 offset: 0,
551 },
552 ),
553 bit_size: 32,
554 array: None,
555 enumm: None,
556 },
557 ],
558 },
559 FieldSet {
560 name: "Ar",
561 extends: None,
562 description: None,
563 bit_size: 32,
564 fields: &[
565 Field {
566 name: "address",
567 description: Some(
568 "Address Address to be sent to the external device. In HyperBus mode, this field must be even as this protocol is 16-bit word oriented. In dual-memory mode, AR[0] is forced to 1. Writes to this field are ignored when BUSY = 1 or when FMODE = 11 (Memory-mapped mode).",
569 ),
570 bit_offset: BitOffset::Regular(
571 RegularBitOffset {
572 offset: 0,
573 },
574 ),
575 bit_size: 32,
576 array: None,
577 enumm: None,
578 },
579 ],
580 },
581 FieldSet {
582 name: "Calfcr",
583 extends: None,
584 description: Some(
585 "HSPI full-cycle calibration configuration.",
586 ),
587 bit_size: 32,
588 fields: &[
589 Field {
590 name: "fine",
591 description: Some(
592 "[6: 0]: Fine calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet).",
593 ),
594 bit_offset: BitOffset::Regular(
595 RegularBitOffset {
596 offset: 0,
597 },
598 ),
599 bit_size: 7,
600 array: None,
601 enumm: None,
602 },
603 Field {
604 name: "coarse",
605 description: Some(
606 "[4: 0]: Coarse calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet).",
607 ),
608 bit_offset: BitOffset::Regular(
609 RegularBitOffset {
610 offset: 16,
611 },
612 ),
613 bit_size: 5,
614 array: None,
615 enumm: None,
616 },
617 Field {
618 name: "calmax",
619 description: Some(
620 "Max value This bit gets set when the memory-clock period is outside the range of DLLM, in which case CALFCR and CALSR are updated with the values for the maximum delay.",
621 ),
622 bit_offset: BitOffset::Regular(
623 RegularBitOffset {
624 offset: 31,
625 },
626 ),
627 bit_size: 1,
628 array: None,
629 enumm: None,
630 },
631 ],
632 },
633 FieldSet {
634 name: "Calmr",
635 extends: None,
636 description: Some(
637 "HSPI DLL master calibration configuration.",
638 ),
639 bit_size: 32,
640 fields: &[
641 Field {
642 name: "fine",
643 description: Some(
644 "[6: 0]: Fine calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet).",
645 ),
646 bit_offset: BitOffset::Regular(
647 RegularBitOffset {
648 offset: 0,
649 },
650 ),
651 bit_size: 7,
652 array: None,
653 enumm: None,
654 },
655 Field {
656 name: "coarse",
657 description: Some(
658 "[4: 0]: Coarse calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet).",
659 ),
660 bit_offset: BitOffset::Regular(
661 RegularBitOffset {
662 offset: 16,
663 },
664 ),
665 bit_size: 5,
666 array: None,
667 enumm: None,
668 },
669 ],
670 },
671 FieldSet {
672 name: "Calsir",
673 extends: None,
674 description: Some(
675 "HSPI DLL slave input calibration configuration.",
676 ),
677 bit_size: 32,
678 fields: &[
679 Field {
680 name: "fine",
681 description: Some(
682 "[6: 0]: Fine calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet).",
683 ),
684 bit_offset: BitOffset::Regular(
685 RegularBitOffset {
686 offset: 0,
687 },
688 ),
689 bit_size: 7,
690 array: None,
691 enumm: None,
692 },
693 Field {
694 name: "coarse",
695 description: Some(
696 "[4: 0]: Coarse calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet).",
697 ),
698 bit_offset: BitOffset::Regular(
699 RegularBitOffset {
700 offset: 16,
701 },
702 ),
703 bit_size: 5,
704 array: None,
705 enumm: None,
706 },
707 ],
708 },
709 FieldSet {
710 name: "Calsor",
711 extends: None,
712 description: Some(
713 "HSPI DLL slave output calibration configuration.",
714 ),
715 bit_size: 32,
716 fields: &[
717 Field {
718 name: "fine",
719 description: Some(
720 "[6: 0]: Fine calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet).",
721 ),
722 bit_offset: BitOffset::Regular(
723 RegularBitOffset {
724 offset: 0,
725 },
726 ),
727 bit_size: 7,
728 array: None,
729 enumm: None,
730 },
731 Field {
732 name: "coarse",
733 description: Some(
734 "[4: 0]: Coarse calibration The unitary value of delay for this field depends on product technology (refer to the product datasheet).",
735 ),
736 bit_offset: BitOffset::Regular(
737 RegularBitOffset {
738 offset: 16,
739 },
740 ),
741 bit_size: 5,
742 array: None,
743 enumm: None,
744 },
745 ],
746 },
747 FieldSet {
748 name: "Ccr",
749 extends: None,
750 description: Some(
751 "HSPI communication configuration register.",
752 ),
753 bit_size: 32,
754 fields: &[
755 Field {
756 name: "imode",
757 description: Some(
758 "Instruction mode This field defines the instruction phase mode of operation. 101-111: Reserved.",
759 ),
760 bit_offset: BitOffset::Regular(
761 RegularBitOffset {
762 offset: 0,
763 },
764 ),
765 bit_size: 3,
766 array: None,
767 enumm: None,
768 },
769 Field {
770 name: "idtr",
771 description: Some(
772 "Instruction double transfer rate This bit sets the DTR mode for the instruction phase.",
773 ),
774 bit_offset: BitOffset::Regular(
775 RegularBitOffset {
776 offset: 3,
777 },
778 ),
779 bit_size: 1,
780 array: None,
781 enumm: None,
782 },
783 Field {
784 name: "isize",
785 description: Some(
786 "Instruction size This bit defines instruction size.",
787 ),
788 bit_offset: BitOffset::Regular(
789 RegularBitOffset {
790 offset: 4,
791 },
792 ),
793 bit_size: 2,
794 array: None,
795 enumm: None,
796 },
797 Field {
798 name: "admode",
799 description: Some(
800 "Address mode This field defines the address phase mode of operation. 101-111: Reserved.",
801 ),
802 bit_offset: BitOffset::Regular(
803 RegularBitOffset {
804 offset: 8,
805 },
806 ),
807 bit_size: 3,
808 array: None,
809 enumm: None,
810 },
811 Field {
812 name: "addtr",
813 description: Some(
814 "Address double transfer rate This bit sets the DTR mode for the address phase.",
815 ),
816 bit_offset: BitOffset::Regular(
817 RegularBitOffset {
818 offset: 11,
819 },
820 ),
821 bit_size: 1,
822 array: None,
823 enumm: None,
824 },
825 Field {
826 name: "adsize",
827 description: Some(
828 "Address size This field defines address size.",
829 ),
830 bit_offset: BitOffset::Regular(
831 RegularBitOffset {
832 offset: 12,
833 },
834 ),
835 bit_size: 2,
836 array: None,
837 enumm: None,
838 },
839 Field {
840 name: "abmode",
841 description: Some(
842 "Alternate-byte mode This field defines the alternate byte phase mode of operation. 100-111: Reserved.",
843 ),
844 bit_offset: BitOffset::Regular(
845 RegularBitOffset {
846 offset: 16,
847 },
848 ),
849 bit_size: 3,
850 array: None,
851 enumm: None,
852 },
853 Field {
854 name: "abdtr",
855 description: Some(
856 "Alternate bytes double transfer rate This bit sets the DTR mode for the alternate bytes phase. This field can be written only when BUSY = 0.",
857 ),
858 bit_offset: BitOffset::Regular(
859 RegularBitOffset {
860 offset: 19,
861 },
862 ),
863 bit_size: 1,
864 array: None,
865 enumm: None,
866 },
867 Field {
868 name: "absize",
869 description: Some(
870 "Alternate bytes size This bit defines alternate bytes size.",
871 ),
872 bit_offset: BitOffset::Regular(
873 RegularBitOffset {
874 offset: 20,
875 },
876 ),
877 bit_size: 2,
878 array: None,
879 enumm: None,
880 },
881 Field {
882 name: "dmode",
883 description: Some(
884 "Data mode This field defines the data phase mode of operation. 110-111: Reserved.",
885 ),
886 bit_offset: BitOffset::Regular(
887 RegularBitOffset {
888 offset: 24,
889 },
890 ),
891 bit_size: 3,
892 array: None,
893 enumm: None,
894 },
895 Field {
896 name: "ddtr",
897 description: Some(
898 "Data double transfer rate This bit sets the DTR mode for the data phase.",
899 ),
900 bit_offset: BitOffset::Regular(
901 RegularBitOffset {
902 offset: 27,
903 },
904 ),
905 bit_size: 1,
906 array: None,
907 enumm: None,
908 },
909 Field {
910 name: "dqse",
911 description: Some(
912 "DQS enable This bit enables the data strobe management.",
913 ),
914 bit_offset: BitOffset::Regular(
915 RegularBitOffset {
916 offset: 29,
917 },
918 ),
919 bit_size: 1,
920 array: None,
921 enumm: None,
922 },
923 Field {
924 name: "sioo",
925 description: Some(
926 "Send instruction only once mode This bit has no effect when IMODE = 00 (see ).",
927 ),
928 bit_offset: BitOffset::Regular(
929 RegularBitOffset {
930 offset: 31,
931 },
932 ),
933 bit_size: 1,
934 array: None,
935 enumm: None,
936 },
937 ],
938 },
939 FieldSet {
940 name: "Cr",
941 extends: None,
942 description: Some(
943 "HSPI control register.",
944 ),
945 bit_size: 32,
946 fields: &[
947 Field {
948 name: "en",
949 description: Some(
950 "Enable This bit enables the HSPI. Note: The DMA request can be aborted without having received the ACK in case this EN bit is cleared during the operation. In case this bit is set to 0 during a DMA transfer, the REQ signal to DMA returns to inactive state without waiting for the ACK signal from DMA to be active.",
951 ),
952 bit_offset: BitOffset::Regular(
953 RegularBitOffset {
954 offset: 0,
955 },
956 ),
957 bit_size: 1,
958 array: None,
959 enumm: None,
960 },
961 Field {
962 name: "abort",
963 description: Some(
964 "Abort request This bit aborts the on-going command sequence. It is automatically reset once the abort is completed. This bit stops the current transfer. Note: This bit is always read as 0.",
965 ),
966 bit_offset: BitOffset::Regular(
967 RegularBitOffset {
968 offset: 1,
969 },
970 ),
971 bit_size: 1,
972 array: None,
973 enumm: None,
974 },
975 Field {
976 name: "dmaen",
977 description: Some(
978 "DMA enable In Indirect mode, the DMA can be used to input or output data via DR. DMA transfers are initiated when FTF is set. Note: Resetting the DMAEN bit while a DMA transfer is ongoing, breaks the handshake with the DMA. Do not write this bit during DMA operation.",
979 ),
980 bit_offset: BitOffset::Regular(
981 RegularBitOffset {
982 offset: 2,
983 },
984 ),
985 bit_size: 1,
986 array: None,
987 enumm: None,
988 },
989 Field {
990 name: "tcen",
991 description: Some(
992 "Timeout counter enable This bit is valid only when the Memory-mapped mode (FMODE[1:0] = 11) is selected. This bit enables the timeout counter.",
993 ),
994 bit_offset: BitOffset::Regular(
995 RegularBitOffset {
996 offset: 3,
997 },
998 ),
999 bit_size: 1,
1000 array: None,
1001 enumm: None,
1002 },
1003 Field {
1004 name: "dmm",
1005 description: Some(
1006 "Dual-memory mode This bit activates the Dual-memory mode, where two external devices are used simultaneously to double the throughput and the capacity.",
1007 ),
1008 bit_offset: BitOffset::Regular(
1009 RegularBitOffset {
1010 offset: 6,
1011 },
1012 ),
1013 bit_size: 1,
1014 array: None,
1015 enumm: None,
1016 },
1017 Field {
1018 name: "fsel",
1019 description: Some(
1020 "Memory select This bit is the mirror of bit 30. Refer to the description of MSEL[1:0] above. This bit is set when 1 is written in bit 30 or bit 7. When this bit is set, both b30 and b7 are read as 1. This bit is reset when bit 30 and bit7 are set to 0. When this bit is reset, both bit 30 and bit7 are read as 0.",
1021 ),
1022 bit_offset: BitOffset::Regular(
1023 RegularBitOffset {
1024 offset: 7,
1025 },
1026 ),
1027 bit_size: 1,
1028 array: None,
1029 enumm: None,
1030 },
1031 Field {
1032 name: "fthres",
1033 description: Some(
1034 "FIFO threshold level This field defines, in Indirect mode, the threshold number of bytes in the FIFO that causes the FIFO threshold flag FTF in SR, to be set. ... Note: If DMAEN = 1, the DMA controller for the corresponding channel must be disabled before changing the FTHRES[5:0] value.",
1035 ),
1036 bit_offset: BitOffset::Regular(
1037 RegularBitOffset {
1038 offset: 8,
1039 },
1040 ),
1041 bit_size: 6,
1042 array: None,
1043 enumm: None,
1044 },
1045 Field {
1046 name: "teie",
1047 description: Some(
1048 "Transfer error interrupt enable This bit enables the transfer error interrupt.",
1049 ),
1050 bit_offset: BitOffset::Regular(
1051 RegularBitOffset {
1052 offset: 16,
1053 },
1054 ),
1055 bit_size: 1,
1056 array: None,
1057 enumm: None,
1058 },
1059 Field {
1060 name: "tcie",
1061 description: Some(
1062 "Transfer complete interrupt enable This bit enables the transfer complete interrupt.",
1063 ),
1064 bit_offset: BitOffset::Regular(
1065 RegularBitOffset {
1066 offset: 17,
1067 },
1068 ),
1069 bit_size: 1,
1070 array: None,
1071 enumm: None,
1072 },
1073 Field {
1074 name: "ftie",
1075 description: Some(
1076 "FIFO threshold interrupt enable This bit enables the FIFO threshold interrupt.",
1077 ),
1078 bit_offset: BitOffset::Regular(
1079 RegularBitOffset {
1080 offset: 18,
1081 },
1082 ),
1083 bit_size: 1,
1084 array: None,
1085 enumm: None,
1086 },
1087 Field {
1088 name: "smie",
1089 description: Some(
1090 "Status match interrupt enable This bit enables the status match interrupt.",
1091 ),
1092 bit_offset: BitOffset::Regular(
1093 RegularBitOffset {
1094 offset: 19,
1095 },
1096 ),
1097 bit_size: 1,
1098 array: None,
1099 enumm: None,
1100 },
1101 Field {
1102 name: "toie",
1103 description: Some(
1104 "Timeout interrupt enable This bit enables the timeout interrupt.",
1105 ),
1106 bit_offset: BitOffset::Regular(
1107 RegularBitOffset {
1108 offset: 20,
1109 },
1110 ),
1111 bit_size: 1,
1112 array: None,
1113 enumm: None,
1114 },
1115 Field {
1116 name: "apms",
1117 description: Some(
1118 "Automatic-polling mode stop This bit determines if the automatic polling is stopped after a match.",
1119 ),
1120 bit_offset: BitOffset::Regular(
1121 RegularBitOffset {
1122 offset: 22,
1123 },
1124 ),
1125 bit_size: 1,
1126 array: None,
1127 enumm: None,
1128 },
1129 Field {
1130 name: "pmm",
1131 description: Some(
1132 "Polling match mode This bit indicates which method must be used to determine a match during the Automatic-polling mode.",
1133 ),
1134 bit_offset: BitOffset::Regular(
1135 RegularBitOffset {
1136 offset: 23,
1137 },
1138 ),
1139 bit_size: 1,
1140 array: None,
1141 enumm: None,
1142 },
1143 Field {
1144 name: "fmode",
1145 description: Some(
1146 "Functional mode This field defines the HSPI functional mode of operation. If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE[1:0] value. If FMODE[1:0] and FTHRES[4:0] are wrongly updated while DMAEN = 1, the DMA request signal automatically goes to inactive state.",
1147 ),
1148 bit_offset: BitOffset::Regular(
1149 RegularBitOffset {
1150 offset: 28,
1151 },
1152 ),
1153 bit_size: 2,
1154 array: None,
1155 enumm: None,
1156 },
1157 Field {
1158 name: "msel",
1159 description: Some(
1160 "Flash select These bits select the memory to be addressed in Single, Dual, Quad or Octal mode in singleâ\u{80}\u{91}memory configuration (when DMM = 0). - when in Quad mode: - when in Octal mode or Dual-quad mode: 0x: data exchanged over IO[7:0] 1x: data exchanged over IO[15:8] These bits are ignored when in dual-octal configuration (data on 8 bits and DMM = 1) or 16â\u{80}\u{91}bit configuration (data exchanged over IO[15:0]).",
1161 ),
1162 bit_offset: BitOffset::Regular(
1163 RegularBitOffset {
1164 offset: 30,
1165 },
1166 ),
1167 bit_size: 2,
1168 array: None,
1169 enumm: None,
1170 },
1171 ],
1172 },
1173 FieldSet {
1174 name: "Dcr1",
1175 extends: None,
1176 description: Some(
1177 "HSPI device configuration register 1.",
1178 ),
1179 bit_size: 32,
1180 fields: &[
1181 Field {
1182 name: "ckmode",
1183 description: Some(
1184 "Mode 0/Mode 3 This bit indicates the level taken by the CLK between commands (when nCS = 1).",
1185 ),
1186 bit_offset: BitOffset::Regular(
1187 RegularBitOffset {
1188 offset: 0,
1189 },
1190 ),
1191 bit_size: 1,
1192 array: None,
1193 enumm: None,
1194 },
1195 Field {
1196 name: "frck",
1197 description: Some(
1198 "Free running clock This bit configures the free running clock.",
1199 ),
1200 bit_offset: BitOffset::Regular(
1201 RegularBitOffset {
1202 offset: 1,
1203 },
1204 ),
1205 bit_size: 1,
1206 array: None,
1207 enumm: None,
1208 },
1209 Field {
1210 name: "dlybyp",
1211 description: Some(
1212 "Delay block bypass.",
1213 ),
1214 bit_offset: BitOffset::Regular(
1215 RegularBitOffset {
1216 offset: 3,
1217 },
1218 ),
1219 bit_size: 1,
1220 array: None,
1221 enumm: None,
1222 },
1223 Field {
1224 name: "csht",
1225 description: Some(
1226 "Chip-select high time CSHT + 1 defines the minimum number of CLK cycles where the chip-select (nCS) must remain high between commands issued to the external device. ... 63: nCS stays high for at least 64 cycles between external device commands. Note: When the extended CSHT timeout feature is not supported, CSHT[5:3] are reserved and the number of cycles is limited to eight (refer to implementation).",
1227 ),
1228 bit_offset: BitOffset::Regular(
1229 RegularBitOffset {
1230 offset: 8,
1231 },
1232 ),
1233 bit_size: 6,
1234 array: None,
1235 enumm: None,
1236 },
1237 Field {
1238 name: "devsize",
1239 description: Some(
1240 "Device size This field defines the size of the external device using the following formula: Number of bytes in device = 2[DEVSIZE+1]. DEVSIZE+1 is effectively the number of address bits required to address the external device. The device capacity can be up to 4 Gbytes (addressed using 32-bits) in Indirect mode, but the addressable space in Memory-mapped mode is limited to 256 Mbytes. In Regular-command mode, if DMM = 1, DEVSIZE[4:0] indicates the total capacity of the two devices together.",
1241 ),
1242 bit_offset: BitOffset::Regular(
1243 RegularBitOffset {
1244 offset: 16,
1245 },
1246 ),
1247 bit_size: 5,
1248 array: None,
1249 enumm: None,
1250 },
1251 Field {
1252 name: "mtyp",
1253 description: Some(
1254 "Memory type This bit indicates the type of memory to be supported. Note: In this mode, DQS signal polarity is inverted with respect to the memory clock signal. This is the default value and care must be taken to change MTYP[2:0] for memories different from Micron. Others: Reserved.",
1255 ),
1256 bit_offset: BitOffset::Regular(
1257 RegularBitOffset {
1258 offset: 24,
1259 },
1260 ),
1261 bit_size: 3,
1262 array: None,
1263 enumm: None,
1264 },
1265 ],
1266 },
1267 FieldSet {
1268 name: "Dcr2",
1269 extends: None,
1270 description: Some(
1271 "HSPI device configuration register 2.",
1272 ),
1273 bit_size: 32,
1274 fields: &[
1275 Field {
1276 name: "prescaler",
1277 description: Some(
1278 "Clock prescaler This field defines the scaler factor for generating the CLK based on the kernel clock (value + 1). 2: FCLK = FKERNEL/3 ... 255: FCLK = FKERNEL/256 For odd clock division factors, the CLK duty cycle is not 50 %. The clock signal remains low one cycle longer than it stays high. Writing this field automatically starts a new calibration of high-speed interface DLL at the start of next transfer, except in case CALOSR or CALISR have been written in the meantime. BUSY stays high during the whole calibration execution.",
1279 ),
1280 bit_offset: BitOffset::Regular(
1281 RegularBitOffset {
1282 offset: 0,
1283 },
1284 ),
1285 bit_size: 8,
1286 array: None,
1287 enumm: None,
1288 },
1289 Field {
1290 name: "wrapsize",
1291 description: Some(
1292 "Wrap size This field indicates the wrap size to which the memory is configured. For memories which have a separate command for wrapped instructions, this field indicates the wrap-size associated with the command held in the WPIR register. 110-111: Reserved.",
1293 ),
1294 bit_offset: BitOffset::Regular(
1295 RegularBitOffset {
1296 offset: 16,
1297 },
1298 ),
1299 bit_size: 3,
1300 array: None,
1301 enumm: None,
1302 },
1303 ],
1304 },
1305 FieldSet {
1306 name: "Dcr3",
1307 extends: None,
1308 description: Some(
1309 "HSPI device configuration register 3.",
1310 ),
1311 bit_size: 32,
1312 fields: &[
1313 Field {
1314 name: "maxtran",
1315 description: Some(
1316 "Maximum transfer This field enables the communication regulation feature. The nCS is released every MAXTRAN+1 clock cycles when the other HSPI request the access to the bus. others: Maximum communication is set to MAXTRAN+1 bytes.",
1317 ),
1318 bit_offset: BitOffset::Regular(
1319 RegularBitOffset {
1320 offset: 0,
1321 },
1322 ),
1323 bit_size: 8,
1324 array: None,
1325 enumm: None,
1326 },
1327 Field {
1328 name: "csbound",
1329 description: Some(
1330 "CS boundary This field enables the transaction boundary feature. When active, a minimum value of 3 is recommended. The nCS is released on each boundary of 2CSBOUND bytes. others: CS boundary set to 2CSBOUND bytes.",
1331 ),
1332 bit_offset: BitOffset::Regular(
1333 RegularBitOffset {
1334 offset: 16,
1335 },
1336 ),
1337 bit_size: 5,
1338 array: None,
1339 enumm: None,
1340 },
1341 ],
1342 },
1343 FieldSet {
1344 name: "Dcr4",
1345 extends: None,
1346 description: Some(
1347 "HSPI device configuration register 4.",
1348 ),
1349 bit_size: 32,
1350 fields: &[
1351 Field {
1352 name: "refresh",
1353 description: Some(
1354 "Refresh rate This field enables the refresh rate feature. The nCS is released every REFRESH+1 clock cycles for writes, and REFRESH+4 clock cycles for reads. Note: These two values can be extended with few clock cycles when refresh occurs during a byte transmission in single, dual or quad mode, because the byte transmission must be completed. others: Maximum communication length is set to REFRESH+1 clock cycles.",
1355 ),
1356 bit_offset: BitOffset::Regular(
1357 RegularBitOffset {
1358 offset: 0,
1359 },
1360 ),
1361 bit_size: 32,
1362 array: None,
1363 enumm: None,
1364 },
1365 ],
1366 },
1367 FieldSet {
1368 name: "Dlr",
1369 extends: None,
1370 description: Some(
1371 "HSPI data length register.",
1372 ),
1373 bit_size: 32,
1374 fields: &[
1375 Field {
1376 name: "dl",
1377 description: Some(
1378 "[31: 0]: Data length Number of data to be retrieved (value+1) in Indirect and Status-polling modes. A value not greater than three (indicating 4 bytes) must be used for status polling-mode. All 1's in Indirect mode means undefined length, where HSPI continues until the end of the memory, as defined by DEVSIZE. 0x0000_0000: 1 byte is to be transferred. 0x0000_0001: 2 bytes are to be transferred. 0x0000_0002: 3 bytes are to be transferred. 0x0000_0003: 4 bytes are to be transferred. ... 0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred. 0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred. 0xFFFF_FFFF: undefined length; all bytes, until the end of the external device, (as defined by DEVSIZE) are to be transferred. Continue reading indefinitely if DEVSIZE = 0x1F. DL[0] is stuck at 1 in Dual-memory mode (DMM = 1) even when 0 is written to this bit, thus assuring that each access transfers an even number of bytes. This field has no effect when in Memory-mapped mode.",
1379 ),
1380 bit_offset: BitOffset::Regular(
1381 RegularBitOffset {
1382 offset: 0,
1383 },
1384 ),
1385 bit_size: 32,
1386 array: None,
1387 enumm: None,
1388 },
1389 ],
1390 },
1391 FieldSet {
1392 name: "Dr",
1393 extends: None,
1394 description: None,
1395 bit_size: 32,
1396 fields: &[
1397 Field {
1398 name: "data",
1399 description: Some(
1400 "[31: 0]: Data Data to be sent/received to/from the external SPI device In Indirect-write mode, data written to this register is stored on the FIFO before it is sent to the external device during the data phase. If the FIFO is too full, a write operation is stalled until the FIFO has enough space to accept the amount of data being written. In Indirect-read mode, reading this register gives (via the FIFO) the data that was received from the external device. If the FIFO does not have as many bytes as requested by the read operation and if BUSY = 1, the read operation is stalled until enough data is present or until the transfer is complete, whichever happens first. In Automatic-polling mode, this register contains the last data read from the external device (without masking). Word, half-word, and byte accesses to this register are supported. In Indirect-write mode, a byte write adds 1 byte to the FIFO, a half-word write 2 bytes, and a word write 4 bytes. Similarly, in Indirect-read mode, a byte read removes 1 byte from the FIFO, a halfword read 2 bytes, and a word read 4 bytes. Accesses in Indirect mode must be aligned to the bottom of this register: A byte read must read DATA[7:0] and a half-word read must read DATA[15:0].",
1401 ),
1402 bit_offset: BitOffset::Regular(
1403 RegularBitOffset {
1404 offset: 0,
1405 },
1406 ),
1407 bit_size: 32,
1408 array: None,
1409 enumm: None,
1410 },
1411 ],
1412 },
1413 FieldSet {
1414 name: "Fcr",
1415 extends: None,
1416 description: None,
1417 bit_size: 32,
1418 fields: &[
1419 Field {
1420 name: "ctef",
1421 description: Some(
1422 "Clear transfer error flag Writing 1 clears the TEF flag in the SR register.",
1423 ),
1424 bit_offset: BitOffset::Regular(
1425 RegularBitOffset {
1426 offset: 0,
1427 },
1428 ),
1429 bit_size: 1,
1430 array: None,
1431 enumm: None,
1432 },
1433 Field {
1434 name: "ctcf",
1435 description: Some(
1436 "Clear transfer complete flag Writing 1 clears the TCF flag in the SR register.",
1437 ),
1438 bit_offset: BitOffset::Regular(
1439 RegularBitOffset {
1440 offset: 1,
1441 },
1442 ),
1443 bit_size: 1,
1444 array: None,
1445 enumm: None,
1446 },
1447 Field {
1448 name: "csmf",
1449 description: Some(
1450 "Clear status match flag Writing 1 clears the SMF flag in the SR register.",
1451 ),
1452 bit_offset: BitOffset::Regular(
1453 RegularBitOffset {
1454 offset: 3,
1455 },
1456 ),
1457 bit_size: 1,
1458 array: None,
1459 enumm: None,
1460 },
1461 Field {
1462 name: "ctof",
1463 description: Some(
1464 "Clear timeout flag Writing 1 clears the TOF flag in the SR register.",
1465 ),
1466 bit_offset: BitOffset::Regular(
1467 RegularBitOffset {
1468 offset: 4,
1469 },
1470 ),
1471 bit_size: 1,
1472 array: None,
1473 enumm: None,
1474 },
1475 ],
1476 },
1477 FieldSet {
1478 name: "Hlcr",
1479 extends: None,
1480 description: Some(
1481 "HSPI HyperBus latency configuration register.",
1482 ),
1483 bit_size: 32,
1484 fields: &[
1485 Field {
1486 name: "lm",
1487 description: Some(
1488 "Latency mode This bit selects the Latency mode.",
1489 ),
1490 bit_offset: BitOffset::Regular(
1491 RegularBitOffset {
1492 offset: 0,
1493 },
1494 ),
1495 bit_size: 1,
1496 array: None,
1497 enumm: None,
1498 },
1499 Field {
1500 name: "wzl",
1501 description: Some(
1502 "Write zero latency This bit enables zero latency on write operations.",
1503 ),
1504 bit_offset: BitOffset::Regular(
1505 RegularBitOffset {
1506 offset: 1,
1507 },
1508 ),
1509 bit_size: 1,
1510 array: None,
1511 enumm: None,
1512 },
1513 Field {
1514 name: "tacc",
1515 description: Some(
1516 "[7: 0]: Access time Device access time expressed in number of communication clock cycles.",
1517 ),
1518 bit_offset: BitOffset::Regular(
1519 RegularBitOffset {
1520 offset: 8,
1521 },
1522 ),
1523 bit_size: 8,
1524 array: None,
1525 enumm: None,
1526 },
1527 Field {
1528 name: "trwr",
1529 description: Some(
1530 "Read write recovery time Device read write recovery time expressed in number of communication clock cycles.",
1531 ),
1532 bit_offset: BitOffset::Regular(
1533 RegularBitOffset {
1534 offset: 16,
1535 },
1536 ),
1537 bit_size: 8,
1538 array: None,
1539 enumm: None,
1540 },
1541 ],
1542 },
1543 FieldSet {
1544 name: "Ir",
1545 extends: None,
1546 description: Some(
1547 "HSPI instruction register.",
1548 ),
1549 bit_size: 32,
1550 fields: &[
1551 Field {
1552 name: "instruction",
1553 description: Some(
1554 "Instruction Instruction to be sent to the external SPI device.",
1555 ),
1556 bit_offset: BitOffset::Regular(
1557 RegularBitOffset {
1558 offset: 0,
1559 },
1560 ),
1561 bit_size: 32,
1562 array: None,
1563 enumm: None,
1564 },
1565 ],
1566 },
1567 FieldSet {
1568 name: "Lptr",
1569 extends: None,
1570 description: Some(
1571 "HSPI low-power timeout register.",
1572 ),
1573 bit_size: 32,
1574 fields: &[
1575 Field {
1576 name: "timeout",
1577 description: Some(
1578 "[15: 0]: Timeout period After each access in Memory-mapped mode, the HSPI prefetches the subsequent bytes and hold them in the FIFO. This field indicates how many CLK cycles the HSPI waits after the clock becomes inactive and until it raises the nCS, putting the external device in a lower-consumption state.",
1579 ),
1580 bit_offset: BitOffset::Regular(
1581 RegularBitOffset {
1582 offset: 0,
1583 },
1584 ),
1585 bit_size: 16,
1586 array: None,
1587 enumm: None,
1588 },
1589 ],
1590 },
1591 FieldSet {
1592 name: "Pir",
1593 extends: None,
1594 description: Some(
1595 "HSPI polling interval register.",
1596 ),
1597 bit_size: 32,
1598 fields: &[
1599 Field {
1600 name: "interval",
1601 description: Some(
1602 "[15: 0]: Polling interval Number of CLK cycle between a read during the automatic-polling phases.",
1603 ),
1604 bit_offset: BitOffset::Regular(
1605 RegularBitOffset {
1606 offset: 0,
1607 },
1608 ),
1609 bit_size: 16,
1610 array: None,
1611 enumm: None,
1612 },
1613 ],
1614 },
1615 FieldSet {
1616 name: "Psmar",
1617 extends: None,
1618 description: Some(
1619 "HSPI polling status match register.",
1620 ),
1621 bit_size: 32,
1622 fields: &[
1623 Field {
1624 name: "match_",
1625 description: Some(
1626 "[31: 0]: Status match Value to be compared with the masked status register to get a match.",
1627 ),
1628 bit_offset: BitOffset::Regular(
1629 RegularBitOffset {
1630 offset: 0,
1631 },
1632 ),
1633 bit_size: 32,
1634 array: None,
1635 enumm: None,
1636 },
1637 ],
1638 },
1639 FieldSet {
1640 name: "Psmkr",
1641 extends: None,
1642 description: Some(
1643 "HSPI polling status mask register.",
1644 ),
1645 bit_size: 32,
1646 fields: &[
1647 Field {
1648 name: "mask",
1649 description: Some(
1650 "Status mask Mask to be applied to the status bytes received in Polling mode For bit n:.",
1651 ),
1652 bit_offset: BitOffset::Regular(
1653 RegularBitOffset {
1654 offset: 0,
1655 },
1656 ),
1657 bit_size: 32,
1658 array: None,
1659 enumm: None,
1660 },
1661 ],
1662 },
1663 FieldSet {
1664 name: "Sr",
1665 extends: None,
1666 description: None,
1667 bit_size: 32,
1668 fields: &[
1669 Field {
1670 name: "tef",
1671 description: Some(
1672 "Transfer error flag This bit is set in Indirect mode when an invalid address is being accessed in Indirect mode. It is cleared by writing 1 to CTEF.",
1673 ),
1674 bit_offset: BitOffset::Regular(
1675 RegularBitOffset {
1676 offset: 0,
1677 },
1678 ),
1679 bit_size: 1,
1680 array: None,
1681 enumm: None,
1682 },
1683 Field {
1684 name: "tcf",
1685 description: Some(
1686 "Transfer complete flag This bit is set in Indirect mode when the programmed number of data has been transferred or in any mode when the transfer has been aborted.It is cleared by writing 1 to CTCF.",
1687 ),
1688 bit_offset: BitOffset::Regular(
1689 RegularBitOffset {
1690 offset: 1,
1691 },
1692 ),
1693 bit_size: 1,
1694 array: None,
1695 enumm: None,
1696 },
1697 Field {
1698 name: "ftf",
1699 description: Some(
1700 "FIFO threshold flag In Indirect mode, this bit is set when the FIFO threshold has been reached, or if there is any data left in the FIFO after the reads from the external device are complete. It is cleared automatically as soon as the threshold condition is no longer true. In Automatic-polling mode this bit is set every time the status register is read, and the bit is cleared when the data register is read.",
1701 ),
1702 bit_offset: BitOffset::Regular(
1703 RegularBitOffset {
1704 offset: 2,
1705 },
1706 ),
1707 bit_size: 1,
1708 array: None,
1709 enumm: None,
1710 },
1711 Field {
1712 name: "smf",
1713 description: Some(
1714 "Status match flag This bit is set in Automatic-polling mode when the unmasked received data matches the corresponding bits in the match register (PSMAR). It is cleared by writing 1 to CSMF.",
1715 ),
1716 bit_offset: BitOffset::Regular(
1717 RegularBitOffset {
1718 offset: 3,
1719 },
1720 ),
1721 bit_size: 1,
1722 array: None,
1723 enumm: None,
1724 },
1725 Field {
1726 name: "tof",
1727 description: Some(
1728 "Timeout flag This bit is set when timeout occurs. It is cleared by writing 1 to CTOF.",
1729 ),
1730 bit_offset: BitOffset::Regular(
1731 RegularBitOffset {
1732 offset: 4,
1733 },
1734 ),
1735 bit_size: 1,
1736 array: None,
1737 enumm: None,
1738 },
1739 Field {
1740 name: "busy",
1741 description: Some(
1742 "Busy This bit is set when an operation is ongoing. It is cleared automatically when the operation with the external device is finished and the FIFO is empty.",
1743 ),
1744 bit_offset: BitOffset::Regular(
1745 RegularBitOffset {
1746 offset: 5,
1747 },
1748 ),
1749 bit_size: 1,
1750 array: None,
1751 enumm: None,
1752 },
1753 Field {
1754 name: "flevel",
1755 description: Some(
1756 "FIFO level This field gives the number of valid bytes that are being held in the FIFO. FLEVEL = 0 when the FIFO is empty, and 64 when it is full. In Automatic-status polling mode, FLEVEL is zero.",
1757 ),
1758 bit_offset: BitOffset::Regular(
1759 RegularBitOffset {
1760 offset: 8,
1761 },
1762 ),
1763 bit_size: 7,
1764 array: None,
1765 enumm: None,
1766 },
1767 ],
1768 },
1769 FieldSet {
1770 name: "Tcr",
1771 extends: None,
1772 description: Some(
1773 "HSPI timing configuration register.",
1774 ),
1775 bit_size: 32,
1776 fields: &[
1777 Field {
1778 name: "dcyc",
1779 description: Some(
1780 "Number of dummy cycles This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31).",
1781 ),
1782 bit_offset: BitOffset::Regular(
1783 RegularBitOffset {
1784 offset: 0,
1785 },
1786 ),
1787 bit_size: 5,
1788 array: None,
1789 enumm: None,
1790 },
1791 Field {
1792 name: "dhqc",
1793 description: Some(
1794 "Delay hold quarter cycle.",
1795 ),
1796 bit_offset: BitOffset::Regular(
1797 RegularBitOffset {
1798 offset: 28,
1799 },
1800 ),
1801 bit_size: 1,
1802 array: None,
1803 enumm: None,
1804 },
1805 Field {
1806 name: "sshift",
1807 description: Some(
1808 "Sample shift By default, the HSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data to be sampled later in order to consider the external signal delays. The software must ensure that SSHIFT = 0 when the data phase is configured in DTR mode (when DDTR = 1.).",
1809 ),
1810 bit_offset: BitOffset::Regular(
1811 RegularBitOffset {
1812 offset: 30,
1813 },
1814 ),
1815 bit_size: 1,
1816 array: None,
1817 enumm: None,
1818 },
1819 ],
1820 },
1821 FieldSet {
1822 name: "Wabr",
1823 extends: None,
1824 description: Some(
1825 "HSPI write alternate bytes register.",
1826 ),
1827 bit_size: 32,
1828 fields: &[
1829 Field {
1830 name: "alternate",
1831 description: Some(
1832 "[31: 0]: Alternate bytes Optional data to be sent to the external SPI device right after the address.",
1833 ),
1834 bit_offset: BitOffset::Regular(
1835 RegularBitOffset {
1836 offset: 0,
1837 },
1838 ),
1839 bit_size: 32,
1840 array: None,
1841 enumm: None,
1842 },
1843 ],
1844 },
1845 FieldSet {
1846 name: "Wccr",
1847 extends: None,
1848 description: Some(
1849 "HSPI write communication configuration register.",
1850 ),
1851 bit_size: 32,
1852 fields: &[
1853 Field {
1854 name: "imode",
1855 description: Some(
1856 "Instruction mode This field defines the instruction phase mode of operation. 101-111: Reserved.",
1857 ),
1858 bit_offset: BitOffset::Regular(
1859 RegularBitOffset {
1860 offset: 0,
1861 },
1862 ),
1863 bit_size: 3,
1864 array: None,
1865 enumm: None,
1866 },
1867 Field {
1868 name: "idtr",
1869 description: Some(
1870 "Instruction double transfer rate This bit sets the DTR mode for the instruction phase.",
1871 ),
1872 bit_offset: BitOffset::Regular(
1873 RegularBitOffset {
1874 offset: 3,
1875 },
1876 ),
1877 bit_size: 1,
1878 array: None,
1879 enumm: None,
1880 },
1881 Field {
1882 name: "isize",
1883 description: Some(
1884 "Instruction size This bit defines instruction size:.",
1885 ),
1886 bit_offset: BitOffset::Regular(
1887 RegularBitOffset {
1888 offset: 4,
1889 },
1890 ),
1891 bit_size: 2,
1892 array: None,
1893 enumm: None,
1894 },
1895 Field {
1896 name: "admode",
1897 description: Some(
1898 "Address mode This field defines the address phase mode of operation. 101-111: Reserved.",
1899 ),
1900 bit_offset: BitOffset::Regular(
1901 RegularBitOffset {
1902 offset: 8,
1903 },
1904 ),
1905 bit_size: 3,
1906 array: None,
1907 enumm: None,
1908 },
1909 Field {
1910 name: "addtr",
1911 description: Some(
1912 "Address double transfer rate This bit sets the DTR mode for the address phase.",
1913 ),
1914 bit_offset: BitOffset::Regular(
1915 RegularBitOffset {
1916 offset: 11,
1917 },
1918 ),
1919 bit_size: 1,
1920 array: None,
1921 enumm: None,
1922 },
1923 Field {
1924 name: "adsize",
1925 description: Some(
1926 "Address size This field defines address size.",
1927 ),
1928 bit_offset: BitOffset::Regular(
1929 RegularBitOffset {
1930 offset: 12,
1931 },
1932 ),
1933 bit_size: 2,
1934 array: None,
1935 enumm: None,
1936 },
1937 Field {
1938 name: "abmode",
1939 description: Some(
1940 "Alternate-byte mode This field defines the alternate-byte phase mode of operation. 101-111: Reserved.",
1941 ),
1942 bit_offset: BitOffset::Regular(
1943 RegularBitOffset {
1944 offset: 16,
1945 },
1946 ),
1947 bit_size: 3,
1948 array: None,
1949 enumm: None,
1950 },
1951 Field {
1952 name: "abdtr",
1953 description: Some(
1954 "Alternate bytes double-transfer rate This bit sets the DTR mode for the alternate-bytes phase.",
1955 ),
1956 bit_offset: BitOffset::Regular(
1957 RegularBitOffset {
1958 offset: 19,
1959 },
1960 ),
1961 bit_size: 1,
1962 array: None,
1963 enumm: None,
1964 },
1965 Field {
1966 name: "absize",
1967 description: Some(
1968 "Alternate bytes size This field defines alternate bytes size:.",
1969 ),
1970 bit_offset: BitOffset::Regular(
1971 RegularBitOffset {
1972 offset: 20,
1973 },
1974 ),
1975 bit_size: 2,
1976 array: None,
1977 enumm: None,
1978 },
1979 Field {
1980 name: "dmode",
1981 description: Some(
1982 "Data mode This field defines the data phase mode of operation.",
1983 ),
1984 bit_offset: BitOffset::Regular(
1985 RegularBitOffset {
1986 offset: 24,
1987 },
1988 ),
1989 bit_size: 3,
1990 array: None,
1991 enumm: None,
1992 },
1993 Field {
1994 name: "ddtr",
1995 description: Some(
1996 "data double transfer rate This bit sets the DTR mode for the data phase.",
1997 ),
1998 bit_offset: BitOffset::Regular(
1999 RegularBitOffset {
2000 offset: 27,
2001 },
2002 ),
2003 bit_size: 1,
2004 array: None,
2005 enumm: None,
2006 },
2007 Field {
2008 name: "dqse",
2009 description: Some(
2010 "DQS enable This bit enables the data strobe management.",
2011 ),
2012 bit_offset: BitOffset::Regular(
2013 RegularBitOffset {
2014 offset: 29,
2015 },
2016 ),
2017 bit_size: 1,
2018 array: None,
2019 enumm: None,
2020 },
2021 ],
2022 },
2023 FieldSet {
2024 name: "Wir",
2025 extends: None,
2026 description: Some(
2027 "HSPI write instruction register.",
2028 ),
2029 bit_size: 32,
2030 fields: &[
2031 Field {
2032 name: "instruction",
2033 description: Some(
2034 "Instruction Instruction to be sent to the external SPI device.",
2035 ),
2036 bit_offset: BitOffset::Regular(
2037 RegularBitOffset {
2038 offset: 0,
2039 },
2040 ),
2041 bit_size: 32,
2042 array: None,
2043 enumm: None,
2044 },
2045 ],
2046 },
2047 FieldSet {
2048 name: "Wpabr",
2049 extends: None,
2050 description: Some(
2051 "HSPI wrap alternate bytes register.",
2052 ),
2053 bit_size: 32,
2054 fields: &[
2055 Field {
2056 name: "alternate",
2057 description: Some(
2058 "[31: 0]: Alternate bytes Optional data to be sent to the external SPI device right after the address.",
2059 ),
2060 bit_offset: BitOffset::Regular(
2061 RegularBitOffset {
2062 offset: 0,
2063 },
2064 ),
2065 bit_size: 32,
2066 array: None,
2067 enumm: None,
2068 },
2069 ],
2070 },
2071 FieldSet {
2072 name: "Wpccr",
2073 extends: None,
2074 description: Some(
2075 "HSPI wrap communication configuration register.",
2076 ),
2077 bit_size: 32,
2078 fields: &[
2079 Field {
2080 name: "imode",
2081 description: Some(
2082 "Instruction mode This field defines the instruction phase mode of operation. 101-111: Reserved.",
2083 ),
2084 bit_offset: BitOffset::Regular(
2085 RegularBitOffset {
2086 offset: 0,
2087 },
2088 ),
2089 bit_size: 3,
2090 array: None,
2091 enumm: None,
2092 },
2093 Field {
2094 name: "idtr",
2095 description: Some(
2096 "Instruction double transfer rate This bit sets the DTR mode for the instruction phase.",
2097 ),
2098 bit_offset: BitOffset::Regular(
2099 RegularBitOffset {
2100 offset: 3,
2101 },
2102 ),
2103 bit_size: 1,
2104 array: None,
2105 enumm: None,
2106 },
2107 Field {
2108 name: "isize",
2109 description: Some(
2110 "Instruction size This field defines instruction size.",
2111 ),
2112 bit_offset: BitOffset::Regular(
2113 RegularBitOffset {
2114 offset: 4,
2115 },
2116 ),
2117 bit_size: 2,
2118 array: None,
2119 enumm: None,
2120 },
2121 Field {
2122 name: "admode",
2123 description: Some(
2124 "Address mode This field defines the address phase mode of operation. 101-111: Reserved.",
2125 ),
2126 bit_offset: BitOffset::Regular(
2127 RegularBitOffset {
2128 offset: 8,
2129 },
2130 ),
2131 bit_size: 3,
2132 array: None,
2133 enumm: None,
2134 },
2135 Field {
2136 name: "addtr",
2137 description: Some(
2138 "Address double transfer rate This bit sets the DTR mode for the address phase.",
2139 ),
2140 bit_offset: BitOffset::Regular(
2141 RegularBitOffset {
2142 offset: 11,
2143 },
2144 ),
2145 bit_size: 1,
2146 array: None,
2147 enumm: None,
2148 },
2149 Field {
2150 name: "adsize",
2151 description: Some(
2152 "Address size This field defines address size.",
2153 ),
2154 bit_offset: BitOffset::Regular(
2155 RegularBitOffset {
2156 offset: 12,
2157 },
2158 ),
2159 bit_size: 2,
2160 array: None,
2161 enumm: None,
2162 },
2163 Field {
2164 name: "abmode",
2165 description: Some(
2166 "Alternate-byte mode This field defines the alternate byte phase mode of operation.",
2167 ),
2168 bit_offset: BitOffset::Regular(
2169 RegularBitOffset {
2170 offset: 16,
2171 },
2172 ),
2173 bit_size: 3,
2174 array: None,
2175 enumm: None,
2176 },
2177 Field {
2178 name: "abdtr",
2179 description: Some(
2180 "Alternate bytes double transfer rate This bit sets the DTR mode for the alternate bytes phase.",
2181 ),
2182 bit_offset: BitOffset::Regular(
2183 RegularBitOffset {
2184 offset: 19,
2185 },
2186 ),
2187 bit_size: 1,
2188 array: None,
2189 enumm: None,
2190 },
2191 Field {
2192 name: "absize",
2193 description: Some(
2194 "Alternate bytes size This bit defines alternate bytes size.",
2195 ),
2196 bit_offset: BitOffset::Regular(
2197 RegularBitOffset {
2198 offset: 20,
2199 },
2200 ),
2201 bit_size: 2,
2202 array: None,
2203 enumm: None,
2204 },
2205 Field {
2206 name: "dmode",
2207 description: Some(
2208 "Data mode This field defines the data phase mode of operation. 101; Data on 16 lines 110-111: Reserved.",
2209 ),
2210 bit_offset: BitOffset::Regular(
2211 RegularBitOffset {
2212 offset: 24,
2213 },
2214 ),
2215 bit_size: 3,
2216 array: None,
2217 enumm: None,
2218 },
2219 Field {
2220 name: "ddtr",
2221 description: Some(
2222 "Data double transfer rate This bit sets the DTR mode for the data phase.",
2223 ),
2224 bit_offset: BitOffset::Regular(
2225 RegularBitOffset {
2226 offset: 27,
2227 },
2228 ),
2229 bit_size: 1,
2230 array: None,
2231 enumm: None,
2232 },
2233 Field {
2234 name: "dqse",
2235 description: Some(
2236 "DQS enable This bit enables the data strobe management.",
2237 ),
2238 bit_offset: BitOffset::Regular(
2239 RegularBitOffset {
2240 offset: 29,
2241 },
2242 ),
2243 bit_size: 1,
2244 array: None,
2245 enumm: None,
2246 },
2247 ],
2248 },
2249 FieldSet {
2250 name: "Wpir",
2251 extends: None,
2252 description: Some(
2253 "HSPI wrap instruction register.",
2254 ),
2255 bit_size: 32,
2256 fields: &[
2257 Field {
2258 name: "instruction",
2259 description: Some(
2260 "[31: 0]: Instruction Instruction to be sent to the external SPI device.",
2261 ),
2262 bit_offset: BitOffset::Regular(
2263 RegularBitOffset {
2264 offset: 0,
2265 },
2266 ),
2267 bit_size: 32,
2268 array: None,
2269 enumm: None,
2270 },
2271 ],
2272 },
2273 FieldSet {
2274 name: "Wptcr",
2275 extends: None,
2276 description: Some(
2277 "HSPI wrap timing configuration register.",
2278 ),
2279 bit_size: 32,
2280 fields: &[
2281 Field {
2282 name: "dcyc",
2283 description: Some(
2284 "Number of dummy cycles This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated.",
2285 ),
2286 bit_offset: BitOffset::Regular(
2287 RegularBitOffset {
2288 offset: 0,
2289 },
2290 ),
2291 bit_size: 5,
2292 array: None,
2293 enumm: None,
2294 },
2295 Field {
2296 name: "dhqc",
2297 description: Some(
2298 "Delay hold quarter cycle Add a quarter cycle delay on the outputs in DTR communication to match hold requirement.",
2299 ),
2300 bit_offset: BitOffset::Regular(
2301 RegularBitOffset {
2302 offset: 28,
2303 },
2304 ),
2305 bit_size: 1,
2306 array: None,
2307 enumm: None,
2308 },
2309 Field {
2310 name: "sshift",
2311 description: Some(
2312 "Sample shift By default, the HSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data to be sampled later in order to consider the external signal delays. The firmware must assure that SSHIFT=0 when the data phase is configured in DTR mode (when DDTR = 1).",
2313 ),
2314 bit_offset: BitOffset::Regular(
2315 RegularBitOffset {
2316 offset: 30,
2317 },
2318 ),
2319 bit_size: 1,
2320 array: None,
2321 enumm: None,
2322 },
2323 ],
2324 },
2325 FieldSet {
2326 name: "Wtcr",
2327 extends: None,
2328 description: Some(
2329 "HSPI write timing configuration register.",
2330 ),
2331 bit_size: 32,
2332 fields: &[
2333 Field {
2334 name: "dcyc",
2335 description: Some(
2336 "Number of dummy cycles This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated.",
2337 ),
2338 bit_offset: BitOffset::Regular(
2339 RegularBitOffset {
2340 offset: 0,
2341 },
2342 ),
2343 bit_size: 5,
2344 array: None,
2345 enumm: None,
2346 },
2347 ],
2348 },
2349 ],
2350 enums: &[],
2351};
2352