1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "I2c",
7 extends: None,
8 description: Some(
9 "Inter-integrated circuit",
10 ),
11 items: &[
12 BlockItem {
13 name: "cr1",
14 description: Some(
15 "Control register 1",
16 ),
17 array: None,
18 byte_offset: 0x0,
19 inner: BlockItemInner::Register(
20 Register {
21 access: Access::ReadWrite,
22 bit_size: 32,
23 fieldset: Some(
24 "Cr1",
25 ),
26 },
27 ),
28 },
29 BlockItem {
30 name: "cr2",
31 description: Some(
32 "Control register 2",
33 ),
34 array: None,
35 byte_offset: 0x4,
36 inner: BlockItemInner::Register(
37 Register {
38 access: Access::ReadWrite,
39 bit_size: 32,
40 fieldset: Some(
41 "Cr2",
42 ),
43 },
44 ),
45 },
46 BlockItem {
47 name: "oar1",
48 description: Some(
49 "Own address register 1",
50 ),
51 array: None,
52 byte_offset: 0x8,
53 inner: BlockItemInner::Register(
54 Register {
55 access: Access::ReadWrite,
56 bit_size: 32,
57 fieldset: Some(
58 "Oar1",
59 ),
60 },
61 ),
62 },
63 BlockItem {
64 name: "oar2",
65 description: Some(
66 "Own address register 2",
67 ),
68 array: None,
69 byte_offset: 0xc,
70 inner: BlockItemInner::Register(
71 Register {
72 access: Access::ReadWrite,
73 bit_size: 32,
74 fieldset: Some(
75 "Oar2",
76 ),
77 },
78 ),
79 },
80 BlockItem {
81 name: "timingr",
82 description: Some(
83 "Timing register",
84 ),
85 array: None,
86 byte_offset: 0x10,
87 inner: BlockItemInner::Register(
88 Register {
89 access: Access::ReadWrite,
90 bit_size: 32,
91 fieldset: Some(
92 "Timingr",
93 ),
94 },
95 ),
96 },
97 BlockItem {
98 name: "timeoutr",
99 description: Some(
100 "Timeout register",
101 ),
102 array: None,
103 byte_offset: 0x14,
104 inner: BlockItemInner::Register(
105 Register {
106 access: Access::ReadWrite,
107 bit_size: 32,
108 fieldset: Some(
109 "Timeoutr",
110 ),
111 },
112 ),
113 },
114 BlockItem {
115 name: "isr",
116 description: Some(
117 "Interrupt and Status register",
118 ),
119 array: None,
120 byte_offset: 0x18,
121 inner: BlockItemInner::Register(
122 Register {
123 access: Access::ReadWrite,
124 bit_size: 32,
125 fieldset: Some(
126 "Isr",
127 ),
128 },
129 ),
130 },
131 BlockItem {
132 name: "icr",
133 description: Some(
134 "Interrupt clear register",
135 ),
136 array: None,
137 byte_offset: 0x1c,
138 inner: BlockItemInner::Register(
139 Register {
140 access: Access::ReadWrite,
141 bit_size: 32,
142 fieldset: Some(
143 "Icr",
144 ),
145 },
146 ),
147 },
148 BlockItem {
149 name: "pecr",
150 description: Some(
151 "PEC register",
152 ),
153 array: None,
154 byte_offset: 0x20,
155 inner: BlockItemInner::Register(
156 Register {
157 access: Access::ReadWrite,
158 bit_size: 32,
159 fieldset: Some(
160 "Pecr",
161 ),
162 },
163 ),
164 },
165 BlockItem {
166 name: "rxdr",
167 description: Some(
168 "Receive data register",
169 ),
170 array: None,
171 byte_offset: 0x24,
172 inner: BlockItemInner::Register(
173 Register {
174 access: Access::ReadWrite,
175 bit_size: 32,
176 fieldset: Some(
177 "Rxdr",
178 ),
179 },
180 ),
181 },
182 BlockItem {
183 name: "txdr",
184 description: Some(
185 "Transmit data register",
186 ),
187 array: None,
188 byte_offset: 0x28,
189 inner: BlockItemInner::Register(
190 Register {
191 access: Access::ReadWrite,
192 bit_size: 32,
193 fieldset: Some(
194 "Txdr",
195 ),
196 },
197 ),
198 },
199 ],
200 },
201 ],
202 fieldsets: &[
203 FieldSet {
204 name: "Cr1",
205 extends: None,
206 description: Some(
207 "Control register 1",
208 ),
209 bit_size: 32,
210 fields: &[
211 Field {
212 name: "pe",
213 description: Some(
214 "Peripheral enable",
215 ),
216 bit_offset: BitOffset::Regular(
217 RegularBitOffset {
218 offset: 0,
219 },
220 ),
221 bit_size: 1,
222 array: None,
223 enumm: None,
224 },
225 Field {
226 name: "txie",
227 description: Some(
228 "TX Interrupt enable",
229 ),
230 bit_offset: BitOffset::Regular(
231 RegularBitOffset {
232 offset: 1,
233 },
234 ),
235 bit_size: 1,
236 array: None,
237 enumm: None,
238 },
239 Field {
240 name: "rxie",
241 description: Some(
242 "RX Interrupt enable",
243 ),
244 bit_offset: BitOffset::Regular(
245 RegularBitOffset {
246 offset: 2,
247 },
248 ),
249 bit_size: 1,
250 array: None,
251 enumm: None,
252 },
253 Field {
254 name: "addrie",
255 description: Some(
256 "Address match interrupt enable (slave only)",
257 ),
258 bit_offset: BitOffset::Regular(
259 RegularBitOffset {
260 offset: 3,
261 },
262 ),
263 bit_size: 1,
264 array: None,
265 enumm: None,
266 },
267 Field {
268 name: "nackie",
269 description: Some(
270 "Not acknowledge received interrupt enable",
271 ),
272 bit_offset: BitOffset::Regular(
273 RegularBitOffset {
274 offset: 4,
275 },
276 ),
277 bit_size: 1,
278 array: None,
279 enumm: None,
280 },
281 Field {
282 name: "stopie",
283 description: Some(
284 "STOP detection Interrupt enable",
285 ),
286 bit_offset: BitOffset::Regular(
287 RegularBitOffset {
288 offset: 5,
289 },
290 ),
291 bit_size: 1,
292 array: None,
293 enumm: None,
294 },
295 Field {
296 name: "tcie",
297 description: Some(
298 "Transfer Complete interrupt enable",
299 ),
300 bit_offset: BitOffset::Regular(
301 RegularBitOffset {
302 offset: 6,
303 },
304 ),
305 bit_size: 1,
306 array: None,
307 enumm: None,
308 },
309 Field {
310 name: "errie",
311 description: Some(
312 "Error interrupts enable",
313 ),
314 bit_offset: BitOffset::Regular(
315 RegularBitOffset {
316 offset: 7,
317 },
318 ),
319 bit_size: 1,
320 array: None,
321 enumm: None,
322 },
323 Field {
324 name: "dnf",
325 description: Some(
326 "Digital noise filter",
327 ),
328 bit_offset: BitOffset::Regular(
329 RegularBitOffset {
330 offset: 8,
331 },
332 ),
333 bit_size: 4,
334 array: None,
335 enumm: Some(
336 "Dnf",
337 ),
338 },
339 Field {
340 name: "anfoff",
341 description: Some(
342 "Analog noise filter OFF",
343 ),
344 bit_offset: BitOffset::Regular(
345 RegularBitOffset {
346 offset: 12,
347 },
348 ),
349 bit_size: 1,
350 array: None,
351 enumm: None,
352 },
353 Field {
354 name: "txdmaen",
355 description: Some(
356 "DMA transmission requests enable",
357 ),
358 bit_offset: BitOffset::Regular(
359 RegularBitOffset {
360 offset: 14,
361 },
362 ),
363 bit_size: 1,
364 array: None,
365 enumm: None,
366 },
367 Field {
368 name: "rxdmaen",
369 description: Some(
370 "DMA reception requests enable",
371 ),
372 bit_offset: BitOffset::Regular(
373 RegularBitOffset {
374 offset: 15,
375 },
376 ),
377 bit_size: 1,
378 array: None,
379 enumm: None,
380 },
381 Field {
382 name: "sbc",
383 description: Some(
384 "Slave byte control",
385 ),
386 bit_offset: BitOffset::Regular(
387 RegularBitOffset {
388 offset: 16,
389 },
390 ),
391 bit_size: 1,
392 array: None,
393 enumm: None,
394 },
395 Field {
396 name: "nostretch",
397 description: Some(
398 "Clock stretching disable",
399 ),
400 bit_offset: BitOffset::Regular(
401 RegularBitOffset {
402 offset: 17,
403 },
404 ),
405 bit_size: 1,
406 array: None,
407 enumm: None,
408 },
409 Field {
410 name: "gcen",
411 description: Some(
412 "General call enable",
413 ),
414 bit_offset: BitOffset::Regular(
415 RegularBitOffset {
416 offset: 19,
417 },
418 ),
419 bit_size: 1,
420 array: None,
421 enumm: None,
422 },
423 Field {
424 name: "smbhen",
425 description: Some(
426 "SMBus Host address enable",
427 ),
428 bit_offset: BitOffset::Regular(
429 RegularBitOffset {
430 offset: 20,
431 },
432 ),
433 bit_size: 1,
434 array: None,
435 enumm: None,
436 },
437 Field {
438 name: "smbden",
439 description: Some(
440 "SMBus Device Default address enable",
441 ),
442 bit_offset: BitOffset::Regular(
443 RegularBitOffset {
444 offset: 21,
445 },
446 ),
447 bit_size: 1,
448 array: None,
449 enumm: None,
450 },
451 Field {
452 name: "alerten",
453 description: Some(
454 "SMBUS alert enable",
455 ),
456 bit_offset: BitOffset::Regular(
457 RegularBitOffset {
458 offset: 22,
459 },
460 ),
461 bit_size: 1,
462 array: None,
463 enumm: None,
464 },
465 Field {
466 name: "pecen",
467 description: Some(
468 "PEC enable",
469 ),
470 bit_offset: BitOffset::Regular(
471 RegularBitOffset {
472 offset: 23,
473 },
474 ),
475 bit_size: 1,
476 array: None,
477 enumm: None,
478 },
479 ],
480 },
481 FieldSet {
482 name: "Cr2",
483 extends: None,
484 description: Some(
485 "Control register 2",
486 ),
487 bit_size: 32,
488 fields: &[
489 Field {
490 name: "sadd",
491 description: Some(
492 "Slave address bit (master mode)",
493 ),
494 bit_offset: BitOffset::Regular(
495 RegularBitOffset {
496 offset: 0,
497 },
498 ),
499 bit_size: 10,
500 array: None,
501 enumm: None,
502 },
503 Field {
504 name: "dir",
505 description: Some(
506 "Transfer direction (master mode)",
507 ),
508 bit_offset: BitOffset::Regular(
509 RegularBitOffset {
510 offset: 10,
511 },
512 ),
513 bit_size: 1,
514 array: None,
515 enumm: Some(
516 "Dir",
517 ),
518 },
519 Field {
520 name: "add10",
521 description: Some(
522 "10-bit addressing mode (master mode)",
523 ),
524 bit_offset: BitOffset::Regular(
525 RegularBitOffset {
526 offset: 11,
527 },
528 ),
529 bit_size: 1,
530 array: None,
531 enumm: Some(
532 "Addmode",
533 ),
534 },
535 Field {
536 name: "head10r",
537 description: Some(
538 "10-bit address header only read direction (master receiver mode)",
539 ),
540 bit_offset: BitOffset::Regular(
541 RegularBitOffset {
542 offset: 12,
543 },
544 ),
545 bit_size: 1,
546 array: None,
547 enumm: Some(
548 "Headr",
549 ),
550 },
551 Field {
552 name: "start",
553 description: Some(
554 "Start generation",
555 ),
556 bit_offset: BitOffset::Regular(
557 RegularBitOffset {
558 offset: 13,
559 },
560 ),
561 bit_size: 1,
562 array: None,
563 enumm: None,
564 },
565 Field {
566 name: "stop",
567 description: Some(
568 "Stop generation (master mode)",
569 ),
570 bit_offset: BitOffset::Regular(
571 RegularBitOffset {
572 offset: 14,
573 },
574 ),
575 bit_size: 1,
576 array: None,
577 enumm: None,
578 },
579 Field {
580 name: "nack",
581 description: Some(
582 "NACK generation (slave mode)",
583 ),
584 bit_offset: BitOffset::Regular(
585 RegularBitOffset {
586 offset: 15,
587 },
588 ),
589 bit_size: 1,
590 array: None,
591 enumm: None,
592 },
593 Field {
594 name: "nbytes",
595 description: Some(
596 "Number of bytes",
597 ),
598 bit_offset: BitOffset::Regular(
599 RegularBitOffset {
600 offset: 16,
601 },
602 ),
603 bit_size: 8,
604 array: None,
605 enumm: None,
606 },
607 Field {
608 name: "reload",
609 description: Some(
610 "NBYTES reload mode",
611 ),
612 bit_offset: BitOffset::Regular(
613 RegularBitOffset {
614 offset: 24,
615 },
616 ),
617 bit_size: 1,
618 array: None,
619 enumm: Some(
620 "Reload",
621 ),
622 },
623 Field {
624 name: "autoend",
625 description: Some(
626 "Automatic end mode (master mode)",
627 ),
628 bit_offset: BitOffset::Regular(
629 RegularBitOffset {
630 offset: 25,
631 },
632 ),
633 bit_size: 1,
634 array: None,
635 enumm: Some(
636 "Autoend",
637 ),
638 },
639 Field {
640 name: "pecbyte",
641 description: Some(
642 "Packet error checking byte",
643 ),
644 bit_offset: BitOffset::Regular(
645 RegularBitOffset {
646 offset: 26,
647 },
648 ),
649 bit_size: 1,
650 array: None,
651 enumm: None,
652 },
653 ],
654 },
655 FieldSet {
656 name: "Icr",
657 extends: None,
658 description: Some(
659 "Interrupt clear register",
660 ),
661 bit_size: 32,
662 fields: &[
663 Field {
664 name: "addrcf",
665 description: Some(
666 "Address Matched flag clear",
667 ),
668 bit_offset: BitOffset::Regular(
669 RegularBitOffset {
670 offset: 3,
671 },
672 ),
673 bit_size: 1,
674 array: None,
675 enumm: None,
676 },
677 Field {
678 name: "nackcf",
679 description: Some(
680 "Not Acknowledge flag clear",
681 ),
682 bit_offset: BitOffset::Regular(
683 RegularBitOffset {
684 offset: 4,
685 },
686 ),
687 bit_size: 1,
688 array: None,
689 enumm: None,
690 },
691 Field {
692 name: "stopcf",
693 description: Some(
694 "Stop detection flag clear",
695 ),
696 bit_offset: BitOffset::Regular(
697 RegularBitOffset {
698 offset: 5,
699 },
700 ),
701 bit_size: 1,
702 array: None,
703 enumm: None,
704 },
705 Field {
706 name: "berrcf",
707 description: Some(
708 "Bus error flag clear",
709 ),
710 bit_offset: BitOffset::Regular(
711 RegularBitOffset {
712 offset: 8,
713 },
714 ),
715 bit_size: 1,
716 array: None,
717 enumm: None,
718 },
719 Field {
720 name: "arlocf",
721 description: Some(
722 "Arbitration lost flag clear",
723 ),
724 bit_offset: BitOffset::Regular(
725 RegularBitOffset {
726 offset: 9,
727 },
728 ),
729 bit_size: 1,
730 array: None,
731 enumm: None,
732 },
733 Field {
734 name: "ovrcf",
735 description: Some(
736 "Overrun/Underrun flag clear",
737 ),
738 bit_offset: BitOffset::Regular(
739 RegularBitOffset {
740 offset: 10,
741 },
742 ),
743 bit_size: 1,
744 array: None,
745 enumm: None,
746 },
747 Field {
748 name: "peccf",
749 description: Some(
750 "PEC Error flag clear",
751 ),
752 bit_offset: BitOffset::Regular(
753 RegularBitOffset {
754 offset: 11,
755 },
756 ),
757 bit_size: 1,
758 array: None,
759 enumm: None,
760 },
761 Field {
762 name: "timoutcf",
763 description: Some(
764 "Timeout detection flag clear",
765 ),
766 bit_offset: BitOffset::Regular(
767 RegularBitOffset {
768 offset: 12,
769 },
770 ),
771 bit_size: 1,
772 array: None,
773 enumm: None,
774 },
775 Field {
776 name: "alertcf",
777 description: Some(
778 "Alert flag clear",
779 ),
780 bit_offset: BitOffset::Regular(
781 RegularBitOffset {
782 offset: 13,
783 },
784 ),
785 bit_size: 1,
786 array: None,
787 enumm: None,
788 },
789 ],
790 },
791 FieldSet {
792 name: "Isr",
793 extends: None,
794 description: Some(
795 "Interrupt and Status register",
796 ),
797 bit_size: 32,
798 fields: &[
799 Field {
800 name: "txe",
801 description: Some(
802 "Transmit data register empty (transmitters)",
803 ),
804 bit_offset: BitOffset::Regular(
805 RegularBitOffset {
806 offset: 0,
807 },
808 ),
809 bit_size: 1,
810 array: None,
811 enumm: None,
812 },
813 Field {
814 name: "txis",
815 description: Some(
816 "Transmit interrupt status (transmitters)",
817 ),
818 bit_offset: BitOffset::Regular(
819 RegularBitOffset {
820 offset: 1,
821 },
822 ),
823 bit_size: 1,
824 array: None,
825 enumm: None,
826 },
827 Field {
828 name: "rxne",
829 description: Some(
830 "Receive data register not empty (receivers)",
831 ),
832 bit_offset: BitOffset::Regular(
833 RegularBitOffset {
834 offset: 2,
835 },
836 ),
837 bit_size: 1,
838 array: None,
839 enumm: None,
840 },
841 Field {
842 name: "addr",
843 description: Some(
844 "Address matched (slave mode)",
845 ),
846 bit_offset: BitOffset::Regular(
847 RegularBitOffset {
848 offset: 3,
849 },
850 ),
851 bit_size: 1,
852 array: None,
853 enumm: None,
854 },
855 Field {
856 name: "nackf",
857 description: Some(
858 "Not acknowledge received flag",
859 ),
860 bit_offset: BitOffset::Regular(
861 RegularBitOffset {
862 offset: 4,
863 },
864 ),
865 bit_size: 1,
866 array: None,
867 enumm: None,
868 },
869 Field {
870 name: "stopf",
871 description: Some(
872 "Stop detection flag",
873 ),
874 bit_offset: BitOffset::Regular(
875 RegularBitOffset {
876 offset: 5,
877 },
878 ),
879 bit_size: 1,
880 array: None,
881 enumm: None,
882 },
883 Field {
884 name: "tc",
885 description: Some(
886 "Transfer Complete (master mode)",
887 ),
888 bit_offset: BitOffset::Regular(
889 RegularBitOffset {
890 offset: 6,
891 },
892 ),
893 bit_size: 1,
894 array: None,
895 enumm: None,
896 },
897 Field {
898 name: "tcr",
899 description: Some(
900 "Transfer Complete Reload",
901 ),
902 bit_offset: BitOffset::Regular(
903 RegularBitOffset {
904 offset: 7,
905 },
906 ),
907 bit_size: 1,
908 array: None,
909 enumm: None,
910 },
911 Field {
912 name: "berr",
913 description: Some(
914 "Bus error",
915 ),
916 bit_offset: BitOffset::Regular(
917 RegularBitOffset {
918 offset: 8,
919 },
920 ),
921 bit_size: 1,
922 array: None,
923 enumm: None,
924 },
925 Field {
926 name: "arlo",
927 description: Some(
928 "Arbitration lost",
929 ),
930 bit_offset: BitOffset::Regular(
931 RegularBitOffset {
932 offset: 9,
933 },
934 ),
935 bit_size: 1,
936 array: None,
937 enumm: None,
938 },
939 Field {
940 name: "ovr",
941 description: Some(
942 "Overrun/Underrun (slave mode)",
943 ),
944 bit_offset: BitOffset::Regular(
945 RegularBitOffset {
946 offset: 10,
947 },
948 ),
949 bit_size: 1,
950 array: None,
951 enumm: None,
952 },
953 Field {
954 name: "pecerr",
955 description: Some(
956 "PEC Error in reception",
957 ),
958 bit_offset: BitOffset::Regular(
959 RegularBitOffset {
960 offset: 11,
961 },
962 ),
963 bit_size: 1,
964 array: None,
965 enumm: None,
966 },
967 Field {
968 name: "timeout",
969 description: Some(
970 "Timeout or t_low detection flag",
971 ),
972 bit_offset: BitOffset::Regular(
973 RegularBitOffset {
974 offset: 12,
975 },
976 ),
977 bit_size: 1,
978 array: None,
979 enumm: None,
980 },
981 Field {
982 name: "alert",
983 description: Some(
984 "SMBus alert",
985 ),
986 bit_offset: BitOffset::Regular(
987 RegularBitOffset {
988 offset: 13,
989 },
990 ),
991 bit_size: 1,
992 array: None,
993 enumm: None,
994 },
995 Field {
996 name: "busy",
997 description: Some(
998 "Bus busy",
999 ),
1000 bit_offset: BitOffset::Regular(
1001 RegularBitOffset {
1002 offset: 15,
1003 },
1004 ),
1005 bit_size: 1,
1006 array: None,
1007 enumm: None,
1008 },
1009 Field {
1010 name: "dir",
1011 description: Some(
1012 "Transfer direction (Slave mode)",
1013 ),
1014 bit_offset: BitOffset::Regular(
1015 RegularBitOffset {
1016 offset: 16,
1017 },
1018 ),
1019 bit_size: 1,
1020 array: None,
1021 enumm: Some(
1022 "Dir",
1023 ),
1024 },
1025 Field {
1026 name: "addcode",
1027 description: Some(
1028 "Address match code (Slave mode)",
1029 ),
1030 bit_offset: BitOffset::Regular(
1031 RegularBitOffset {
1032 offset: 17,
1033 },
1034 ),
1035 bit_size: 7,
1036 array: None,
1037 enumm: None,
1038 },
1039 ],
1040 },
1041 FieldSet {
1042 name: "Oar1",
1043 extends: None,
1044 description: Some(
1045 "Own address register 1",
1046 ),
1047 bit_size: 32,
1048 fields: &[
1049 Field {
1050 name: "oa1",
1051 description: Some(
1052 "Interface address",
1053 ),
1054 bit_offset: BitOffset::Regular(
1055 RegularBitOffset {
1056 offset: 0,
1057 },
1058 ),
1059 bit_size: 10,
1060 array: None,
1061 enumm: None,
1062 },
1063 Field {
1064 name: "oa1mode",
1065 description: Some(
1066 "Own Address 1 10-bit mode",
1067 ),
1068 bit_offset: BitOffset::Regular(
1069 RegularBitOffset {
1070 offset: 10,
1071 },
1072 ),
1073 bit_size: 1,
1074 array: None,
1075 enumm: Some(
1076 "Addmode",
1077 ),
1078 },
1079 Field {
1080 name: "oa1en",
1081 description: Some(
1082 "Own Address 1 enable",
1083 ),
1084 bit_offset: BitOffset::Regular(
1085 RegularBitOffset {
1086 offset: 15,
1087 },
1088 ),
1089 bit_size: 1,
1090 array: None,
1091 enumm: None,
1092 },
1093 ],
1094 },
1095 FieldSet {
1096 name: "Oar2",
1097 extends: None,
1098 description: Some(
1099 "Own address register 2",
1100 ),
1101 bit_size: 32,
1102 fields: &[
1103 Field {
1104 name: "oa2",
1105 description: Some(
1106 "Interface address",
1107 ),
1108 bit_offset: BitOffset::Regular(
1109 RegularBitOffset {
1110 offset: 1,
1111 },
1112 ),
1113 bit_size: 7,
1114 array: None,
1115 enumm: None,
1116 },
1117 Field {
1118 name: "oa2msk",
1119 description: Some(
1120 "Own Address 2 masks",
1121 ),
1122 bit_offset: BitOffset::Regular(
1123 RegularBitOffset {
1124 offset: 8,
1125 },
1126 ),
1127 bit_size: 3,
1128 array: None,
1129 enumm: Some(
1130 "Oamsk",
1131 ),
1132 },
1133 Field {
1134 name: "oa2en",
1135 description: Some(
1136 "Own Address 2 enable",
1137 ),
1138 bit_offset: BitOffset::Regular(
1139 RegularBitOffset {
1140 offset: 15,
1141 },
1142 ),
1143 bit_size: 1,
1144 array: None,
1145 enumm: None,
1146 },
1147 ],
1148 },
1149 FieldSet {
1150 name: "Pecr",
1151 extends: None,
1152 description: Some(
1153 "PEC register",
1154 ),
1155 bit_size: 32,
1156 fields: &[
1157 Field {
1158 name: "pec",
1159 description: Some(
1160 "Packet error checking register",
1161 ),
1162 bit_offset: BitOffset::Regular(
1163 RegularBitOffset {
1164 offset: 0,
1165 },
1166 ),
1167 bit_size: 8,
1168 array: None,
1169 enumm: None,
1170 },
1171 ],
1172 },
1173 FieldSet {
1174 name: "Rxdr",
1175 extends: None,
1176 description: Some(
1177 "Receive data register",
1178 ),
1179 bit_size: 32,
1180 fields: &[
1181 Field {
1182 name: "rxdata",
1183 description: Some(
1184 "8-bit receive data",
1185 ),
1186 bit_offset: BitOffset::Regular(
1187 RegularBitOffset {
1188 offset: 0,
1189 },
1190 ),
1191 bit_size: 8,
1192 array: None,
1193 enumm: None,
1194 },
1195 ],
1196 },
1197 FieldSet {
1198 name: "Timeoutr",
1199 extends: None,
1200 description: Some(
1201 "Timeout register",
1202 ),
1203 bit_size: 32,
1204 fields: &[
1205 Field {
1206 name: "timeouta",
1207 description: Some(
1208 "Bus timeout A",
1209 ),
1210 bit_offset: BitOffset::Regular(
1211 RegularBitOffset {
1212 offset: 0,
1213 },
1214 ),
1215 bit_size: 12,
1216 array: None,
1217 enumm: None,
1218 },
1219 Field {
1220 name: "tidle",
1221 description: Some(
1222 "Idle clock timeout detection",
1223 ),
1224 bit_offset: BitOffset::Regular(
1225 RegularBitOffset {
1226 offset: 12,
1227 },
1228 ),
1229 bit_size: 1,
1230 array: None,
1231 enumm: None,
1232 },
1233 Field {
1234 name: "timouten",
1235 description: Some(
1236 "Clock timeout enable",
1237 ),
1238 bit_offset: BitOffset::Regular(
1239 RegularBitOffset {
1240 offset: 15,
1241 },
1242 ),
1243 bit_size: 1,
1244 array: None,
1245 enumm: None,
1246 },
1247 Field {
1248 name: "timeoutb",
1249 description: Some(
1250 "Bus timeout B",
1251 ),
1252 bit_offset: BitOffset::Regular(
1253 RegularBitOffset {
1254 offset: 16,
1255 },
1256 ),
1257 bit_size: 12,
1258 array: None,
1259 enumm: None,
1260 },
1261 Field {
1262 name: "texten",
1263 description: Some(
1264 "Extended clock timeout enable",
1265 ),
1266 bit_offset: BitOffset::Regular(
1267 RegularBitOffset {
1268 offset: 31,
1269 },
1270 ),
1271 bit_size: 1,
1272 array: None,
1273 enumm: None,
1274 },
1275 ],
1276 },
1277 FieldSet {
1278 name: "Timingr",
1279 extends: None,
1280 description: Some(
1281 "Timing register",
1282 ),
1283 bit_size: 32,
1284 fields: &[
1285 Field {
1286 name: "scll",
1287 description: Some(
1288 "SCL low period (master mode)",
1289 ),
1290 bit_offset: BitOffset::Regular(
1291 RegularBitOffset {
1292 offset: 0,
1293 },
1294 ),
1295 bit_size: 8,
1296 array: None,
1297 enumm: None,
1298 },
1299 Field {
1300 name: "sclh",
1301 description: Some(
1302 "SCL high period (master mode)",
1303 ),
1304 bit_offset: BitOffset::Regular(
1305 RegularBitOffset {
1306 offset: 8,
1307 },
1308 ),
1309 bit_size: 8,
1310 array: None,
1311 enumm: None,
1312 },
1313 Field {
1314 name: "sdadel",
1315 description: Some(
1316 "Data hold time",
1317 ),
1318 bit_offset: BitOffset::Regular(
1319 RegularBitOffset {
1320 offset: 16,
1321 },
1322 ),
1323 bit_size: 4,
1324 array: None,
1325 enumm: None,
1326 },
1327 Field {
1328 name: "scldel",
1329 description: Some(
1330 "Data setup time",
1331 ),
1332 bit_offset: BitOffset::Regular(
1333 RegularBitOffset {
1334 offset: 20,
1335 },
1336 ),
1337 bit_size: 4,
1338 array: None,
1339 enumm: None,
1340 },
1341 Field {
1342 name: "presc",
1343 description: Some(
1344 "Timing prescaler",
1345 ),
1346 bit_offset: BitOffset::Regular(
1347 RegularBitOffset {
1348 offset: 28,
1349 },
1350 ),
1351 bit_size: 4,
1352 array: None,
1353 enumm: None,
1354 },
1355 ],
1356 },
1357 FieldSet {
1358 name: "Txdr",
1359 extends: None,
1360 description: Some(
1361 "Transmit data register",
1362 ),
1363 bit_size: 32,
1364 fields: &[
1365 Field {
1366 name: "txdata",
1367 description: Some(
1368 "8-bit transmit data",
1369 ),
1370 bit_offset: BitOffset::Regular(
1371 RegularBitOffset {
1372 offset: 0,
1373 },
1374 ),
1375 bit_size: 8,
1376 array: None,
1377 enumm: None,
1378 },
1379 ],
1380 },
1381 ],
1382 enums: &[
1383 Enum {
1384 name: "Addmode",
1385 description: None,
1386 bit_size: 1,
1387 variants: &[
1388 EnumVariant {
1389 name: "BIT7",
1390 description: Some(
1391 "7-bit addressing mode",
1392 ),
1393 value: 0,
1394 },
1395 EnumVariant {
1396 name: "BIT10",
1397 description: Some(
1398 "10-bit addressing mode",
1399 ),
1400 value: 1,
1401 },
1402 ],
1403 },
1404 Enum {
1405 name: "Autoend",
1406 description: None,
1407 bit_size: 1,
1408 variants: &[
1409 EnumVariant {
1410 name: "SOFTWARE",
1411 description: Some(
1412 "Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low",
1413 ),
1414 value: 0,
1415 },
1416 EnumVariant {
1417 name: "AUTOMATIC",
1418 description: Some(
1419 "Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred",
1420 ),
1421 value: 1,
1422 },
1423 ],
1424 },
1425 Enum {
1426 name: "Dir",
1427 description: None,
1428 bit_size: 1,
1429 variants: &[
1430 EnumVariant {
1431 name: "WRITE",
1432 description: Some(
1433 "Write transfer, slave enters receiver mode",
1434 ),
1435 value: 0,
1436 },
1437 EnumVariant {
1438 name: "READ",
1439 description: Some(
1440 "Read transfer, slave enters transmitter mode",
1441 ),
1442 value: 1,
1443 },
1444 ],
1445 },
1446 Enum {
1447 name: "Dnf",
1448 description: None,
1449 bit_size: 4,
1450 variants: &[
1451 EnumVariant {
1452 name: "NO_FILTER",
1453 description: Some(
1454 "Digital filter disabled",
1455 ),
1456 value: 0,
1457 },
1458 EnumVariant {
1459 name: "FILTER1",
1460 description: Some(
1461 "Digital filter enabled and filtering capability up to 1 tI2CCLK",
1462 ),
1463 value: 1,
1464 },
1465 EnumVariant {
1466 name: "FILTER2",
1467 description: Some(
1468 "Digital filter enabled and filtering capability up to 2 tI2CCLK",
1469 ),
1470 value: 2,
1471 },
1472 EnumVariant {
1473 name: "FILTER3",
1474 description: Some(
1475 "Digital filter enabled and filtering capability up to 3 tI2CCLK",
1476 ),
1477 value: 3,
1478 },
1479 EnumVariant {
1480 name: "FILTER4",
1481 description: Some(
1482 "Digital filter enabled and filtering capability up to 4 tI2CCLK",
1483 ),
1484 value: 4,
1485 },
1486 EnumVariant {
1487 name: "FILTER5",
1488 description: Some(
1489 "Digital filter enabled and filtering capability up to 5 tI2CCLK",
1490 ),
1491 value: 5,
1492 },
1493 EnumVariant {
1494 name: "FILTER6",
1495 description: Some(
1496 "Digital filter enabled and filtering capability up to 6 tI2CCLK",
1497 ),
1498 value: 6,
1499 },
1500 EnumVariant {
1501 name: "FILTER7",
1502 description: Some(
1503 "Digital filter enabled and filtering capability up to 7 tI2CCLK",
1504 ),
1505 value: 7,
1506 },
1507 EnumVariant {
1508 name: "FILTER8",
1509 description: Some(
1510 "Digital filter enabled and filtering capability up to 8 tI2CCLK",
1511 ),
1512 value: 8,
1513 },
1514 EnumVariant {
1515 name: "FILTER9",
1516 description: Some(
1517 "Digital filter enabled and filtering capability up to 9 tI2CCLK",
1518 ),
1519 value: 9,
1520 },
1521 EnumVariant {
1522 name: "FILTER10",
1523 description: Some(
1524 "Digital filter enabled and filtering capability up to 10 tI2CCLK",
1525 ),
1526 value: 10,
1527 },
1528 EnumVariant {
1529 name: "FILTER11",
1530 description: Some(
1531 "Digital filter enabled and filtering capability up to 11 tI2CCLK",
1532 ),
1533 value: 11,
1534 },
1535 EnumVariant {
1536 name: "FILTER12",
1537 description: Some(
1538 "Digital filter enabled and filtering capability up to 12 tI2CCLK",
1539 ),
1540 value: 12,
1541 },
1542 EnumVariant {
1543 name: "FILTER13",
1544 description: Some(
1545 "Digital filter enabled and filtering capability up to 13 tI2CCLK",
1546 ),
1547 value: 13,
1548 },
1549 EnumVariant {
1550 name: "FILTER14",
1551 description: Some(
1552 "Digital filter enabled and filtering capability up to 14 tI2CCLK",
1553 ),
1554 value: 14,
1555 },
1556 EnumVariant {
1557 name: "FILTER15",
1558 description: Some(
1559 "Digital filter enabled and filtering capability up to 15 tI2CCLK",
1560 ),
1561 value: 15,
1562 },
1563 ],
1564 },
1565 Enum {
1566 name: "Headr",
1567 description: None,
1568 bit_size: 1,
1569 variants: &[
1570 EnumVariant {
1571 name: "COMPLETE",
1572 description: Some(
1573 "The master sends the complete 10 bit slave address read sequence",
1574 ),
1575 value: 0,
1576 },
1577 EnumVariant {
1578 name: "PARTIAL",
1579 description: Some(
1580 "The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction",
1581 ),
1582 value: 1,
1583 },
1584 ],
1585 },
1586 Enum {
1587 name: "Oamsk",
1588 description: None,
1589 bit_size: 3,
1590 variants: &[
1591 EnumVariant {
1592 name: "NO_MASK",
1593 description: Some(
1594 "No mask",
1595 ),
1596 value: 0,
1597 },
1598 EnumVariant {
1599 name: "MASK1",
1600 description: Some(
1601 "OA2[1] is masked and don’t care. Only OA2[7:2] are compared",
1602 ),
1603 value: 1,
1604 },
1605 EnumVariant {
1606 name: "MASK2",
1607 description: Some(
1608 "OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared",
1609 ),
1610 value: 2,
1611 },
1612 EnumVariant {
1613 name: "MASK3",
1614 description: Some(
1615 "OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared",
1616 ),
1617 value: 3,
1618 },
1619 EnumVariant {
1620 name: "MASK4",
1621 description: Some(
1622 "OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared",
1623 ),
1624 value: 4,
1625 },
1626 EnumVariant {
1627 name: "MASK5",
1628 description: Some(
1629 "OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared",
1630 ),
1631 value: 5,
1632 },
1633 EnumVariant {
1634 name: "MASK6",
1635 description: Some(
1636 "OA2[6:1] are masked and don’t care. Only OA2[7] is compared.",
1637 ),
1638 value: 6,
1639 },
1640 EnumVariant {
1641 name: "MASK7",
1642 description: Some(
1643 "OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged",
1644 ),
1645 value: 7,
1646 },
1647 ],
1648 },
1649 Enum {
1650 name: "Reload",
1651 description: None,
1652 bit_size: 1,
1653 variants: &[
1654 EnumVariant {
1655 name: "COMPLETED",
1656 description: Some(
1657 "The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)",
1658 ),
1659 value: 0,
1660 },
1661 EnumVariant {
1662 name: "NOT_COMPLETED",
1663 description: Some(
1664 "The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)",
1665 ),
1666 value: 1,
1667 },
1668 ],
1669 },
1670 ],
1671};
1672