1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Icache",
7 extends: None,
8 description: Some(
9 "Instruction Cache Control Registers.",
10 ),
11 items: &[
12 BlockItem {
13 name: "cr",
14 description: Some(
15 "ICACHE control register.",
16 ),
17 array: None,
18 byte_offset: 0x0,
19 inner: BlockItemInner::Register(
20 Register {
21 access: Access::ReadWrite,
22 bit_size: 32,
23 fieldset: Some(
24 "Cr",
25 ),
26 },
27 ),
28 },
29 BlockItem {
30 name: "sr",
31 description: Some(
32 "ICACHE status register.",
33 ),
34 array: None,
35 byte_offset: 0x4,
36 inner: BlockItemInner::Register(
37 Register {
38 access: Access::Read,
39 bit_size: 32,
40 fieldset: Some(
41 "Sr",
42 ),
43 },
44 ),
45 },
46 BlockItem {
47 name: "ier",
48 description: Some(
49 "ICACHE interrupt enable register.",
50 ),
51 array: None,
52 byte_offset: 0x8,
53 inner: BlockItemInner::Register(
54 Register {
55 access: Access::ReadWrite,
56 bit_size: 32,
57 fieldset: Some(
58 "Ier",
59 ),
60 },
61 ),
62 },
63 BlockItem {
64 name: "fcr",
65 description: Some(
66 "ICACHE flag clear register.",
67 ),
68 array: None,
69 byte_offset: 0xc,
70 inner: BlockItemInner::Register(
71 Register {
72 access: Access::Write,
73 bit_size: 32,
74 fieldset: Some(
75 "Fcr",
76 ),
77 },
78 ),
79 },
80 BlockItem {
81 name: "hmonr",
82 description: Some(
83 "ICACHE hit monitor register.",
84 ),
85 array: None,
86 byte_offset: 0x10,
87 inner: BlockItemInner::Register(
88 Register {
89 access: Access::Read,
90 bit_size: 32,
91 fieldset: None,
92 },
93 ),
94 },
95 BlockItem {
96 name: "mmonr",
97 description: Some(
98 "ICACHE miss monitor register.",
99 ),
100 array: None,
101 byte_offset: 0x14,
102 inner: BlockItemInner::Register(
103 Register {
104 access: Access::Read,
105 bit_size: 32,
106 fieldset: Some(
107 "Mmonr",
108 ),
109 },
110 ),
111 },
112 BlockItem {
113 name: "crr",
114 description: Some(
115 "Cluster CRR%s, container region configuration registers.",
116 ),
117 array: Some(
118 Array::Regular(
119 RegularArray {
120 len: 3,
121 stride: 4,
122 },
123 ),
124 ),
125 byte_offset: 0x20,
126 inner: BlockItemInner::Register(
127 Register {
128 access: Access::ReadWrite,
129 bit_size: 32,
130 fieldset: Some(
131 "Crr",
132 ),
133 },
134 ),
135 },
136 ],
137 },
138 ],
139 fieldsets: &[
140 FieldSet {
141 name: "Cr",
142 extends: None,
143 description: Some(
144 "ICACHE control register.",
145 ),
146 bit_size: 32,
147 fields: &[
148 Field {
149 name: "en",
150 description: Some(
151 "EN.",
152 ),
153 bit_offset: BitOffset::Regular(
154 RegularBitOffset {
155 offset: 0,
156 },
157 ),
158 bit_size: 1,
159 array: None,
160 enumm: None,
161 },
162 Field {
163 name: "cacheinv",
164 description: Some(
165 "Set by software and cleared by hardware when the BUSYF flag is set (during cache maintenance operation). Writing 0 has no effect.",
166 ),
167 bit_offset: BitOffset::Regular(
168 RegularBitOffset {
169 offset: 1,
170 },
171 ),
172 bit_size: 1,
173 array: None,
174 enumm: None,
175 },
176 Field {
177 name: "waysel",
178 description: Some(
179 "This bit allows user to choose ICACHE set-associativity. It can be written by software only when cache is disabled (EN = 0).",
180 ),
181 bit_offset: BitOffset::Regular(
182 RegularBitOffset {
183 offset: 2,
184 },
185 ),
186 bit_size: 1,
187 array: None,
188 enumm: Some(
189 "Waysel",
190 ),
191 },
192 Field {
193 name: "hitmen",
194 description: Some(
195 "Hit monitor enable.",
196 ),
197 bit_offset: BitOffset::Regular(
198 RegularBitOffset {
199 offset: 16,
200 },
201 ),
202 bit_size: 1,
203 array: None,
204 enumm: None,
205 },
206 Field {
207 name: "missmen",
208 description: Some(
209 "Miss monitor enable.",
210 ),
211 bit_offset: BitOffset::Regular(
212 RegularBitOffset {
213 offset: 17,
214 },
215 ),
216 bit_size: 1,
217 array: None,
218 enumm: None,
219 },
220 Field {
221 name: "hitmrst",
222 description: Some(
223 "Hit monitor reset.",
224 ),
225 bit_offset: BitOffset::Regular(
226 RegularBitOffset {
227 offset: 18,
228 },
229 ),
230 bit_size: 1,
231 array: None,
232 enumm: None,
233 },
234 Field {
235 name: "missmrst",
236 description: Some(
237 "Miss monitor reset.",
238 ),
239 bit_offset: BitOffset::Regular(
240 RegularBitOffset {
241 offset: 19,
242 },
243 ),
244 bit_size: 1,
245 array: None,
246 enumm: None,
247 },
248 ],
249 },
250 FieldSet {
251 name: "Crr",
252 extends: None,
253 description: Some(
254 "ICACHE region configuration register.",
255 ),
256 bit_size: 32,
257 fields: &[
258 Field {
259 name: "baseaddr",
260 description: Some(
261 "base address for region.",
262 ),
263 bit_offset: BitOffset::Regular(
264 RegularBitOffset {
265 offset: 0,
266 },
267 ),
268 bit_size: 8,
269 array: None,
270 enumm: None,
271 },
272 Field {
273 name: "rsize",
274 description: Some(
275 "size for region.",
276 ),
277 bit_offset: BitOffset::Regular(
278 RegularBitOffset {
279 offset: 9,
280 },
281 ),
282 bit_size: 3,
283 array: None,
284 enumm: Some(
285 "Rsize",
286 ),
287 },
288 Field {
289 name: "ren",
290 description: Some(
291 "enable for region.",
292 ),
293 bit_offset: BitOffset::Regular(
294 RegularBitOffset {
295 offset: 15,
296 },
297 ),
298 bit_size: 1,
299 array: None,
300 enumm: None,
301 },
302 Field {
303 name: "remapaddr",
304 description: Some(
305 "remapped address for region.",
306 ),
307 bit_offset: BitOffset::Regular(
308 RegularBitOffset {
309 offset: 16,
310 },
311 ),
312 bit_size: 11,
313 array: None,
314 enumm: None,
315 },
316 Field {
317 name: "mstsel",
318 description: Some(
319 "AHB cache master selection for region.",
320 ),
321 bit_offset: BitOffset::Regular(
322 RegularBitOffset {
323 offset: 28,
324 },
325 ),
326 bit_size: 1,
327 array: None,
328 enumm: Some(
329 "Mstsel",
330 ),
331 },
332 Field {
333 name: "hburst",
334 description: Some(
335 "output burst type for region.",
336 ),
337 bit_offset: BitOffset::Regular(
338 RegularBitOffset {
339 offset: 31,
340 },
341 ),
342 bit_size: 1,
343 array: None,
344 enumm: Some(
345 "Hburst",
346 ),
347 },
348 ],
349 },
350 FieldSet {
351 name: "Fcr",
352 extends: None,
353 description: Some(
354 "ICACHE flag clear register.",
355 ),
356 bit_size: 32,
357 fields: &[
358 Field {
359 name: "cbsyendf",
360 description: Some(
361 "Clear busy end flag.",
362 ),
363 bit_offset: BitOffset::Regular(
364 RegularBitOffset {
365 offset: 1,
366 },
367 ),
368 bit_size: 1,
369 array: None,
370 enumm: None,
371 },
372 Field {
373 name: "cerrf",
374 description: Some(
375 "Clear ERRF flag in SR.",
376 ),
377 bit_offset: BitOffset::Regular(
378 RegularBitOffset {
379 offset: 2,
380 },
381 ),
382 bit_size: 1,
383 array: None,
384 enumm: None,
385 },
386 ],
387 },
388 FieldSet {
389 name: "Ier",
390 extends: None,
391 description: Some(
392 "ICACHE interrupt enable register.",
393 ),
394 bit_size: 32,
395 fields: &[
396 Field {
397 name: "bsyendie",
398 description: Some(
399 "Interrupt enable on busy end.",
400 ),
401 bit_offset: BitOffset::Regular(
402 RegularBitOffset {
403 offset: 1,
404 },
405 ),
406 bit_size: 1,
407 array: None,
408 enumm: None,
409 },
410 Field {
411 name: "errie",
412 description: Some(
413 "Error interrupt on cache error.",
414 ),
415 bit_offset: BitOffset::Regular(
416 RegularBitOffset {
417 offset: 2,
418 },
419 ),
420 bit_size: 1,
421 array: None,
422 enumm: None,
423 },
424 ],
425 },
426 FieldSet {
427 name: "Mmonr",
428 extends: None,
429 description: Some(
430 "ICACHE miss monitor register.",
431 ),
432 bit_size: 32,
433 fields: &[
434 Field {
435 name: "missmon",
436 description: Some(
437 "Miss monitor register.",
438 ),
439 bit_offset: BitOffset::Regular(
440 RegularBitOffset {
441 offset: 0,
442 },
443 ),
444 bit_size: 16,
445 array: None,
446 enumm: None,
447 },
448 ],
449 },
450 FieldSet {
451 name: "Sr",
452 extends: None,
453 description: Some(
454 "ICACHE status register.",
455 ),
456 bit_size: 32,
457 fields: &[
458 Field {
459 name: "busyf",
460 description: Some(
461 "cache busy executing a full invalidate CACHEINV operation.",
462 ),
463 bit_offset: BitOffset::Regular(
464 RegularBitOffset {
465 offset: 0,
466 },
467 ),
468 bit_size: 1,
469 array: None,
470 enumm: None,
471 },
472 Field {
473 name: "bsyendf",
474 description: Some(
475 "full invalidate CACHEINV operation finished.",
476 ),
477 bit_offset: BitOffset::Regular(
478 RegularBitOffset {
479 offset: 1,
480 },
481 ),
482 bit_size: 1,
483 array: None,
484 enumm: None,
485 },
486 Field {
487 name: "errf",
488 description: Some(
489 "an error occurred during the operation.",
490 ),
491 bit_offset: BitOffset::Regular(
492 RegularBitOffset {
493 offset: 2,
494 },
495 ),
496 bit_size: 1,
497 array: None,
498 enumm: None,
499 },
500 ],
501 },
502 ],
503 enums: &[
504 Enum {
505 name: "Hburst",
506 description: None,
507 bit_size: 1,
508 variants: &[
509 EnumVariant {
510 name: "WRAP",
511 description: None,
512 value: 0,
513 },
514 EnumVariant {
515 name: "INCREMENT",
516 description: None,
517 value: 1,
518 },
519 ],
520 },
521 Enum {
522 name: "Mstsel",
523 description: None,
524 bit_size: 1,
525 variants: &[
526 EnumVariant {
527 name: "MASTER1SELECTED",
528 description: None,
529 value: 0,
530 },
531 EnumVariant {
532 name: "MASTER2SELECTED",
533 description: None,
534 value: 1,
535 },
536 ],
537 },
538 Enum {
539 name: "Rsize",
540 description: None,
541 bit_size: 3,
542 variants: &[
543 EnumVariant {
544 name: "MEGA_BYTES2",
545 description: None,
546 value: 1,
547 },
548 EnumVariant {
549 name: "MEGA_BYTES4",
550 description: None,
551 value: 2,
552 },
553 EnumVariant {
554 name: "MEGA_BYTES8",
555 description: None,
556 value: 3,
557 },
558 EnumVariant {
559 name: "MEGA_BYTES16",
560 description: None,
561 value: 4,
562 },
563 EnumVariant {
564 name: "MEGA_BYTES32",
565 description: None,
566 value: 5,
567 },
568 EnumVariant {
569 name: "MEGA_BYTES64",
570 description: None,
571 value: 6,
572 },
573 EnumVariant {
574 name: "MEGA_BYTES128",
575 description: None,
576 value: 7,
577 },
578 ],
579 },
580 Enum {
581 name: "Waysel",
582 description: None,
583 bit_size: 1,
584 variants: &[
585 EnumVariant {
586 name: "DIRECT_MAPPED",
587 description: Some(
588 "direct mapped cache (1-way cache)",
589 ),
590 value: 0,
591 },
592 EnumVariant {
593 name: "NWAY_SET_ASSOCIATIVE",
594 description: Some(
595 "n-way set associative cache (reset value)",
596 ),
597 value: 1,
598 },
599 ],
600 },
601 ],
602};
603