1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Iwdg",
7 extends: None,
8 description: Some(
9 "Independent watchdog",
10 ),
11 items: &[
12 BlockItem {
13 name: "kr",
14 description: Some(
15 "Key register",
16 ),
17 array: None,
18 byte_offset: 0x0,
19 inner: BlockItemInner::Register(
20 Register {
21 access: Access::ReadWrite,
22 bit_size: 32,
23 fieldset: Some(
24 "Kr",
25 ),
26 },
27 ),
28 },
29 BlockItem {
30 name: "pr",
31 description: Some(
32 "Prescaler register",
33 ),
34 array: None,
35 byte_offset: 0x4,
36 inner: BlockItemInner::Register(
37 Register {
38 access: Access::ReadWrite,
39 bit_size: 32,
40 fieldset: Some(
41 "Pr",
42 ),
43 },
44 ),
45 },
46 BlockItem {
47 name: "rlr",
48 description: Some(
49 "Reload register",
50 ),
51 array: None,
52 byte_offset: 0x8,
53 inner: BlockItemInner::Register(
54 Register {
55 access: Access::ReadWrite,
56 bit_size: 32,
57 fieldset: Some(
58 "Rlr",
59 ),
60 },
61 ),
62 },
63 BlockItem {
64 name: "sr",
65 description: Some(
66 "Status register",
67 ),
68 array: None,
69 byte_offset: 0xc,
70 inner: BlockItemInner::Register(
71 Register {
72 access: Access::ReadWrite,
73 bit_size: 32,
74 fieldset: Some(
75 "Sr",
76 ),
77 },
78 ),
79 },
80 BlockItem {
81 name: "winr",
82 description: Some(
83 "Window register",
84 ),
85 array: None,
86 byte_offset: 0x10,
87 inner: BlockItemInner::Register(
88 Register {
89 access: Access::ReadWrite,
90 bit_size: 32,
91 fieldset: Some(
92 "Winr",
93 ),
94 },
95 ),
96 },
97 BlockItem {
98 name: "ewcr",
99 description: Some(
100 "IWDG early wakeup interrupt register.",
101 ),
102 array: None,
103 byte_offset: 0x14,
104 inner: BlockItemInner::Register(
105 Register {
106 access: Access::ReadWrite,
107 bit_size: 32,
108 fieldset: Some(
109 "Ewcr",
110 ),
111 },
112 ),
113 },
114 ],
115 },
116 ],
117 fieldsets: &[
118 FieldSet {
119 name: "Ewcr",
120 extends: None,
121 description: Some(
122 "IWDG early wakeup interrupt register.",
123 ),
124 bit_size: 32,
125 fields: &[
126 Field {
127 name: "ewit",
128 description: Some(
129 "Watchdog counter window value These bits are write access protected (see ). They are written by software to define at which position of the IWDCNT down-counter the early wakeup interrupt must be generated. The early interrupt is generated when the IWDCNT is lower or equal to EWIT[11:0] - 1. EWIT[11:0] must be bigger than 1. An interrupt is generated only if EWIE = 1. The EWU bit in the must be reset to be able to change the reload value. Note: Reading this register returns the Early wakeup comparator value and the Interrupt enable bit from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing, hence the value read from this register is valid only when the EWU bit in the is reset.",
130 ),
131 bit_offset: BitOffset::Regular(
132 RegularBitOffset {
133 offset: 0,
134 },
135 ),
136 bit_size: 12,
137 array: None,
138 enumm: None,
139 },
140 Field {
141 name: "ewic",
142 description: Some(
143 "Watchdog early interrupt acknowledge The software must write a 1 into this bit in order to acknowledge the early wakeup interrupt and to clear the EWIF flag. Writing 0 has not effect, reading this flag returns a 0.",
144 ),
145 bit_offset: BitOffset::Regular(
146 RegularBitOffset {
147 offset: 14,
148 },
149 ),
150 bit_size: 1,
151 array: None,
152 enumm: None,
153 },
154 Field {
155 name: "ewie",
156 description: Some(
157 "Watchdog early interrupt enable Set and reset by software. The EWU bit in the must be reset to be able to change the value of this bit.",
158 ),
159 bit_offset: BitOffset::Regular(
160 RegularBitOffset {
161 offset: 15,
162 },
163 ),
164 bit_size: 1,
165 array: None,
166 enumm: None,
167 },
168 ],
169 },
170 FieldSet {
171 name: "Kr",
172 extends: None,
173 description: Some(
174 "Key register",
175 ),
176 bit_size: 32,
177 fields: &[
178 Field {
179 name: "key",
180 description: Some(
181 "Key value (write only, read 0000h)",
182 ),
183 bit_offset: BitOffset::Regular(
184 RegularBitOffset {
185 offset: 0,
186 },
187 ),
188 bit_size: 16,
189 array: None,
190 enumm: Some(
191 "Key",
192 ),
193 },
194 ],
195 },
196 FieldSet {
197 name: "Pr",
198 extends: None,
199 description: Some(
200 "Prescaler register",
201 ),
202 bit_size: 32,
203 fields: &[
204 Field {
205 name: "pr",
206 description: Some(
207 "Prescaler divider",
208 ),
209 bit_offset: BitOffset::Regular(
210 RegularBitOffset {
211 offset: 0,
212 },
213 ),
214 bit_size: 4,
215 array: None,
216 enumm: Some(
217 "Pr",
218 ),
219 },
220 ],
221 },
222 FieldSet {
223 name: "Rlr",
224 extends: None,
225 description: Some(
226 "Reload register",
227 ),
228 bit_size: 32,
229 fields: &[
230 Field {
231 name: "rl",
232 description: Some(
233 "Watchdog counter reload value",
234 ),
235 bit_offset: BitOffset::Regular(
236 RegularBitOffset {
237 offset: 0,
238 },
239 ),
240 bit_size: 12,
241 array: None,
242 enumm: None,
243 },
244 ],
245 },
246 FieldSet {
247 name: "Sr",
248 extends: None,
249 description: Some(
250 "Status register",
251 ),
252 bit_size: 32,
253 fields: &[
254 Field {
255 name: "pvu",
256 description: Some(
257 "Watchdog prescaler value update",
258 ),
259 bit_offset: BitOffset::Regular(
260 RegularBitOffset {
261 offset: 0,
262 },
263 ),
264 bit_size: 1,
265 array: None,
266 enumm: None,
267 },
268 Field {
269 name: "rvu",
270 description: Some(
271 "Watchdog counter reload value update",
272 ),
273 bit_offset: BitOffset::Regular(
274 RegularBitOffset {
275 offset: 1,
276 },
277 ),
278 bit_size: 1,
279 array: None,
280 enumm: None,
281 },
282 Field {
283 name: "wvu",
284 description: Some(
285 "Watchdog counter window value update",
286 ),
287 bit_offset: BitOffset::Regular(
288 RegularBitOffset {
289 offset: 2,
290 },
291 ),
292 bit_size: 1,
293 array: None,
294 enumm: None,
295 },
296 Field {
297 name: "ewu",
298 description: Some(
299 "Watchdog interrupt comparator value update This bit is set by hardware to indicate that an update of the interrupt comparator value (EWIT[11:0]) or an update of the EWIE is ongoing. It is reset by hardware when the update operation is completed in the VDD voltage domain (takes up to three periods of the IWDG kernel clock iwdg_ker_ck). The EWIT[11:0] and EWIE fields can be updated only when EWU bit is reset.",
300 ),
301 bit_offset: BitOffset::Regular(
302 RegularBitOffset {
303 offset: 3,
304 },
305 ),
306 bit_size: 1,
307 array: None,
308 enumm: None,
309 },
310 Field {
311 name: "ewif",
312 description: Some(
313 "Watchdog early interrupt flag This bit is set to ‘1’ by hardware in order to indicate that an early interrupt is pending. This bit must be cleared by the software by writing the bit EWIC of IWDG_EWCR register to ‘1’.",
314 ),
315 bit_offset: BitOffset::Regular(
316 RegularBitOffset {
317 offset: 14,
318 },
319 ),
320 bit_size: 1,
321 array: None,
322 enumm: None,
323 },
324 ],
325 },
326 FieldSet {
327 name: "Winr",
328 extends: None,
329 description: Some(
330 "Window register",
331 ),
332 bit_size: 32,
333 fields: &[
334 Field {
335 name: "win",
336 description: Some(
337 "Watchdog counter window value",
338 ),
339 bit_offset: BitOffset::Regular(
340 RegularBitOffset {
341 offset: 0,
342 },
343 ),
344 bit_size: 12,
345 array: None,
346 enumm: None,
347 },
348 ],
349 },
350 ],
351 enums: &[
352 Enum {
353 name: "Key",
354 description: None,
355 bit_size: 16,
356 variants: &[
357 EnumVariant {
358 name: "ENABLE",
359 description: Some(
360 "Enable access to PR, RLR and WINR registers (0x5555)",
361 ),
362 value: 21845,
363 },
364 EnumVariant {
365 name: "RESET",
366 description: Some(
367 "Reset the watchdog value (0xAAAA)",
368 ),
369 value: 43690,
370 },
371 EnumVariant {
372 name: "START",
373 description: Some(
374 "Start the watchdog (0xCCCC)",
375 ),
376 value: 52428,
377 },
378 ],
379 },
380 Enum {
381 name: "Pr",
382 description: None,
383 bit_size: 4,
384 variants: &[
385 EnumVariant {
386 name: "DIVIDE_BY4",
387 description: Some(
388 "Divider /4",
389 ),
390 value: 0,
391 },
392 EnumVariant {
393 name: "DIVIDE_BY8",
394 description: Some(
395 "Divider /8",
396 ),
397 value: 1,
398 },
399 EnumVariant {
400 name: "DIVIDE_BY16",
401 description: Some(
402 "Divider /16",
403 ),
404 value: 2,
405 },
406 EnumVariant {
407 name: "DIVIDE_BY32",
408 description: Some(
409 "Divider /32",
410 ),
411 value: 3,
412 },
413 EnumVariant {
414 name: "DIVIDE_BY64",
415 description: Some(
416 "Divider /64",
417 ),
418 value: 4,
419 },
420 EnumVariant {
421 name: "DIVIDE_BY128",
422 description: Some(
423 "Divider /128",
424 ),
425 value: 5,
426 },
427 EnumVariant {
428 name: "DIVIDE_BY256",
429 description: Some(
430 "Divider /256",
431 ),
432 value: 6,
433 },
434 EnumVariant {
435 name: "DIVIDE_BY512",
436 description: Some(
437 "Divider /512",
438 ),
439 value: 7,
440 },
441 EnumVariant {
442 name: "DIVIDE_BY1024",
443 description: Some(
444 "Divider /1024",
445 ),
446 value: 8,
447 },
448 ],
449 },
450 ],
451};
452