1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Channel",
7 extends: None,
8 description: None,
9 items: &[
10 BlockItem {
11 name: "lbar",
12 description: Some(
13 "LPDMA channel 15 linked-list base address register",
14 ),
15 array: None,
16 byte_offset: 0x0,
17 inner: BlockItemInner::Register(
18 Register {
19 access: Access::ReadWrite,
20 bit_size: 32,
21 fieldset: Some(
22 "ChLbar",
23 ),
24 },
25 ),
26 },
27 BlockItem {
28 name: "fcr",
29 description: Some(
30 "LPDMA channel 15 flag clear register",
31 ),
32 array: None,
33 byte_offset: 0xc,
34 inner: BlockItemInner::Register(
35 Register {
36 access: Access::ReadWrite,
37 bit_size: 32,
38 fieldset: Some(
39 "ChFcr",
40 ),
41 },
42 ),
43 },
44 BlockItem {
45 name: "sr",
46 description: Some(
47 "LPDMA channel 15 status register",
48 ),
49 array: None,
50 byte_offset: 0x10,
51 inner: BlockItemInner::Register(
52 Register {
53 access: Access::ReadWrite,
54 bit_size: 32,
55 fieldset: Some(
56 "ChSr",
57 ),
58 },
59 ),
60 },
61 BlockItem {
62 name: "cr",
63 description: Some(
64 "LPDMA channel 15 control register",
65 ),
66 array: None,
67 byte_offset: 0x14,
68 inner: BlockItemInner::Register(
69 Register {
70 access: Access::ReadWrite,
71 bit_size: 32,
72 fieldset: Some(
73 "ChCr",
74 ),
75 },
76 ),
77 },
78 BlockItem {
79 name: "tr1",
80 description: Some(
81 "LPDMA channel 15 transfer register 1",
82 ),
83 array: None,
84 byte_offset: 0x40,
85 inner: BlockItemInner::Register(
86 Register {
87 access: Access::ReadWrite,
88 bit_size: 32,
89 fieldset: Some(
90 "ChTr1",
91 ),
92 },
93 ),
94 },
95 BlockItem {
96 name: "tr2",
97 description: Some(
98 "LPDMA channel 15 transfer register 2",
99 ),
100 array: None,
101 byte_offset: 0x44,
102 inner: BlockItemInner::Register(
103 Register {
104 access: Access::ReadWrite,
105 bit_size: 32,
106 fieldset: Some(
107 "ChTr2",
108 ),
109 },
110 ),
111 },
112 BlockItem {
113 name: "br1",
114 description: Some(
115 "LPDMA channel 15 alternate block register 1",
116 ),
117 array: None,
118 byte_offset: 0x48,
119 inner: BlockItemInner::Register(
120 Register {
121 access: Access::ReadWrite,
122 bit_size: 32,
123 fieldset: Some(
124 "ChBr1",
125 ),
126 },
127 ),
128 },
129 BlockItem {
130 name: "sar",
131 description: Some(
132 "LPDMA channel 15 source address register",
133 ),
134 array: None,
135 byte_offset: 0x4c,
136 inner: BlockItemInner::Register(
137 Register {
138 access: Access::ReadWrite,
139 bit_size: 32,
140 fieldset: None,
141 },
142 ),
143 },
144 BlockItem {
145 name: "dar",
146 description: Some(
147 "LPDMA channel 15 destination address register",
148 ),
149 array: None,
150 byte_offset: 0x50,
151 inner: BlockItemInner::Register(
152 Register {
153 access: Access::ReadWrite,
154 bit_size: 32,
155 fieldset: None,
156 },
157 ),
158 },
159 BlockItem {
160 name: "tr3",
161 description: Some(
162 "LPDMA channel 15 transfer register 3",
163 ),
164 array: None,
165 byte_offset: 0x54,
166 inner: BlockItemInner::Register(
167 Register {
168 access: Access::ReadWrite,
169 bit_size: 32,
170 fieldset: Some(
171 "ChTr3",
172 ),
173 },
174 ),
175 },
176 BlockItem {
177 name: "br2",
178 description: Some(
179 "LPDMA channel 15 block register 2",
180 ),
181 array: None,
182 byte_offset: 0x58,
183 inner: BlockItemInner::Register(
184 Register {
185 access: Access::ReadWrite,
186 bit_size: 32,
187 fieldset: Some(
188 "ChBr2",
189 ),
190 },
191 ),
192 },
193 BlockItem {
194 name: "llr",
195 description: Some(
196 "LPDMA channel 15 alternate linked-list address register",
197 ),
198 array: None,
199 byte_offset: 0x7c,
200 inner: BlockItemInner::Register(
201 Register {
202 access: Access::ReadWrite,
203 bit_size: 32,
204 fieldset: Some(
205 "ChLlr",
206 ),
207 },
208 ),
209 },
210 ],
211 },
212 Block {
213 name: "Lpdma",
214 extends: None,
215 description: Some(
216 "LPDMA",
217 ),
218 items: &[
219 BlockItem {
220 name: "seccfgr",
221 description: Some(
222 "LPDMA secure configuration register",
223 ),
224 array: None,
225 byte_offset: 0x0,
226 inner: BlockItemInner::Register(
227 Register {
228 access: Access::ReadWrite,
229 bit_size: 32,
230 fieldset: Some(
231 "Seccfgr",
232 ),
233 },
234 ),
235 },
236 BlockItem {
237 name: "privcfgr",
238 description: Some(
239 "LPDMA privileged configuration register",
240 ),
241 array: None,
242 byte_offset: 0x4,
243 inner: BlockItemInner::Register(
244 Register {
245 access: Access::ReadWrite,
246 bit_size: 32,
247 fieldset: Some(
248 "Privcfgr",
249 ),
250 },
251 ),
252 },
253 BlockItem {
254 name: "rcfglockr",
255 description: Some(
256 "LPDMA configuration lock register",
257 ),
258 array: None,
259 byte_offset: 0x8,
260 inner: BlockItemInner::Register(
261 Register {
262 access: Access::ReadWrite,
263 bit_size: 32,
264 fieldset: Some(
265 "Rcfglockr",
266 ),
267 },
268 ),
269 },
270 BlockItem {
271 name: "misr",
272 description: Some(
273 "LPDMA non-secure masked interrupt status register",
274 ),
275 array: None,
276 byte_offset: 0xc,
277 inner: BlockItemInner::Register(
278 Register {
279 access: Access::ReadWrite,
280 bit_size: 32,
281 fieldset: Some(
282 "Misr",
283 ),
284 },
285 ),
286 },
287 BlockItem {
288 name: "smisr",
289 description: Some(
290 "LPDMA secure masked interrupt status register",
291 ),
292 array: None,
293 byte_offset: 0x10,
294 inner: BlockItemInner::Register(
295 Register {
296 access: Access::ReadWrite,
297 bit_size: 32,
298 fieldset: Some(
299 "Misr",
300 ),
301 },
302 ),
303 },
304 BlockItem {
305 name: "ch",
306 description: None,
307 array: Some(
308 Array::Regular(
309 RegularArray {
310 len: 4,
311 stride: 128,
312 },
313 ),
314 ),
315 byte_offset: 0x50,
316 inner: BlockItemInner::Block(
317 BlockItemBlock {
318 block: "Channel",
319 },
320 ),
321 },
322 ],
323 },
324 ],
325 fieldsets: &[
326 FieldSet {
327 name: "ChBr1",
328 extends: None,
329 description: Some(
330 "LPDMA channel 15 alternate block register 1",
331 ),
332 bit_size: 32,
333 fields: &[
334 Field {
335 name: "bndt",
336 description: Some(
337 "block number of data bytes to transfer from the source. Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if CH[x].LLR.UB1 = 1, this field is updated by the LLI in the memory. - if CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. - if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if CH[x].LLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. When configured in packing mode (CH[x].TR1.PAM[1]=1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued.",
338 ),
339 bit_offset: BitOffset::Regular(
340 RegularBitOffset {
341 offset: 0,
342 },
343 ),
344 bit_size: 16,
345 array: None,
346 enumm: None,
347 },
348 Field {
349 name: "brc",
350 description: Some(
351 "Block repeat counter. This field contains the number of repetitions of the current block (0 to 2047). When the channel is enabled, this field becomes read-only. After decrements, this field indicates the remaining number of blocks, excluding the current one. This counter is hardware decremented for each completed block transfer. Once the last block transfer is completed (BRC[10:0] = BNDT[15:0] = 0): If CH[x].LLR.UB1 = 1, all CH[x].BR1 fields are updated by the next LLI in the memory. If CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). if CH[x].LLR = 0, this field is kept as zero following the last LLI and data transfer.",
352 ),
353 bit_offset: BitOffset::Regular(
354 RegularBitOffset {
355 offset: 16,
356 },
357 ),
358 bit_size: 11,
359 array: None,
360 enumm: None,
361 },
362 Field {
363 name: "sdec",
364 description: Some(
365 "source address decrement",
366 ),
367 bit_offset: BitOffset::Regular(
368 RegularBitOffset {
369 offset: 28,
370 },
371 ),
372 bit_size: 1,
373 array: None,
374 enumm: Some(
375 "Dec",
376 ),
377 },
378 Field {
379 name: "ddec",
380 description: Some(
381 "destination address decrement",
382 ),
383 bit_offset: BitOffset::Regular(
384 RegularBitOffset {
385 offset: 29,
386 },
387 ),
388 bit_size: 1,
389 array: None,
390 enumm: Some(
391 "Dec",
392 ),
393 },
394 Field {
395 name: "brsdec",
396 description: Some(
397 "Block repeat source address decrement. Note: On top of this increment/decrement (depending on BRSDEC), CH[x].SAR is in the same time also updated by the increment/decrement (depending on SDEC) of the CH[x].TR3.SAO value, as it is done after any programmed burst transfer.",
398 ),
399 bit_offset: BitOffset::Regular(
400 RegularBitOffset {
401 offset: 30,
402 },
403 ),
404 bit_size: 1,
405 array: None,
406 enumm: Some(
407 "Dec",
408 ),
409 },
410 Field {
411 name: "brddec",
412 description: Some(
413 "Block repeat destination address decrement. Note: On top of this increment/decrement (depending on BRDDEC), CH[x].DAR is in the same time also updated by the increment/decrement (depending on DDEC) of the CH[x].TR3.DAO value, as it is usually done at the end of each programmed burst transfer.",
414 ),
415 bit_offset: BitOffset::Regular(
416 RegularBitOffset {
417 offset: 31,
418 },
419 ),
420 bit_size: 1,
421 array: None,
422 enumm: Some(
423 "Dec",
424 ),
425 },
426 ],
427 },
428 FieldSet {
429 name: "ChBr2",
430 extends: None,
431 description: Some(
432 "LPDMA channel 12 block register 2",
433 ),
434 bit_size: 32,
435 fields: &[
436 Field {
437 name: "brsao",
438 description: Some(
439 "Block repeated source address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRSDEC) the current source address (CH[x].SAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (BRSAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued.",
440 ),
441 bit_offset: BitOffset::Regular(
442 RegularBitOffset {
443 offset: 0,
444 },
445 ),
446 bit_size: 16,
447 array: None,
448 enumm: None,
449 },
450 Field {
451 name: "brdao",
452 description: Some(
453 "Block repeated destination address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRDDEC) the current destination address (CH[x].DAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (BRDAO[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued.",
454 ),
455 bit_offset: BitOffset::Regular(
456 RegularBitOffset {
457 offset: 16,
458 },
459 ),
460 bit_size: 16,
461 array: None,
462 enumm: None,
463 },
464 ],
465 },
466 FieldSet {
467 name: "ChCr",
468 extends: None,
469 description: Some(
470 "LPDMA channel 11 control register",
471 ),
472 bit_size: 32,
473 fields: &[
474 Field {
475 name: "en",
476 description: Some(
477 "enable. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored.",
478 ),
479 bit_offset: BitOffset::Regular(
480 RegularBitOffset {
481 offset: 0,
482 },
483 ),
484 bit_size: 1,
485 array: None,
486 enumm: None,
487 },
488 Field {
489 name: "reset",
490 description: Some(
491 "reset. This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the FIFO, the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (CH[x].SR.SUSPF = 1 and CH[x].SR.IDLEF = CH[x].CR.EN = 1). - channel in disabled state (CH[x].SR.IDLEF = 1 and CH[x].CR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (CH[x].BR1, CH[x].SAR and CH[x].DAR) before enabling again the channel (see the programming sequence in ).",
492 ),
493 bit_offset: BitOffset::Regular(
494 RegularBitOffset {
495 offset: 1,
496 },
497 ),
498 bit_size: 1,
499 array: None,
500 enumm: None,
501 },
502 Field {
503 name: "susp",
504 description: Some(
505 "suspend. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going LPDMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in .",
506 ),
507 bit_offset: BitOffset::Regular(
508 RegularBitOffset {
509 offset: 2,
510 },
511 ),
512 bit_size: 1,
513 array: None,
514 enumm: None,
515 },
516 Field {
517 name: "tcie",
518 description: Some(
519 "transfer complete interrupt enable",
520 ),
521 bit_offset: BitOffset::Regular(
522 RegularBitOffset {
523 offset: 8,
524 },
525 ),
526 bit_size: 1,
527 array: None,
528 enumm: None,
529 },
530 Field {
531 name: "htie",
532 description: Some(
533 "half transfer complete interrupt enable",
534 ),
535 bit_offset: BitOffset::Regular(
536 RegularBitOffset {
537 offset: 9,
538 },
539 ),
540 bit_size: 1,
541 array: None,
542 enumm: None,
543 },
544 Field {
545 name: "dteie",
546 description: Some(
547 "data transfer error interrupt enable",
548 ),
549 bit_offset: BitOffset::Regular(
550 RegularBitOffset {
551 offset: 10,
552 },
553 ),
554 bit_size: 1,
555 array: None,
556 enumm: None,
557 },
558 Field {
559 name: "uleie",
560 description: Some(
561 "update link transfer error interrupt enable",
562 ),
563 bit_offset: BitOffset::Regular(
564 RegularBitOffset {
565 offset: 11,
566 },
567 ),
568 bit_size: 1,
569 array: None,
570 enumm: None,
571 },
572 Field {
573 name: "useie",
574 description: Some(
575 "user setting error interrupt enable",
576 ),
577 bit_offset: BitOffset::Regular(
578 RegularBitOffset {
579 offset: 12,
580 },
581 ),
582 bit_size: 1,
583 array: None,
584 enumm: None,
585 },
586 Field {
587 name: "suspie",
588 description: Some(
589 "completed suspension interrupt enable",
590 ),
591 bit_offset: BitOffset::Regular(
592 RegularBitOffset {
593 offset: 13,
594 },
595 ),
596 bit_size: 1,
597 array: None,
598 enumm: None,
599 },
600 Field {
601 name: "toie",
602 description: Some(
603 "trigger overrun interrupt enable",
604 ),
605 bit_offset: BitOffset::Regular(
606 RegularBitOffset {
607 offset: 14,
608 },
609 ),
610 bit_size: 1,
611 array: None,
612 enumm: None,
613 },
614 Field {
615 name: "lsm",
616 description: Some(
617 "Link step mode. First the (possible 1D/repeated) block transfer is executed as defined by the current internal register file until CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present. Secondly the next linked-list data structure is conditionally uploaded from memory as defined by CH[x].LLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1.",
618 ),
619 bit_offset: BitOffset::Regular(
620 RegularBitOffset {
621 offset: 16,
622 },
623 ),
624 bit_size: 1,
625 array: None,
626 enumm: Some(
627 "Lsm",
628 ),
629 },
630 Field {
631 name: "prio",
632 description: Some(
633 "priority level of the channel x LPDMA transfer versus others. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.",
634 ),
635 bit_offset: BitOffset::Regular(
636 RegularBitOffset {
637 offset: 22,
638 },
639 ),
640 bit_size: 2,
641 array: None,
642 enumm: Some(
643 "Prio",
644 ),
645 },
646 ],
647 },
648 FieldSet {
649 name: "ChFcr",
650 extends: None,
651 description: Some(
652 "LPDMA channel 7 flag clear register",
653 ),
654 bit_size: 32,
655 fields: &[
656 Field {
657 name: "tcf",
658 description: Some(
659 "transfer complete flag clear",
660 ),
661 bit_offset: BitOffset::Regular(
662 RegularBitOffset {
663 offset: 8,
664 },
665 ),
666 bit_size: 1,
667 array: None,
668 enumm: None,
669 },
670 Field {
671 name: "htf",
672 description: Some(
673 "half transfer flag clear",
674 ),
675 bit_offset: BitOffset::Regular(
676 RegularBitOffset {
677 offset: 9,
678 },
679 ),
680 bit_size: 1,
681 array: None,
682 enumm: None,
683 },
684 Field {
685 name: "dtef",
686 description: Some(
687 "data transfer error flag clear",
688 ),
689 bit_offset: BitOffset::Regular(
690 RegularBitOffset {
691 offset: 10,
692 },
693 ),
694 bit_size: 1,
695 array: None,
696 enumm: None,
697 },
698 Field {
699 name: "ulef",
700 description: Some(
701 "update link transfer error flag clear",
702 ),
703 bit_offset: BitOffset::Regular(
704 RegularBitOffset {
705 offset: 11,
706 },
707 ),
708 bit_size: 1,
709 array: None,
710 enumm: None,
711 },
712 Field {
713 name: "usef",
714 description: Some(
715 "user setting error flag clear",
716 ),
717 bit_offset: BitOffset::Regular(
718 RegularBitOffset {
719 offset: 12,
720 },
721 ),
722 bit_size: 1,
723 array: None,
724 enumm: None,
725 },
726 Field {
727 name: "suspf",
728 description: Some(
729 "completed suspension flag clear",
730 ),
731 bit_offset: BitOffset::Regular(
732 RegularBitOffset {
733 offset: 13,
734 },
735 ),
736 bit_size: 1,
737 array: None,
738 enumm: None,
739 },
740 Field {
741 name: "tof",
742 description: Some(
743 "trigger overrun flag clear",
744 ),
745 bit_offset: BitOffset::Regular(
746 RegularBitOffset {
747 offset: 14,
748 },
749 ),
750 bit_size: 1,
751 array: None,
752 enumm: None,
753 },
754 ],
755 },
756 FieldSet {
757 name: "ChLbar",
758 extends: None,
759 description: Some(
760 "LPDMA channel 14 linked-list base address register",
761 ),
762 bit_size: 32,
763 fields: &[
764 Field {
765 name: "lba",
766 description: Some(
767 "linked-list base address of LPDMA channel x",
768 ),
769 bit_offset: BitOffset::Regular(
770 RegularBitOffset {
771 offset: 16,
772 },
773 ),
774 bit_size: 16,
775 array: None,
776 enumm: None,
777 },
778 ],
779 },
780 FieldSet {
781 name: "ChLlr",
782 extends: None,
783 description: Some(
784 "LPDMA channel 15 alternate linked-list address register",
785 ),
786 bit_size: 32,
787 fields: &[
788 Field {
789 name: "la",
790 description: Some(
791 "pointer (16-bit low-significant address) to the next linked-list data structure. If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list LPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list LPDMA internal register file (CH[x].CTR1, CH[x].TR2, CH[x].BR1, CH[x].SAR, CH[x].DAR and CH[x].LLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored.",
792 ),
793 bit_offset: BitOffset::Regular(
794 RegularBitOffset {
795 offset: 2,
796 },
797 ),
798 bit_size: 14,
799 array: None,
800 enumm: None,
801 },
802 Field {
803 name: "ull",
804 description: Some(
805 "Update CH[x].LLR register from memory. This bit is used to control the update of CH[x].LLR from the memory during the link transfer.",
806 ),
807 bit_offset: BitOffset::Regular(
808 RegularBitOffset {
809 offset: 16,
810 },
811 ),
812 bit_size: 1,
813 array: None,
814 enumm: None,
815 },
816 Field {
817 name: "ub2",
818 description: Some(
819 "Update CH[x].BR2 from memory. This bit controls the update of CH[x].BR2 from the memory during the link transfer.",
820 ),
821 bit_offset: BitOffset::Regular(
822 RegularBitOffset {
823 offset: 25,
824 },
825 ),
826 bit_size: 1,
827 array: None,
828 enumm: None,
829 },
830 Field {
831 name: "ut3",
832 description: Some(
833 "Update CH[x].TR3 from memory. This bit controls the update of CH[x].TR3 from the memory during the link transfer.",
834 ),
835 bit_offset: BitOffset::Regular(
836 RegularBitOffset {
837 offset: 26,
838 },
839 ),
840 bit_size: 1,
841 array: None,
842 enumm: None,
843 },
844 Field {
845 name: "uda",
846 description: Some(
847 "Update CH[x].DAR register from memory. This bit is used to control the update of CH[x].DAR from the memory during the link transfer.",
848 ),
849 bit_offset: BitOffset::Regular(
850 RegularBitOffset {
851 offset: 27,
852 },
853 ),
854 bit_size: 1,
855 array: None,
856 enumm: None,
857 },
858 Field {
859 name: "usa",
860 description: Some(
861 "update CH[x].SAR from memory. This bit controls the update of CH[x].SAR from the memory during the link transfer.",
862 ),
863 bit_offset: BitOffset::Regular(
864 RegularBitOffset {
865 offset: 28,
866 },
867 ),
868 bit_size: 1,
869 array: None,
870 enumm: None,
871 },
872 Field {
873 name: "ub1",
874 description: Some(
875 "Update CH[x].BR1 from memory. This bit controls the update of CH[x].BR1 from the memory during the link transfer. If UB1 = 0 and if CH[x].LLR ≠ 0, the linked-list is not completed. CH[x].BR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer.",
876 ),
877 bit_offset: BitOffset::Regular(
878 RegularBitOffset {
879 offset: 29,
880 },
881 ),
882 bit_size: 1,
883 array: None,
884 enumm: None,
885 },
886 Field {
887 name: "ut2",
888 description: Some(
889 "Update CH[x].TR2 from memory. This bit controls the update of CH[x].TR2 from the memory during the link transfer.",
890 ),
891 bit_offset: BitOffset::Regular(
892 RegularBitOffset {
893 offset: 30,
894 },
895 ),
896 bit_size: 1,
897 array: None,
898 enumm: None,
899 },
900 Field {
901 name: "ut1",
902 description: Some(
903 "Update CH[x].TR1 from memory. This bit controls the update of CH[x].TR1 from the memory during the link transfer.",
904 ),
905 bit_offset: BitOffset::Regular(
906 RegularBitOffset {
907 offset: 31,
908 },
909 ),
910 bit_size: 1,
911 array: None,
912 enumm: None,
913 },
914 ],
915 },
916 FieldSet {
917 name: "ChSr",
918 extends: None,
919 description: Some(
920 "LPDMA channel 15 status register",
921 ),
922 bit_size: 32,
923 fields: &[
924 Field {
925 name: "idlef",
926 description: Some(
927 "idle flag. This idle flag is de-asserted by hardware when the channel is enabled (CH[x].CR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state).",
928 ),
929 bit_offset: BitOffset::Regular(
930 RegularBitOffset {
931 offset: 0,
932 },
933 ),
934 bit_size: 1,
935 array: None,
936 enumm: None,
937 },
938 Field {
939 name: "tcf",
940 description: Some(
941 "transfer complete flag. A transfer complete event is either a block transfer complete, a 2D/repeated block transfer complete, a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0]).",
942 ),
943 bit_offset: BitOffset::Regular(
944 RegularBitOffset {
945 offset: 8,
946 },
947 ),
948 bit_size: 1,
949 array: None,
950 enumm: None,
951 },
952 Field {
953 name: "htf",
954 description: Some(
955 "half transfer flag. An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0]). An half block transfer occurs when half of the bytes of the source block size (rounded up integer of CH[x].BR1.BNDT[15:0]/2) has been transferred to the destination. An half 2D/repeated block transfer occurs when half of the repeated blocks (rounded up integer of (CH[x].BR1.BRC[10:0]+1)/2)) has been transferred to the destination.",
956 ),
957 bit_offset: BitOffset::Regular(
958 RegularBitOffset {
959 offset: 9,
960 },
961 ),
962 bit_size: 1,
963 array: None,
964 enumm: None,
965 },
966 Field {
967 name: "dtef",
968 description: Some(
969 "data transfer error flag",
970 ),
971 bit_offset: BitOffset::Regular(
972 RegularBitOffset {
973 offset: 10,
974 },
975 ),
976 bit_size: 1,
977 array: None,
978 enumm: None,
979 },
980 Field {
981 name: "ulef",
982 description: Some(
983 "update link transfer error flag",
984 ),
985 bit_offset: BitOffset::Regular(
986 RegularBitOffset {
987 offset: 11,
988 },
989 ),
990 bit_size: 1,
991 array: None,
992 enumm: None,
993 },
994 Field {
995 name: "usef",
996 description: Some(
997 "user setting error flag",
998 ),
999 bit_offset: BitOffset::Regular(
1000 RegularBitOffset {
1001 offset: 12,
1002 },
1003 ),
1004 bit_size: 1,
1005 array: None,
1006 enumm: None,
1007 },
1008 Field {
1009 name: "suspf",
1010 description: Some(
1011 "completed suspension flag",
1012 ),
1013 bit_offset: BitOffset::Regular(
1014 RegularBitOffset {
1015 offset: 13,
1016 },
1017 ),
1018 bit_size: 1,
1019 array: None,
1020 enumm: None,
1021 },
1022 Field {
1023 name: "tof",
1024 description: Some(
1025 "trigger overrun flag",
1026 ),
1027 bit_offset: BitOffset::Regular(
1028 RegularBitOffset {
1029 offset: 14,
1030 },
1031 ),
1032 bit_size: 1,
1033 array: None,
1034 enumm: None,
1035 },
1036 ],
1037 },
1038 FieldSet {
1039 name: "ChTr1",
1040 extends: None,
1041 description: Some(
1042 "LPDMA channel 8 transfer register 1",
1043 ),
1044 bit_size: 32,
1045 fields: &[
1046 Field {
1047 name: "sdw",
1048 description: Some(
1049 "binary logarithm of the source data width of a burst in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and no transfer is issued. A source block size must be a multiple of the source data width (CH[x].BR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address CH[x].SAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued.",
1050 ),
1051 bit_offset: BitOffset::Regular(
1052 RegularBitOffset {
1053 offset: 0,
1054 },
1055 ),
1056 bit_size: 2,
1057 array: None,
1058 enumm: Some(
1059 "Dw",
1060 ),
1061 },
1062 Field {
1063 name: "sinc",
1064 description: Some(
1065 "source incrementing burst. The source address, pointed by CH[x].SAR, is kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer.",
1066 ),
1067 bit_offset: BitOffset::Regular(
1068 RegularBitOffset {
1069 offset: 3,
1070 },
1071 ),
1072 bit_size: 1,
1073 array: None,
1074 enumm: None,
1075 },
1076 Field {
1077 name: "pam",
1078 description: Some(
1079 "padding/alignment mode. If DDW[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination transfer is equal to the data width of a burst source transfer, these bits are ignored. Else: - Case 1: If destination data width > source data width. 1x: successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer. - Case 2: If destination data width < source data width. 1x: source data is FIFO queued and unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination. Note:",
1080 ),
1081 bit_offset: BitOffset::Regular(
1082 RegularBitOffset {
1083 offset: 11,
1084 },
1085 ),
1086 bit_size: 2,
1087 array: None,
1088 enumm: Some(
1089 "Pam",
1090 ),
1091 },
1092 Field {
1093 name: "ssec",
1094 description: Some(
1095 "security attribute of the LPDMA transfer from the source. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx =1 . A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer from the source is non-secure.",
1096 ),
1097 bit_offset: BitOffset::Regular(
1098 RegularBitOffset {
1099 offset: 15,
1100 },
1101 ),
1102 bit_size: 1,
1103 array: None,
1104 enumm: None,
1105 },
1106 Field {
1107 name: "ddw",
1108 description: Some(
1109 "binary logarithm of the destination data width of a burst, in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination burst transfer must have an aligned address with its data width (start address CH[x].DAR[2:0] and address offset CH[x].TR3.DAO[2:0], versus DDW[1:0]). Otherwise a user setting error is reported and no transfer is issued.",
1110 ),
1111 bit_offset: BitOffset::Regular(
1112 RegularBitOffset {
1113 offset: 16,
1114 },
1115 ),
1116 bit_size: 2,
1117 array: None,
1118 enumm: Some(
1119 "Dw",
1120 ),
1121 },
1122 Field {
1123 name: "dinc",
1124 description: Some(
1125 "destination incrementing burst. The destination address, pointed by CH[x].DAR, is kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer.",
1126 ),
1127 bit_offset: BitOffset::Regular(
1128 RegularBitOffset {
1129 offset: 19,
1130 },
1131 ),
1132 bit_size: 1,
1133 array: None,
1134 enumm: None,
1135 },
1136 Field {
1137 name: "dsec",
1138 description: Some(
1139 "security attribute of the LPDMA transfer to the destination. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx = 1. A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer to the destination is non-secure.",
1140 ),
1141 bit_offset: BitOffset::Regular(
1142 RegularBitOffset {
1143 offset: 31,
1144 },
1145 ),
1146 bit_size: 1,
1147 array: None,
1148 enumm: None,
1149 },
1150 ],
1151 },
1152 FieldSet {
1153 name: "ChTr2",
1154 extends: None,
1155 description: Some(
1156 "LPDMA channel 10 transfer register 2",
1157 ),
1158 bit_size: 32,
1159 fields: &[
1160 Field {
1161 name: "reqsel",
1162 description: Some(
1163 "LPDMA hardware request selection. These bits are ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per . The user must not assign a same input hardware request (same REQSEL[6:0] value) to different active LPDMA channels (CH[x].CR.EN = 1 and CH[x].TR2.SWREQ = 0 for these channels). LPDMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting.",
1164 ),
1165 bit_offset: BitOffset::Regular(
1166 RegularBitOffset {
1167 offset: 0,
1168 },
1169 ),
1170 bit_size: 7,
1171 array: None,
1172 enumm: None,
1173 },
1174 Field {
1175 name: "swreq",
1176 description: Some(
1177 "software request. This bit is internally taken into account when CH[x].CR.EN is asserted.",
1178 ),
1179 bit_offset: BitOffset::Regular(
1180 RegularBitOffset {
1181 offset: 9,
1182 },
1183 ),
1184 bit_size: 1,
1185 array: None,
1186 enumm: Some(
1187 "Swreq",
1188 ),
1189 },
1190 Field {
1191 name: "dreq",
1192 description: Some(
1193 "destination hardware request. This bit is ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else: Note:",
1194 ),
1195 bit_offset: BitOffset::Regular(
1196 RegularBitOffset {
1197 offset: 10,
1198 },
1199 ),
1200 bit_size: 1,
1201 array: None,
1202 enumm: Some(
1203 "Dreq",
1204 ),
1205 },
1206 Field {
1207 name: "breq",
1208 description: Some(
1209 "Block hardware request. If the channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else:",
1210 ),
1211 bit_offset: BitOffset::Regular(
1212 RegularBitOffset {
1213 offset: 11,
1214 },
1215 ),
1216 bit_size: 1,
1217 array: None,
1218 enumm: Some(
1219 "Breq",
1220 ),
1221 },
1222 Field {
1223 name: "trigm",
1224 description: Some(
1225 "trigger mode. These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (CH[x].CR.EN asserted) with TRIGPOL[1:0] = 00 or 11, these TRIGM[1:0] bits are ignored. Else, a LPDMA transfer is conditioned by at least one trigger hit: first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. – If the peripheral is programmed as a source (DREQ = 0) of the LLI data transfer, each programmed burst read is conditioned. – If the peripheral is programmed as a destination (DREQ = 1) of the LLI data transfer, each programmed burst write is conditioned. The first memory burst read of a (possibly 2D/repeated) block, also named as the first ready FIFO-based source burst, is gated by the occurrence of both the hardware request and the first trigger hit. The LPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 01 or respectively TRIGPOL[1:0] = 10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[5:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the CH[x].TR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized.memorized. A trigger overrun flag is reported (CH[x].SR.TOF =1 ), and an interrupt is generated if enabled (CH[x].CR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0] = 11 and (SWREQ =1 or (SWREQ = 0 and DREQ =0 )), the shortened burst transfer (by singles or/and by bursts of lower length) is conditioned once by the trigger. When the programmed destination burst is internally shortened by singles or/and by bursts of lower length (versus FIFO size, versus block size, 1-Kbyte boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0] = 11 and SWREQ = 0 and DREQ = 1), this shortened destination burst transfer is conditioned once by the trigger.",
1226 ),
1227 bit_offset: BitOffset::Regular(
1228 RegularBitOffset {
1229 offset: 14,
1230 },
1231 ),
1232 bit_size: 2,
1233 array: None,
1234 enumm: Some(
1235 "Trigm",
1236 ),
1237 },
1238 Field {
1239 name: "trigsel",
1240 description: Some(
1241 "trigger event input selection. These bits select the trigger event input of the LPDMA transfer (as per ), with an active trigger event if TRIGPOL[1:0] ≠ 00.",
1242 ),
1243 bit_offset: BitOffset::Regular(
1244 RegularBitOffset {
1245 offset: 16,
1246 },
1247 ),
1248 bit_size: 6,
1249 array: None,
1250 enumm: None,
1251 },
1252 Field {
1253 name: "trigpol",
1254 description: Some(
1255 "trigger event polarity. These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0].",
1256 ),
1257 bit_offset: BitOffset::Regular(
1258 RegularBitOffset {
1259 offset: 24,
1260 },
1261 ),
1262 bit_size: 2,
1263 array: None,
1264 enumm: Some(
1265 "Trigpol",
1266 ),
1267 },
1268 Field {
1269 name: "tcem",
1270 description: Some(
1271 "transfer complete event mode. These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1.",
1272 ),
1273 bit_offset: BitOffset::Regular(
1274 RegularBitOffset {
1275 offset: 30,
1276 },
1277 ),
1278 bit_size: 2,
1279 array: None,
1280 enumm: Some(
1281 "Tcem",
1282 ),
1283 },
1284 ],
1285 },
1286 FieldSet {
1287 name: "ChTr3",
1288 extends: None,
1289 description: Some(
1290 "LPDMA channel 14 transfer register 3",
1291 ),
1292 bit_size: 32,
1293 fields: &[
1294 Field {
1295 name: "sao",
1296 description: Some(
1297 "source address offset increment. The source address, pointed by CH[x].SAR, is incremented or decremented (depending on CH[x].BR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.SINC = 1). Note: A source address offset must be aligned with the programmed data width of a source burst (SAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional CH[x].TR3.SAO[12:0] is not applied.",
1298 ),
1299 bit_offset: BitOffset::Regular(
1300 RegularBitOffset {
1301 offset: 0,
1302 },
1303 ),
1304 bit_size: 13,
1305 array: None,
1306 enumm: None,
1307 },
1308 Field {
1309 name: "dao",
1310 description: Some(
1311 "destination address offset increment. The destination address, pointed by CH[x].DAR, is incremented or decremented (depending on CH[x].BR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.DINC = 1). Note: A destination address offset must be aligned with the programmed data width of a destination burst (DAO[2:0] versus CH[x].TR1.DDW[1:0]). Else, a user setting error is reported and no transfer is issued.",
1312 ),
1313 bit_offset: BitOffset::Regular(
1314 RegularBitOffset {
1315 offset: 16,
1316 },
1317 ),
1318 bit_size: 13,
1319 array: None,
1320 enumm: None,
1321 },
1322 ],
1323 },
1324 FieldSet {
1325 name: "Misr",
1326 extends: None,
1327 description: Some(
1328 "LPDMA secure masked interrupt status register",
1329 ),
1330 bit_size: 32,
1331 fields: &[
1332 Field {
1333 name: "mis",
1334 description: Some(
1335 "MIS0",
1336 ),
1337 bit_offset: BitOffset::Regular(
1338 RegularBitOffset {
1339 offset: 0,
1340 },
1341 ),
1342 bit_size: 1,
1343 array: Some(
1344 Array::Regular(
1345 RegularArray {
1346 len: 16,
1347 stride: 1,
1348 },
1349 ),
1350 ),
1351 enumm: None,
1352 },
1353 ],
1354 },
1355 FieldSet {
1356 name: "Privcfgr",
1357 extends: None,
1358 description: Some(
1359 "LPDMA privileged configuration register",
1360 ),
1361 bit_size: 32,
1362 fields: &[
1363 Field {
1364 name: "priv_",
1365 description: Some(
1366 "PRIV0",
1367 ),
1368 bit_offset: BitOffset::Regular(
1369 RegularBitOffset {
1370 offset: 0,
1371 },
1372 ),
1373 bit_size: 1,
1374 array: Some(
1375 Array::Regular(
1376 RegularArray {
1377 len: 16,
1378 stride: 1,
1379 },
1380 ),
1381 ),
1382 enumm: None,
1383 },
1384 ],
1385 },
1386 FieldSet {
1387 name: "Rcfglockr",
1388 extends: None,
1389 description: Some(
1390 "LPDMA configuration lock register",
1391 ),
1392 bit_size: 32,
1393 fields: &[
1394 Field {
1395 name: "lock",
1396 description: Some(
1397 "LOCK0",
1398 ),
1399 bit_offset: BitOffset::Regular(
1400 RegularBitOffset {
1401 offset: 0,
1402 },
1403 ),
1404 bit_size: 1,
1405 array: Some(
1406 Array::Regular(
1407 RegularArray {
1408 len: 16,
1409 stride: 1,
1410 },
1411 ),
1412 ),
1413 enumm: None,
1414 },
1415 ],
1416 },
1417 FieldSet {
1418 name: "Seccfgr",
1419 extends: None,
1420 description: Some(
1421 "LPDMA secure configuration register",
1422 ),
1423 bit_size: 32,
1424 fields: &[
1425 Field {
1426 name: "sec",
1427 description: Some(
1428 "SEC0",
1429 ),
1430 bit_offset: BitOffset::Regular(
1431 RegularBitOffset {
1432 offset: 0,
1433 },
1434 ),
1435 bit_size: 1,
1436 array: Some(
1437 Array::Regular(
1438 RegularArray {
1439 len: 16,
1440 stride: 1,
1441 },
1442 ),
1443 ),
1444 enumm: None,
1445 },
1446 ],
1447 },
1448 ],
1449 enums: &[
1450 Enum {
1451 name: "Breq",
1452 description: None,
1453 bit_size: 1,
1454 variants: &[
1455 EnumVariant {
1456 name: "BURST",
1457 description: Some(
1458 "the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level.",
1459 ),
1460 value: 0,
1461 },
1462 EnumVariant {
1463 name: "BLOCK",
1464 description: Some(
1465 "the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ).",
1466 ),
1467 value: 1,
1468 },
1469 ],
1470 },
1471 Enum {
1472 name: "Dec",
1473 description: None,
1474 bit_size: 1,
1475 variants: &[
1476 EnumVariant {
1477 name: "ADD",
1478 description: Some(
1479 "The address is incremented by the programmed offset.",
1480 ),
1481 value: 0,
1482 },
1483 EnumVariant {
1484 name: "SUBTRACT",
1485 description: Some(
1486 "The address is decremented by the programmed offset.",
1487 ),
1488 value: 1,
1489 },
1490 ],
1491 },
1492 Enum {
1493 name: "Dreq",
1494 description: None,
1495 bit_size: 1,
1496 variants: &[
1497 EnumVariant {
1498 name: "SOURCE_PERIPHERAL",
1499 description: Some(
1500 "selected hardware request driven by a source peripheral (request signal taken into account by the LPDMA transfer scheduler over the source/read port)",
1501 ),
1502 value: 0,
1503 },
1504 EnumVariant {
1505 name: "DESTINATION_PERIPHERAL",
1506 description: Some(
1507 "selected hardware request driven by a destination peripheral (request signal taken into account by the LPDMA transfer scheduler over the destination/write port)",
1508 ),
1509 value: 1,
1510 },
1511 ],
1512 },
1513 Enum {
1514 name: "Dw",
1515 description: None,
1516 bit_size: 2,
1517 variants: &[
1518 EnumVariant {
1519 name: "BYTE",
1520 description: Some(
1521 "byte",
1522 ),
1523 value: 0,
1524 },
1525 EnumVariant {
1526 name: "HALF_WORD",
1527 description: Some(
1528 "half-word (2 bytes)",
1529 ),
1530 value: 1,
1531 },
1532 EnumVariant {
1533 name: "WORD",
1534 description: Some(
1535 "word (4 bytes)",
1536 ),
1537 value: 2,
1538 },
1539 ],
1540 },
1541 Enum {
1542 name: "Lsm",
1543 description: None,
1544 bit_size: 1,
1545 variants: &[
1546 EnumVariant {
1547 name: "RUN_TO_COMPLETION",
1548 description: Some(
1549 "channel executed for the full linked-list and completed at the end of the last LLI (CH[x].LLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 =UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present.",
1550 ),
1551 value: 0,
1552 },
1553 EnumVariant {
1554 name: "LINK_STEP",
1555 description: Some(
1556 "channel executed once for the current LLI",
1557 ),
1558 value: 1,
1559 },
1560 ],
1561 },
1562 Enum {
1563 name: "Pam",
1564 description: None,
1565 bit_size: 2,
1566 variants: &[
1567 EnumVariant {
1568 name: "ZERO_EXTEND_OR_LEFT_TRUNCATE",
1569 description: Some(
1570 "If destination is wider: source data is transferred as right aligned, padded with 0s up to the destination data width\nIf source is wider: source data is transferred as right aligned, left-truncated down to the destination data width",
1571 ),
1572 value: 0,
1573 },
1574 EnumVariant {
1575 name: "SIGN_EXTEND_OR_RIGHT_TRUNCATE",
1576 description: Some(
1577 "If destination is wider: source data is transferred as right aligned, sign extended up to the destination data width\nIf source is wider: source data is transferred as left-aligned, right-truncated down to the destination data width",
1578 ),
1579 value: 1,
1580 },
1581 EnumVariant {
1582 name: "PACK",
1583 description: Some(
1584 "source data is FIFO queued and packed/unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination",
1585 ),
1586 value: 2,
1587 },
1588 ],
1589 },
1590 Enum {
1591 name: "Prio",
1592 description: None,
1593 bit_size: 2,
1594 variants: &[
1595 EnumVariant {
1596 name: "LOW_WITH_LOWH_WEIGHT",
1597 description: Some(
1598 "low priority, low weight",
1599 ),
1600 value: 0,
1601 },
1602 EnumVariant {
1603 name: "LOW_WITH_MID_WEIGHT",
1604 description: Some(
1605 "low priority, mid weight",
1606 ),
1607 value: 1,
1608 },
1609 EnumVariant {
1610 name: "LOW_WITH_HIGH_WEIGHT",
1611 description: Some(
1612 "low priority, high weight",
1613 ),
1614 value: 2,
1615 },
1616 EnumVariant {
1617 name: "HIGH",
1618 description: Some(
1619 "high priority",
1620 ),
1621 value: 3,
1622 },
1623 ],
1624 },
1625 Enum {
1626 name: "Swreq",
1627 description: None,
1628 bit_size: 1,
1629 variants: &[
1630 EnumVariant {
1631 name: "HARDWARE",
1632 description: Some(
1633 "no software request. The selected hardware request REQSEL[6:0] is taken into account.",
1634 ),
1635 value: 0,
1636 },
1637 EnumVariant {
1638 name: "SOFTWARE",
1639 description: Some(
1640 "software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored.",
1641 ),
1642 value: 1,
1643 },
1644 ],
1645 },
1646 Enum {
1647 name: "Tcem",
1648 description: None,
1649 bit_size: 2,
1650 variants: &[
1651 EnumVariant {
1652 name: "EACH_BLOCK",
1653 description: Some(
1654 "at block level (when CH[x].BR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block.",
1655 ),
1656 value: 0,
1657 },
1658 EnumVariant {
1659 name: "EACH2DBLOCK",
1660 description: Some(
1661 "channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when CH[x].BR1.BRC[10:0] = 0 and CH[x].BR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block.",
1662 ),
1663 value: 1,
1664 },
1665 EnumVariant {
1666 name: "EACH_LINKED_LIST_ITEM",
1667 description: Some(
1668 "at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer.",
1669 ),
1670 value: 2,
1671 },
1672 EnumVariant {
1673 name: "LAST_LINKED_LIST_ITEM",
1674 description: Some(
1675 "at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address CH[x].LLR.LA[15:2] to zero and clears all the CH[x].LLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated.",
1676 ),
1677 value: 3,
1678 },
1679 ],
1680 },
1681 Enum {
1682 name: "Trigm",
1683 description: None,
1684 bit_size: 2,
1685 variants: &[
1686 EnumVariant {
1687 name: "BLOCK",
1688 description: Some(
1689 "at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with CH[x].BR1.BRC[10:0] ≠ 0).",
1690 ),
1691 value: 0,
1692 },
1693 EnumVariant {
1694 name: "_2DBLOCK",
1695 description: Some(
1696 "channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the",
1697 ),
1698 value: 1,
1699 },
1700 EnumVariant {
1701 name: "LINKED_LIST_ITEM",
1702 description: Some(
1703 "at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned.",
1704 ),
1705 value: 2,
1706 },
1707 EnumVariant {
1708 name: "BURST",
1709 description: Some(
1710 "at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger.",
1711 ),
1712 value: 3,
1713 },
1714 ],
1715 },
1716 Enum {
1717 name: "Trigpol",
1718 description: None,
1719 bit_size: 2,
1720 variants: &[
1721 EnumVariant {
1722 name: "NONE",
1723 description: Some(
1724 "no trigger (masked trigger event)",
1725 ),
1726 value: 0,
1727 },
1728 EnumVariant {
1729 name: "RISING_EDGE",
1730 description: Some(
1731 "trigger on the rising edge",
1732 ),
1733 value: 1,
1734 },
1735 EnumVariant {
1736 name: "FALLING_EDGE",
1737 description: Some(
1738 "trigger on the falling edge",
1739 ),
1740 value: 2,
1741 },
1742 EnumVariant {
1743 name: "NONE_ALT",
1744 description: Some(
1745 "same as 00",
1746 ),
1747 value: 3,
1748 },
1749 ],
1750 },
1751 ],
1752};
1753