1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Lptim",
7 extends: Some(
8 "LPTIM_BASIC",
9 ),
10 description: Some(
11 "Low power timer with Output Compare",
12 ),
13 items: &[
14 BlockItem {
15 name: "isr",
16 description: Some(
17 "LPTIM interrupt and status register.",
18 ),
19 array: None,
20 byte_offset: 0x0,
21 inner: BlockItemInner::Register(
22 Register {
23 access: Access::ReadWrite,
24 bit_size: 32,
25 fieldset: Some(
26 "IsrAdv",
27 ),
28 },
29 ),
30 },
31 BlockItem {
32 name: "icr",
33 description: Some(
34 "LPTIM interrupt clear register.",
35 ),
36 array: None,
37 byte_offset: 0x4,
38 inner: BlockItemInner::Register(
39 Register {
40 access: Access::ReadWrite,
41 bit_size: 32,
42 fieldset: Some(
43 "IcrAdv",
44 ),
45 },
46 ),
47 },
48 BlockItem {
49 name: "dier",
50 description: Some(
51 "LPTIM interrupt enable register.",
52 ),
53 array: None,
54 byte_offset: 0x8,
55 inner: BlockItemInner::Register(
56 Register {
57 access: Access::ReadWrite,
58 bit_size: 32,
59 fieldset: Some(
60 "DierAdv",
61 ),
62 },
63 ),
64 },
65 BlockItem {
66 name: "cfgr",
67 description: Some(
68 "LPTIM configuration register.",
69 ),
70 array: None,
71 byte_offset: 0xc,
72 inner: BlockItemInner::Register(
73 Register {
74 access: Access::ReadWrite,
75 bit_size: 32,
76 fieldset: Some(
77 "Cfgr",
78 ),
79 },
80 ),
81 },
82 BlockItem {
83 name: "cr",
84 description: Some(
85 "LPTIM control register.",
86 ),
87 array: None,
88 byte_offset: 0x10,
89 inner: BlockItemInner::Register(
90 Register {
91 access: Access::ReadWrite,
92 bit_size: 32,
93 fieldset: Some(
94 "Cr",
95 ),
96 },
97 ),
98 },
99 BlockItem {
100 name: "ccr",
101 description: Some(
102 "LPTIM compare register 1.",
103 ),
104 array: Some(
105 Array::Regular(
106 RegularArray {
107 len: 2,
108 stride: 32,
109 },
110 ),
111 ),
112 byte_offset: 0x14,
113 inner: BlockItemInner::Register(
114 Register {
115 access: Access::ReadWrite,
116 bit_size: 32,
117 fieldset: Some(
118 "Ccr",
119 ),
120 },
121 ),
122 },
123 BlockItem {
124 name: "arr",
125 description: Some(
126 "LPTIM autoreload register.",
127 ),
128 array: None,
129 byte_offset: 0x18,
130 inner: BlockItemInner::Register(
131 Register {
132 access: Access::ReadWrite,
133 bit_size: 32,
134 fieldset: Some(
135 "Arr",
136 ),
137 },
138 ),
139 },
140 BlockItem {
141 name: "cnt",
142 description: Some(
143 "LPTIM counter register.",
144 ),
145 array: None,
146 byte_offset: 0x1c,
147 inner: BlockItemInner::Register(
148 Register {
149 access: Access::ReadWrite,
150 bit_size: 32,
151 fieldset: Some(
152 "Cnt",
153 ),
154 },
155 ),
156 },
157 BlockItem {
158 name: "cfgr2",
159 description: Some(
160 "LPTIM configuration register 2.",
161 ),
162 array: None,
163 byte_offset: 0x24,
164 inner: BlockItemInner::Register(
165 Register {
166 access: Access::ReadWrite,
167 bit_size: 32,
168 fieldset: Some(
169 "Cfgr2",
170 ),
171 },
172 ),
173 },
174 BlockItem {
175 name: "rcr",
176 description: Some(
177 "LPTIM repetition register.",
178 ),
179 array: None,
180 byte_offset: 0x28,
181 inner: BlockItemInner::Register(
182 Register {
183 access: Access::ReadWrite,
184 bit_size: 32,
185 fieldset: Some(
186 "Rcr",
187 ),
188 },
189 ),
190 },
191 BlockItem {
192 name: "ccmr",
193 description: Some(
194 "LPTIM capture/compare mode register 1.",
195 ),
196 array: Some(
197 Array::Regular(
198 RegularArray {
199 len: 1,
200 stride: 1,
201 },
202 ),
203 ),
204 byte_offset: 0x2c,
205 inner: BlockItemInner::Register(
206 Register {
207 access: Access::ReadWrite,
208 bit_size: 32,
209 fieldset: Some(
210 "Ccmr",
211 ),
212 },
213 ),
214 },
215 ],
216 },
217 Block {
218 name: "LptimBasic",
219 extends: None,
220 description: Some(
221 "Low power timer with Output Compare",
222 ),
223 items: &[
224 BlockItem {
225 name: "isr",
226 description: Some(
227 "LPTIM interrupt and status register.",
228 ),
229 array: None,
230 byte_offset: 0x0,
231 inner: BlockItemInner::Register(
232 Register {
233 access: Access::ReadWrite,
234 bit_size: 32,
235 fieldset: Some(
236 "IsrBasic",
237 ),
238 },
239 ),
240 },
241 BlockItem {
242 name: "icr",
243 description: Some(
244 "LPTIM interrupt clear register.",
245 ),
246 array: None,
247 byte_offset: 0x4,
248 inner: BlockItemInner::Register(
249 Register {
250 access: Access::ReadWrite,
251 bit_size: 32,
252 fieldset: Some(
253 "IcrBasic",
254 ),
255 },
256 ),
257 },
258 BlockItem {
259 name: "dier",
260 description: Some(
261 "LPTIM interrupt enable register.",
262 ),
263 array: None,
264 byte_offset: 0x8,
265 inner: BlockItemInner::Register(
266 Register {
267 access: Access::ReadWrite,
268 bit_size: 32,
269 fieldset: Some(
270 "DierBasic",
271 ),
272 },
273 ),
274 },
275 BlockItem {
276 name: "cfgr",
277 description: Some(
278 "LPTIM configuration register.",
279 ),
280 array: None,
281 byte_offset: 0xc,
282 inner: BlockItemInner::Register(
283 Register {
284 access: Access::ReadWrite,
285 bit_size: 32,
286 fieldset: Some(
287 "Cfgr",
288 ),
289 },
290 ),
291 },
292 BlockItem {
293 name: "cr",
294 description: Some(
295 "LPTIM control register.",
296 ),
297 array: None,
298 byte_offset: 0x10,
299 inner: BlockItemInner::Register(
300 Register {
301 access: Access::ReadWrite,
302 bit_size: 32,
303 fieldset: Some(
304 "Cr",
305 ),
306 },
307 ),
308 },
309 BlockItem {
310 name: "ccr",
311 description: Some(
312 "LPTIM compare register 1.",
313 ),
314 array: Some(
315 Array::Regular(
316 RegularArray {
317 len: 1,
318 stride: 32,
319 },
320 ),
321 ),
322 byte_offset: 0x14,
323 inner: BlockItemInner::Register(
324 Register {
325 access: Access::ReadWrite,
326 bit_size: 32,
327 fieldset: Some(
328 "Ccr",
329 ),
330 },
331 ),
332 },
333 BlockItem {
334 name: "arr",
335 description: Some(
336 "LPTIM autoreload register.",
337 ),
338 array: None,
339 byte_offset: 0x18,
340 inner: BlockItemInner::Register(
341 Register {
342 access: Access::ReadWrite,
343 bit_size: 32,
344 fieldset: Some(
345 "Arr",
346 ),
347 },
348 ),
349 },
350 BlockItem {
351 name: "cnt",
352 description: Some(
353 "LPTIM counter register.",
354 ),
355 array: None,
356 byte_offset: 0x1c,
357 inner: BlockItemInner::Register(
358 Register {
359 access: Access::ReadWrite,
360 bit_size: 32,
361 fieldset: Some(
362 "Cnt",
363 ),
364 },
365 ),
366 },
367 BlockItem {
368 name: "cfgr2",
369 description: Some(
370 "LPTIM configuration register 2.",
371 ),
372 array: None,
373 byte_offset: 0x24,
374 inner: BlockItemInner::Register(
375 Register {
376 access: Access::ReadWrite,
377 bit_size: 32,
378 fieldset: Some(
379 "Cfgr2",
380 ),
381 },
382 ),
383 },
384 BlockItem {
385 name: "rcr",
386 description: Some(
387 "LPTIM repetition register.",
388 ),
389 array: None,
390 byte_offset: 0x28,
391 inner: BlockItemInner::Register(
392 Register {
393 access: Access::ReadWrite,
394 bit_size: 32,
395 fieldset: Some(
396 "Rcr",
397 ),
398 },
399 ),
400 },
401 ],
402 },
403 ],
404 fieldsets: &[
405 FieldSet {
406 name: "Arr",
407 extends: None,
408 description: Some(
409 "LPTIM autoreload register.",
410 ),
411 bit_size: 32,
412 fields: &[
413 Field {
414 name: "arr",
415 description: Some(
416 "Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value.",
417 ),
418 bit_offset: BitOffset::Regular(
419 RegularBitOffset {
420 offset: 0,
421 },
422 ),
423 bit_size: 16,
424 array: None,
425 enumm: None,
426 },
427 ],
428 },
429 FieldSet {
430 name: "Ccmr",
431 extends: None,
432 description: Some(
433 "LPTIM capture/compare mode register 1.",
434 ),
435 bit_size: 32,
436 fields: &[
437 Field {
438 name: "ccsel",
439 description: Some(
440 "Capture/compare 1 selection This bitfield defines the direction of the channel input (capture) or output mode.",
441 ),
442 bit_offset: BitOffset::Regular(
443 RegularBitOffset {
444 offset: 0,
445 },
446 ),
447 bit_size: 1,
448 array: Some(
449 Array::Regular(
450 RegularArray {
451 len: 2,
452 stride: 16,
453 },
454 ),
455 ),
456 enumm: Some(
457 "Ccsel",
458 ),
459 },
460 Field {
461 name: "cce",
462 description: Some(
463 "Capture/compare 1 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not.",
464 ),
465 bit_offset: BitOffset::Regular(
466 RegularBitOffset {
467 offset: 1,
468 },
469 ),
470 bit_size: 1,
471 array: Some(
472 Array::Regular(
473 RegularArray {
474 len: 2,
475 stride: 16,
476 },
477 ),
478 ),
479 enumm: None,
480 },
481 Field {
482 name: "ccp_input",
483 description: Some(
484 "Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations.",
485 ),
486 bit_offset: BitOffset::Regular(
487 RegularBitOffset {
488 offset: 2,
489 },
490 ),
491 bit_size: 2,
492 array: Some(
493 Array::Regular(
494 RegularArray {
495 len: 2,
496 stride: 16,
497 },
498 ),
499 ),
500 enumm: Some(
501 "CcpInput",
502 ),
503 },
504 Field {
505 name: "ccp_output",
506 description: Some(
507 "Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations.",
508 ),
509 bit_offset: BitOffset::Regular(
510 RegularBitOffset {
511 offset: 2,
512 },
513 ),
514 bit_size: 2,
515 array: Some(
516 Array::Regular(
517 RegularArray {
518 len: 2,
519 stride: 16,
520 },
521 ),
522 ),
523 enumm: Some(
524 "CcpOutput",
525 ),
526 },
527 Field {
528 name: "icpsc",
529 description: Some(
530 "Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1).",
531 ),
532 bit_offset: BitOffset::Regular(
533 RegularBitOffset {
534 offset: 8,
535 },
536 ),
537 bit_size: 2,
538 array: Some(
539 Array::Regular(
540 RegularArray {
541 len: 2,
542 stride: 16,
543 },
544 ),
545 ),
546 enumm: Some(
547 "Filter",
548 ),
549 },
550 Field {
551 name: "icf",
552 description: Some(
553 "Input capture 1 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.",
554 ),
555 bit_offset: BitOffset::Regular(
556 RegularBitOffset {
557 offset: 12,
558 },
559 ),
560 bit_size: 2,
561 array: Some(
562 Array::Regular(
563 RegularArray {
564 len: 2,
565 stride: 16,
566 },
567 ),
568 ),
569 enumm: Some(
570 "Filter",
571 ),
572 },
573 ],
574 },
575 FieldSet {
576 name: "Ccr",
577 extends: None,
578 description: Some(
579 "LPTIM compare register 1.",
580 ),
581 bit_size: 32,
582 fields: &[
583 Field {
584 name: "ccr",
585 description: Some(
586 "Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.",
587 ),
588 bit_offset: BitOffset::Regular(
589 RegularBitOffset {
590 offset: 0,
591 },
592 ),
593 bit_size: 16,
594 array: None,
595 enumm: None,
596 },
597 ],
598 },
599 FieldSet {
600 name: "Cfgr",
601 extends: None,
602 description: Some(
603 "LPTIM configuration register.",
604 ),
605 bit_size: 32,
606 fields: &[
607 Field {
608 name: "cksel",
609 description: Some(
610 "Clock selector The CKSEL bit selects which clock source the LPTIM uses:.",
611 ),
612 bit_offset: BitOffset::Regular(
613 RegularBitOffset {
614 offset: 0,
615 },
616 ),
617 bit_size: 1,
618 array: None,
619 enumm: Some(
620 "ClockSource",
621 ),
622 },
623 Field {
624 name: "ckpol",
625 description: Some(
626 "Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.",
627 ),
628 bit_offset: BitOffset::Regular(
629 RegularBitOffset {
630 offset: 1,
631 },
632 ),
633 bit_size: 2,
634 array: None,
635 enumm: Some(
636 "Ckpol",
637 ),
638 },
639 Field {
640 name: "ckflt",
641 description: Some(
642 "Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.",
643 ),
644 bit_offset: BitOffset::Regular(
645 RegularBitOffset {
646 offset: 3,
647 },
648 ),
649 bit_size: 2,
650 array: None,
651 enumm: Some(
652 "Filter",
653 ),
654 },
655 Field {
656 name: "trgflt",
657 description: Some(
658 "Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature.",
659 ),
660 bit_offset: BitOffset::Regular(
661 RegularBitOffset {
662 offset: 6,
663 },
664 ),
665 bit_size: 2,
666 array: None,
667 enumm: Some(
668 "Filter",
669 ),
670 },
671 Field {
672 name: "presc",
673 description: Some(
674 "Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:.",
675 ),
676 bit_offset: BitOffset::Regular(
677 RegularBitOffset {
678 offset: 9,
679 },
680 ),
681 bit_size: 3,
682 array: None,
683 enumm: Some(
684 "Presc",
685 ),
686 },
687 Field {
688 name: "trigsel",
689 description: Some(
690 "Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.",
691 ),
692 bit_offset: BitOffset::Regular(
693 RegularBitOffset {
694 offset: 13,
695 },
696 ),
697 bit_size: 3,
698 array: None,
699 enumm: None,
700 },
701 Field {
702 name: "trigen",
703 description: Some(
704 "Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:.",
705 ),
706 bit_offset: BitOffset::Regular(
707 RegularBitOffset {
708 offset: 17,
709 },
710 ),
711 bit_size: 2,
712 array: None,
713 enumm: Some(
714 "Trigen",
715 ),
716 },
717 Field {
718 name: "timout",
719 description: Some(
720 "Timeout enable The TIMOUT bit controls the Timeout feature.",
721 ),
722 bit_offset: BitOffset::Regular(
723 RegularBitOffset {
724 offset: 19,
725 },
726 ),
727 bit_size: 1,
728 array: None,
729 enumm: None,
730 },
731 Field {
732 name: "wave",
733 description: Some(
734 "Waveform shape The WAVE bit controls the output shape.",
735 ),
736 bit_offset: BitOffset::Regular(
737 RegularBitOffset {
738 offset: 20,
739 },
740 ),
741 bit_size: 1,
742 array: None,
743 enumm: None,
744 },
745 Field {
746 name: "wavpol",
747 description: Some(
748 "Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.",
749 ),
750 bit_offset: BitOffset::Regular(
751 RegularBitOffset {
752 offset: 21,
753 },
754 ),
755 bit_size: 1,
756 array: None,
757 enumm: Some(
758 "Wavpol",
759 ),
760 },
761 Field {
762 name: "preload",
763 description: Some(
764 "Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality.",
765 ),
766 bit_offset: BitOffset::Regular(
767 RegularBitOffset {
768 offset: 22,
769 },
770 ),
771 bit_size: 1,
772 array: None,
773 enumm: None,
774 },
775 Field {
776 name: "countmode",
777 description: Some(
778 "counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:.",
779 ),
780 bit_offset: BitOffset::Regular(
781 RegularBitOffset {
782 offset: 23,
783 },
784 ),
785 bit_size: 1,
786 array: None,
787 enumm: Some(
788 "ClockSource",
789 ),
790 },
791 Field {
792 name: "enc",
793 description: Some(
794 "Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.",
795 ),
796 bit_offset: BitOffset::Regular(
797 RegularBitOffset {
798 offset: 24,
799 },
800 ),
801 bit_size: 1,
802 array: None,
803 enumm: None,
804 },
805 ],
806 },
807 FieldSet {
808 name: "Cfgr2",
809 extends: None,
810 description: Some(
811 "LPTIM configuration register 2.",
812 ),
813 bit_size: 32,
814 fields: &[
815 Field {
816 name: "insel",
817 description: Some(
818 "LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to.",
819 ),
820 bit_offset: BitOffset::Regular(
821 RegularBitOffset {
822 offset: 0,
823 },
824 ),
825 bit_size: 2,
826 array: Some(
827 Array::Regular(
828 RegularArray {
829 len: 2,
830 stride: 4,
831 },
832 ),
833 ),
834 enumm: None,
835 },
836 Field {
837 name: "icsel",
838 description: Some(
839 "LPTIM input capture 1 selection The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture 1 to one of the available inputs. For connection details refer to.",
840 ),
841 bit_offset: BitOffset::Regular(
842 RegularBitOffset {
843 offset: 16,
844 },
845 ),
846 bit_size: 2,
847 array: Some(
848 Array::Regular(
849 RegularArray {
850 len: 2,
851 stride: 4,
852 },
853 ),
854 ),
855 enumm: None,
856 },
857 ],
858 },
859 FieldSet {
860 name: "Cnt",
861 extends: None,
862 description: Some(
863 "LPTIM counter register.",
864 ),
865 bit_size: 32,
866 fields: &[
867 Field {
868 name: "cnt",
869 description: Some(
870 "Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.",
871 ),
872 bit_offset: BitOffset::Regular(
873 RegularBitOffset {
874 offset: 0,
875 },
876 ),
877 bit_size: 16,
878 array: None,
879 enumm: None,
880 },
881 ],
882 },
883 FieldSet {
884 name: "Cr",
885 extends: None,
886 description: Some(
887 "LPTIM control register.",
888 ),
889 bit_size: 32,
890 fields: &[
891 Field {
892 name: "enable",
893 description: Some(
894 "LPTIM enable The ENABLE bit is set and cleared by software.",
895 ),
896 bit_offset: BitOffset::Regular(
897 RegularBitOffset {
898 offset: 0,
899 },
900 ),
901 bit_size: 1,
902 array: None,
903 enumm: None,
904 },
905 Field {
906 name: "sngstrt",
907 description: Some(
908 "LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware.",
909 ),
910 bit_offset: BitOffset::Regular(
911 RegularBitOffset {
912 offset: 1,
913 },
914 ),
915 bit_size: 1,
916 array: None,
917 enumm: None,
918 },
919 Field {
920 name: "cntstrt",
921 description: Some(
922 "Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware.",
923 ),
924 bit_offset: BitOffset::Regular(
925 RegularBitOffset {
926 offset: 2,
927 },
928 ),
929 bit_size: 1,
930 array: None,
931 enumm: None,
932 },
933 Field {
934 name: "countrst",
935 description: Some(
936 "Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'.",
937 ),
938 bit_offset: BitOffset::Regular(
939 RegularBitOffset {
940 offset: 3,
941 },
942 ),
943 bit_size: 1,
944 array: None,
945 enumm: None,
946 },
947 Field {
948 name: "rstare",
949 description: Some(
950 "Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled.",
951 ),
952 bit_offset: BitOffset::Regular(
953 RegularBitOffset {
954 offset: 4,
955 },
956 ),
957 bit_size: 1,
958 array: None,
959 enumm: None,
960 },
961 ],
962 },
963 FieldSet {
964 name: "DierAdv",
965 extends: Some(
966 "DIER_BASIC",
967 ),
968 description: Some(
969 "LPTIM interrupt enable register.",
970 ),
971 bit_size: 32,
972 fields: &[
973 Field {
974 name: "ccie",
975 description: Some(
976 "Capture/compare 1 interrupt enable.",
977 ),
978 bit_offset: BitOffset::Regular(
979 RegularBitOffset {
980 offset: 0,
981 },
982 ),
983 bit_size: 1,
984 array: Some(
985 Array::Regular(
986 RegularArray {
987 len: 2,
988 stride: 9,
989 },
990 ),
991 ),
992 enumm: None,
993 },
994 Field {
995 name: "arrmie",
996 description: Some(
997 "Autoreload match Interrupt Enable.",
998 ),
999 bit_offset: BitOffset::Regular(
1000 RegularBitOffset {
1001 offset: 1,
1002 },
1003 ),
1004 bit_size: 1,
1005 array: None,
1006 enumm: None,
1007 },
1008 Field {
1009 name: "exttrigie",
1010 description: Some(
1011 "External trigger valid edge Interrupt Enable.",
1012 ),
1013 bit_offset: BitOffset::Regular(
1014 RegularBitOffset {
1015 offset: 2,
1016 },
1017 ),
1018 bit_size: 1,
1019 array: None,
1020 enumm: None,
1021 },
1022 Field {
1023 name: "cmpokie",
1024 description: Some(
1025 "Compare register 1 update OK interrupt enable.",
1026 ),
1027 bit_offset: BitOffset::Regular(
1028 RegularBitOffset {
1029 offset: 3,
1030 },
1031 ),
1032 bit_size: 1,
1033 array: Some(
1034 Array::Regular(
1035 RegularArray {
1036 len: 2,
1037 stride: 16,
1038 },
1039 ),
1040 ),
1041 enumm: None,
1042 },
1043 Field {
1044 name: "arrokie",
1045 description: Some(
1046 "Autoreload register update OK Interrupt Enable.",
1047 ),
1048 bit_offset: BitOffset::Regular(
1049 RegularBitOffset {
1050 offset: 4,
1051 },
1052 ),
1053 bit_size: 1,
1054 array: None,
1055 enumm: None,
1056 },
1057 Field {
1058 name: "upie",
1059 description: Some(
1060 "Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.",
1061 ),
1062 bit_offset: BitOffset::Regular(
1063 RegularBitOffset {
1064 offset: 5,
1065 },
1066 ),
1067 bit_size: 1,
1068 array: None,
1069 enumm: None,
1070 },
1071 Field {
1072 name: "downie",
1073 description: Some(
1074 "Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.",
1075 ),
1076 bit_offset: BitOffset::Regular(
1077 RegularBitOffset {
1078 offset: 6,
1079 },
1080 ),
1081 bit_size: 1,
1082 array: None,
1083 enumm: None,
1084 },
1085 Field {
1086 name: "ueie",
1087 description: Some(
1088 "Update event interrupt enable.",
1089 ),
1090 bit_offset: BitOffset::Regular(
1091 RegularBitOffset {
1092 offset: 7,
1093 },
1094 ),
1095 bit_size: 1,
1096 array: None,
1097 enumm: None,
1098 },
1099 Field {
1100 name: "repokie",
1101 description: Some(
1102 "Repetition register update OK interrupt Enable.",
1103 ),
1104 bit_offset: BitOffset::Regular(
1105 RegularBitOffset {
1106 offset: 8,
1107 },
1108 ),
1109 bit_size: 1,
1110 array: None,
1111 enumm: None,
1112 },
1113 Field {
1114 name: "ccoie",
1115 description: Some(
1116 "Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.",
1117 ),
1118 bit_offset: BitOffset::Regular(
1119 RegularBitOffset {
1120 offset: 12,
1121 },
1122 ),
1123 bit_size: 1,
1124 array: Some(
1125 Array::Regular(
1126 RegularArray {
1127 len: 2,
1128 stride: 1,
1129 },
1130 ),
1131 ),
1132 enumm: None,
1133 },
1134 Field {
1135 name: "ccde",
1136 description: Some(
1137 "Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.",
1138 ),
1139 bit_offset: BitOffset::Regular(
1140 RegularBitOffset {
1141 offset: 16,
1142 },
1143 ),
1144 bit_size: 1,
1145 array: Some(
1146 Array::Regular(
1147 RegularArray {
1148 len: 2,
1149 stride: 9,
1150 },
1151 ),
1152 ),
1153 enumm: None,
1154 },
1155 ],
1156 },
1157 FieldSet {
1158 name: "DierBasic",
1159 extends: None,
1160 description: Some(
1161 "LPTIM interrupt enable register.",
1162 ),
1163 bit_size: 32,
1164 fields: &[
1165 Field {
1166 name: "ccie",
1167 description: Some(
1168 "Capture/compare 1 interrupt enable.",
1169 ),
1170 bit_offset: BitOffset::Regular(
1171 RegularBitOffset {
1172 offset: 0,
1173 },
1174 ),
1175 bit_size: 1,
1176 array: Some(
1177 Array::Regular(
1178 RegularArray {
1179 len: 1,
1180 stride: 9,
1181 },
1182 ),
1183 ),
1184 enumm: None,
1185 },
1186 Field {
1187 name: "arrmie",
1188 description: Some(
1189 "Autoreload match Interrupt Enable.",
1190 ),
1191 bit_offset: BitOffset::Regular(
1192 RegularBitOffset {
1193 offset: 1,
1194 },
1195 ),
1196 bit_size: 1,
1197 array: None,
1198 enumm: None,
1199 },
1200 Field {
1201 name: "exttrigie",
1202 description: Some(
1203 "External trigger valid edge Interrupt Enable.",
1204 ),
1205 bit_offset: BitOffset::Regular(
1206 RegularBitOffset {
1207 offset: 2,
1208 },
1209 ),
1210 bit_size: 1,
1211 array: None,
1212 enumm: None,
1213 },
1214 Field {
1215 name: "cmpokie",
1216 description: Some(
1217 "Compare register 1 update OK interrupt enable.",
1218 ),
1219 bit_offset: BitOffset::Regular(
1220 RegularBitOffset {
1221 offset: 3,
1222 },
1223 ),
1224 bit_size: 1,
1225 array: Some(
1226 Array::Regular(
1227 RegularArray {
1228 len: 1,
1229 stride: 16,
1230 },
1231 ),
1232 ),
1233 enumm: None,
1234 },
1235 Field {
1236 name: "arrokie",
1237 description: Some(
1238 "Autoreload register update OK Interrupt Enable.",
1239 ),
1240 bit_offset: BitOffset::Regular(
1241 RegularBitOffset {
1242 offset: 4,
1243 },
1244 ),
1245 bit_size: 1,
1246 array: None,
1247 enumm: None,
1248 },
1249 Field {
1250 name: "upie",
1251 description: Some(
1252 "Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.",
1253 ),
1254 bit_offset: BitOffset::Regular(
1255 RegularBitOffset {
1256 offset: 5,
1257 },
1258 ),
1259 bit_size: 1,
1260 array: None,
1261 enumm: None,
1262 },
1263 Field {
1264 name: "downie",
1265 description: Some(
1266 "Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.",
1267 ),
1268 bit_offset: BitOffset::Regular(
1269 RegularBitOffset {
1270 offset: 6,
1271 },
1272 ),
1273 bit_size: 1,
1274 array: None,
1275 enumm: None,
1276 },
1277 Field {
1278 name: "ueie",
1279 description: Some(
1280 "Update event interrupt enable.",
1281 ),
1282 bit_offset: BitOffset::Regular(
1283 RegularBitOffset {
1284 offset: 7,
1285 },
1286 ),
1287 bit_size: 1,
1288 array: None,
1289 enumm: None,
1290 },
1291 Field {
1292 name: "repokie",
1293 description: Some(
1294 "Repetition register update OK interrupt Enable.",
1295 ),
1296 bit_offset: BitOffset::Regular(
1297 RegularBitOffset {
1298 offset: 8,
1299 },
1300 ),
1301 bit_size: 1,
1302 array: None,
1303 enumm: None,
1304 },
1305 ],
1306 },
1307 FieldSet {
1308 name: "IcrAdv",
1309 extends: Some(
1310 "ICR_BASIC",
1311 ),
1312 description: Some(
1313 "LPTIM interrupt clear register.",
1314 ),
1315 bit_size: 32,
1316 fields: &[
1317 Field {
1318 name: "cccf",
1319 description: Some(
1320 "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.",
1321 ),
1322 bit_offset: BitOffset::Regular(
1323 RegularBitOffset {
1324 offset: 0,
1325 },
1326 ),
1327 bit_size: 1,
1328 array: Some(
1329 Array::Regular(
1330 RegularArray {
1331 len: 2,
1332 stride: 9,
1333 },
1334 ),
1335 ),
1336 enumm: None,
1337 },
1338 Field {
1339 name: "arrmcf",
1340 description: Some(
1341 "Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.",
1342 ),
1343 bit_offset: BitOffset::Regular(
1344 RegularBitOffset {
1345 offset: 1,
1346 },
1347 ),
1348 bit_size: 1,
1349 array: None,
1350 enumm: None,
1351 },
1352 Field {
1353 name: "exttrigcf",
1354 description: Some(
1355 "External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.",
1356 ),
1357 bit_offset: BitOffset::Regular(
1358 RegularBitOffset {
1359 offset: 2,
1360 },
1361 ),
1362 bit_size: 1,
1363 array: None,
1364 enumm: None,
1365 },
1366 Field {
1367 name: "cmpokcf",
1368 description: Some(
1369 "Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.",
1370 ),
1371 bit_offset: BitOffset::Regular(
1372 RegularBitOffset {
1373 offset: 3,
1374 },
1375 ),
1376 bit_size: 1,
1377 array: Some(
1378 Array::Regular(
1379 RegularArray {
1380 len: 2,
1381 stride: 16,
1382 },
1383 ),
1384 ),
1385 enumm: None,
1386 },
1387 Field {
1388 name: "arrokcf",
1389 description: Some(
1390 "Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.",
1391 ),
1392 bit_offset: BitOffset::Regular(
1393 RegularBitOffset {
1394 offset: 4,
1395 },
1396 ),
1397 bit_size: 1,
1398 array: None,
1399 enumm: None,
1400 },
1401 Field {
1402 name: "upcf",
1403 description: Some(
1404 "Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.",
1405 ),
1406 bit_offset: BitOffset::Regular(
1407 RegularBitOffset {
1408 offset: 5,
1409 },
1410 ),
1411 bit_size: 1,
1412 array: None,
1413 enumm: None,
1414 },
1415 Field {
1416 name: "downcf",
1417 description: Some(
1418 "Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.",
1419 ),
1420 bit_offset: BitOffset::Regular(
1421 RegularBitOffset {
1422 offset: 6,
1423 },
1424 ),
1425 bit_size: 1,
1426 array: None,
1427 enumm: None,
1428 },
1429 Field {
1430 name: "uecf",
1431 description: Some(
1432 "Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register.",
1433 ),
1434 bit_offset: BitOffset::Regular(
1435 RegularBitOffset {
1436 offset: 7,
1437 },
1438 ),
1439 bit_size: 1,
1440 array: None,
1441 enumm: None,
1442 },
1443 Field {
1444 name: "repokcf",
1445 description: Some(
1446 "Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register.",
1447 ),
1448 bit_offset: BitOffset::Regular(
1449 RegularBitOffset {
1450 offset: 8,
1451 },
1452 ),
1453 bit_size: 1,
1454 array: None,
1455 enumm: None,
1456 },
1457 Field {
1458 name: "ccocf",
1459 description: Some(
1460 "Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.",
1461 ),
1462 bit_offset: BitOffset::Regular(
1463 RegularBitOffset {
1464 offset: 12,
1465 },
1466 ),
1467 bit_size: 1,
1468 array: Some(
1469 Array::Regular(
1470 RegularArray {
1471 len: 2,
1472 stride: 1,
1473 },
1474 ),
1475 ),
1476 enumm: None,
1477 },
1478 Field {
1479 name: "dierokcf",
1480 description: Some(
1481 "Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register.",
1482 ),
1483 bit_offset: BitOffset::Regular(
1484 RegularBitOffset {
1485 offset: 24,
1486 },
1487 ),
1488 bit_size: 1,
1489 array: None,
1490 enumm: None,
1491 },
1492 ],
1493 },
1494 FieldSet {
1495 name: "IcrBasic",
1496 extends: None,
1497 description: Some(
1498 "LPTIM interrupt clear register.",
1499 ),
1500 bit_size: 32,
1501 fields: &[
1502 Field {
1503 name: "cccf",
1504 description: Some(
1505 "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.",
1506 ),
1507 bit_offset: BitOffset::Regular(
1508 RegularBitOffset {
1509 offset: 0,
1510 },
1511 ),
1512 bit_size: 1,
1513 array: Some(
1514 Array::Regular(
1515 RegularArray {
1516 len: 1,
1517 stride: 9,
1518 },
1519 ),
1520 ),
1521 enumm: None,
1522 },
1523 Field {
1524 name: "arrmcf",
1525 description: Some(
1526 "Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.",
1527 ),
1528 bit_offset: BitOffset::Regular(
1529 RegularBitOffset {
1530 offset: 1,
1531 },
1532 ),
1533 bit_size: 1,
1534 array: None,
1535 enumm: None,
1536 },
1537 Field {
1538 name: "exttrigcf",
1539 description: Some(
1540 "External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.",
1541 ),
1542 bit_offset: BitOffset::Regular(
1543 RegularBitOffset {
1544 offset: 2,
1545 },
1546 ),
1547 bit_size: 1,
1548 array: None,
1549 enumm: None,
1550 },
1551 Field {
1552 name: "cmpokcf",
1553 description: Some(
1554 "Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.",
1555 ),
1556 bit_offset: BitOffset::Regular(
1557 RegularBitOffset {
1558 offset: 3,
1559 },
1560 ),
1561 bit_size: 1,
1562 array: Some(
1563 Array::Regular(
1564 RegularArray {
1565 len: 1,
1566 stride: 16,
1567 },
1568 ),
1569 ),
1570 enumm: None,
1571 },
1572 Field {
1573 name: "arrokcf",
1574 description: Some(
1575 "Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.",
1576 ),
1577 bit_offset: BitOffset::Regular(
1578 RegularBitOffset {
1579 offset: 4,
1580 },
1581 ),
1582 bit_size: 1,
1583 array: None,
1584 enumm: None,
1585 },
1586 Field {
1587 name: "upcf",
1588 description: Some(
1589 "Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.",
1590 ),
1591 bit_offset: BitOffset::Regular(
1592 RegularBitOffset {
1593 offset: 5,
1594 },
1595 ),
1596 bit_size: 1,
1597 array: None,
1598 enumm: None,
1599 },
1600 Field {
1601 name: "downcf",
1602 description: Some(
1603 "Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.",
1604 ),
1605 bit_offset: BitOffset::Regular(
1606 RegularBitOffset {
1607 offset: 6,
1608 },
1609 ),
1610 bit_size: 1,
1611 array: None,
1612 enumm: None,
1613 },
1614 Field {
1615 name: "uecf",
1616 description: Some(
1617 "Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register.",
1618 ),
1619 bit_offset: BitOffset::Regular(
1620 RegularBitOffset {
1621 offset: 7,
1622 },
1623 ),
1624 bit_size: 1,
1625 array: None,
1626 enumm: None,
1627 },
1628 Field {
1629 name: "repokcf",
1630 description: Some(
1631 "Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register.",
1632 ),
1633 bit_offset: BitOffset::Regular(
1634 RegularBitOffset {
1635 offset: 8,
1636 },
1637 ),
1638 bit_size: 1,
1639 array: None,
1640 enumm: None,
1641 },
1642 Field {
1643 name: "dierokcf",
1644 description: Some(
1645 "Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register.",
1646 ),
1647 bit_offset: BitOffset::Regular(
1648 RegularBitOffset {
1649 offset: 24,
1650 },
1651 ),
1652 bit_size: 1,
1653 array: None,
1654 enumm: None,
1655 },
1656 ],
1657 },
1658 FieldSet {
1659 name: "IsrAdv",
1660 extends: Some(
1661 "ISR_BASIC",
1662 ),
1663 description: Some(
1664 "LPTIM interrupt and status register.",
1665 ),
1666 bit_size: 32,
1667 fields: &[
1668 Field {
1669 name: "ccif",
1670 description: Some(
1671 "Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.",
1672 ),
1673 bit_offset: BitOffset::Regular(
1674 RegularBitOffset {
1675 offset: 0,
1676 },
1677 ),
1678 bit_size: 1,
1679 array: Some(
1680 Array::Regular(
1681 RegularArray {
1682 len: 2,
1683 stride: 9,
1684 },
1685 ),
1686 ),
1687 enumm: None,
1688 },
1689 Field {
1690 name: "arrm",
1691 description: Some(
1692 "Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.",
1693 ),
1694 bit_offset: BitOffset::Regular(
1695 RegularBitOffset {
1696 offset: 1,
1697 },
1698 ),
1699 bit_size: 1,
1700 array: None,
1701 enumm: None,
1702 },
1703 Field {
1704 name: "exttrig",
1705 description: Some(
1706 "External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.",
1707 ),
1708 bit_offset: BitOffset::Regular(
1709 RegularBitOffset {
1710 offset: 2,
1711 },
1712 ),
1713 bit_size: 1,
1714 array: None,
1715 enumm: None,
1716 },
1717 Field {
1718 name: "cmpok",
1719 description: Some(
1720 "Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.",
1721 ),
1722 bit_offset: BitOffset::Regular(
1723 RegularBitOffset {
1724 offset: 3,
1725 },
1726 ),
1727 bit_size: 1,
1728 array: Some(
1729 Array::Regular(
1730 RegularArray {
1731 len: 2,
1732 stride: 16,
1733 },
1734 ),
1735 ),
1736 enumm: None,
1737 },
1738 Field {
1739 name: "arrok",
1740 description: Some(
1741 "Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.",
1742 ),
1743 bit_offset: BitOffset::Regular(
1744 RegularBitOffset {
1745 offset: 4,
1746 },
1747 ),
1748 bit_size: 1,
1749 array: None,
1750 enumm: None,
1751 },
1752 Field {
1753 name: "up",
1754 description: Some(
1755 "Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.",
1756 ),
1757 bit_offset: BitOffset::Regular(
1758 RegularBitOffset {
1759 offset: 5,
1760 },
1761 ),
1762 bit_size: 1,
1763 array: None,
1764 enumm: None,
1765 },
1766 Field {
1767 name: "down",
1768 description: Some(
1769 "Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.",
1770 ),
1771 bit_offset: BitOffset::Regular(
1772 RegularBitOffset {
1773 offset: 6,
1774 },
1775 ),
1776 bit_size: 1,
1777 array: None,
1778 enumm: None,
1779 },
1780 Field {
1781 name: "ue",
1782 description: Some(
1783 "LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register.",
1784 ),
1785 bit_offset: BitOffset::Regular(
1786 RegularBitOffset {
1787 offset: 7,
1788 },
1789 ),
1790 bit_size: 1,
1791 array: None,
1792 enumm: None,
1793 },
1794 Field {
1795 name: "repok",
1796 description: Some(
1797 "Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register.",
1798 ),
1799 bit_offset: BitOffset::Regular(
1800 RegularBitOffset {
1801 offset: 8,
1802 },
1803 ),
1804 bit_size: 1,
1805 array: None,
1806 enumm: None,
1807 },
1808 Field {
1809 name: "ccof",
1810 description: Some(
1811 "Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.",
1812 ),
1813 bit_offset: BitOffset::Regular(
1814 RegularBitOffset {
1815 offset: 12,
1816 },
1817 ),
1818 bit_size: 1,
1819 array: Some(
1820 Array::Regular(
1821 RegularArray {
1822 len: 2,
1823 stride: 1,
1824 },
1825 ),
1826 ),
1827 enumm: None,
1828 },
1829 Field {
1830 name: "dierok",
1831 description: Some(
1832 "Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register.",
1833 ),
1834 bit_offset: BitOffset::Regular(
1835 RegularBitOffset {
1836 offset: 24,
1837 },
1838 ),
1839 bit_size: 1,
1840 array: None,
1841 enumm: None,
1842 },
1843 ],
1844 },
1845 FieldSet {
1846 name: "IsrBasic",
1847 extends: None,
1848 description: Some(
1849 "LPTIM interrupt and status register.",
1850 ),
1851 bit_size: 32,
1852 fields: &[
1853 Field {
1854 name: "ccif",
1855 description: Some(
1856 "Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.",
1857 ),
1858 bit_offset: BitOffset::Regular(
1859 RegularBitOffset {
1860 offset: 0,
1861 },
1862 ),
1863 bit_size: 1,
1864 array: Some(
1865 Array::Regular(
1866 RegularArray {
1867 len: 1,
1868 stride: 9,
1869 },
1870 ),
1871 ),
1872 enumm: None,
1873 },
1874 Field {
1875 name: "arrm",
1876 description: Some(
1877 "Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.",
1878 ),
1879 bit_offset: BitOffset::Regular(
1880 RegularBitOffset {
1881 offset: 1,
1882 },
1883 ),
1884 bit_size: 1,
1885 array: None,
1886 enumm: None,
1887 },
1888 Field {
1889 name: "exttrig",
1890 description: Some(
1891 "External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.",
1892 ),
1893 bit_offset: BitOffset::Regular(
1894 RegularBitOffset {
1895 offset: 2,
1896 },
1897 ),
1898 bit_size: 1,
1899 array: None,
1900 enumm: None,
1901 },
1902 Field {
1903 name: "cmpok",
1904 description: Some(
1905 "Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.",
1906 ),
1907 bit_offset: BitOffset::Regular(
1908 RegularBitOffset {
1909 offset: 3,
1910 },
1911 ),
1912 bit_size: 1,
1913 array: Some(
1914 Array::Regular(
1915 RegularArray {
1916 len: 1,
1917 stride: 16,
1918 },
1919 ),
1920 ),
1921 enumm: None,
1922 },
1923 Field {
1924 name: "arrok",
1925 description: Some(
1926 "Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.",
1927 ),
1928 bit_offset: BitOffset::Regular(
1929 RegularBitOffset {
1930 offset: 4,
1931 },
1932 ),
1933 bit_size: 1,
1934 array: None,
1935 enumm: None,
1936 },
1937 Field {
1938 name: "up",
1939 description: Some(
1940 "Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.",
1941 ),
1942 bit_offset: BitOffset::Regular(
1943 RegularBitOffset {
1944 offset: 5,
1945 },
1946 ),
1947 bit_size: 1,
1948 array: None,
1949 enumm: None,
1950 },
1951 Field {
1952 name: "down",
1953 description: Some(
1954 "Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.",
1955 ),
1956 bit_offset: BitOffset::Regular(
1957 RegularBitOffset {
1958 offset: 6,
1959 },
1960 ),
1961 bit_size: 1,
1962 array: None,
1963 enumm: None,
1964 },
1965 Field {
1966 name: "ue",
1967 description: Some(
1968 "LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register.",
1969 ),
1970 bit_offset: BitOffset::Regular(
1971 RegularBitOffset {
1972 offset: 7,
1973 },
1974 ),
1975 bit_size: 1,
1976 array: None,
1977 enumm: None,
1978 },
1979 Field {
1980 name: "repok",
1981 description: Some(
1982 "Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register.",
1983 ),
1984 bit_offset: BitOffset::Regular(
1985 RegularBitOffset {
1986 offset: 8,
1987 },
1988 ),
1989 bit_size: 1,
1990 array: None,
1991 enumm: None,
1992 },
1993 Field {
1994 name: "dierok",
1995 description: Some(
1996 "Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register.",
1997 ),
1998 bit_offset: BitOffset::Regular(
1999 RegularBitOffset {
2000 offset: 24,
2001 },
2002 ),
2003 bit_size: 1,
2004 array: None,
2005 enumm: None,
2006 },
2007 ],
2008 },
2009 FieldSet {
2010 name: "Rcr",
2011 extends: None,
2012 description: Some(
2013 "LPTIM repetition register.",
2014 ),
2015 bit_size: 32,
2016 fields: &[
2017 Field {
2018 name: "rep",
2019 description: Some(
2020 "Repetition register value REP is the repetition value for the LPTIM.",
2021 ),
2022 bit_offset: BitOffset::Regular(
2023 RegularBitOffset {
2024 offset: 0,
2025 },
2026 ),
2027 bit_size: 8,
2028 array: None,
2029 enumm: None,
2030 },
2031 ],
2032 },
2033 ],
2034 enums: &[
2035 Enum {
2036 name: "CcpInput",
2037 description: None,
2038 bit_size: 2,
2039 variants: &[
2040 EnumVariant {
2041 name: "RISING",
2042 description: None,
2043 value: 0,
2044 },
2045 EnumVariant {
2046 name: "FALLING",
2047 description: None,
2048 value: 1,
2049 },
2050 EnumVariant {
2051 name: "BOTH",
2052 description: None,
2053 value: 3,
2054 },
2055 ],
2056 },
2057 Enum {
2058 name: "CcpOutput",
2059 description: None,
2060 bit_size: 2,
2061 variants: &[
2062 EnumVariant {
2063 name: "ACTIVE_HIGH",
2064 description: None,
2065 value: 0,
2066 },
2067 EnumVariant {
2068 name: "ACTIVE_LOW",
2069 description: None,
2070 value: 1,
2071 },
2072 ],
2073 },
2074 Enum {
2075 name: "Ccsel",
2076 description: None,
2077 bit_size: 1,
2078 variants: &[
2079 EnumVariant {
2080 name: "OUTPUT_COMPARE",
2081 description: Some(
2082 "channel is configured in output PWM mode",
2083 ),
2084 value: 0,
2085 },
2086 EnumVariant {
2087 name: "INPUT_CAPTURE",
2088 description: Some(
2089 "channel is configured in input capture mode",
2090 ),
2091 value: 1,
2092 },
2093 ],
2094 },
2095 Enum {
2096 name: "Ckpol",
2097 description: None,
2098 bit_size: 2,
2099 variants: &[
2100 EnumVariant {
2101 name: "RISING",
2102 description: Some(
2103 "the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active.",
2104 ),
2105 value: 0,
2106 },
2107 EnumVariant {
2108 name: "FALLING",
2109 description: Some(
2110 "the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active.",
2111 ),
2112 value: 1,
2113 },
2114 EnumVariant {
2115 name: "BOTH",
2116 description: Some(
2117 "both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.",
2118 ),
2119 value: 2,
2120 },
2121 ],
2122 },
2123 Enum {
2124 name: "ClockSource",
2125 description: None,
2126 bit_size: 1,
2127 variants: &[
2128 EnumVariant {
2129 name: "INTERNAL",
2130 description: Some(
2131 "clocked by internal clock source (APB clock or any of the embedded oscillators)",
2132 ),
2133 value: 0,
2134 },
2135 EnumVariant {
2136 name: "EXTERNAL",
2137 description: Some(
2138 "clocked by an external clock source through the LPTIM external Input1",
2139 ),
2140 value: 1,
2141 },
2142 ],
2143 },
2144 Enum {
2145 name: "Filter",
2146 description: None,
2147 bit_size: 2,
2148 variants: &[
2149 EnumVariant {
2150 name: "COUNT1",
2151 description: None,
2152 value: 0,
2153 },
2154 EnumVariant {
2155 name: "COUNT2",
2156 description: None,
2157 value: 1,
2158 },
2159 EnumVariant {
2160 name: "COUNT4",
2161 description: None,
2162 value: 2,
2163 },
2164 EnumVariant {
2165 name: "COUNT8",
2166 description: None,
2167 value: 3,
2168 },
2169 ],
2170 },
2171 Enum {
2172 name: "Presc",
2173 description: None,
2174 bit_size: 3,
2175 variants: &[
2176 EnumVariant {
2177 name: "DIV1",
2178 description: None,
2179 value: 0,
2180 },
2181 EnumVariant {
2182 name: "DIV2",
2183 description: None,
2184 value: 1,
2185 },
2186 EnumVariant {
2187 name: "DIV4",
2188 description: None,
2189 value: 2,
2190 },
2191 EnumVariant {
2192 name: "DIV8",
2193 description: None,
2194 value: 3,
2195 },
2196 EnumVariant {
2197 name: "DIV16",
2198 description: None,
2199 value: 4,
2200 },
2201 EnumVariant {
2202 name: "DIV32",
2203 description: None,
2204 value: 5,
2205 },
2206 EnumVariant {
2207 name: "DIV64",
2208 description: None,
2209 value: 6,
2210 },
2211 EnumVariant {
2212 name: "DIV128",
2213 description: None,
2214 value: 7,
2215 },
2216 ],
2217 },
2218 Enum {
2219 name: "Trigen",
2220 description: None,
2221 bit_size: 2,
2222 variants: &[
2223 EnumVariant {
2224 name: "SOFTWARE",
2225 description: Some(
2226 "software trigger (counting start is initiated by software)",
2227 ),
2228 value: 0,
2229 },
2230 EnumVariant {
2231 name: "RISING_EDGE",
2232 description: Some(
2233 "rising edge is the active edge",
2234 ),
2235 value: 1,
2236 },
2237 EnumVariant {
2238 name: "FALLING_EDGE",
2239 description: Some(
2240 "falling edge is the active edge",
2241 ),
2242 value: 2,
2243 },
2244 EnumVariant {
2245 name: "BOTH_EDGE",
2246 description: Some(
2247 "both edges are active edges",
2248 ),
2249 value: 3,
2250 },
2251 ],
2252 },
2253 Enum {
2254 name: "Wavpol",
2255 description: None,
2256 bit_size: 1,
2257 variants: &[
2258 EnumVariant {
2259 name: "POSITIVE",
2260 description: Some(
2261 "The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers.",
2262 ),
2263 value: 0,
2264 },
2265 EnumVariant {
2266 name: "NEGATIVE",
2267 description: Some(
2268 "The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers.",
2269 ),
2270 value: 1,
2271 },
2272 ],
2273 },
2274 ],
2275};
2276