1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Layer",
7 extends: None,
8 description: Some(
9 "Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR",
10 ),
11 items: &[
12 BlockItem {
13 name: "cr",
14 description: Some(
15 "Layerx Control Register",
16 ),
17 array: None,
18 byte_offset: 0x0,
19 inner: BlockItemInner::Register(
20 Register {
21 access: Access::ReadWrite,
22 bit_size: 32,
23 fieldset: Some(
24 "Cr",
25 ),
26 },
27 ),
28 },
29 BlockItem {
30 name: "whpcr",
31 description: Some(
32 "Layerx Window Horizontal Position Configuration Register",
33 ),
34 array: None,
35 byte_offset: 0x4,
36 inner: BlockItemInner::Register(
37 Register {
38 access: Access::ReadWrite,
39 bit_size: 32,
40 fieldset: Some(
41 "Whpcr",
42 ),
43 },
44 ),
45 },
46 BlockItem {
47 name: "wvpcr",
48 description: Some(
49 "Layerx Window Vertical Position Configuration Register",
50 ),
51 array: None,
52 byte_offset: 0x8,
53 inner: BlockItemInner::Register(
54 Register {
55 access: Access::ReadWrite,
56 bit_size: 32,
57 fieldset: Some(
58 "Wvpcr",
59 ),
60 },
61 ),
62 },
63 BlockItem {
64 name: "ckcr",
65 description: Some(
66 "Layerx Color Keying Configuration Register",
67 ),
68 array: None,
69 byte_offset: 0xc,
70 inner: BlockItemInner::Register(
71 Register {
72 access: Access::ReadWrite,
73 bit_size: 32,
74 fieldset: Some(
75 "Ckcr",
76 ),
77 },
78 ),
79 },
80 BlockItem {
81 name: "pfcr",
82 description: Some(
83 "Layerx Pixel Format Configuration Register",
84 ),
85 array: None,
86 byte_offset: 0x10,
87 inner: BlockItemInner::Register(
88 Register {
89 access: Access::ReadWrite,
90 bit_size: 32,
91 fieldset: Some(
92 "Pfcr",
93 ),
94 },
95 ),
96 },
97 BlockItem {
98 name: "cacr",
99 description: Some(
100 "Layerx Constant Alpha Configuration Register",
101 ),
102 array: None,
103 byte_offset: 0x14,
104 inner: BlockItemInner::Register(
105 Register {
106 access: Access::ReadWrite,
107 bit_size: 32,
108 fieldset: Some(
109 "Cacr",
110 ),
111 },
112 ),
113 },
114 BlockItem {
115 name: "dccr",
116 description: Some(
117 "Layerx Default Color Configuration Register",
118 ),
119 array: None,
120 byte_offset: 0x18,
121 inner: BlockItemInner::Register(
122 Register {
123 access: Access::ReadWrite,
124 bit_size: 32,
125 fieldset: Some(
126 "Dccr",
127 ),
128 },
129 ),
130 },
131 BlockItem {
132 name: "bfcr",
133 description: Some(
134 "Layerx Blending Factors Configuration Register",
135 ),
136 array: None,
137 byte_offset: 0x1c,
138 inner: BlockItemInner::Register(
139 Register {
140 access: Access::ReadWrite,
141 bit_size: 32,
142 fieldset: Some(
143 "Bfcr",
144 ),
145 },
146 ),
147 },
148 BlockItem {
149 name: "cfbar",
150 description: Some(
151 "Layerx Color Frame Buffer Address Register",
152 ),
153 array: None,
154 byte_offset: 0x28,
155 inner: BlockItemInner::Register(
156 Register {
157 access: Access::ReadWrite,
158 bit_size: 32,
159 fieldset: Some(
160 "Cfbar",
161 ),
162 },
163 ),
164 },
165 BlockItem {
166 name: "cfblr",
167 description: Some(
168 "Layerx Color Frame Buffer Length Register",
169 ),
170 array: None,
171 byte_offset: 0x2c,
172 inner: BlockItemInner::Register(
173 Register {
174 access: Access::ReadWrite,
175 bit_size: 32,
176 fieldset: Some(
177 "Cfblr",
178 ),
179 },
180 ),
181 },
182 BlockItem {
183 name: "cfblnr",
184 description: Some(
185 "Layerx ColorFrame Buffer Line Number Register",
186 ),
187 array: None,
188 byte_offset: 0x30,
189 inner: BlockItemInner::Register(
190 Register {
191 access: Access::ReadWrite,
192 bit_size: 32,
193 fieldset: Some(
194 "Cfblnr",
195 ),
196 },
197 ),
198 },
199 BlockItem {
200 name: "clutwr",
201 description: Some(
202 "Layerx CLUT Write Register",
203 ),
204 array: None,
205 byte_offset: 0x40,
206 inner: BlockItemInner::Register(
207 Register {
208 access: Access::Write,
209 bit_size: 32,
210 fieldset: Some(
211 "Clutwr",
212 ),
213 },
214 ),
215 },
216 ],
217 },
218 Block {
219 name: "Ltdc",
220 extends: None,
221 description: Some(
222 "LCD-TFT Controller",
223 ),
224 items: &[
225 BlockItem {
226 name: "sscr",
227 description: Some(
228 "Synchronization Size Configuration Register",
229 ),
230 array: None,
231 byte_offset: 0x8,
232 inner: BlockItemInner::Register(
233 Register {
234 access: Access::ReadWrite,
235 bit_size: 32,
236 fieldset: Some(
237 "Sscr",
238 ),
239 },
240 ),
241 },
242 BlockItem {
243 name: "bpcr",
244 description: Some(
245 "Back Porch Configuration Register",
246 ),
247 array: None,
248 byte_offset: 0xc,
249 inner: BlockItemInner::Register(
250 Register {
251 access: Access::ReadWrite,
252 bit_size: 32,
253 fieldset: Some(
254 "Bpcr",
255 ),
256 },
257 ),
258 },
259 BlockItem {
260 name: "awcr",
261 description: Some(
262 "Active Width Configuration Register",
263 ),
264 array: None,
265 byte_offset: 0x10,
266 inner: BlockItemInner::Register(
267 Register {
268 access: Access::ReadWrite,
269 bit_size: 32,
270 fieldset: Some(
271 "Awcr",
272 ),
273 },
274 ),
275 },
276 BlockItem {
277 name: "twcr",
278 description: Some(
279 "Total Width Configuration Register",
280 ),
281 array: None,
282 byte_offset: 0x14,
283 inner: BlockItemInner::Register(
284 Register {
285 access: Access::ReadWrite,
286 bit_size: 32,
287 fieldset: Some(
288 "Twcr",
289 ),
290 },
291 ),
292 },
293 BlockItem {
294 name: "gcr",
295 description: Some(
296 "Global Control Register",
297 ),
298 array: None,
299 byte_offset: 0x18,
300 inner: BlockItemInner::Register(
301 Register {
302 access: Access::ReadWrite,
303 bit_size: 32,
304 fieldset: Some(
305 "Gcr",
306 ),
307 },
308 ),
309 },
310 BlockItem {
311 name: "srcr",
312 description: Some(
313 "Shadow Reload Configuration Register",
314 ),
315 array: None,
316 byte_offset: 0x24,
317 inner: BlockItemInner::Register(
318 Register {
319 access: Access::ReadWrite,
320 bit_size: 32,
321 fieldset: Some(
322 "Srcr",
323 ),
324 },
325 ),
326 },
327 BlockItem {
328 name: "bccr",
329 description: Some(
330 "Background Color Configuration Register",
331 ),
332 array: None,
333 byte_offset: 0x2c,
334 inner: BlockItemInner::Register(
335 Register {
336 access: Access::ReadWrite,
337 bit_size: 32,
338 fieldset: Some(
339 "Bccr",
340 ),
341 },
342 ),
343 },
344 BlockItem {
345 name: "ier",
346 description: Some(
347 "Interrupt Enable Register",
348 ),
349 array: None,
350 byte_offset: 0x34,
351 inner: BlockItemInner::Register(
352 Register {
353 access: Access::ReadWrite,
354 bit_size: 32,
355 fieldset: Some(
356 "Ier",
357 ),
358 },
359 ),
360 },
361 BlockItem {
362 name: "isr",
363 description: Some(
364 "Interrupt Status Register",
365 ),
366 array: None,
367 byte_offset: 0x38,
368 inner: BlockItemInner::Register(
369 Register {
370 access: Access::Read,
371 bit_size: 32,
372 fieldset: Some(
373 "Isr",
374 ),
375 },
376 ),
377 },
378 BlockItem {
379 name: "icr",
380 description: Some(
381 "Interrupt Clear Register",
382 ),
383 array: None,
384 byte_offset: 0x3c,
385 inner: BlockItemInner::Register(
386 Register {
387 access: Access::Write,
388 bit_size: 32,
389 fieldset: Some(
390 "Icr",
391 ),
392 },
393 ),
394 },
395 BlockItem {
396 name: "lipcr",
397 description: Some(
398 "Line Interrupt Position Configuration Register",
399 ),
400 array: None,
401 byte_offset: 0x40,
402 inner: BlockItemInner::Register(
403 Register {
404 access: Access::ReadWrite,
405 bit_size: 32,
406 fieldset: Some(
407 "Lipcr",
408 ),
409 },
410 ),
411 },
412 BlockItem {
413 name: "cpsr",
414 description: Some(
415 "Current Position Status Register",
416 ),
417 array: None,
418 byte_offset: 0x44,
419 inner: BlockItemInner::Register(
420 Register {
421 access: Access::Read,
422 bit_size: 32,
423 fieldset: Some(
424 "Cpsr",
425 ),
426 },
427 ),
428 },
429 BlockItem {
430 name: "cdsr",
431 description: Some(
432 "Current Display Status Register",
433 ),
434 array: None,
435 byte_offset: 0x48,
436 inner: BlockItemInner::Register(
437 Register {
438 access: Access::Read,
439 bit_size: 32,
440 fieldset: Some(
441 "Cdsr",
442 ),
443 },
444 ),
445 },
446 BlockItem {
447 name: "layer",
448 description: Some(
449 "Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR",
450 ),
451 array: Some(
452 Array::Regular(
453 RegularArray {
454 len: 2,
455 stride: 128,
456 },
457 ),
458 ),
459 byte_offset: 0x84,
460 inner: BlockItemInner::Block(
461 BlockItemBlock {
462 block: "Layer",
463 },
464 ),
465 },
466 ],
467 },
468 ],
469 fieldsets: &[
470 FieldSet {
471 name: "Awcr",
472 extends: None,
473 description: Some(
474 "Active Width Configuration Register",
475 ),
476 bit_size: 32,
477 fields: &[
478 Field {
479 name: "aah",
480 description: Some(
481 "Accumulated Active Height (in units of horizontal scan line)",
482 ),
483 bit_offset: BitOffset::Regular(
484 RegularBitOffset {
485 offset: 0,
486 },
487 ),
488 bit_size: 11,
489 array: None,
490 enumm: None,
491 },
492 Field {
493 name: "aaw",
494 description: Some(
495 "Accumulated Active Width (in units of pixel clock period)",
496 ),
497 bit_offset: BitOffset::Regular(
498 RegularBitOffset {
499 offset: 16,
500 },
501 ),
502 bit_size: 12,
503 array: None,
504 enumm: None,
505 },
506 ],
507 },
508 FieldSet {
509 name: "Bccr",
510 extends: None,
511 description: Some(
512 "Background Color Configuration Register",
513 ),
514 bit_size: 32,
515 fields: &[
516 Field {
517 name: "bcblue",
518 description: Some(
519 "Background color blue value",
520 ),
521 bit_offset: BitOffset::Regular(
522 RegularBitOffset {
523 offset: 0,
524 },
525 ),
526 bit_size: 8,
527 array: None,
528 enumm: None,
529 },
530 Field {
531 name: "bcgreen",
532 description: Some(
533 "Background color green value",
534 ),
535 bit_offset: BitOffset::Regular(
536 RegularBitOffset {
537 offset: 8,
538 },
539 ),
540 bit_size: 8,
541 array: None,
542 enumm: None,
543 },
544 Field {
545 name: "bcred",
546 description: Some(
547 "Background color red value",
548 ),
549 bit_offset: BitOffset::Regular(
550 RegularBitOffset {
551 offset: 16,
552 },
553 ),
554 bit_size: 8,
555 array: None,
556 enumm: None,
557 },
558 ],
559 },
560 FieldSet {
561 name: "Bfcr",
562 extends: None,
563 description: Some(
564 "Layerx Blending Factors Configuration Register",
565 ),
566 bit_size: 32,
567 fields: &[
568 Field {
569 name: "bf2",
570 description: Some(
571 "Blending Factor 2",
572 ),
573 bit_offset: BitOffset::Regular(
574 RegularBitOffset {
575 offset: 0,
576 },
577 ),
578 bit_size: 3,
579 array: None,
580 enumm: Some(
581 "Bf2",
582 ),
583 },
584 Field {
585 name: "bf1",
586 description: Some(
587 "Blending Factor 1",
588 ),
589 bit_offset: BitOffset::Regular(
590 RegularBitOffset {
591 offset: 8,
592 },
593 ),
594 bit_size: 3,
595 array: None,
596 enumm: Some(
597 "Bf1",
598 ),
599 },
600 ],
601 },
602 FieldSet {
603 name: "Bpcr",
604 extends: None,
605 description: Some(
606 "Back Porch Configuration Register",
607 ),
608 bit_size: 32,
609 fields: &[
610 Field {
611 name: "avbp",
612 description: Some(
613 "Accumulated Vertical back porch (in units of horizontal scan line)",
614 ),
615 bit_offset: BitOffset::Regular(
616 RegularBitOffset {
617 offset: 0,
618 },
619 ),
620 bit_size: 11,
621 array: None,
622 enumm: None,
623 },
624 Field {
625 name: "ahbp",
626 description: Some(
627 "Accumulated Horizontal back porch (in units of pixel clock period)",
628 ),
629 bit_offset: BitOffset::Regular(
630 RegularBitOffset {
631 offset: 16,
632 },
633 ),
634 bit_size: 12,
635 array: None,
636 enumm: None,
637 },
638 ],
639 },
640 FieldSet {
641 name: "Cacr",
642 extends: None,
643 description: Some(
644 "Layerx Constant Alpha Configuration Register",
645 ),
646 bit_size: 32,
647 fields: &[
648 Field {
649 name: "consta",
650 description: Some(
651 "Constant Alpha",
652 ),
653 bit_offset: BitOffset::Regular(
654 RegularBitOffset {
655 offset: 0,
656 },
657 ),
658 bit_size: 8,
659 array: None,
660 enumm: None,
661 },
662 ],
663 },
664 FieldSet {
665 name: "Cdsr",
666 extends: None,
667 description: Some(
668 "Current Display Status Register",
669 ),
670 bit_size: 32,
671 fields: &[
672 Field {
673 name: "vdes",
674 description: Some(
675 "Vertical Data Enable display Status",
676 ),
677 bit_offset: BitOffset::Regular(
678 RegularBitOffset {
679 offset: 0,
680 },
681 ),
682 bit_size: 1,
683 array: None,
684 enumm: None,
685 },
686 Field {
687 name: "hdes",
688 description: Some(
689 "Horizontal Data Enable display Status",
690 ),
691 bit_offset: BitOffset::Regular(
692 RegularBitOffset {
693 offset: 1,
694 },
695 ),
696 bit_size: 1,
697 array: None,
698 enumm: None,
699 },
700 Field {
701 name: "vsyncs",
702 description: Some(
703 "Vertical Synchronization display Status",
704 ),
705 bit_offset: BitOffset::Regular(
706 RegularBitOffset {
707 offset: 2,
708 },
709 ),
710 bit_size: 1,
711 array: None,
712 enumm: None,
713 },
714 Field {
715 name: "hsyncs",
716 description: Some(
717 "Horizontal Synchronization display Status",
718 ),
719 bit_offset: BitOffset::Regular(
720 RegularBitOffset {
721 offset: 3,
722 },
723 ),
724 bit_size: 1,
725 array: None,
726 enumm: None,
727 },
728 ],
729 },
730 FieldSet {
731 name: "Cfbar",
732 extends: None,
733 description: Some(
734 "Layerx Color Frame Buffer Address Register",
735 ),
736 bit_size: 32,
737 fields: &[
738 Field {
739 name: "cfbadd",
740 description: Some(
741 "Color Frame Buffer Start Address",
742 ),
743 bit_offset: BitOffset::Regular(
744 RegularBitOffset {
745 offset: 0,
746 },
747 ),
748 bit_size: 32,
749 array: None,
750 enumm: None,
751 },
752 ],
753 },
754 FieldSet {
755 name: "Cfblnr",
756 extends: None,
757 description: Some(
758 "Layerx ColorFrame Buffer Line Number Register",
759 ),
760 bit_size: 32,
761 fields: &[
762 Field {
763 name: "cfblnbr",
764 description: Some(
765 "Frame Buffer Line Number",
766 ),
767 bit_offset: BitOffset::Regular(
768 RegularBitOffset {
769 offset: 0,
770 },
771 ),
772 bit_size: 11,
773 array: None,
774 enumm: None,
775 },
776 ],
777 },
778 FieldSet {
779 name: "Cfblr",
780 extends: None,
781 description: Some(
782 "Layerx Color Frame Buffer Length Register",
783 ),
784 bit_size: 32,
785 fields: &[
786 Field {
787 name: "cfbll",
788 description: Some(
789 "Color Frame Buffer Line Length",
790 ),
791 bit_offset: BitOffset::Regular(
792 RegularBitOffset {
793 offset: 0,
794 },
795 ),
796 bit_size: 13,
797 array: None,
798 enumm: None,
799 },
800 Field {
801 name: "cfbp",
802 description: Some(
803 "Color Frame Buffer Pitch in bytes",
804 ),
805 bit_offset: BitOffset::Regular(
806 RegularBitOffset {
807 offset: 16,
808 },
809 ),
810 bit_size: 13,
811 array: None,
812 enumm: None,
813 },
814 ],
815 },
816 FieldSet {
817 name: "Ckcr",
818 extends: None,
819 description: Some(
820 "Layerx Color Keying Configuration Register",
821 ),
822 bit_size: 32,
823 fields: &[
824 Field {
825 name: "ckblue",
826 description: Some(
827 "Color Key Blue value",
828 ),
829 bit_offset: BitOffset::Regular(
830 RegularBitOffset {
831 offset: 0,
832 },
833 ),
834 bit_size: 8,
835 array: None,
836 enumm: None,
837 },
838 Field {
839 name: "ckgreen",
840 description: Some(
841 "Color Key Green value",
842 ),
843 bit_offset: BitOffset::Regular(
844 RegularBitOffset {
845 offset: 8,
846 },
847 ),
848 bit_size: 8,
849 array: None,
850 enumm: None,
851 },
852 Field {
853 name: "ckred",
854 description: Some(
855 "Color Key Red value",
856 ),
857 bit_offset: BitOffset::Regular(
858 RegularBitOffset {
859 offset: 16,
860 },
861 ),
862 bit_size: 8,
863 array: None,
864 enumm: None,
865 },
866 ],
867 },
868 FieldSet {
869 name: "Clutwr",
870 extends: None,
871 description: Some(
872 "Layerx CLUT Write Register",
873 ),
874 bit_size: 32,
875 fields: &[
876 Field {
877 name: "blue",
878 description: Some(
879 "Blue value",
880 ),
881 bit_offset: BitOffset::Regular(
882 RegularBitOffset {
883 offset: 0,
884 },
885 ),
886 bit_size: 8,
887 array: None,
888 enumm: None,
889 },
890 Field {
891 name: "green",
892 description: Some(
893 "Green value",
894 ),
895 bit_offset: BitOffset::Regular(
896 RegularBitOffset {
897 offset: 8,
898 },
899 ),
900 bit_size: 8,
901 array: None,
902 enumm: None,
903 },
904 Field {
905 name: "red",
906 description: Some(
907 "Red value",
908 ),
909 bit_offset: BitOffset::Regular(
910 RegularBitOffset {
911 offset: 16,
912 },
913 ),
914 bit_size: 8,
915 array: None,
916 enumm: None,
917 },
918 Field {
919 name: "clutadd",
920 description: Some(
921 "CLUT Address",
922 ),
923 bit_offset: BitOffset::Regular(
924 RegularBitOffset {
925 offset: 24,
926 },
927 ),
928 bit_size: 8,
929 array: None,
930 enumm: None,
931 },
932 ],
933 },
934 FieldSet {
935 name: "Cpsr",
936 extends: None,
937 description: Some(
938 "Current Position Status Register",
939 ),
940 bit_size: 32,
941 fields: &[
942 Field {
943 name: "cypos",
944 description: Some(
945 "Current Y Position",
946 ),
947 bit_offset: BitOffset::Regular(
948 RegularBitOffset {
949 offset: 0,
950 },
951 ),
952 bit_size: 16,
953 array: None,
954 enumm: None,
955 },
956 Field {
957 name: "cxpos",
958 description: Some(
959 "Current X Position",
960 ),
961 bit_offset: BitOffset::Regular(
962 RegularBitOffset {
963 offset: 16,
964 },
965 ),
966 bit_size: 16,
967 array: None,
968 enumm: None,
969 },
970 ],
971 },
972 FieldSet {
973 name: "Cr",
974 extends: None,
975 description: Some(
976 "Layerx Control Register",
977 ),
978 bit_size: 32,
979 fields: &[
980 Field {
981 name: "len",
982 description: Some(
983 "Layer Enable",
984 ),
985 bit_offset: BitOffset::Regular(
986 RegularBitOffset {
987 offset: 0,
988 },
989 ),
990 bit_size: 1,
991 array: None,
992 enumm: None,
993 },
994 Field {
995 name: "colken",
996 description: Some(
997 "Color Keying Enable",
998 ),
999 bit_offset: BitOffset::Regular(
1000 RegularBitOffset {
1001 offset: 1,
1002 },
1003 ),
1004 bit_size: 1,
1005 array: None,
1006 enumm: None,
1007 },
1008 Field {
1009 name: "cluten",
1010 description: Some(
1011 "Color Look-Up Table Enable",
1012 ),
1013 bit_offset: BitOffset::Regular(
1014 RegularBitOffset {
1015 offset: 4,
1016 },
1017 ),
1018 bit_size: 1,
1019 array: None,
1020 enumm: None,
1021 },
1022 ],
1023 },
1024 FieldSet {
1025 name: "Dccr",
1026 extends: None,
1027 description: Some(
1028 "Layerx Default Color Configuration Register",
1029 ),
1030 bit_size: 32,
1031 fields: &[
1032 Field {
1033 name: "dcblue",
1034 description: Some(
1035 "Default Color Blue",
1036 ),
1037 bit_offset: BitOffset::Regular(
1038 RegularBitOffset {
1039 offset: 0,
1040 },
1041 ),
1042 bit_size: 8,
1043 array: None,
1044 enumm: None,
1045 },
1046 Field {
1047 name: "dcgreen",
1048 description: Some(
1049 "Default Color Green",
1050 ),
1051 bit_offset: BitOffset::Regular(
1052 RegularBitOffset {
1053 offset: 8,
1054 },
1055 ),
1056 bit_size: 8,
1057 array: None,
1058 enumm: None,
1059 },
1060 Field {
1061 name: "dcred",
1062 description: Some(
1063 "Default Color Red",
1064 ),
1065 bit_offset: BitOffset::Regular(
1066 RegularBitOffset {
1067 offset: 16,
1068 },
1069 ),
1070 bit_size: 8,
1071 array: None,
1072 enumm: None,
1073 },
1074 Field {
1075 name: "dcalpha",
1076 description: Some(
1077 "Default Color Alpha",
1078 ),
1079 bit_offset: BitOffset::Regular(
1080 RegularBitOffset {
1081 offset: 24,
1082 },
1083 ),
1084 bit_size: 8,
1085 array: None,
1086 enumm: None,
1087 },
1088 ],
1089 },
1090 FieldSet {
1091 name: "Gcr",
1092 extends: None,
1093 description: Some(
1094 "Global Control Register",
1095 ),
1096 bit_size: 32,
1097 fields: &[
1098 Field {
1099 name: "ltdcen",
1100 description: Some(
1101 "LCD-TFT controller enable bit",
1102 ),
1103 bit_offset: BitOffset::Regular(
1104 RegularBitOffset {
1105 offset: 0,
1106 },
1107 ),
1108 bit_size: 1,
1109 array: None,
1110 enumm: None,
1111 },
1112 Field {
1113 name: "dbw",
1114 description: Some(
1115 "Dither Blue Width",
1116 ),
1117 bit_offset: BitOffset::Regular(
1118 RegularBitOffset {
1119 offset: 4,
1120 },
1121 ),
1122 bit_size: 3,
1123 array: None,
1124 enumm: None,
1125 },
1126 Field {
1127 name: "dgw",
1128 description: Some(
1129 "Dither Green Width",
1130 ),
1131 bit_offset: BitOffset::Regular(
1132 RegularBitOffset {
1133 offset: 8,
1134 },
1135 ),
1136 bit_size: 3,
1137 array: None,
1138 enumm: None,
1139 },
1140 Field {
1141 name: "drw",
1142 description: Some(
1143 "Dither Red Width",
1144 ),
1145 bit_offset: BitOffset::Regular(
1146 RegularBitOffset {
1147 offset: 12,
1148 },
1149 ),
1150 bit_size: 3,
1151 array: None,
1152 enumm: None,
1153 },
1154 Field {
1155 name: "den",
1156 description: Some(
1157 "Dither Enable",
1158 ),
1159 bit_offset: BitOffset::Regular(
1160 RegularBitOffset {
1161 offset: 16,
1162 },
1163 ),
1164 bit_size: 1,
1165 array: None,
1166 enumm: None,
1167 },
1168 Field {
1169 name: "pcpol",
1170 description: Some(
1171 "Pixel Clock Polarity",
1172 ),
1173 bit_offset: BitOffset::Regular(
1174 RegularBitOffset {
1175 offset: 28,
1176 },
1177 ),
1178 bit_size: 1,
1179 array: None,
1180 enumm: Some(
1181 "Pcpol",
1182 ),
1183 },
1184 Field {
1185 name: "depol",
1186 description: Some(
1187 "Data Enable Polarity",
1188 ),
1189 bit_offset: BitOffset::Regular(
1190 RegularBitOffset {
1191 offset: 29,
1192 },
1193 ),
1194 bit_size: 1,
1195 array: None,
1196 enumm: Some(
1197 "Depol",
1198 ),
1199 },
1200 Field {
1201 name: "vspol",
1202 description: Some(
1203 "Vertical Synchronization Polarity",
1204 ),
1205 bit_offset: BitOffset::Regular(
1206 RegularBitOffset {
1207 offset: 30,
1208 },
1209 ),
1210 bit_size: 1,
1211 array: None,
1212 enumm: Some(
1213 "Vspol",
1214 ),
1215 },
1216 Field {
1217 name: "hspol",
1218 description: Some(
1219 "Horizontal Synchronization Polarity",
1220 ),
1221 bit_offset: BitOffset::Regular(
1222 RegularBitOffset {
1223 offset: 31,
1224 },
1225 ),
1226 bit_size: 1,
1227 array: None,
1228 enumm: Some(
1229 "Hspol",
1230 ),
1231 },
1232 ],
1233 },
1234 FieldSet {
1235 name: "Icr",
1236 extends: None,
1237 description: Some(
1238 "Interrupt Clear Register",
1239 ),
1240 bit_size: 32,
1241 fields: &[
1242 Field {
1243 name: "clif",
1244 description: Some(
1245 "Clears the Line Interrupt Flag",
1246 ),
1247 bit_offset: BitOffset::Regular(
1248 RegularBitOffset {
1249 offset: 0,
1250 },
1251 ),
1252 bit_size: 1,
1253 array: None,
1254 enumm: Some(
1255 "Clif",
1256 ),
1257 },
1258 Field {
1259 name: "cfuif",
1260 description: Some(
1261 "Clears the FIFO Underrun Interrupt flag",
1262 ),
1263 bit_offset: BitOffset::Regular(
1264 RegularBitOffset {
1265 offset: 1,
1266 },
1267 ),
1268 bit_size: 1,
1269 array: None,
1270 enumm: Some(
1271 "Cfuif",
1272 ),
1273 },
1274 Field {
1275 name: "cterrif",
1276 description: Some(
1277 "Clears the Transfer Error Interrupt Flag",
1278 ),
1279 bit_offset: BitOffset::Regular(
1280 RegularBitOffset {
1281 offset: 2,
1282 },
1283 ),
1284 bit_size: 1,
1285 array: None,
1286 enumm: Some(
1287 "Cterrif",
1288 ),
1289 },
1290 Field {
1291 name: "crrif",
1292 description: Some(
1293 "Clears Register Reload Interrupt Flag",
1294 ),
1295 bit_offset: BitOffset::Regular(
1296 RegularBitOffset {
1297 offset: 3,
1298 },
1299 ),
1300 bit_size: 1,
1301 array: None,
1302 enumm: Some(
1303 "Crrif",
1304 ),
1305 },
1306 ],
1307 },
1308 FieldSet {
1309 name: "Ier",
1310 extends: None,
1311 description: Some(
1312 "Interrupt Enable Register",
1313 ),
1314 bit_size: 32,
1315 fields: &[
1316 Field {
1317 name: "lie",
1318 description: Some(
1319 "Line Interrupt Enable",
1320 ),
1321 bit_offset: BitOffset::Regular(
1322 RegularBitOffset {
1323 offset: 0,
1324 },
1325 ),
1326 bit_size: 1,
1327 array: None,
1328 enumm: None,
1329 },
1330 Field {
1331 name: "fuie",
1332 description: Some(
1333 "FIFO Underrun Interrupt Enable",
1334 ),
1335 bit_offset: BitOffset::Regular(
1336 RegularBitOffset {
1337 offset: 1,
1338 },
1339 ),
1340 bit_size: 1,
1341 array: None,
1342 enumm: None,
1343 },
1344 Field {
1345 name: "terrie",
1346 description: Some(
1347 "Transfer Error Interrupt Enable",
1348 ),
1349 bit_offset: BitOffset::Regular(
1350 RegularBitOffset {
1351 offset: 2,
1352 },
1353 ),
1354 bit_size: 1,
1355 array: None,
1356 enumm: None,
1357 },
1358 Field {
1359 name: "rrie",
1360 description: Some(
1361 "Register Reload interrupt enable",
1362 ),
1363 bit_offset: BitOffset::Regular(
1364 RegularBitOffset {
1365 offset: 3,
1366 },
1367 ),
1368 bit_size: 1,
1369 array: None,
1370 enumm: None,
1371 },
1372 ],
1373 },
1374 FieldSet {
1375 name: "Isr",
1376 extends: None,
1377 description: Some(
1378 "Interrupt Status Register",
1379 ),
1380 bit_size: 32,
1381 fields: &[
1382 Field {
1383 name: "lif",
1384 description: Some(
1385 "Line Interrupt flag",
1386 ),
1387 bit_offset: BitOffset::Regular(
1388 RegularBitOffset {
1389 offset: 0,
1390 },
1391 ),
1392 bit_size: 1,
1393 array: None,
1394 enumm: None,
1395 },
1396 Field {
1397 name: "fuif",
1398 description: Some(
1399 "FIFO Underrun Interrupt flag",
1400 ),
1401 bit_offset: BitOffset::Regular(
1402 RegularBitOffset {
1403 offset: 1,
1404 },
1405 ),
1406 bit_size: 1,
1407 array: None,
1408 enumm: None,
1409 },
1410 Field {
1411 name: "terrif",
1412 description: Some(
1413 "Transfer Error interrupt flag",
1414 ),
1415 bit_offset: BitOffset::Regular(
1416 RegularBitOffset {
1417 offset: 2,
1418 },
1419 ),
1420 bit_size: 1,
1421 array: None,
1422 enumm: None,
1423 },
1424 Field {
1425 name: "rrif",
1426 description: Some(
1427 "Register Reload Interrupt Flag",
1428 ),
1429 bit_offset: BitOffset::Regular(
1430 RegularBitOffset {
1431 offset: 3,
1432 },
1433 ),
1434 bit_size: 1,
1435 array: None,
1436 enumm: None,
1437 },
1438 ],
1439 },
1440 FieldSet {
1441 name: "Lipcr",
1442 extends: None,
1443 description: Some(
1444 "Line Interrupt Position Configuration Register",
1445 ),
1446 bit_size: 32,
1447 fields: &[
1448 Field {
1449 name: "lipos",
1450 description: Some(
1451 "Line Interrupt Position",
1452 ),
1453 bit_offset: BitOffset::Regular(
1454 RegularBitOffset {
1455 offset: 0,
1456 },
1457 ),
1458 bit_size: 11,
1459 array: None,
1460 enumm: None,
1461 },
1462 ],
1463 },
1464 FieldSet {
1465 name: "Pfcr",
1466 extends: None,
1467 description: Some(
1468 "Layerx Pixel Format Configuration Register",
1469 ),
1470 bit_size: 32,
1471 fields: &[
1472 Field {
1473 name: "pf",
1474 description: Some(
1475 "Pixel Format",
1476 ),
1477 bit_offset: BitOffset::Regular(
1478 RegularBitOffset {
1479 offset: 0,
1480 },
1481 ),
1482 bit_size: 3,
1483 array: None,
1484 enumm: Some(
1485 "Pf",
1486 ),
1487 },
1488 ],
1489 },
1490 FieldSet {
1491 name: "Srcr",
1492 extends: None,
1493 description: Some(
1494 "Shadow Reload Configuration Register",
1495 ),
1496 bit_size: 32,
1497 fields: &[
1498 Field {
1499 name: "imr",
1500 description: Some(
1501 "Immediate Reload",
1502 ),
1503 bit_offset: BitOffset::Regular(
1504 RegularBitOffset {
1505 offset: 0,
1506 },
1507 ),
1508 bit_size: 1,
1509 array: None,
1510 enumm: Some(
1511 "Imr",
1512 ),
1513 },
1514 Field {
1515 name: "vbr",
1516 description: Some(
1517 "Vertical Blanking Reload",
1518 ),
1519 bit_offset: BitOffset::Regular(
1520 RegularBitOffset {
1521 offset: 1,
1522 },
1523 ),
1524 bit_size: 1,
1525 array: None,
1526 enumm: Some(
1527 "Vbr",
1528 ),
1529 },
1530 ],
1531 },
1532 FieldSet {
1533 name: "Sscr",
1534 extends: None,
1535 description: Some(
1536 "Synchronization Size Configuration Register",
1537 ),
1538 bit_size: 32,
1539 fields: &[
1540 Field {
1541 name: "vsh",
1542 description: Some(
1543 "Vertical Synchronization Height (in units of horizontal scan line)",
1544 ),
1545 bit_offset: BitOffset::Regular(
1546 RegularBitOffset {
1547 offset: 0,
1548 },
1549 ),
1550 bit_size: 11,
1551 array: None,
1552 enumm: None,
1553 },
1554 Field {
1555 name: "hsw",
1556 description: Some(
1557 "Horizontal Synchronization Width (in units of pixel clock period)",
1558 ),
1559 bit_offset: BitOffset::Regular(
1560 RegularBitOffset {
1561 offset: 16,
1562 },
1563 ),
1564 bit_size: 12,
1565 array: None,
1566 enumm: None,
1567 },
1568 ],
1569 },
1570 FieldSet {
1571 name: "Twcr",
1572 extends: None,
1573 description: Some(
1574 "Total Width Configuration Register",
1575 ),
1576 bit_size: 32,
1577 fields: &[
1578 Field {
1579 name: "totalh",
1580 description: Some(
1581 "Total Height (in units of horizontal scan line)",
1582 ),
1583 bit_offset: BitOffset::Regular(
1584 RegularBitOffset {
1585 offset: 0,
1586 },
1587 ),
1588 bit_size: 11,
1589 array: None,
1590 enumm: None,
1591 },
1592 Field {
1593 name: "totalw",
1594 description: Some(
1595 "Total Width (in units of pixel clock period)",
1596 ),
1597 bit_offset: BitOffset::Regular(
1598 RegularBitOffset {
1599 offset: 16,
1600 },
1601 ),
1602 bit_size: 12,
1603 array: None,
1604 enumm: None,
1605 },
1606 ],
1607 },
1608 FieldSet {
1609 name: "Whpcr",
1610 extends: None,
1611 description: Some(
1612 "Layerx Window Horizontal Position Configuration Register",
1613 ),
1614 bit_size: 32,
1615 fields: &[
1616 Field {
1617 name: "whstpos",
1618 description: Some(
1619 "Window Horizontal Start Position",
1620 ),
1621 bit_offset: BitOffset::Regular(
1622 RegularBitOffset {
1623 offset: 0,
1624 },
1625 ),
1626 bit_size: 12,
1627 array: None,
1628 enumm: None,
1629 },
1630 Field {
1631 name: "whsppos",
1632 description: Some(
1633 "Window Horizontal Stop Position",
1634 ),
1635 bit_offset: BitOffset::Regular(
1636 RegularBitOffset {
1637 offset: 16,
1638 },
1639 ),
1640 bit_size: 12,
1641 array: None,
1642 enumm: None,
1643 },
1644 ],
1645 },
1646 FieldSet {
1647 name: "Wvpcr",
1648 extends: None,
1649 description: Some(
1650 "Layerx Window Vertical Position Configuration Register",
1651 ),
1652 bit_size: 32,
1653 fields: &[
1654 Field {
1655 name: "wvstpos",
1656 description: Some(
1657 "Window Vertical Start Position",
1658 ),
1659 bit_offset: BitOffset::Regular(
1660 RegularBitOffset {
1661 offset: 0,
1662 },
1663 ),
1664 bit_size: 11,
1665 array: None,
1666 enumm: None,
1667 },
1668 Field {
1669 name: "wvsppos",
1670 description: Some(
1671 "Window Vertical Stop Position",
1672 ),
1673 bit_offset: BitOffset::Regular(
1674 RegularBitOffset {
1675 offset: 16,
1676 },
1677 ),
1678 bit_size: 11,
1679 array: None,
1680 enumm: None,
1681 },
1682 ],
1683 },
1684 ],
1685 enums: &[
1686 Enum {
1687 name: "Bf1",
1688 description: None,
1689 bit_size: 3,
1690 variants: &[
1691 EnumVariant {
1692 name: "CONSTANT",
1693 description: Some(
1694 "BF1 = constant alpha",
1695 ),
1696 value: 4,
1697 },
1698 EnumVariant {
1699 name: "PIXEL",
1700 description: Some(
1701 "BF1 = pixel alpha * constant alpha",
1702 ),
1703 value: 6,
1704 },
1705 ],
1706 },
1707 Enum {
1708 name: "Bf2",
1709 description: None,
1710 bit_size: 3,
1711 variants: &[
1712 EnumVariant {
1713 name: "CONSTANT",
1714 description: Some(
1715 "BF2 = 1 - constant alpha",
1716 ),
1717 value: 5,
1718 },
1719 EnumVariant {
1720 name: "PIXEL",
1721 description: Some(
1722 "BF2 = 1 - pixel alpha * constant alpha",
1723 ),
1724 value: 7,
1725 },
1726 ],
1727 },
1728 Enum {
1729 name: "Cfuif",
1730 description: None,
1731 bit_size: 1,
1732 variants: &[
1733 EnumVariant {
1734 name: "CLEAR",
1735 description: Some(
1736 "Clears the FUIF flag in the ISR register",
1737 ),
1738 value: 1,
1739 },
1740 ],
1741 },
1742 Enum {
1743 name: "Clif",
1744 description: None,
1745 bit_size: 1,
1746 variants: &[
1747 EnumVariant {
1748 name: "CLEAR",
1749 description: Some(
1750 "Clears the LIF flag in the ISR register",
1751 ),
1752 value: 1,
1753 },
1754 ],
1755 },
1756 Enum {
1757 name: "Crrif",
1758 description: None,
1759 bit_size: 1,
1760 variants: &[
1761 EnumVariant {
1762 name: "CLEAR",
1763 description: Some(
1764 "Clears the RRIF flag in the ISR register",
1765 ),
1766 value: 1,
1767 },
1768 ],
1769 },
1770 Enum {
1771 name: "Cterrif",
1772 description: None,
1773 bit_size: 1,
1774 variants: &[
1775 EnumVariant {
1776 name: "CLEAR",
1777 description: Some(
1778 "Clears the TERRIF flag in the ISR register",
1779 ),
1780 value: 1,
1781 },
1782 ],
1783 },
1784 Enum {
1785 name: "Depol",
1786 description: None,
1787 bit_size: 1,
1788 variants: &[
1789 EnumVariant {
1790 name: "ACTIVE_LOW",
1791 description: Some(
1792 "Data enable polarity is active low",
1793 ),
1794 value: 0,
1795 },
1796 EnumVariant {
1797 name: "ACTIVE_HIGH",
1798 description: Some(
1799 "Data enable polarity is active high",
1800 ),
1801 value: 1,
1802 },
1803 ],
1804 },
1805 Enum {
1806 name: "Hspol",
1807 description: None,
1808 bit_size: 1,
1809 variants: &[
1810 EnumVariant {
1811 name: "ACTIVE_LOW",
1812 description: Some(
1813 "Horizontal synchronization polarity is active low",
1814 ),
1815 value: 0,
1816 },
1817 EnumVariant {
1818 name: "ACTIVE_HIGH",
1819 description: Some(
1820 "Horizontal synchronization polarity is active high",
1821 ),
1822 value: 1,
1823 },
1824 ],
1825 },
1826 Enum {
1827 name: "Imr",
1828 description: None,
1829 bit_size: 1,
1830 variants: &[
1831 EnumVariant {
1832 name: "NO_EFFECT",
1833 description: Some(
1834 "This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set)",
1835 ),
1836 value: 0,
1837 },
1838 EnumVariant {
1839 name: "RELOAD",
1840 description: Some(
1841 "The shadow registers are reloaded immediately. This bit is set by software and cleared only by hardware after reload",
1842 ),
1843 value: 1,
1844 },
1845 ],
1846 },
1847 Enum {
1848 name: "Pcpol",
1849 description: None,
1850 bit_size: 1,
1851 variants: &[
1852 EnumVariant {
1853 name: "RISING_EDGE",
1854 description: Some(
1855 "Pixel clock on rising edge",
1856 ),
1857 value: 0,
1858 },
1859 EnumVariant {
1860 name: "FALLING_EDGE",
1861 description: Some(
1862 "Pixel clock on falling edge",
1863 ),
1864 value: 1,
1865 },
1866 ],
1867 },
1868 Enum {
1869 name: "Pf",
1870 description: None,
1871 bit_size: 3,
1872 variants: &[
1873 EnumVariant {
1874 name: "ARGB8888",
1875 description: Some(
1876 "ARGB8888",
1877 ),
1878 value: 0,
1879 },
1880 EnumVariant {
1881 name: "RGB888",
1882 description: Some(
1883 "RGB888",
1884 ),
1885 value: 1,
1886 },
1887 EnumVariant {
1888 name: "RGB565",
1889 description: Some(
1890 "RGB565",
1891 ),
1892 value: 2,
1893 },
1894 EnumVariant {
1895 name: "ARGB1555",
1896 description: Some(
1897 "ARGB1555",
1898 ),
1899 value: 3,
1900 },
1901 EnumVariant {
1902 name: "ARGB4444",
1903 description: Some(
1904 "ARGB4444",
1905 ),
1906 value: 4,
1907 },
1908 EnumVariant {
1909 name: "L8",
1910 description: Some(
1911 "L8 (8-bit luminance)",
1912 ),
1913 value: 5,
1914 },
1915 EnumVariant {
1916 name: "AL44",
1917 description: Some(
1918 "AL44 (4-bit alpha, 4-bit luminance)",
1919 ),
1920 value: 6,
1921 },
1922 EnumVariant {
1923 name: "AL88",
1924 description: Some(
1925 "AL88 (8-bit alpha, 8-bit luminance)",
1926 ),
1927 value: 7,
1928 },
1929 ],
1930 },
1931 Enum {
1932 name: "Vbr",
1933 description: None,
1934 bit_size: 1,
1935 variants: &[
1936 EnumVariant {
1937 name: "NO_EFFECT",
1938 description: Some(
1939 "This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set)",
1940 ),
1941 value: 0,
1942 },
1943 EnumVariant {
1944 name: "RELOAD",
1945 description: Some(
1946 "The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area).",
1947 ),
1948 value: 1,
1949 },
1950 ],
1951 },
1952 Enum {
1953 name: "Vspol",
1954 description: None,
1955 bit_size: 1,
1956 variants: &[
1957 EnumVariant {
1958 name: "ACTIVE_LOW",
1959 description: Some(
1960 "Vertical synchronization polarity is active low",
1961 ),
1962 value: 0,
1963 },
1964 EnumVariant {
1965 name: "ACTIVE_HIGH",
1966 description: Some(
1967 "Vertical synchronization polarity is active high",
1968 ),
1969 value: 1,
1970 },
1971 ],
1972 },
1973 ],
1974};
1975