1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Octospi",
7 extends: None,
8 description: Some(
9 "OctoSPI",
10 ),
11 items: &[
12 BlockItem {
13 name: "cr",
14 description: Some(
15 "control register",
16 ),
17 array: None,
18 byte_offset: 0x0,
19 inner: BlockItemInner::Register(
20 Register {
21 access: Access::ReadWrite,
22 bit_size: 32,
23 fieldset: Some(
24 "Cr",
25 ),
26 },
27 ),
28 },
29 BlockItem {
30 name: "dcr1",
31 description: Some(
32 "device configuration register 1",
33 ),
34 array: None,
35 byte_offset: 0x8,
36 inner: BlockItemInner::Register(
37 Register {
38 access: Access::ReadWrite,
39 bit_size: 32,
40 fieldset: Some(
41 "Dcr1",
42 ),
43 },
44 ),
45 },
46 BlockItem {
47 name: "dcr2",
48 description: Some(
49 "device configuration register 2",
50 ),
51 array: None,
52 byte_offset: 0xc,
53 inner: BlockItemInner::Register(
54 Register {
55 access: Access::ReadWrite,
56 bit_size: 32,
57 fieldset: Some(
58 "Dcr2",
59 ),
60 },
61 ),
62 },
63 BlockItem {
64 name: "dcr3",
65 description: Some(
66 "device configuration register 3",
67 ),
68 array: None,
69 byte_offset: 0x10,
70 inner: BlockItemInner::Register(
71 Register {
72 access: Access::ReadWrite,
73 bit_size: 32,
74 fieldset: Some(
75 "Dcr3",
76 ),
77 },
78 ),
79 },
80 BlockItem {
81 name: "dcr4",
82 description: Some(
83 "device configuration register 4",
84 ),
85 array: None,
86 byte_offset: 0x14,
87 inner: BlockItemInner::Register(
88 Register {
89 access: Access::ReadWrite,
90 bit_size: 32,
91 fieldset: Some(
92 "Dcr4",
93 ),
94 },
95 ),
96 },
97 BlockItem {
98 name: "sr",
99 description: Some(
100 "status register",
101 ),
102 array: None,
103 byte_offset: 0x20,
104 inner: BlockItemInner::Register(
105 Register {
106 access: Access::Read,
107 bit_size: 32,
108 fieldset: Some(
109 "Sr",
110 ),
111 },
112 ),
113 },
114 BlockItem {
115 name: "fcr",
116 description: Some(
117 "flag clear register",
118 ),
119 array: None,
120 byte_offset: 0x24,
121 inner: BlockItemInner::Register(
122 Register {
123 access: Access::Write,
124 bit_size: 32,
125 fieldset: Some(
126 "Fcr",
127 ),
128 },
129 ),
130 },
131 BlockItem {
132 name: "dlr",
133 description: Some(
134 "data length register",
135 ),
136 array: None,
137 byte_offset: 0x40,
138 inner: BlockItemInner::Register(
139 Register {
140 access: Access::ReadWrite,
141 bit_size: 32,
142 fieldset: Some(
143 "Dlr",
144 ),
145 },
146 ),
147 },
148 BlockItem {
149 name: "ar",
150 description: Some(
151 "address register",
152 ),
153 array: None,
154 byte_offset: 0x48,
155 inner: BlockItemInner::Register(
156 Register {
157 access: Access::ReadWrite,
158 bit_size: 32,
159 fieldset: Some(
160 "Ar",
161 ),
162 },
163 ),
164 },
165 BlockItem {
166 name: "dr",
167 description: Some(
168 "data register",
169 ),
170 array: None,
171 byte_offset: 0x50,
172 inner: BlockItemInner::Register(
173 Register {
174 access: Access::ReadWrite,
175 bit_size: 32,
176 fieldset: Some(
177 "Dr",
178 ),
179 },
180 ),
181 },
182 BlockItem {
183 name: "psmkr",
184 description: Some(
185 "polling status mask register",
186 ),
187 array: None,
188 byte_offset: 0x80,
189 inner: BlockItemInner::Register(
190 Register {
191 access: Access::ReadWrite,
192 bit_size: 32,
193 fieldset: Some(
194 "Psmkr",
195 ),
196 },
197 ),
198 },
199 BlockItem {
200 name: "psmar",
201 description: Some(
202 "polling status match register",
203 ),
204 array: None,
205 byte_offset: 0x88,
206 inner: BlockItemInner::Register(
207 Register {
208 access: Access::ReadWrite,
209 bit_size: 32,
210 fieldset: Some(
211 "Psmar",
212 ),
213 },
214 ),
215 },
216 BlockItem {
217 name: "pir",
218 description: Some(
219 "polling interval register",
220 ),
221 array: None,
222 byte_offset: 0x90,
223 inner: BlockItemInner::Register(
224 Register {
225 access: Access::ReadWrite,
226 bit_size: 32,
227 fieldset: Some(
228 "Pir",
229 ),
230 },
231 ),
232 },
233 BlockItem {
234 name: "ccr",
235 description: Some(
236 "communication configuration register",
237 ),
238 array: None,
239 byte_offset: 0x100,
240 inner: BlockItemInner::Register(
241 Register {
242 access: Access::ReadWrite,
243 bit_size: 32,
244 fieldset: Some(
245 "Ccr",
246 ),
247 },
248 ),
249 },
250 BlockItem {
251 name: "tcr",
252 description: Some(
253 "timing configuration register",
254 ),
255 array: None,
256 byte_offset: 0x108,
257 inner: BlockItemInner::Register(
258 Register {
259 access: Access::ReadWrite,
260 bit_size: 32,
261 fieldset: Some(
262 "Tcr",
263 ),
264 },
265 ),
266 },
267 BlockItem {
268 name: "ir",
269 description: Some(
270 "instruction register",
271 ),
272 array: None,
273 byte_offset: 0x110,
274 inner: BlockItemInner::Register(
275 Register {
276 access: Access::ReadWrite,
277 bit_size: 32,
278 fieldset: Some(
279 "Ir",
280 ),
281 },
282 ),
283 },
284 BlockItem {
285 name: "abr",
286 description: Some(
287 "alternate bytes register",
288 ),
289 array: None,
290 byte_offset: 0x120,
291 inner: BlockItemInner::Register(
292 Register {
293 access: Access::ReadWrite,
294 bit_size: 32,
295 fieldset: Some(
296 "Abr",
297 ),
298 },
299 ),
300 },
301 BlockItem {
302 name: "lptr",
303 description: Some(
304 "low-power timeout register",
305 ),
306 array: None,
307 byte_offset: 0x130,
308 inner: BlockItemInner::Register(
309 Register {
310 access: Access::ReadWrite,
311 bit_size: 32,
312 fieldset: Some(
313 "Lptr",
314 ),
315 },
316 ),
317 },
318 BlockItem {
319 name: "wpccr",
320 description: Some(
321 "wrap communication configuration register",
322 ),
323 array: None,
324 byte_offset: 0x140,
325 inner: BlockItemInner::Register(
326 Register {
327 access: Access::ReadWrite,
328 bit_size: 32,
329 fieldset: Some(
330 "Wpccr",
331 ),
332 },
333 ),
334 },
335 BlockItem {
336 name: "wptcr",
337 description: Some(
338 "wrap timing configuration register",
339 ),
340 array: None,
341 byte_offset: 0x148,
342 inner: BlockItemInner::Register(
343 Register {
344 access: Access::ReadWrite,
345 bit_size: 32,
346 fieldset: Some(
347 "Wptcr",
348 ),
349 },
350 ),
351 },
352 BlockItem {
353 name: "wpir",
354 description: Some(
355 "wrap instruction register",
356 ),
357 array: None,
358 byte_offset: 0x150,
359 inner: BlockItemInner::Register(
360 Register {
361 access: Access::ReadWrite,
362 bit_size: 32,
363 fieldset: Some(
364 "Wpir",
365 ),
366 },
367 ),
368 },
369 BlockItem {
370 name: "wpabr",
371 description: Some(
372 "wrap alternate bytes register",
373 ),
374 array: None,
375 byte_offset: 0x160,
376 inner: BlockItemInner::Register(
377 Register {
378 access: Access::ReadWrite,
379 bit_size: 32,
380 fieldset: Some(
381 "Wpabr",
382 ),
383 },
384 ),
385 },
386 BlockItem {
387 name: "wccr",
388 description: Some(
389 "write communication configuration register",
390 ),
391 array: None,
392 byte_offset: 0x180,
393 inner: BlockItemInner::Register(
394 Register {
395 access: Access::ReadWrite,
396 bit_size: 32,
397 fieldset: Some(
398 "Wccr",
399 ),
400 },
401 ),
402 },
403 BlockItem {
404 name: "wtcr",
405 description: Some(
406 "write timing configuration register",
407 ),
408 array: None,
409 byte_offset: 0x188,
410 inner: BlockItemInner::Register(
411 Register {
412 access: Access::ReadWrite,
413 bit_size: 32,
414 fieldset: Some(
415 "Wtcr",
416 ),
417 },
418 ),
419 },
420 BlockItem {
421 name: "wir",
422 description: Some(
423 "write instruction register",
424 ),
425 array: None,
426 byte_offset: 0x190,
427 inner: BlockItemInner::Register(
428 Register {
429 access: Access::ReadWrite,
430 bit_size: 32,
431 fieldset: Some(
432 "Wir",
433 ),
434 },
435 ),
436 },
437 BlockItem {
438 name: "wabr",
439 description: Some(
440 "write alternate bytes register",
441 ),
442 array: None,
443 byte_offset: 0x1a0,
444 inner: BlockItemInner::Register(
445 Register {
446 access: Access::ReadWrite,
447 bit_size: 32,
448 fieldset: Some(
449 "Wabr",
450 ),
451 },
452 ),
453 },
454 BlockItem {
455 name: "hlcr",
456 description: Some(
457 "OCTOSPI HyperBus latency configuration register",
458 ),
459 array: None,
460 byte_offset: 0x200,
461 inner: BlockItemInner::Register(
462 Register {
463 access: Access::ReadWrite,
464 bit_size: 32,
465 fieldset: Some(
466 "Hlcr",
467 ),
468 },
469 ),
470 },
471 ],
472 },
473 ],
474 fieldsets: &[
475 FieldSet {
476 name: "Abr",
477 extends: None,
478 description: Some(
479 "alternate bytes register",
480 ),
481 bit_size: 32,
482 fields: &[
483 Field {
484 name: "alternate",
485 description: Some(
486 "Alternate bytes",
487 ),
488 bit_offset: BitOffset::Regular(
489 RegularBitOffset {
490 offset: 0,
491 },
492 ),
493 bit_size: 32,
494 array: None,
495 enumm: None,
496 },
497 ],
498 },
499 FieldSet {
500 name: "Ar",
501 extends: None,
502 description: Some(
503 "address register",
504 ),
505 bit_size: 32,
506 fields: &[
507 Field {
508 name: "address",
509 description: Some(
510 "Address to be sent to the external device. In HyperBus protocol, this field must be even as this protocol is 16-bit word oriented. In dual-memory configuration, AR[0] is forced to 1. Writes to. this field are ignored when BUSY = 1 or when FMODE = 11 (Memory-mapped mode).",
511 ),
512 bit_offset: BitOffset::Regular(
513 RegularBitOffset {
514 offset: 0,
515 },
516 ),
517 bit_size: 32,
518 array: None,
519 enumm: None,
520 },
521 ],
522 },
523 FieldSet {
524 name: "Ccr",
525 extends: None,
526 description: Some(
527 "communication configuration register",
528 ),
529 bit_size: 32,
530 fields: &[
531 Field {
532 name: "imode",
533 description: Some(
534 "Instruction mode. This field defines the instruction phase mode of operation. 101-111: Reserved",
535 ),
536 bit_offset: BitOffset::Regular(
537 RegularBitOffset {
538 offset: 0,
539 },
540 ),
541 bit_size: 3,
542 array: None,
543 enumm: Some(
544 "PhaseMode",
545 ),
546 },
547 Field {
548 name: "idtr",
549 description: Some(
550 "Instruction double transfer rate. This bit sets the DTR mode for the instruction phase.",
551 ),
552 bit_offset: BitOffset::Regular(
553 RegularBitOffset {
554 offset: 3,
555 },
556 ),
557 bit_size: 1,
558 array: None,
559 enumm: None,
560 },
561 Field {
562 name: "isize",
563 description: Some(
564 "Instruction size. This bit defines instruction size.",
565 ),
566 bit_offset: BitOffset::Regular(
567 RegularBitOffset {
568 offset: 4,
569 },
570 ),
571 bit_size: 2,
572 array: None,
573 enumm: Some(
574 "SizeInBits",
575 ),
576 },
577 Field {
578 name: "admode",
579 description: Some(
580 "Address mode. This field defines the address phase mode of operation. 101-111: Reserved",
581 ),
582 bit_offset: BitOffset::Regular(
583 RegularBitOffset {
584 offset: 8,
585 },
586 ),
587 bit_size: 3,
588 array: None,
589 enumm: Some(
590 "PhaseMode",
591 ),
592 },
593 Field {
594 name: "addtr",
595 description: Some(
596 "Address double transfer rate. This bit sets the DTR mode for the address phase.",
597 ),
598 bit_offset: BitOffset::Regular(
599 RegularBitOffset {
600 offset: 11,
601 },
602 ),
603 bit_size: 1,
604 array: None,
605 enumm: None,
606 },
607 Field {
608 name: "adsize",
609 description: Some(
610 "Address size. This field defines address size.",
611 ),
612 bit_offset: BitOffset::Regular(
613 RegularBitOffset {
614 offset: 12,
615 },
616 ),
617 bit_size: 2,
618 array: None,
619 enumm: Some(
620 "SizeInBits",
621 ),
622 },
623 Field {
624 name: "abmode",
625 description: Some(
626 "Alternate-byte mode. This field defines the alternate-byte phase mode of operation. 101-111: Reserved",
627 ),
628 bit_offset: BitOffset::Regular(
629 RegularBitOffset {
630 offset: 16,
631 },
632 ),
633 bit_size: 3,
634 array: None,
635 enumm: Some(
636 "PhaseMode",
637 ),
638 },
639 Field {
640 name: "abdtr",
641 description: Some(
642 "Alternate bytes double transfer rate. This bit sets the DTR mode for the alternate bytes phase. This field can be written only when BUSY = 0.",
643 ),
644 bit_offset: BitOffset::Regular(
645 RegularBitOffset {
646 offset: 19,
647 },
648 ),
649 bit_size: 1,
650 array: None,
651 enumm: None,
652 },
653 Field {
654 name: "absize",
655 description: Some(
656 "Alternate bytes size. This bit defines alternate bytes size.",
657 ),
658 bit_offset: BitOffset::Regular(
659 RegularBitOffset {
660 offset: 20,
661 },
662 ),
663 bit_size: 2,
664 array: None,
665 enumm: Some(
666 "SizeInBits",
667 ),
668 },
669 Field {
670 name: "dmode",
671 description: Some(
672 "Data mode. This field defines the data phase mode of operation. 101-111: Reserved",
673 ),
674 bit_offset: BitOffset::Regular(
675 RegularBitOffset {
676 offset: 24,
677 },
678 ),
679 bit_size: 3,
680 array: None,
681 enumm: Some(
682 "PhaseMode",
683 ),
684 },
685 Field {
686 name: "ddtr",
687 description: Some(
688 "Data double transfer rate. This bit sets the DTR mode for the data phase.",
689 ),
690 bit_offset: BitOffset::Regular(
691 RegularBitOffset {
692 offset: 27,
693 },
694 ),
695 bit_size: 1,
696 array: None,
697 enumm: None,
698 },
699 Field {
700 name: "dqse",
701 description: Some(
702 "DQS enable. This bit enables the data strobe management.",
703 ),
704 bit_offset: BitOffset::Regular(
705 RegularBitOffset {
706 offset: 29,
707 },
708 ),
709 bit_size: 1,
710 array: None,
711 enumm: None,
712 },
713 Field {
714 name: "sioo",
715 description: Some(
716 "Send instruction only once mode. This bit has no effect when IMODE = 00 (see ).",
717 ),
718 bit_offset: BitOffset::Regular(
719 RegularBitOffset {
720 offset: 31,
721 },
722 ),
723 bit_size: 1,
724 array: None,
725 enumm: None,
726 },
727 ],
728 },
729 FieldSet {
730 name: "Cr",
731 extends: None,
732 description: Some(
733 "control register",
734 ),
735 bit_size: 32,
736 fields: &[
737 Field {
738 name: "en",
739 description: Some(
740 "Enable This bit enables the OCTOSPI. Note: The DMA request can be aborted without having received the ACK in case this EN bit is cleared during the operation. In case. this bit is set to 0 during a DMA transfer, the REQ signal to DMA returns to inactive state without waiting for the ACK signal from DMA to be active.",
741 ),
742 bit_offset: BitOffset::Regular(
743 RegularBitOffset {
744 offset: 0,
745 },
746 ),
747 bit_size: 1,
748 array: None,
749 enumm: None,
750 },
751 Field {
752 name: "abort",
753 description: Some(
754 "Abort request. This bit aborts the ongoing command sequence. It is automatically reset once the abort is completed. This bit stops the current transfer. Note: This bit is always read as 0.",
755 ),
756 bit_offset: BitOffset::Regular(
757 RegularBitOffset {
758 offset: 1,
759 },
760 ),
761 bit_size: 1,
762 array: None,
763 enumm: None,
764 },
765 Field {
766 name: "dmaen",
767 description: Some(
768 "DMA enable In Indirect mode, the DMA can be used to input or output data via DR. DMA transfers are initiated when FTF is set. Note: Resetting the DMAEN bit while a DMA transfer is ongoing, breaks the handshake with the DMA. Do not write. this bit during DMA operation.",
769 ),
770 bit_offset: BitOffset::Regular(
771 RegularBitOffset {
772 offset: 2,
773 },
774 ),
775 bit_size: 1,
776 array: None,
777 enumm: None,
778 },
779 Field {
780 name: "tcen",
781 description: Some(
782 "Timeout counter enable. This bit is valid only when the Memory-mapped mode (FMODE[1:0] = 11) is selected. This bit enables the timeout counter.",
783 ),
784 bit_offset: BitOffset::Regular(
785 RegularBitOffset {
786 offset: 3,
787 },
788 ),
789 bit_size: 1,
790 array: None,
791 enumm: None,
792 },
793 Field {
794 name: "dmm",
795 description: Some(
796 "Dual-memory configuration. This bit activates the dual-memory configuration, where two external devices are used simultaneously to double the throughput and the capacity",
797 ),
798 bit_offset: BitOffset::Regular(
799 RegularBitOffset {
800 offset: 6,
801 },
802 ),
803 bit_size: 1,
804 array: None,
805 enumm: None,
806 },
807 Field {
808 name: "fsel",
809 description: Some(
810 "Flash select. This bit selects the Flash memory to be addressed in Single-, Dual-, Quad-SPI mode in single-memory configuration (when DMM = 0). This bit is ignored when DMM = 1 or when Octal-SPI mode is selected.",
811 ),
812 bit_offset: BitOffset::Regular(
813 RegularBitOffset {
814 offset: 7,
815 },
816 ),
817 bit_size: 1,
818 array: None,
819 enumm: Some(
820 "FlashSelect",
821 ),
822 },
823 Field {
824 name: "fthres",
825 description: Some(
826 "FIFO threshold level. This field defines, in Indirect mode, the threshold number of bytes in the FIFO that causes the FIFO threshold flag FTF in SR, to be set. ... Note: If DMAEN = 1, the DMA controller for the corresponding channel must be disabled before changing the FTHRES[4:0] value.",
827 ),
828 bit_offset: BitOffset::Regular(
829 RegularBitOffset {
830 offset: 8,
831 },
832 ),
833 bit_size: 5,
834 array: None,
835 enumm: Some(
836 "Threshold",
837 ),
838 },
839 Field {
840 name: "teie",
841 description: Some(
842 "Transfer error interrupt enable. This bit enables the transfer error interrupt.",
843 ),
844 bit_offset: BitOffset::Regular(
845 RegularBitOffset {
846 offset: 16,
847 },
848 ),
849 bit_size: 1,
850 array: None,
851 enumm: None,
852 },
853 Field {
854 name: "tcie",
855 description: Some(
856 "Transfer complete interrupt enable. This bit enables the transfer complete interrupt.",
857 ),
858 bit_offset: BitOffset::Regular(
859 RegularBitOffset {
860 offset: 17,
861 },
862 ),
863 bit_size: 1,
864 array: None,
865 enumm: None,
866 },
867 Field {
868 name: "ftie",
869 description: Some(
870 "FIFO threshold interrupt enable. This bit enables the FIFO threshold interrupt.",
871 ),
872 bit_offset: BitOffset::Regular(
873 RegularBitOffset {
874 offset: 18,
875 },
876 ),
877 bit_size: 1,
878 array: None,
879 enumm: None,
880 },
881 Field {
882 name: "smie",
883 description: Some(
884 "Status match interrupt enable. This bit enables the status match interrupt.",
885 ),
886 bit_offset: BitOffset::Regular(
887 RegularBitOffset {
888 offset: 19,
889 },
890 ),
891 bit_size: 1,
892 array: None,
893 enumm: None,
894 },
895 Field {
896 name: "toie",
897 description: Some(
898 "Timeout interrupt enable. This bit enables the timeout interrupt.",
899 ),
900 bit_offset: BitOffset::Regular(
901 RegularBitOffset {
902 offset: 20,
903 },
904 ),
905 bit_size: 1,
906 array: None,
907 enumm: None,
908 },
909 Field {
910 name: "apms",
911 description: Some(
912 "Automatic status-polling mode stop. This bit determines if the Automatic status-polling mode is stopped after a match.",
913 ),
914 bit_offset: BitOffset::Regular(
915 RegularBitOffset {
916 offset: 22,
917 },
918 ),
919 bit_size: 1,
920 array: None,
921 enumm: None,
922 },
923 Field {
924 name: "pmm",
925 description: Some(
926 "Polling match mode. This bit indicates which method must be used to determine a match during the Automatic status-polling mode.",
927 ),
928 bit_offset: BitOffset::Regular(
929 RegularBitOffset {
930 offset: 23,
931 },
932 ),
933 bit_size: 1,
934 array: None,
935 enumm: Some(
936 "MatchMode",
937 ),
938 },
939 Field {
940 name: "fmode",
941 description: Some(
942 "Functional mode. This field defines the OCTOSPI functional mode of operation. If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE[1:0] value. If FMODE[1:0] and FTHRES[4:0] are wrongly updated while DMAEN = 1, the DMA request signal automatically goes to inactive state.",
943 ),
944 bit_offset: BitOffset::Regular(
945 RegularBitOffset {
946 offset: 28,
947 },
948 ),
949 bit_size: 2,
950 array: None,
951 enumm: Some(
952 "FunctionalMode",
953 ),
954 },
955 ],
956 },
957 FieldSet {
958 name: "Dcr1",
959 extends: None,
960 description: Some(
961 "device configuration register 1",
962 ),
963 bit_size: 32,
964 fields: &[
965 Field {
966 name: "ckmode",
967 description: Some(
968 "Mode 0/Mode 3 This bit indicates the level taken by the CLK between commands (when NCS = 1).",
969 ),
970 bit_offset: BitOffset::Regular(
971 RegularBitOffset {
972 offset: 0,
973 },
974 ),
975 bit_size: 1,
976 array: None,
977 enumm: None,
978 },
979 Field {
980 name: "frck",
981 description: Some(
982 "Free running clock. This bit configures the free running clock.",
983 ),
984 bit_offset: BitOffset::Regular(
985 RegularBitOffset {
986 offset: 1,
987 },
988 ),
989 bit_size: 1,
990 array: None,
991 enumm: None,
992 },
993 Field {
994 name: "dlybyp",
995 description: Some(
996 "Delay block bypass",
997 ),
998 bit_offset: BitOffset::Regular(
999 RegularBitOffset {
1000 offset: 3,
1001 },
1002 ),
1003 bit_size: 1,
1004 array: None,
1005 enumm: None,
1006 },
1007 Field {
1008 name: "csht",
1009 description: Some(
1010 "Chip-select high time CSHT + 1 defines the minimum number of CLK cycles where the chip-select (NCS) must remain high between commands issued to the external device. ...",
1011 ),
1012 bit_offset: BitOffset::Regular(
1013 RegularBitOffset {
1014 offset: 8,
1015 },
1016 ),
1017 bit_size: 6,
1018 array: None,
1019 enumm: None,
1020 },
1021 Field {
1022 name: "devsize",
1023 description: Some(
1024 "Device size. This field defines the size of the external device using the following formula: Number of bytes in device = 2[DEVSIZE+1]. DEVSIZE+1 is effectively the number of address bits required to address the external device. The device capacity can be up to 4 Gbytes (addressed using 32-bits) in Indirect mode, but the addressable space in Memory-mapped mode is limited to 256 Mbytes. In Regular-command protocol, if DMM = 1, DEVSIZE[4:0] indicates the total capacity of the two devices together.",
1025 ),
1026 bit_offset: BitOffset::Regular(
1027 RegularBitOffset {
1028 offset: 16,
1029 },
1030 ),
1031 bit_size: 5,
1032 array: None,
1033 enumm: None,
1034 },
1035 Field {
1036 name: "mtyp",
1037 description: Some(
1038 "Memory type. This bit indicates the type of memory to be supported. Note: In. this mode, DQS signal polarity is inverted with respect to the memory clock signal. This is the default value and care must be taken to change MTYP[2:0] for memories different from Micron. Others: Reserved",
1039 ),
1040 bit_offset: BitOffset::Regular(
1041 RegularBitOffset {
1042 offset: 24,
1043 },
1044 ),
1045 bit_size: 3,
1046 array: None,
1047 enumm: Some(
1048 "MemType",
1049 ),
1050 },
1051 ],
1052 },
1053 FieldSet {
1054 name: "Dcr2",
1055 extends: None,
1056 description: Some(
1057 "device configuration register 2",
1058 ),
1059 bit_size: 32,
1060 fields: &[
1061 Field {
1062 name: "prescaler",
1063 description: Some(
1064 "Clock prescaler. This field defines the scaler factor for generating the CLK based on the kernel clock (value + 1). 2: FCLK = FKERNEL/3 ... 255: FCLK = FKERNEL/256 For odd clock division factors, the CLK duty cycle is not 50 %. The clock signal remains low one cycle longer than it stays high.",
1065 ),
1066 bit_offset: BitOffset::Regular(
1067 RegularBitOffset {
1068 offset: 0,
1069 },
1070 ),
1071 bit_size: 8,
1072 array: None,
1073 enumm: None,
1074 },
1075 Field {
1076 name: "wrapsize",
1077 description: Some(
1078 "Wrap size. This field indicates the wrap size to which the memory is configured. For memories which have a separate command for wrapped instructions, this field indicates the wrap-size associated with the command held in the OCTOSPI1_WPIR register. 110-111: Reserved",
1079 ),
1080 bit_offset: BitOffset::Regular(
1081 RegularBitOffset {
1082 offset: 16,
1083 },
1084 ),
1085 bit_size: 3,
1086 array: None,
1087 enumm: None,
1088 },
1089 ],
1090 },
1091 FieldSet {
1092 name: "Dcr3",
1093 extends: None,
1094 description: Some(
1095 "device configuration register 3",
1096 ),
1097 bit_size: 32,
1098 fields: &[
1099 Field {
1100 name: "maxtran",
1101 description: Some(
1102 "Maximum transfer",
1103 ),
1104 bit_offset: BitOffset::Regular(
1105 RegularBitOffset {
1106 offset: 0,
1107 },
1108 ),
1109 bit_size: 8,
1110 array: None,
1111 enumm: None,
1112 },
1113 Field {
1114 name: "csbound",
1115 description: Some(
1116 "NCS boundary. This field enables the transaction boundary feature. When active, a minimum value of 3 is recommended. The NCS is released on each boundary of 2CSBOUND bytes. others: NCS boundary set to 2CSBOUND bytes",
1117 ),
1118 bit_offset: BitOffset::Regular(
1119 RegularBitOffset {
1120 offset: 16,
1121 },
1122 ),
1123 bit_size: 5,
1124 array: None,
1125 enumm: None,
1126 },
1127 ],
1128 },
1129 FieldSet {
1130 name: "Dcr4",
1131 extends: None,
1132 description: Some(
1133 "device configuration register 4",
1134 ),
1135 bit_size: 32,
1136 fields: &[
1137 Field {
1138 name: "refresh",
1139 description: Some(
1140 "Refresh rate. This field enables the refresh rate feature. The NCS is released every REFRESH + 1 clock cycles for writes, and REFRESH + 4 clock cycles for reads. Note: These two values can be extended with few clock cycles when refresh occurs during a byte transmission in Single-, Dual- or Quad-SPI mode, because the byte transmission must be completed. others: Maximum communication length is set to REFRESH + 1 clock cycles.",
1141 ),
1142 bit_offset: BitOffset::Regular(
1143 RegularBitOffset {
1144 offset: 0,
1145 },
1146 ),
1147 bit_size: 32,
1148 array: None,
1149 enumm: None,
1150 },
1151 ],
1152 },
1153 FieldSet {
1154 name: "Dlr",
1155 extends: None,
1156 description: Some(
1157 "data length register",
1158 ),
1159 bit_size: 32,
1160 fields: &[
1161 Field {
1162 name: "dl",
1163 description: Some(
1164 "[31: 0]: Data length Number of data to be retrieved (value+1) in Indirect and Automatic status-polling modes. A value not greater than three (indicating 4 bytes) must be used for Automatic status-polling mode. All 1’s in Indirect mode means undefined length, where OCTOSPI continues until the end of the memory, as defined by DEVSIZE. 0x0000_0000: 1 byte is to be transferred. 0x0000_0001: 2 bytes are to be transferred. 0x0000_0002: 3 bytes are to be transferred. 0x0000_0003: 4 bytes are to be transferred. ... 0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred. 0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred. 0xFFFF_FFFF: undefined length; all bytes, until the end of the external device, (as defined by DEVSIZE) are to be transferred. Continue reading indefinitely if DEVSIZE = 0x1F. DL[0] is stuck at 1 in dual-memory configuration (DMM = 1) even when 0 is written to. this bit, thus assuring that each access transfers an even number of bytes. This field has no effect in Memory-mapped mode.",
1165 ),
1166 bit_offset: BitOffset::Regular(
1167 RegularBitOffset {
1168 offset: 0,
1169 },
1170 ),
1171 bit_size: 32,
1172 array: None,
1173 enumm: None,
1174 },
1175 ],
1176 },
1177 FieldSet {
1178 name: "Dr",
1179 extends: None,
1180 description: Some(
1181 "data register",
1182 ),
1183 bit_size: 32,
1184 fields: &[
1185 Field {
1186 name: "data",
1187 description: Some(
1188 "[31: 0]: Data Data to be sent/received to/from the external SPI device In Indirect-write mode, data written to this register is stored on the FIFO before it is sent to the external device during the data phase. If the FIFO is too full, a write operation is stalled until the FIFO has enough space to accept the amount of data being written. In Indirect-read mode, reading this register gives (via the FIFO) the data that was received from the external device. If the FIFO does not have as many bytes as requested by the read operation and if BUSY = 1, the read operation is stalled until enough data is present or until the transfer is complete, whichever happens first. In Automatic status-polling mode, this register contains the last data read from the external device (without masking). Word, half-word, and byte accesses to this register are supported. In Indirect-write mode, a byte write adds 1 byte to the FIFO, a half-word write 2 bytes, and a word write 4 bytes. Similarly, in Indirect-read mode, a byte read removes 1 byte from the FIFO, a halfword read 2 bytes, and a word read 4 bytes. Accesses in Indirect mode must be aligned to the bottom of. this register: A byte read must read DATA[7:0] and a half-word read must read DATA[15:0].",
1189 ),
1190 bit_offset: BitOffset::Regular(
1191 RegularBitOffset {
1192 offset: 0,
1193 },
1194 ),
1195 bit_size: 32,
1196 array: None,
1197 enumm: None,
1198 },
1199 ],
1200 },
1201 FieldSet {
1202 name: "Fcr",
1203 extends: None,
1204 description: Some(
1205 "flag clear register",
1206 ),
1207 bit_size: 32,
1208 fields: &[
1209 Field {
1210 name: "ctef",
1211 description: Some(
1212 "Clear transfer error flag Writing 1 clears the TEF flag in the SR register.",
1213 ),
1214 bit_offset: BitOffset::Regular(
1215 RegularBitOffset {
1216 offset: 0,
1217 },
1218 ),
1219 bit_size: 1,
1220 array: None,
1221 enumm: None,
1222 },
1223 Field {
1224 name: "ctcf",
1225 description: Some(
1226 "Clear transfer complete flag Writing 1 clears the TCF flag in the SR register.",
1227 ),
1228 bit_offset: BitOffset::Regular(
1229 RegularBitOffset {
1230 offset: 1,
1231 },
1232 ),
1233 bit_size: 1,
1234 array: None,
1235 enumm: None,
1236 },
1237 Field {
1238 name: "csmf",
1239 description: Some(
1240 "Clear status match flag Writing 1 clears the SMF flag in the SR register.",
1241 ),
1242 bit_offset: BitOffset::Regular(
1243 RegularBitOffset {
1244 offset: 3,
1245 },
1246 ),
1247 bit_size: 1,
1248 array: None,
1249 enumm: None,
1250 },
1251 Field {
1252 name: "ctof",
1253 description: Some(
1254 "Clear timeout flag Writing 1 clears the TOF flag in the SR register.",
1255 ),
1256 bit_offset: BitOffset::Regular(
1257 RegularBitOffset {
1258 offset: 4,
1259 },
1260 ),
1261 bit_size: 1,
1262 array: None,
1263 enumm: None,
1264 },
1265 ],
1266 },
1267 FieldSet {
1268 name: "Hlcr",
1269 extends: None,
1270 description: Some(
1271 "OCTOSPI HyperBus latency configuration register",
1272 ),
1273 bit_size: 32,
1274 fields: &[
1275 Field {
1276 name: "lm",
1277 description: Some(
1278 "Latency mode. This bit selects the Latency mode.",
1279 ),
1280 bit_offset: BitOffset::Regular(
1281 RegularBitOffset {
1282 offset: 0,
1283 },
1284 ),
1285 bit_size: 1,
1286 array: None,
1287 enumm: Some(
1288 "LatencyMode",
1289 ),
1290 },
1291 Field {
1292 name: "wzl",
1293 description: Some(
1294 "Write zero latency. This bit enables zero latency on write operations.",
1295 ),
1296 bit_offset: BitOffset::Regular(
1297 RegularBitOffset {
1298 offset: 1,
1299 },
1300 ),
1301 bit_size: 1,
1302 array: None,
1303 enumm: None,
1304 },
1305 Field {
1306 name: "tacc",
1307 description: Some(
1308 "[7: 0]: Access time. Device access time expressed in number of communication clock cycles",
1309 ),
1310 bit_offset: BitOffset::Regular(
1311 RegularBitOffset {
1312 offset: 8,
1313 },
1314 ),
1315 bit_size: 8,
1316 array: None,
1317 enumm: None,
1318 },
1319 Field {
1320 name: "trwr",
1321 description: Some(
1322 "Read write recovery time Device read write recovery time expressed in number of communication clock cycles",
1323 ),
1324 bit_offset: BitOffset::Regular(
1325 RegularBitOffset {
1326 offset: 16,
1327 },
1328 ),
1329 bit_size: 8,
1330 array: None,
1331 enumm: None,
1332 },
1333 ],
1334 },
1335 FieldSet {
1336 name: "Ir",
1337 extends: None,
1338 description: Some(
1339 "instruction register",
1340 ),
1341 bit_size: 32,
1342 fields: &[
1343 Field {
1344 name: "instruction",
1345 description: Some(
1346 "Instruction to be sent to the external SPI device",
1347 ),
1348 bit_offset: BitOffset::Regular(
1349 RegularBitOffset {
1350 offset: 0,
1351 },
1352 ),
1353 bit_size: 32,
1354 array: None,
1355 enumm: None,
1356 },
1357 ],
1358 },
1359 FieldSet {
1360 name: "Lptr",
1361 extends: None,
1362 description: Some(
1363 "low-power timeout register",
1364 ),
1365 bit_size: 32,
1366 fields: &[
1367 Field {
1368 name: "timeout",
1369 description: Some(
1370 "[15: 0]: Timeout period After each access in Memory-mapped mode, the OCTOSPI prefetches the subsequent bytes and hold them in the FIFO. This field indicates how many CLK cycles the OCTOSPI waits after the clock becomes inactive and until it raises the NCS, putting the external device in a lower-consumption state.",
1371 ),
1372 bit_offset: BitOffset::Regular(
1373 RegularBitOffset {
1374 offset: 0,
1375 },
1376 ),
1377 bit_size: 16,
1378 array: None,
1379 enumm: None,
1380 },
1381 ],
1382 },
1383 FieldSet {
1384 name: "Pir",
1385 extends: None,
1386 description: Some(
1387 "polling interval register",
1388 ),
1389 bit_size: 32,
1390 fields: &[
1391 Field {
1392 name: "interval",
1393 description: Some(
1394 "[15: 0]: Polling interval Number of CLK cycle between a read during the Automatic status-polling phases",
1395 ),
1396 bit_offset: BitOffset::Regular(
1397 RegularBitOffset {
1398 offset: 0,
1399 },
1400 ),
1401 bit_size: 16,
1402 array: None,
1403 enumm: None,
1404 },
1405 ],
1406 },
1407 FieldSet {
1408 name: "Psmar",
1409 extends: None,
1410 description: Some(
1411 "polling status match register",
1412 ),
1413 bit_size: 32,
1414 fields: &[
1415 Field {
1416 name: "match_",
1417 description: Some(
1418 "[31: 0]: Status match Value to be compared with the masked status register to get a match",
1419 ),
1420 bit_offset: BitOffset::Regular(
1421 RegularBitOffset {
1422 offset: 0,
1423 },
1424 ),
1425 bit_size: 32,
1426 array: None,
1427 enumm: None,
1428 },
1429 ],
1430 },
1431 FieldSet {
1432 name: "Psmkr",
1433 extends: None,
1434 description: Some(
1435 "polling status mask register",
1436 ),
1437 bit_size: 32,
1438 fields: &[
1439 Field {
1440 name: "mask",
1441 description: Some(
1442 "Status mask Mask to be applied to the status bytes received in Automatic status-polling mode For bit n:",
1443 ),
1444 bit_offset: BitOffset::Regular(
1445 RegularBitOffset {
1446 offset: 0,
1447 },
1448 ),
1449 bit_size: 32,
1450 array: None,
1451 enumm: None,
1452 },
1453 ],
1454 },
1455 FieldSet {
1456 name: "Sr",
1457 extends: None,
1458 description: Some(
1459 "status register",
1460 ),
1461 bit_size: 32,
1462 fields: &[
1463 Field {
1464 name: "tef",
1465 description: Some(
1466 "Transfer error flag. This bit is set in Indirect mode when an invalid address is being accessed in Indirect mode. It is cleared by writing 1 to CTEF.",
1467 ),
1468 bit_offset: BitOffset::Regular(
1469 RegularBitOffset {
1470 offset: 0,
1471 },
1472 ),
1473 bit_size: 1,
1474 array: None,
1475 enumm: None,
1476 },
1477 Field {
1478 name: "tcf",
1479 description: Some(
1480 "Transfer complete flag. This bit is set in Indirect mode when the programmed number of data has been transferred or in any mode when the transfer has been aborted.It is cleared by writing 1 to CTCF.",
1481 ),
1482 bit_offset: BitOffset::Regular(
1483 RegularBitOffset {
1484 offset: 1,
1485 },
1486 ),
1487 bit_size: 1,
1488 array: None,
1489 enumm: None,
1490 },
1491 Field {
1492 name: "ftf",
1493 description: Some(
1494 "FIFO threshold flag In Indirect mode, this bit is set when the FIFO threshold has been reached, or if there is any data left in the FIFO after the reads from the external device are complete. It is cleared automatically as soon as the threshold condition is no longer true. In Automatic status-polling mode, this bit is set every time the status register is read, and the bit is cleared when the data register is read.",
1495 ),
1496 bit_offset: BitOffset::Regular(
1497 RegularBitOffset {
1498 offset: 2,
1499 },
1500 ),
1501 bit_size: 1,
1502 array: None,
1503 enumm: None,
1504 },
1505 Field {
1506 name: "smf",
1507 description: Some(
1508 "Status match flag. This bit is set in Automatic status-polling mode when the unmasked received data matches the corresponding bits in the match register (PSMAR). It is cleared by writing 1 to CSMF.",
1509 ),
1510 bit_offset: BitOffset::Regular(
1511 RegularBitOffset {
1512 offset: 3,
1513 },
1514 ),
1515 bit_size: 1,
1516 array: None,
1517 enumm: None,
1518 },
1519 Field {
1520 name: "tof",
1521 description: Some(
1522 "Timeout flag. This bit is set when timeout occurs. It is cleared by writing 1 to CTOF.",
1523 ),
1524 bit_offset: BitOffset::Regular(
1525 RegularBitOffset {
1526 offset: 4,
1527 },
1528 ),
1529 bit_size: 1,
1530 array: None,
1531 enumm: None,
1532 },
1533 Field {
1534 name: "busy",
1535 description: Some(
1536 "Busy. This bit is set when an operation is ongoing. It is cleared automatically when the operation with the external device is finished and the FIFO is empty.",
1537 ),
1538 bit_offset: BitOffset::Regular(
1539 RegularBitOffset {
1540 offset: 5,
1541 },
1542 ),
1543 bit_size: 1,
1544 array: None,
1545 enumm: None,
1546 },
1547 Field {
1548 name: "flevel",
1549 description: Some(
1550 "FIFO level. This field gives the number of valid bytes that are being held in the FIFO. FLEVEL = 0 when the FIFO is empty, and 32 when it is full. In Automatic status-polling mode, FLEVEL is zero.",
1551 ),
1552 bit_offset: BitOffset::Regular(
1553 RegularBitOffset {
1554 offset: 8,
1555 },
1556 ),
1557 bit_size: 6,
1558 array: None,
1559 enumm: None,
1560 },
1561 ],
1562 },
1563 FieldSet {
1564 name: "Tcr",
1565 extends: None,
1566 description: Some(
1567 "timing configuration register",
1568 ),
1569 bit_size: 32,
1570 fields: &[
1571 Field {
1572 name: "dcyc",
1573 description: Some(
1574 "Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least six dummy cycles when using memories with DQS activated.",
1575 ),
1576 bit_offset: BitOffset::Regular(
1577 RegularBitOffset {
1578 offset: 0,
1579 },
1580 ),
1581 bit_size: 5,
1582 array: None,
1583 enumm: None,
1584 },
1585 Field {
1586 name: "dhqc",
1587 description: Some(
1588 "Delay hold quarter cycle",
1589 ),
1590 bit_offset: BitOffset::Regular(
1591 RegularBitOffset {
1592 offset: 28,
1593 },
1594 ),
1595 bit_size: 1,
1596 array: None,
1597 enumm: None,
1598 },
1599 Field {
1600 name: "sshift",
1601 description: Some(
1602 "Sample shift By default, the OCTOSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data to be sampled later in order to consider the external signal delays. The software must ensure that SSHIFT = 0 when the data phase is configured in DTR mode (when DDTR = 1.)",
1603 ),
1604 bit_offset: BitOffset::Regular(
1605 RegularBitOffset {
1606 offset: 30,
1607 },
1608 ),
1609 bit_size: 1,
1610 array: None,
1611 enumm: Some(
1612 "SampleShift",
1613 ),
1614 },
1615 ],
1616 },
1617 FieldSet {
1618 name: "Wabr",
1619 extends: None,
1620 description: Some(
1621 "write alternate bytes register",
1622 ),
1623 bit_size: 32,
1624 fields: &[
1625 Field {
1626 name: "alternate",
1627 description: Some(
1628 "[31: 0]: Alternate bytes. Optional data to be sent to the external SPI device right after the address",
1629 ),
1630 bit_offset: BitOffset::Regular(
1631 RegularBitOffset {
1632 offset: 0,
1633 },
1634 ),
1635 bit_size: 32,
1636 array: None,
1637 enumm: None,
1638 },
1639 ],
1640 },
1641 FieldSet {
1642 name: "Wccr",
1643 extends: None,
1644 description: Some(
1645 "OCTOSPI write communication configuration register",
1646 ),
1647 bit_size: 32,
1648 fields: &[
1649 Field {
1650 name: "imode",
1651 description: Some(
1652 "Instruction mode. This field defines the instruction phase mode of operation. 101-111: Reserved",
1653 ),
1654 bit_offset: BitOffset::Regular(
1655 RegularBitOffset {
1656 offset: 0,
1657 },
1658 ),
1659 bit_size: 3,
1660 array: None,
1661 enumm: Some(
1662 "PhaseMode",
1663 ),
1664 },
1665 Field {
1666 name: "idtr",
1667 description: Some(
1668 "Instruction double transfer rate. This bit sets the DTR mode for the instruction phase.",
1669 ),
1670 bit_offset: BitOffset::Regular(
1671 RegularBitOffset {
1672 offset: 3,
1673 },
1674 ),
1675 bit_size: 1,
1676 array: None,
1677 enumm: None,
1678 },
1679 Field {
1680 name: "isize",
1681 description: Some(
1682 "Instruction size. This bit defines instruction size:",
1683 ),
1684 bit_offset: BitOffset::Regular(
1685 RegularBitOffset {
1686 offset: 4,
1687 },
1688 ),
1689 bit_size: 2,
1690 array: None,
1691 enumm: Some(
1692 "SizeInBits",
1693 ),
1694 },
1695 Field {
1696 name: "admode",
1697 description: Some(
1698 "Address mode. This field defines the address phase mode of operation. 101-111: Reserved",
1699 ),
1700 bit_offset: BitOffset::Regular(
1701 RegularBitOffset {
1702 offset: 8,
1703 },
1704 ),
1705 bit_size: 3,
1706 array: None,
1707 enumm: Some(
1708 "PhaseMode",
1709 ),
1710 },
1711 Field {
1712 name: "addtr",
1713 description: Some(
1714 "Address double transfer rate. This bit sets the DTR mode for the address phase.",
1715 ),
1716 bit_offset: BitOffset::Regular(
1717 RegularBitOffset {
1718 offset: 11,
1719 },
1720 ),
1721 bit_size: 1,
1722 array: None,
1723 enumm: None,
1724 },
1725 Field {
1726 name: "adsize",
1727 description: Some(
1728 "Address size. This field defines address size.",
1729 ),
1730 bit_offset: BitOffset::Regular(
1731 RegularBitOffset {
1732 offset: 12,
1733 },
1734 ),
1735 bit_size: 2,
1736 array: None,
1737 enumm: Some(
1738 "SizeInBits",
1739 ),
1740 },
1741 Field {
1742 name: "abmode",
1743 description: Some(
1744 "Alternate-byte mode. This field defines the alternate-byte phase mode of operation. 101-111: Reserved",
1745 ),
1746 bit_offset: BitOffset::Regular(
1747 RegularBitOffset {
1748 offset: 16,
1749 },
1750 ),
1751 bit_size: 3,
1752 array: None,
1753 enumm: Some(
1754 "PhaseMode",
1755 ),
1756 },
1757 Field {
1758 name: "abdtr",
1759 description: Some(
1760 "Alternate bytes double transfer rate. This bit sets the DTR mode for the alternate-bytes phase.",
1761 ),
1762 bit_offset: BitOffset::Regular(
1763 RegularBitOffset {
1764 offset: 19,
1765 },
1766 ),
1767 bit_size: 1,
1768 array: None,
1769 enumm: None,
1770 },
1771 Field {
1772 name: "absize",
1773 description: Some(
1774 "Alternate bytes size. This field defines alternate bytes size:",
1775 ),
1776 bit_offset: BitOffset::Regular(
1777 RegularBitOffset {
1778 offset: 20,
1779 },
1780 ),
1781 bit_size: 2,
1782 array: None,
1783 enumm: Some(
1784 "SizeInBits",
1785 ),
1786 },
1787 Field {
1788 name: "dmode",
1789 description: Some(
1790 "Data mode. This field defines the data phase mode of operation. 101-111: Reserved",
1791 ),
1792 bit_offset: BitOffset::Regular(
1793 RegularBitOffset {
1794 offset: 24,
1795 },
1796 ),
1797 bit_size: 3,
1798 array: None,
1799 enumm: Some(
1800 "PhaseMode",
1801 ),
1802 },
1803 Field {
1804 name: "ddtr",
1805 description: Some(
1806 "data double transfer rate. This bit sets the DTR mode for the data phase.",
1807 ),
1808 bit_offset: BitOffset::Regular(
1809 RegularBitOffset {
1810 offset: 27,
1811 },
1812 ),
1813 bit_size: 1,
1814 array: None,
1815 enumm: None,
1816 },
1817 Field {
1818 name: "dqse",
1819 description: Some(
1820 "DQS enable. This bit enables the data strobe management.",
1821 ),
1822 bit_offset: BitOffset::Regular(
1823 RegularBitOffset {
1824 offset: 29,
1825 },
1826 ),
1827 bit_size: 1,
1828 array: None,
1829 enumm: None,
1830 },
1831 ],
1832 },
1833 FieldSet {
1834 name: "Wir",
1835 extends: None,
1836 description: Some(
1837 "write instruction register",
1838 ),
1839 bit_size: 32,
1840 fields: &[
1841 Field {
1842 name: "instruction",
1843 description: Some(
1844 "Instruction Instruction to be sent to the external SPI device",
1845 ),
1846 bit_offset: BitOffset::Regular(
1847 RegularBitOffset {
1848 offset: 0,
1849 },
1850 ),
1851 bit_size: 32,
1852 array: None,
1853 enumm: None,
1854 },
1855 ],
1856 },
1857 FieldSet {
1858 name: "Wpabr",
1859 extends: None,
1860 description: Some(
1861 "wrap alternate bytes register",
1862 ),
1863 bit_size: 32,
1864 fields: &[
1865 Field {
1866 name: "alternate",
1867 description: Some(
1868 "[31: 0]: Alternate bytes Optional data to be sent to the external SPI device right after the address",
1869 ),
1870 bit_offset: BitOffset::Regular(
1871 RegularBitOffset {
1872 offset: 0,
1873 },
1874 ),
1875 bit_size: 32,
1876 array: None,
1877 enumm: None,
1878 },
1879 ],
1880 },
1881 FieldSet {
1882 name: "Wpccr",
1883 extends: None,
1884 description: Some(
1885 "OCTOSPI wrap communication configuration register",
1886 ),
1887 bit_size: 32,
1888 fields: &[
1889 Field {
1890 name: "imode",
1891 description: Some(
1892 "Instruction mode. This field defines the instruction phase mode of operation. 101-111: Reserved",
1893 ),
1894 bit_offset: BitOffset::Regular(
1895 RegularBitOffset {
1896 offset: 0,
1897 },
1898 ),
1899 bit_size: 3,
1900 array: None,
1901 enumm: Some(
1902 "PhaseMode",
1903 ),
1904 },
1905 Field {
1906 name: "idtr",
1907 description: Some(
1908 "Instruction double transfer rate. This bit sets the DTR mode for the instruction phase.",
1909 ),
1910 bit_offset: BitOffset::Regular(
1911 RegularBitOffset {
1912 offset: 3,
1913 },
1914 ),
1915 bit_size: 1,
1916 array: None,
1917 enumm: None,
1918 },
1919 Field {
1920 name: "isize",
1921 description: Some(
1922 "Instruction size. This field defines instruction size.",
1923 ),
1924 bit_offset: BitOffset::Regular(
1925 RegularBitOffset {
1926 offset: 4,
1927 },
1928 ),
1929 bit_size: 2,
1930 array: None,
1931 enumm: Some(
1932 "SizeInBits",
1933 ),
1934 },
1935 Field {
1936 name: "admode",
1937 description: Some(
1938 "Address mode. This field defines the address phase mode of operation. 101-111: Reserved",
1939 ),
1940 bit_offset: BitOffset::Regular(
1941 RegularBitOffset {
1942 offset: 8,
1943 },
1944 ),
1945 bit_size: 3,
1946 array: None,
1947 enumm: Some(
1948 "PhaseMode",
1949 ),
1950 },
1951 Field {
1952 name: "addtr",
1953 description: Some(
1954 "Address double transfer rate. This bit sets the DTR mode for the address phase.",
1955 ),
1956 bit_offset: BitOffset::Regular(
1957 RegularBitOffset {
1958 offset: 11,
1959 },
1960 ),
1961 bit_size: 1,
1962 array: None,
1963 enumm: None,
1964 },
1965 Field {
1966 name: "adsize",
1967 description: Some(
1968 "Address size. This field defines address size.",
1969 ),
1970 bit_offset: BitOffset::Regular(
1971 RegularBitOffset {
1972 offset: 12,
1973 },
1974 ),
1975 bit_size: 2,
1976 array: None,
1977 enumm: Some(
1978 "SizeInBits",
1979 ),
1980 },
1981 Field {
1982 name: "abmode",
1983 description: Some(
1984 "Alternate-byte mode. This field defines the alternate byte phase mode of operation. 101-111: Reserved",
1985 ),
1986 bit_offset: BitOffset::Regular(
1987 RegularBitOffset {
1988 offset: 16,
1989 },
1990 ),
1991 bit_size: 3,
1992 array: None,
1993 enumm: Some(
1994 "PhaseMode",
1995 ),
1996 },
1997 Field {
1998 name: "abdtr",
1999 description: Some(
2000 "Alternate bytes double transfer rate. This bit sets the DTR mode for the alternate bytes phase.",
2001 ),
2002 bit_offset: BitOffset::Regular(
2003 RegularBitOffset {
2004 offset: 19,
2005 },
2006 ),
2007 bit_size: 1,
2008 array: None,
2009 enumm: None,
2010 },
2011 Field {
2012 name: "absize",
2013 description: Some(
2014 "Alternate bytes size. This bit defines alternate bytes size.",
2015 ),
2016 bit_offset: BitOffset::Regular(
2017 RegularBitOffset {
2018 offset: 20,
2019 },
2020 ),
2021 bit_size: 2,
2022 array: None,
2023 enumm: Some(
2024 "SizeInBits",
2025 ),
2026 },
2027 Field {
2028 name: "dmode",
2029 description: Some(
2030 "Data mode. This field defines the data phase mode of operation. 101-111: Reserved",
2031 ),
2032 bit_offset: BitOffset::Regular(
2033 RegularBitOffset {
2034 offset: 24,
2035 },
2036 ),
2037 bit_size: 3,
2038 array: None,
2039 enumm: Some(
2040 "PhaseMode",
2041 ),
2042 },
2043 Field {
2044 name: "ddtr",
2045 description: Some(
2046 "Data double transfer rate. This bit sets the DTR mode for the data phase.",
2047 ),
2048 bit_offset: BitOffset::Regular(
2049 RegularBitOffset {
2050 offset: 27,
2051 },
2052 ),
2053 bit_size: 1,
2054 array: None,
2055 enumm: None,
2056 },
2057 Field {
2058 name: "dqse",
2059 description: Some(
2060 "DQS enable. This bit enables the data strobe management.",
2061 ),
2062 bit_offset: BitOffset::Regular(
2063 RegularBitOffset {
2064 offset: 29,
2065 },
2066 ),
2067 bit_size: 1,
2068 array: None,
2069 enumm: None,
2070 },
2071 ],
2072 },
2073 FieldSet {
2074 name: "Wpir",
2075 extends: None,
2076 description: Some(
2077 "wrap instruction register",
2078 ),
2079 bit_size: 32,
2080 fields: &[
2081 Field {
2082 name: "instruction",
2083 description: Some(
2084 "[31: 0]: Instruction Instruction to be sent to the external SPI device",
2085 ),
2086 bit_offset: BitOffset::Regular(
2087 RegularBitOffset {
2088 offset: 0,
2089 },
2090 ),
2091 bit_size: 32,
2092 array: None,
2093 enumm: None,
2094 },
2095 ],
2096 },
2097 FieldSet {
2098 name: "Wptcr",
2099 extends: None,
2100 description: Some(
2101 "wrap timing configuration register",
2102 ),
2103 bit_size: 32,
2104 fields: &[
2105 Field {
2106 name: "dcyc",
2107 description: Some(
2108 "Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated.",
2109 ),
2110 bit_offset: BitOffset::Regular(
2111 RegularBitOffset {
2112 offset: 0,
2113 },
2114 ),
2115 bit_size: 5,
2116 array: None,
2117 enumm: None,
2118 },
2119 Field {
2120 name: "dhqc",
2121 description: Some(
2122 "Delay hold quarter cycle. Add a quarter cycle delay on the outputs in DTR communication to match hold requirement.",
2123 ),
2124 bit_offset: BitOffset::Regular(
2125 RegularBitOffset {
2126 offset: 28,
2127 },
2128 ),
2129 bit_size: 1,
2130 array: None,
2131 enumm: None,
2132 },
2133 Field {
2134 name: "sshift",
2135 description: Some(
2136 "Sample shift By default, the OCTOSPI samples data 1/2 of a CLK cycle after the data is driven by the external device. This bit allows the data to be sampled later in order to consider the external signal delays. The firmware must assure that SSHIFT=0 when the data phase is configured in DTR mode (when DDTR = 1).",
2137 ),
2138 bit_offset: BitOffset::Regular(
2139 RegularBitOffset {
2140 offset: 30,
2141 },
2142 ),
2143 bit_size: 1,
2144 array: None,
2145 enumm: Some(
2146 "SampleShift",
2147 ),
2148 },
2149 ],
2150 },
2151 FieldSet {
2152 name: "Wtcr",
2153 extends: None,
2154 description: Some(
2155 "write timing configuration register",
2156 ),
2157 bit_size: 32,
2158 fields: &[
2159 Field {
2160 name: "dcyc",
2161 description: Some(
2162 "Number of dummy cycles. This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated.",
2163 ),
2164 bit_offset: BitOffset::Regular(
2165 RegularBitOffset {
2166 offset: 0,
2167 },
2168 ),
2169 bit_size: 5,
2170 array: None,
2171 enumm: None,
2172 },
2173 ],
2174 },
2175 ],
2176 enums: &[
2177 Enum {
2178 name: "FlashSelect",
2179 description: None,
2180 bit_size: 1,
2181 variants: &[
2182 EnumVariant {
2183 name: "FLASH_ONE",
2184 description: Some(
2185 "FLASH 1 selected (data exchanged over IO[3:0])",
2186 ),
2187 value: 0,
2188 },
2189 EnumVariant {
2190 name: "FLASH_TWO",
2191 description: Some(
2192 "FLASH 2 selected (data exchanged over IO[7:4])",
2193 ),
2194 value: 1,
2195 },
2196 ],
2197 },
2198 Enum {
2199 name: "FunctionalMode",
2200 description: None,
2201 bit_size: 2,
2202 variants: &[
2203 EnumVariant {
2204 name: "INDIRECT_WRITE",
2205 description: Some(
2206 "Indirect-write mode",
2207 ),
2208 value: 0,
2209 },
2210 EnumVariant {
2211 name: "INDIRECT_READ",
2212 description: Some(
2213 "Indirect-read mode",
2214 ),
2215 value: 1,
2216 },
2217 EnumVariant {
2218 name: "AUTO_STATUS_POLLING",
2219 description: Some(
2220 "Automatic status-polling mode",
2221 ),
2222 value: 2,
2223 },
2224 EnumVariant {
2225 name: "MEMORY_MAPPED",
2226 description: Some(
2227 "Memory-mapped mode",
2228 ),
2229 value: 3,
2230 },
2231 ],
2232 },
2233 Enum {
2234 name: "LatencyMode",
2235 description: None,
2236 bit_size: 1,
2237 variants: &[
2238 EnumVariant {
2239 name: "VARIABLE",
2240 description: Some(
2241 "Variable initial latency",
2242 ),
2243 value: 0,
2244 },
2245 EnumVariant {
2246 name: "FIXED",
2247 description: Some(
2248 "Fixed latency",
2249 ),
2250 value: 1,
2251 },
2252 ],
2253 },
2254 Enum {
2255 name: "MatchMode",
2256 description: None,
2257 bit_size: 1,
2258 variants: &[
2259 EnumVariant {
2260 name: "MATCH_AND",
2261 description: Some(
2262 "AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register.",
2263 ),
2264 value: 0,
2265 },
2266 EnumVariant {
2267 name: "MATCH_OR",
2268 description: Some(
2269 "OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register.",
2270 ),
2271 value: 1,
2272 },
2273 ],
2274 },
2275 Enum {
2276 name: "MemType",
2277 description: None,
2278 bit_size: 3,
2279 variants: &[
2280 EnumVariant {
2281 name: "MICRON",
2282 description: Some(
2283 "Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes.",
2284 ),
2285 value: 0,
2286 },
2287 EnumVariant {
2288 name: "MACRONIX",
2289 description: Some(
2290 "Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes.",
2291 ),
2292 value: 1,
2293 },
2294 EnumVariant {
2295 name: "B_STANDARD",
2296 description: Some(
2297 "Standard mode",
2298 ),
2299 value: 2,
2300 },
2301 EnumVariant {
2302 name: "MACRONIX_RAM",
2303 description: Some(
2304 "Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes with dedicated address mapping.",
2305 ),
2306 value: 3,
2307 },
2308 EnumVariant {
2309 name: "HYPER_BUS_MEMORY",
2310 description: Some(
2311 "HyperBus memory mode, the protocol follows the HyperBus specification. 8-data-bit DTR mode must be selected.",
2312 ),
2313 value: 4,
2314 },
2315 EnumVariant {
2316 name: "HYPER_BUS_REGISTER",
2317 description: Some(
2318 "HyperBus register mode, addressing register space. The memory-mapped accesses in. this mode must be non-cacheable, or Indirect read/write modes must be used.",
2319 ),
2320 value: 5,
2321 },
2322 ],
2323 },
2324 Enum {
2325 name: "PhaseMode",
2326 description: None,
2327 bit_size: 3,
2328 variants: &[
2329 EnumVariant {
2330 name: "NONE",
2331 description: Some(
2332 "No alternate bytes",
2333 ),
2334 value: 0,
2335 },
2336 EnumVariant {
2337 name: "ONE_LINE",
2338 description: Some(
2339 "Alternate bytes on a single line",
2340 ),
2341 value: 1,
2342 },
2343 EnumVariant {
2344 name: "TWO_LINES",
2345 description: Some(
2346 "Alternate bytes on two lines",
2347 ),
2348 value: 2,
2349 },
2350 EnumVariant {
2351 name: "FOUR_LINES",
2352 description: Some(
2353 "Alternate bytes on four lines",
2354 ),
2355 value: 3,
2356 },
2357 EnumVariant {
2358 name: "EIGHT_LINES",
2359 description: Some(
2360 "Alternate bytes on eight lines",
2361 ),
2362 value: 4,
2363 },
2364 ],
2365 },
2366 Enum {
2367 name: "SampleShift",
2368 description: None,
2369 bit_size: 1,
2370 variants: &[
2371 EnumVariant {
2372 name: "NONE",
2373 description: Some(
2374 "No shift",
2375 ),
2376 value: 0,
2377 },
2378 EnumVariant {
2379 name: "HALF_CYCLE",
2380 description: Some(
2381 "1/2 cycle shift",
2382 ),
2383 value: 1,
2384 },
2385 ],
2386 },
2387 Enum {
2388 name: "SizeInBits",
2389 description: None,
2390 bit_size: 2,
2391 variants: &[
2392 EnumVariant {
2393 name: "_8BIT",
2394 description: Some(
2395 "8-bit alternate bytes",
2396 ),
2397 value: 0,
2398 },
2399 EnumVariant {
2400 name: "_16BIT",
2401 description: Some(
2402 "16-bit alternate bytes",
2403 ),
2404 value: 1,
2405 },
2406 EnumVariant {
2407 name: "_24BIT",
2408 description: Some(
2409 "24-bit alternate bytes",
2410 ),
2411 value: 2,
2412 },
2413 EnumVariant {
2414 name: "_32BIT",
2415 description: Some(
2416 "32-bit alternate bytes",
2417 ),
2418 value: 3,
2419 },
2420 ],
2421 },
2422 Enum {
2423 name: "Threshold",
2424 description: None,
2425 bit_size: 5,
2426 variants: &[
2427 EnumVariant {
2428 name: "NEED_ONE_BYTE",
2429 description: Some(
2430 "FTF is set if there are one or more free bytes available to be written to in the FIFO in Indirect-write mode, or if there are one or more valid bytes can be read from the FIFO in Indirect-read mode.",
2431 ),
2432 value: 0,
2433 },
2434 EnumVariant {
2435 name: "NEED_TWO_BYTES",
2436 description: Some(
2437 "FTF is set if there are two or more free bytes available to be written to in the FIFO in Indirect‑write mode, or if there are two or more valid bytes can be read from the FIFO in Indirect-read mode.",
2438 ),
2439 value: 1,
2440 },
2441 EnumVariant {
2442 name: "NEED_THIRTY_TWO_BYTES",
2443 description: Some(
2444 "FTF is set if there are 32 free bytes available to be written to in the FIFO in Indirect-write mode, or if there are 32 valid bytes can be read from the FIFO in Indirect-read mode.",
2445 ),
2446 value: 31,
2447 },
2448 ],
2449 },
2450 ],
2451};
2452