1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[Block {
5 name: "Octospim",
6 extends: None,
7 description: Some("OctoSPI IO Manager"),
8 items: &[
9 BlockItem {
10 name: "cr",
11 description: Some("control register"),
12 array: None,
13 byte_offset: 0x0,
14 inner: BlockItemInner::Register(Register {
15 access: Access::ReadWrite,
16 bit_size: 32,
17 fieldset: Some("Cr"),
18 }),
19 },
20 BlockItem {
21 name: "p1cr",
22 description: Some("OctoSPI IO Manager Port 1 Configuration Register"),
23 array: None,
24 byte_offset: 0x4,
25 inner: BlockItemInner::Register(Register {
26 access: Access::ReadWrite,
27 bit_size: 32,
28 fieldset: Some("P1cr"),
29 }),
30 },
31 BlockItem {
32 name: "p2cr",
33 description: Some("OctoSPI IO Manager Port 2 Configuration Register"),
34 array: None,
35 byte_offset: 0x8,
36 inner: BlockItemInner::Register(Register {
37 access: Access::ReadWrite,
38 bit_size: 32,
39 fieldset: Some("P2cr"),
40 }),
41 },
42 ],
43 }],
44 fieldsets: &[
45 FieldSet {
46 name: "Cr",
47 extends: None,
48 description: Some("control register"),
49 bit_size: 32,
50 fields: &[
51 Field {
52 name: "muxen",
53 description: Some("Multiplexed mode enable"),
54 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
55 bit_size: 1,
56 array: None,
57 enumm: None,
58 },
59 Field {
60 name: "req2ack_time",
61 description: Some("REQ to ACK time"),
62 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
63 bit_size: 8,
64 array: None,
65 enumm: None,
66 },
67 ],
68 },
69 FieldSet {
70 name: "P1cr",
71 extends: None,
72 description: Some("OctoSPI IO Manager Port 1 Configuration Register"),
73 bit_size: 32,
74 fields: &[
75 Field {
76 name: "clken",
77 description: Some("CLK/CLK Enable for Port"),
78 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
79 bit_size: 1,
80 array: None,
81 enumm: None,
82 },
83 Field {
84 name: "clksrc",
85 description: Some("CLK/CLK Source for Port"),
86 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
87 bit_size: 1,
88 array: None,
89 enumm: None,
90 },
91 Field {
92 name: "dqsen",
93 description: Some("DQS Enable for Port"),
94 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
95 bit_size: 1,
96 array: None,
97 enumm: None,
98 },
99 Field {
100 name: "dqssrc",
101 description: Some("DQS Source for Port"),
102 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
103 bit_size: 1,
104 array: None,
105 enumm: None,
106 },
107 Field {
108 name: "ncsen",
109 description: Some("CS Enable for Port"),
110 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
111 bit_size: 1,
112 array: None,
113 enumm: None,
114 },
115 Field {
116 name: "ncssrc",
117 description: Some("CS Source for Port"),
118 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
119 bit_size: 1,
120 array: None,
121 enumm: None,
122 },
123 Field {
124 name: "iolen",
125 description: Some("Enable for Port"),
126 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
127 bit_size: 1,
128 array: None,
129 enumm: None,
130 },
131 Field {
132 name: "iolsrc",
133 description: Some("Source for Port"),
134 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 17 }),
135 bit_size: 2,
136 array: None,
137 enumm: None,
138 },
139 Field {
140 name: "iohen",
141 description: Some("Enable for Port n"),
142 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
143 bit_size: 1,
144 array: None,
145 enumm: None,
146 },
147 Field {
148 name: "iohsrc",
149 description: Some("Source for Port"),
150 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 25 }),
151 bit_size: 2,
152 array: None,
153 enumm: None,
154 },
155 ],
156 },
157 FieldSet {
158 name: "P2cr",
159 extends: None,
160 description: Some("OctoSPI IO Manager Port 2 Configuration Register"),
161 bit_size: 32,
162 fields: &[
163 Field {
164 name: "clken",
165 description: Some("CLK/CLK Enable for Port"),
166 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
167 bit_size: 1,
168 array: None,
169 enumm: None,
170 },
171 Field {
172 name: "clksrc",
173 description: Some("CLK/CLK Source for Port"),
174 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
175 bit_size: 1,
176 array: None,
177 enumm: None,
178 },
179 Field {
180 name: "dqsen",
181 description: Some("DQS Enable for Port"),
182 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
183 bit_size: 1,
184 array: None,
185 enumm: None,
186 },
187 Field {
188 name: "dqssrc",
189 description: Some("DQS Source for Port"),
190 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
191 bit_size: 1,
192 array: None,
193 enumm: None,
194 },
195 Field {
196 name: "ncsen",
197 description: Some("CS Enable for Port"),
198 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
199 bit_size: 1,
200 array: None,
201 enumm: None,
202 },
203 Field {
204 name: "ncssrc",
205 description: Some("CS Source for Port"),
206 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
207 bit_size: 1,
208 array: None,
209 enumm: None,
210 },
211 Field {
212 name: "iolen",
213 description: Some("Enable for Port"),
214 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
215 bit_size: 1,
216 array: None,
217 enumm: None,
218 },
219 Field {
220 name: "iolsrc",
221 description: Some("Source for Port"),
222 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 17 }),
223 bit_size: 2,
224 array: None,
225 enumm: None,
226 },
227 Field {
228 name: "iohen",
229 description: Some("Enable for Port n"),
230 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
231 bit_size: 1,
232 array: None,
233 enumm: None,
234 },
235 Field {
236 name: "iohsrc",
237 description: Some("Source for Port"),
238 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 25 }),
239 bit_size: 2,
240 array: None,
241 enumm: None,
242 },
243 ],
244 },
245 ],
246 enums: &[],
247};
248