1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Pka",
7 extends: None,
8 description: Some(
9 "Public key accelerator.",
10 ),
11 items: &[
12 BlockItem {
13 name: "cr",
14 description: Some(
15 "PKA control register.",
16 ),
17 array: None,
18 byte_offset: 0x0,
19 inner: BlockItemInner::Register(
20 Register {
21 access: Access::ReadWrite,
22 bit_size: 32,
23 fieldset: Some(
24 "Cr",
25 ),
26 },
27 ),
28 },
29 BlockItem {
30 name: "sr",
31 description: Some(
32 "PKA status register.",
33 ),
34 array: None,
35 byte_offset: 0x4,
36 inner: BlockItemInner::Register(
37 Register {
38 access: Access::ReadWrite,
39 bit_size: 32,
40 fieldset: Some(
41 "Sr",
42 ),
43 },
44 ),
45 },
46 BlockItem {
47 name: "clrfr",
48 description: Some(
49 "PKA clear flag register.",
50 ),
51 array: None,
52 byte_offset: 0x8,
53 inner: BlockItemInner::Register(
54 Register {
55 access: Access::ReadWrite,
56 bit_size: 32,
57 fieldset: Some(
58 "Clrfr",
59 ),
60 },
61 ),
62 },
63 BlockItem {
64 name: "ram",
65 description: Some(
66 "PKA internal memeory.",
67 ),
68 array: Some(
69 Array::Regular(
70 RegularArray {
71 len: 1334,
72 stride: 4,
73 },
74 ),
75 ),
76 byte_offset: 0x400,
77 inner: BlockItemInner::Register(
78 Register {
79 access: Access::ReadWrite,
80 bit_size: 32,
81 fieldset: None,
82 },
83 ),
84 },
85 ],
86 },
87 ],
88 fieldsets: &[
89 FieldSet {
90 name: "Clrfr",
91 extends: None,
92 description: Some(
93 "PKA clear flag register.",
94 ),
95 bit_size: 32,
96 fields: &[
97 Field {
98 name: "procendfc",
99 description: Some(
100 "Clear PKA End of Operation flag.",
101 ),
102 bit_offset: BitOffset::Regular(
103 RegularBitOffset {
104 offset: 17,
105 },
106 ),
107 bit_size: 1,
108 array: None,
109 enumm: None,
110 },
111 Field {
112 name: "ramerrfc",
113 description: Some(
114 "Clear PKA RAM error flag.",
115 ),
116 bit_offset: BitOffset::Regular(
117 RegularBitOffset {
118 offset: 19,
119 },
120 ),
121 bit_size: 1,
122 array: None,
123 enumm: None,
124 },
125 Field {
126 name: "addrerrfc",
127 description: Some(
128 "Clear address error flag.",
129 ),
130 bit_offset: BitOffset::Regular(
131 RegularBitOffset {
132 offset: 20,
133 },
134 ),
135 bit_size: 1,
136 array: None,
137 enumm: None,
138 },
139 Field {
140 name: "operrfc",
141 description: Some(
142 "Clear operation error flag.",
143 ),
144 bit_offset: BitOffset::Regular(
145 RegularBitOffset {
146 offset: 21,
147 },
148 ),
149 bit_size: 1,
150 array: None,
151 enumm: None,
152 },
153 ],
154 },
155 FieldSet {
156 name: "Cr",
157 extends: None,
158 description: Some(
159 "PKA control register.",
160 ),
161 bit_size: 32,
162 fields: &[
163 Field {
164 name: "en",
165 description: Some(
166 "PKA enable. When an illegal operation is selected while EN=1 OPERRF bit is set in PKA_SR. See PKA_CR.MODE bitfield for details. When EN=0 PKA RAM can still be accessed by the application.",
167 ),
168 bit_offset: BitOffset::Regular(
169 RegularBitOffset {
170 offset: 0,
171 },
172 ),
173 bit_size: 1,
174 array: None,
175 enumm: None,
176 },
177 Field {
178 name: "start",
179 description: Some(
180 "start the operation Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as 0. When an illegal operation is selected while START bit is set no operation is started, and OPERRF bit is set in PKA_SR. START is ignored if PKA is busy.",
181 ),
182 bit_offset: BitOffset::Regular(
183 RegularBitOffset {
184 offset: 1,
185 },
186 ),
187 bit_size: 1,
188 array: None,
189 enumm: None,
190 },
191 Field {
192 name: "mode",
193 description: Some(
194 "PKA operation code When an operation not listed here is written by the application with EN bit set, OPERRF bit is set in PKA_SR register, and the write to MODE bitfield is ignored. When PKA is configured in limited mode (LMF = 1 in PKA_SR), writing a MODE different from 0x26 with EN bit to 1 triggers OPERRF bit to be set and write to MODE bit is ignored.",
195 ),
196 bit_offset: BitOffset::Regular(
197 RegularBitOffset {
198 offset: 8,
199 },
200 ),
201 bit_size: 6,
202 array: None,
203 enumm: None,
204 },
205 Field {
206 name: "procendie",
207 description: Some(
208 "End of operation interrupt enable.",
209 ),
210 bit_offset: BitOffset::Regular(
211 RegularBitOffset {
212 offset: 17,
213 },
214 ),
215 bit_size: 1,
216 array: None,
217 enumm: None,
218 },
219 Field {
220 name: "ramerrie",
221 description: Some(
222 "RAM error interrupt enable.",
223 ),
224 bit_offset: BitOffset::Regular(
225 RegularBitOffset {
226 offset: 19,
227 },
228 ),
229 bit_size: 1,
230 array: None,
231 enumm: None,
232 },
233 Field {
234 name: "addrerrie",
235 description: Some(
236 "Address error interrupt enable.",
237 ),
238 bit_offset: BitOffset::Regular(
239 RegularBitOffset {
240 offset: 20,
241 },
242 ),
243 bit_size: 1,
244 array: None,
245 enumm: None,
246 },
247 Field {
248 name: "operrie",
249 description: Some(
250 "Operation error interrupt enable.",
251 ),
252 bit_offset: BitOffset::Regular(
253 RegularBitOffset {
254 offset: 21,
255 },
256 ),
257 bit_size: 1,
258 array: None,
259 enumm: None,
260 },
261 ],
262 },
263 FieldSet {
264 name: "Sr",
265 extends: None,
266 description: Some(
267 "PKA status register.",
268 ),
269 bit_size: 32,
270 fields: &[
271 Field {
272 name: "initok",
273 description: Some(
274 "PKA initialization OK This bit is asserted when PKA initialization is complete. When RNG is not able to output proper random numbers INITOK stays at 0.",
275 ),
276 bit_offset: BitOffset::Regular(
277 RegularBitOffset {
278 offset: 0,
279 },
280 ),
281 bit_size: 1,
282 array: None,
283 enumm: None,
284 },
285 Field {
286 name: "busy",
287 description: Some(
288 "PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0).",
289 ),
290 bit_offset: BitOffset::Regular(
291 RegularBitOffset {
292 offset: 16,
293 },
294 ),
295 bit_size: 1,
296 array: None,
297 enumm: None,
298 },
299 Field {
300 name: "procendf",
301 description: Some(
302 "PKA End of Operation flag.",
303 ),
304 bit_offset: BitOffset::Regular(
305 RegularBitOffset {
306 offset: 17,
307 },
308 ),
309 bit_size: 1,
310 array: None,
311 enumm: None,
312 },
313 Field {
314 name: "ramerrf",
315 description: Some(
316 "PKA RAM error flag This bit is cleared using RAMERRFC bit in PKA_CLRFR.",
317 ),
318 bit_offset: BitOffset::Regular(
319 RegularBitOffset {
320 offset: 19,
321 },
322 ),
323 bit_size: 1,
324 array: None,
325 enumm: None,
326 },
327 Field {
328 name: "addrerrf",
329 description: Some(
330 "Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR.",
331 ),
332 bit_offset: BitOffset::Regular(
333 RegularBitOffset {
334 offset: 20,
335 },
336 ),
337 bit_size: 1,
338 array: None,
339 enumm: None,
340 },
341 Field {
342 name: "operrf",
343 description: Some(
344 "Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR.",
345 ),
346 bit_offset: BitOffset::Regular(
347 RegularBitOffset {
348 offset: 21,
349 },
350 ),
351 bit_size: 1,
352 array: None,
353 enumm: None,
354 },
355 ],
356 },
357 ],
358 enums: &[],
359};
360