1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Pssi",
7 extends: None,
8 description: Some(
9 "Parallel synchronous slave interface.",
10 ),
11 items: &[
12 BlockItem {
13 name: "cr",
14 description: Some(
15 "PSSI control register.",
16 ),
17 array: None,
18 byte_offset: 0x0,
19 inner: BlockItemInner::Register(
20 Register {
21 access: Access::ReadWrite,
22 bit_size: 32,
23 fieldset: Some(
24 "Cr",
25 ),
26 },
27 ),
28 },
29 BlockItem {
30 name: "sr",
31 description: Some(
32 "PSSI status register.",
33 ),
34 array: None,
35 byte_offset: 0x4,
36 inner: BlockItemInner::Register(
37 Register {
38 access: Access::ReadWrite,
39 bit_size: 32,
40 fieldset: Some(
41 "Sr",
42 ),
43 },
44 ),
45 },
46 BlockItem {
47 name: "ris",
48 description: Some(
49 "PSSI raw interrupt status register.",
50 ),
51 array: None,
52 byte_offset: 0x8,
53 inner: BlockItemInner::Register(
54 Register {
55 access: Access::ReadWrite,
56 bit_size: 32,
57 fieldset: Some(
58 "Ris",
59 ),
60 },
61 ),
62 },
63 BlockItem {
64 name: "ier",
65 description: Some(
66 "PSSI interrupt enable register.",
67 ),
68 array: None,
69 byte_offset: 0xc,
70 inner: BlockItemInner::Register(
71 Register {
72 access: Access::ReadWrite,
73 bit_size: 32,
74 fieldset: Some(
75 "Ier",
76 ),
77 },
78 ),
79 },
80 BlockItem {
81 name: "mis",
82 description: Some(
83 "PSSI masked interrupt status register.",
84 ),
85 array: None,
86 byte_offset: 0x10,
87 inner: BlockItemInner::Register(
88 Register {
89 access: Access::ReadWrite,
90 bit_size: 32,
91 fieldset: Some(
92 "Mis",
93 ),
94 },
95 ),
96 },
97 BlockItem {
98 name: "icr",
99 description: Some(
100 "PSSI interrupt clear register.",
101 ),
102 array: None,
103 byte_offset: 0x14,
104 inner: BlockItemInner::Register(
105 Register {
106 access: Access::ReadWrite,
107 bit_size: 32,
108 fieldset: Some(
109 "Icr",
110 ),
111 },
112 ),
113 },
114 BlockItem {
115 name: "dr",
116 description: Some(
117 "PSSI data register.",
118 ),
119 array: None,
120 byte_offset: 0x28,
121 inner: BlockItemInner::Register(
122 Register {
123 access: Access::ReadWrite,
124 bit_size: 32,
125 fieldset: Some(
126 "Dr",
127 ),
128 },
129 ),
130 },
131 ],
132 },
133 ],
134 fieldsets: &[
135 FieldSet {
136 name: "Cr",
137 extends: None,
138 description: Some(
139 "PSSI control register.",
140 ),
141 bit_size: 32,
142 fields: &[
143 Field {
144 name: "ckpol",
145 description: Some(
146 "Parallel data clock polarity This bit configures the capture edge of the parallel clock or the edge used for driving outputs, depending on OUTEN.",
147 ),
148 bit_offset: BitOffset::Regular(
149 RegularBitOffset {
150 offset: 5,
151 },
152 ),
153 bit_size: 1,
154 array: None,
155 enumm: Some(
156 "Ckpol",
157 ),
158 },
159 Field {
160 name: "depol",
161 description: Some(
162 "Data enable (PSSI_DE) polarity This bit indicates the level on the PSSI_DE pin when the data are not valid on the parallel interface.",
163 ),
164 bit_offset: BitOffset::Regular(
165 RegularBitOffset {
166 offset: 6,
167 },
168 ),
169 bit_size: 1,
170 array: None,
171 enumm: Some(
172 "Depol",
173 ),
174 },
175 Field {
176 name: "rdypol",
177 description: Some(
178 "Ready (PSSI_RDY) polarity This bit indicates the level on the PSSI_RDY pin when the data are not valid on the parallel interface.",
179 ),
180 bit_offset: BitOffset::Regular(
181 RegularBitOffset {
182 offset: 8,
183 },
184 ),
185 bit_size: 1,
186 array: None,
187 enumm: Some(
188 "Rdypol",
189 ),
190 },
191 Field {
192 name: "edm",
193 description: Some(
194 "Extended data mode.",
195 ),
196 bit_offset: BitOffset::Regular(
197 RegularBitOffset {
198 offset: 10,
199 },
200 ),
201 bit_size: 2,
202 array: None,
203 enumm: Some(
204 "Edm",
205 ),
206 },
207 Field {
208 name: "enable",
209 description: Some(
210 "PSSI enable The contents of the FIFO are flushed when ENABLE is cleared to 0. Note: When ENABLE=1, the content of PSSI_CR must not be changed, except for the ENABLE bit itself. All configuration bits can change as soon as ENABLE changes from 0 to 1. The DMA controller and all PSSI configuration registers must be programmed correctly before setting the ENABLE bit to 1. The ENABLE bit and the DCMI ENABLE bit (bit 15 of DCMI_CR) must not be set to 1 at the same time.",
211 ),
212 bit_offset: BitOffset::Regular(
213 RegularBitOffset {
214 offset: 14,
215 },
216 ),
217 bit_size: 1,
218 array: None,
219 enumm: None,
220 },
221 Field {
222 name: "derdycfg",
223 description: Some(
224 "Data enable and ready configuration When the PSSI_RDY function is mapped to the PSSI_DE pin (settings 101 or 111), it is still the RDYPOL bit which determines its polarity. Similarly, when the PSSI_DE function is mapped to the PSSI_RDY pin (settings 110 or 111), it is still the DEPOL bit which determines its polarity.",
225 ),
226 bit_offset: BitOffset::Regular(
227 RegularBitOffset {
228 offset: 18,
229 },
230 ),
231 bit_size: 3,
232 array: None,
233 enumm: Some(
234 "Derdycfg",
235 ),
236 },
237 Field {
238 name: "dmaen",
239 description: Some(
240 "DMA enable bit.",
241 ),
242 bit_offset: BitOffset::Regular(
243 RegularBitOffset {
244 offset: 30,
245 },
246 ),
247 bit_size: 1,
248 array: None,
249 enumm: None,
250 },
251 Field {
252 name: "outen",
253 description: Some(
254 "Data direction selection bit.",
255 ),
256 bit_offset: BitOffset::Regular(
257 RegularBitOffset {
258 offset: 31,
259 },
260 ),
261 bit_size: 1,
262 array: None,
263 enumm: Some(
264 "Outen",
265 ),
266 },
267 ],
268 },
269 FieldSet {
270 name: "Dr",
271 extends: None,
272 description: Some(
273 "PSSI data register.",
274 ),
275 bit_size: 32,
276 fields: &[
277 Field {
278 name: "byte",
279 description: Some(
280 "Data byte 0.",
281 ),
282 bit_offset: BitOffset::Regular(
283 RegularBitOffset {
284 offset: 0,
285 },
286 ),
287 bit_size: 8,
288 array: Some(
289 Array::Regular(
290 RegularArray {
291 len: 4,
292 stride: 8,
293 },
294 ),
295 ),
296 enumm: None,
297 },
298 ],
299 },
300 FieldSet {
301 name: "Icr",
302 extends: None,
303 description: Some(
304 "PSSI interrupt clear register.",
305 ),
306 bit_size: 32,
307 fields: &[
308 Field {
309 name: "ovr_isc",
310 description: Some(
311 "Data buffer overrun/underrun interrupt status clear Writing this bit to 1 clears the OVR_RIS bit in PSSI_RIS.",
312 ),
313 bit_offset: BitOffset::Regular(
314 RegularBitOffset {
315 offset: 1,
316 },
317 ),
318 bit_size: 1,
319 array: None,
320 enumm: None,
321 },
322 ],
323 },
324 FieldSet {
325 name: "Ier",
326 extends: None,
327 description: Some(
328 "PSSI interrupt enable register.",
329 ),
330 bit_size: 32,
331 fields: &[
332 Field {
333 name: "ovr_ie",
334 description: Some(
335 "Data buffer overrun/underrun interrupt enable.",
336 ),
337 bit_offset: BitOffset::Regular(
338 RegularBitOffset {
339 offset: 1,
340 },
341 ),
342 bit_size: 1,
343 array: None,
344 enumm: None,
345 },
346 ],
347 },
348 FieldSet {
349 name: "Mis",
350 extends: None,
351 description: Some(
352 "PSSI masked interrupt status register.",
353 ),
354 bit_size: 32,
355 fields: &[
356 Field {
357 name: "ovr_mis",
358 description: Some(
359 "Data buffer overrun/underrun masked interrupt status This bit is set to 1 only when PSSI_IER/OVR_IE and PSSI_RIS/OVR_RIS are both set to 1.",
360 ),
361 bit_offset: BitOffset::Regular(
362 RegularBitOffset {
363 offset: 1,
364 },
365 ),
366 bit_size: 1,
367 array: None,
368 enumm: None,
369 },
370 ],
371 },
372 FieldSet {
373 name: "Ris",
374 extends: None,
375 description: Some(
376 "PSSI raw interrupt status register.",
377 ),
378 bit_size: 32,
379 fields: &[
380 Field {
381 name: "ovr_ris",
382 description: Some(
383 "Data buffer overrun/underrun raw interrupt status This bit is cleared by writing a 1 to the OVR_ISC bit in PSSI_ICR.",
384 ),
385 bit_offset: BitOffset::Regular(
386 RegularBitOffset {
387 offset: 1,
388 },
389 ),
390 bit_size: 1,
391 array: None,
392 enumm: None,
393 },
394 ],
395 },
396 FieldSet {
397 name: "Sr",
398 extends: None,
399 description: Some(
400 "PSSI status register.",
401 ),
402 bit_size: 32,
403 fields: &[
404 Field {
405 name: "rtt4b",
406 description: Some(
407 "FIFO is ready to transfer four bytes.",
408 ),
409 bit_offset: BitOffset::Regular(
410 RegularBitOffset {
411 offset: 2,
412 },
413 ),
414 bit_size: 1,
415 array: None,
416 enumm: None,
417 },
418 Field {
419 name: "rtt1b",
420 description: Some(
421 "FIFO is ready to transfer one byte.",
422 ),
423 bit_offset: BitOffset::Regular(
424 RegularBitOffset {
425 offset: 3,
426 },
427 ),
428 bit_size: 1,
429 array: None,
430 enumm: None,
431 },
432 ],
433 },
434 ],
435 enums: &[
436 Enum {
437 name: "Ckpol",
438 description: None,
439 bit_size: 1,
440 variants: &[
441 EnumVariant {
442 name: "FALLING_EDGE",
443 description: Some(
444 "Falling edge active for inputs or rising edge active for outputs.",
445 ),
446 value: 0,
447 },
448 EnumVariant {
449 name: "RISING_EDGE",
450 description: Some(
451 "Rising edge active for inputs or falling edge active for outputs.",
452 ),
453 value: 1,
454 },
455 ],
456 },
457 Enum {
458 name: "Depol",
459 description: None,
460 bit_size: 1,
461 variants: &[
462 EnumVariant {
463 name: "ACTIVE_LOW",
464 description: Some(
465 "PSSI_DE active low (0 indicates that data is valid).",
466 ),
467 value: 0,
468 },
469 EnumVariant {
470 name: "ACTIVE_HIGH",
471 description: Some(
472 "PSSI_DE active high (1 indicates that data is valid).",
473 ),
474 value: 1,
475 },
476 ],
477 },
478 Enum {
479 name: "Derdycfg",
480 description: None,
481 bit_size: 3,
482 variants: &[
483 EnumVariant {
484 name: "DISABLED",
485 description: Some(
486 "PSSI_DE and PSSI_RDY both disabled.",
487 ),
488 value: 0,
489 },
490 EnumVariant {
491 name: "RDY",
492 description: Some(
493 "Only PSSI_RDY enabled.",
494 ),
495 value: 1,
496 },
497 EnumVariant {
498 name: "DE",
499 description: Some(
500 "Only PSSI_DE enabled.",
501 ),
502 value: 2,
503 },
504 EnumVariant {
505 name: "RDY_DE_ALT",
506 description: Some(
507 "Both PSSI_RDY and PSSI_DE alternate functions enabled.",
508 ),
509 value: 3,
510 },
511 EnumVariant {
512 name: "RDY_DE",
513 description: Some(
514 "Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_RDY pin.",
515 ),
516 value: 4,
517 },
518 EnumVariant {
519 name: "RDY_REMAPPED",
520 description: Some(
521 "Only PSSI_RDY function enabled, but mapped to PSSI_DE pin.",
522 ),
523 value: 5,
524 },
525 EnumVariant {
526 name: "DE_REMAPPED",
527 description: Some(
528 "Only PSSI_DE function enabled, but mapped to PSSI_RDY pin.",
529 ),
530 value: 6,
531 },
532 EnumVariant {
533 name: "RDY_DE_BIDI",
534 description: Some(
535 "Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_DE pin.",
536 ),
537 value: 7,
538 },
539 ],
540 },
541 Enum {
542 name: "Edm",
543 description: None,
544 bit_size: 2,
545 variants: &[
546 EnumVariant {
547 name: "BIT_WIDTH8",
548 description: Some(
549 "Interface captures 8-bit data on every parallel data clock.",
550 ),
551 value: 0,
552 },
553 EnumVariant {
554 name: "BIT_WIDTH16",
555 description: Some(
556 "The interface captures 16-bit data on every parallel data clock.",
557 ),
558 value: 3,
559 },
560 ],
561 },
562 Enum {
563 name: "Outen",
564 description: None,
565 bit_size: 1,
566 variants: &[
567 EnumVariant {
568 name: "RECEIVE_MODE",
569 description: Some(
570 "Data is input synchronously with PSSI_PDCK.",
571 ),
572 value: 0,
573 },
574 EnumVariant {
575 name: "TRANSMIT_MODE",
576 description: Some(
577 "Data is output synchronously with PSSI_PDCK.",
578 ),
579 value: 1,
580 },
581 ],
582 },
583 Enum {
584 name: "Rdypol",
585 description: None,
586 bit_size: 1,
587 variants: &[
588 EnumVariant {
589 name: "ACTIVE_LOW",
590 description: Some(
591 "PSSI_RDY active low (0 indicates that the receiver is ready to receive).",
592 ),
593 value: 0,
594 },
595 EnumVariant {
596 name: "ACTIVE_HIGH",
597 description: Some(
598 "PSSI_RDY active high (1 indicates that the receiver is ready to receive).",
599 ),
600 value: 1,
601 },
602 ],
603 },
604 ],
605};
606