1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Pwr",
7 extends: None,
8 description: Some(
9 "Power control",
10 ),
11 items: &[
12 BlockItem {
13 name: "cr1",
14 description: Some(
15 "control register 1",
16 ),
17 array: None,
18 byte_offset: 0x0,
19 inner: BlockItemInner::Register(
20 Register {
21 access: Access::ReadWrite,
22 bit_size: 32,
23 fieldset: Some(
24 "Cr1",
25 ),
26 },
27 ),
28 },
29 BlockItem {
30 name: "cr2",
31 description: Some(
32 "control register 2",
33 ),
34 array: None,
35 byte_offset: 0x4,
36 inner: BlockItemInner::Register(
37 Register {
38 access: Access::ReadWrite,
39 bit_size: 32,
40 fieldset: Some(
41 "Cr2",
42 ),
43 },
44 ),
45 },
46 BlockItem {
47 name: "cr3",
48 description: Some(
49 "control register 3",
50 ),
51 array: None,
52 byte_offset: 0x8,
53 inner: BlockItemInner::Register(
54 Register {
55 access: Access::ReadWrite,
56 bit_size: 32,
57 fieldset: Some(
58 "Cr3",
59 ),
60 },
61 ),
62 },
63 BlockItem {
64 name: "vosr",
65 description: Some(
66 "voltage scaling register",
67 ),
68 array: None,
69 byte_offset: 0xc,
70 inner: BlockItemInner::Register(
71 Register {
72 access: Access::ReadWrite,
73 bit_size: 32,
74 fieldset: Some(
75 "Vosr",
76 ),
77 },
78 ),
79 },
80 BlockItem {
81 name: "svmcr",
82 description: Some(
83 "supply voltage monitoring control register",
84 ),
85 array: None,
86 byte_offset: 0x10,
87 inner: BlockItemInner::Register(
88 Register {
89 access: Access::ReadWrite,
90 bit_size: 32,
91 fieldset: Some(
92 "Svmcr",
93 ),
94 },
95 ),
96 },
97 BlockItem {
98 name: "wucr1",
99 description: Some(
100 "wakeup control register 1",
101 ),
102 array: None,
103 byte_offset: 0x14,
104 inner: BlockItemInner::Register(
105 Register {
106 access: Access::ReadWrite,
107 bit_size: 32,
108 fieldset: Some(
109 "Wucr1",
110 ),
111 },
112 ),
113 },
114 BlockItem {
115 name: "wucr2",
116 description: Some(
117 "wakeup control register 2",
118 ),
119 array: None,
120 byte_offset: 0x18,
121 inner: BlockItemInner::Register(
122 Register {
123 access: Access::ReadWrite,
124 bit_size: 32,
125 fieldset: Some(
126 "Wucr2",
127 ),
128 },
129 ),
130 },
131 BlockItem {
132 name: "wucr3",
133 description: Some(
134 "wakeup control register 3",
135 ),
136 array: None,
137 byte_offset: 0x1c,
138 inner: BlockItemInner::Register(
139 Register {
140 access: Access::ReadWrite,
141 bit_size: 32,
142 fieldset: Some(
143 "Wucr3",
144 ),
145 },
146 ),
147 },
148 BlockItem {
149 name: "bdcr1",
150 description: Some(
151 "Backup domain control register 1",
152 ),
153 array: None,
154 byte_offset: 0x20,
155 inner: BlockItemInner::Register(
156 Register {
157 access: Access::ReadWrite,
158 bit_size: 32,
159 fieldset: Some(
160 "Bdcr1",
161 ),
162 },
163 ),
164 },
165 BlockItem {
166 name: "bdcr2",
167 description: Some(
168 "Backup domain control register 2",
169 ),
170 array: None,
171 byte_offset: 0x24,
172 inner: BlockItemInner::Register(
173 Register {
174 access: Access::ReadWrite,
175 bit_size: 32,
176 fieldset: Some(
177 "Bdcr2",
178 ),
179 },
180 ),
181 },
182 BlockItem {
183 name: "dbpcr",
184 description: Some(
185 "disable Backup domain register",
186 ),
187 array: None,
188 byte_offset: 0x28,
189 inner: BlockItemInner::Register(
190 Register {
191 access: Access::ReadWrite,
192 bit_size: 32,
193 fieldset: Some(
194 "Dbpcr",
195 ),
196 },
197 ),
198 },
199 BlockItem {
200 name: "ucpdr",
201 description: Some(
202 "USB Type-C™ and Power Delivery register",
203 ),
204 array: None,
205 byte_offset: 0x2c,
206 inner: BlockItemInner::Register(
207 Register {
208 access: Access::ReadWrite,
209 bit_size: 32,
210 fieldset: Some(
211 "Ucpdr",
212 ),
213 },
214 ),
215 },
216 BlockItem {
217 name: "seccfgr",
218 description: Some(
219 "security configuration register",
220 ),
221 array: None,
222 byte_offset: 0x30,
223 inner: BlockItemInner::Register(
224 Register {
225 access: Access::ReadWrite,
226 bit_size: 32,
227 fieldset: Some(
228 "Seccfgr",
229 ),
230 },
231 ),
232 },
233 BlockItem {
234 name: "privcfgr",
235 description: Some(
236 "privilege control register",
237 ),
238 array: None,
239 byte_offset: 0x34,
240 inner: BlockItemInner::Register(
241 Register {
242 access: Access::ReadWrite,
243 bit_size: 32,
244 fieldset: Some(
245 "Privcfgr",
246 ),
247 },
248 ),
249 },
250 BlockItem {
251 name: "sr",
252 description: Some(
253 "status register",
254 ),
255 array: None,
256 byte_offset: 0x38,
257 inner: BlockItemInner::Register(
258 Register {
259 access: Access::ReadWrite,
260 bit_size: 32,
261 fieldset: Some(
262 "Sr",
263 ),
264 },
265 ),
266 },
267 BlockItem {
268 name: "svmsr",
269 description: None,
270 array: None,
271 byte_offset: 0x3c,
272 inner: BlockItemInner::Register(
273 Register {
274 access: Access::ReadWrite,
275 bit_size: 32,
276 fieldset: Some(
277 "Svmsr",
278 ),
279 },
280 ),
281 },
282 BlockItem {
283 name: "bdsr",
284 description: Some(
285 "Backup domain status register",
286 ),
287 array: None,
288 byte_offset: 0x40,
289 inner: BlockItemInner::Register(
290 Register {
291 access: Access::ReadWrite,
292 bit_size: 32,
293 fieldset: Some(
294 "Bdsr",
295 ),
296 },
297 ),
298 },
299 BlockItem {
300 name: "wusr",
301 description: Some(
302 "wakeup status register",
303 ),
304 array: None,
305 byte_offset: 0x44,
306 inner: BlockItemInner::Register(
307 Register {
308 access: Access::ReadWrite,
309 bit_size: 32,
310 fieldset: Some(
311 "Wusr",
312 ),
313 },
314 ),
315 },
316 BlockItem {
317 name: "wuscr",
318 description: Some(
319 "wakeup status clear register",
320 ),
321 array: None,
322 byte_offset: 0x48,
323 inner: BlockItemInner::Register(
324 Register {
325 access: Access::ReadWrite,
326 bit_size: 32,
327 fieldset: Some(
328 "Wuscr",
329 ),
330 },
331 ),
332 },
333 BlockItem {
334 name: "apcr",
335 description: Some(
336 "apply pull configuration register",
337 ),
338 array: None,
339 byte_offset: 0x4c,
340 inner: BlockItemInner::Register(
341 Register {
342 access: Access::ReadWrite,
343 bit_size: 32,
344 fieldset: Some(
345 "Apcr",
346 ),
347 },
348 ),
349 },
350 BlockItem {
351 name: "pucr",
352 description: Some(
353 "Power Port pull-up control register",
354 ),
355 array: Some(
356 Array::Regular(
357 RegularArray {
358 len: 9,
359 stride: 8,
360 },
361 ),
362 ),
363 byte_offset: 0x50,
364 inner: BlockItemInner::Register(
365 Register {
366 access: Access::ReadWrite,
367 bit_size: 32,
368 fieldset: Some(
369 "Pcr",
370 ),
371 },
372 ),
373 },
374 BlockItem {
375 name: "pdcr",
376 description: Some(
377 "Power Port pull-down control register",
378 ),
379 array: Some(
380 Array::Regular(
381 RegularArray {
382 len: 9,
383 stride: 8,
384 },
385 ),
386 ),
387 byte_offset: 0x54,
388 inner: BlockItemInner::Register(
389 Register {
390 access: Access::ReadWrite,
391 bit_size: 32,
392 fieldset: Some(
393 "Pcr",
394 ),
395 },
396 ),
397 },
398 ],
399 },
400 ],
401 fieldsets: &[
402 FieldSet {
403 name: "Apcr",
404 extends: None,
405 description: Some(
406 "apply pull configuration register",
407 ),
408 bit_size: 32,
409 fields: &[
410 Field {
411 name: "apc",
412 description: Some(
413 "Apply pull-up and pull-down configuration\r When this bit is set, the I/O pull-up and pull-down configurations defined in PUCRx and PDCRx are applied. When this bit is cleared, PUCRx and PDCRx are not applied to the I/Os.",
414 ),
415 bit_offset: BitOffset::Regular(
416 RegularBitOffset {
417 offset: 0,
418 },
419 ),
420 bit_size: 1,
421 array: None,
422 enumm: None,
423 },
424 ],
425 },
426 FieldSet {
427 name: "Bdcr1",
428 extends: None,
429 description: Some(
430 "Backup domain control register 1",
431 ),
432 bit_size: 32,
433 fields: &[
434 Field {
435 name: "bren",
436 description: Some(
437 "Backup RAM retention in Standby and VBAT modes\r When this bit is set, the backup RAM content is kept in Standby and VBAT modes.\r If BREN is reset, the backup RAM can still be used in Run, Sleep and Stop modes. However, its content is lost in Standby, Shutdown and VBAT modes. This bit can be written only when the regulator is LDO, which must be configured before switching to SMPS.\r Note: Backup RAM cannot be preserved in Shutdown mode.",
438 ),
439 bit_offset: BitOffset::Regular(
440 RegularBitOffset {
441 offset: 0,
442 },
443 ),
444 bit_size: 1,
445 array: None,
446 enumm: None,
447 },
448 Field {
449 name: "monen",
450 description: Some(
451 "Backup domain voltage and temperature monitoring enable",
452 ),
453 bit_offset: BitOffset::Regular(
454 RegularBitOffset {
455 offset: 4,
456 },
457 ),
458 bit_size: 1,
459 array: None,
460 enumm: None,
461 },
462 ],
463 },
464 FieldSet {
465 name: "Bdcr2",
466 extends: None,
467 description: Some(
468 "Backup domain control register 2",
469 ),
470 bit_size: 32,
471 fields: &[
472 Field {
473 name: "vbe",
474 description: Some(
475 "VBAT charging enable",
476 ),
477 bit_offset: BitOffset::Regular(
478 RegularBitOffset {
479 offset: 0,
480 },
481 ),
482 bit_size: 1,
483 array: None,
484 enumm: Some(
485 "Vbe",
486 ),
487 },
488 Field {
489 name: "vbrs",
490 description: Some(
491 "VBAT charging resistor selection",
492 ),
493 bit_offset: BitOffset::Regular(
494 RegularBitOffset {
495 offset: 1,
496 },
497 ),
498 bit_size: 1,
499 array: None,
500 enumm: Some(
501 "Vbrs",
502 ),
503 },
504 ],
505 },
506 FieldSet {
507 name: "Bdsr",
508 extends: None,
509 description: Some(
510 "Backup domain status register",
511 ),
512 bit_size: 32,
513 fields: &[
514 Field {
515 name: "vbath",
516 description: Some(
517 "Backup domain voltage level monitoring versus high threshold",
518 ),
519 bit_offset: BitOffset::Regular(
520 RegularBitOffset {
521 offset: 1,
522 },
523 ),
524 bit_size: 1,
525 array: None,
526 enumm: Some(
527 "Vbath",
528 ),
529 },
530 Field {
531 name: "templ",
532 description: Some(
533 "Temperature level monitoring versus low threshold",
534 ),
535 bit_offset: BitOffset::Regular(
536 RegularBitOffset {
537 offset: 2,
538 },
539 ),
540 bit_size: 1,
541 array: None,
542 enumm: Some(
543 "Templ",
544 ),
545 },
546 Field {
547 name: "temph",
548 description: Some(
549 "Temperature level monitoring versus high threshold",
550 ),
551 bit_offset: BitOffset::Regular(
552 RegularBitOffset {
553 offset: 3,
554 },
555 ),
556 bit_size: 1,
557 array: None,
558 enumm: Some(
559 "Temph",
560 ),
561 },
562 ],
563 },
564 FieldSet {
565 name: "Cr1",
566 extends: None,
567 description: Some(
568 "control register 1",
569 ),
570 bit_size: 32,
571 fields: &[
572 Field {
573 name: "lpms",
574 description: Some(
575 "Low-power mode selection\r These bits select the low-power mode entered when the CPU enters the Deepsleep mode.\r 10x: Standby mode (Standby mode also entered if LPMS=11X in CR1\r with BREN=1 in BDCR1)\r 11x: Shutdown mode if BREN = 0 in BDCR1",
576 ),
577 bit_offset: BitOffset::Regular(
578 RegularBitOffset {
579 offset: 0,
580 },
581 ),
582 bit_size: 3,
583 array: None,
584 enumm: Some(
585 "Lpms",
586 ),
587 },
588 Field {
589 name: "rrsb1",
590 description: Some(
591 "SRAM2 page 1 retention in Stop 3 and Standby modes\r This bit is used to keep the SRAM2 page 1 content in Stop 3 and Standby modes. The SRAM2 page 1 corresponds to the first 8 Kbytes of the SRAM2\r (from SRAM2 base address to SRAM2 base address + 0x1FFF).\r Note: This bit has no effect in Shutdown mode.",
592 ),
593 bit_offset: BitOffset::Regular(
594 RegularBitOffset {
595 offset: 5,
596 },
597 ),
598 bit_size: 1,
599 array: None,
600 enumm: None,
601 },
602 Field {
603 name: "rrsb2",
604 description: Some(
605 "SRAM2 page 2 retention in Stop 3 and Standby modes\r This bit is used to keep the SRAM2 page 2 content in Stop 3 and Standby modes. The SRAM2 page 2 corresponds to the last 56 Kbytes of the SRAM2\r (from SRAM2 base address + 0x2000 to SRAM2 base address + 0xFFFF).\r Note: This bit has no effect in Shutdown mode.",
606 ),
607 bit_offset: BitOffset::Regular(
608 RegularBitOffset {
609 offset: 6,
610 },
611 ),
612 bit_size: 1,
613 array: None,
614 enumm: None,
615 },
616 Field {
617 name: "ulpmen",
618 description: Some(
619 "BOR ultra-low power mode\r This bit is used to reduce the consumption by configuring the BOR in discontinuous mode.\r This bit must be set to reach the lowest power consumption in the low-power modes.",
620 ),
621 bit_offset: BitOffset::Regular(
622 RegularBitOffset {
623 offset: 7,
624 },
625 ),
626 bit_size: 1,
627 array: None,
628 enumm: None,
629 },
630 Field {
631 name: "sram1pd",
632 description: Some(
633 "SRAM1 power down\r This bit is used to reduce the consumption by powering off the SRAM1.",
634 ),
635 bit_offset: BitOffset::Regular(
636 RegularBitOffset {
637 offset: 8,
638 },
639 ),
640 bit_size: 1,
641 array: None,
642 enumm: Some(
643 "Srampd",
644 ),
645 },
646 Field {
647 name: "sram2pd",
648 description: Some(
649 "SRAM2 power down\r This bit is used to reduce the consumption by powering off the SRAM2.",
650 ),
651 bit_offset: BitOffset::Regular(
652 RegularBitOffset {
653 offset: 9,
654 },
655 ),
656 bit_size: 1,
657 array: None,
658 enumm: Some(
659 "Srampd",
660 ),
661 },
662 Field {
663 name: "sram3pd",
664 description: Some(
665 "SRAM3 power down\r This bit is used to reduce the consumption by powering off the SRAM3.",
666 ),
667 bit_offset: BitOffset::Regular(
668 RegularBitOffset {
669 offset: 10,
670 },
671 ),
672 bit_size: 1,
673 array: None,
674 enumm: Some(
675 "Srampd",
676 ),
677 },
678 Field {
679 name: "sram4pd",
680 description: Some(
681 "SRAM4 power down\r This bit is used to reduce the consumption by powering off the SRAM4.",
682 ),
683 bit_offset: BitOffset::Regular(
684 RegularBitOffset {
685 offset: 11,
686 },
687 ),
688 bit_size: 1,
689 array: None,
690 enumm: Some(
691 "Srampd",
692 ),
693 },
694 ],
695 },
696 FieldSet {
697 name: "Cr2",
698 extends: None,
699 description: Some(
700 "control register 2",
701 ),
702 bit_size: 32,
703 fields: &[
704 Field {
705 name: "sram1pds1",
706 description: Some(
707 "SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)",
708 ),
709 bit_offset: BitOffset::Regular(
710 RegularBitOffset {
711 offset: 0,
712 },
713 ),
714 bit_size: 1,
715 array: None,
716 enumm: Some(
717 "Pds",
718 ),
719 },
720 Field {
721 name: "sram1pds2",
722 description: Some(
723 "SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)",
724 ),
725 bit_offset: BitOffset::Regular(
726 RegularBitOffset {
727 offset: 1,
728 },
729 ),
730 bit_size: 1,
731 array: None,
732 enumm: Some(
733 "Pds",
734 ),
735 },
736 Field {
737 name: "sram1pds3",
738 description: Some(
739 "SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)",
740 ),
741 bit_offset: BitOffset::Regular(
742 RegularBitOffset {
743 offset: 2,
744 },
745 ),
746 bit_size: 1,
747 array: None,
748 enumm: Some(
749 "Pds",
750 ),
751 },
752 Field {
753 name: "sram2pds1",
754 description: Some(
755 "SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0, 1, 2)\r Note: The SRAM2 page 1 retention in Stop 3 is controlled by RRSB1 bit in CR1.",
756 ),
757 bit_offset: BitOffset::Regular(
758 RegularBitOffset {
759 offset: 4,
760 },
761 ),
762 bit_size: 1,
763 array: None,
764 enumm: Some(
765 "Pds",
766 ),
767 },
768 Field {
769 name: "sram2pds2",
770 description: Some(
771 "SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0, 1, 2)\r Note: The SRAM2 page 2 retention in Stop 3 is controlled by RRSB2 bit in CR1.",
772 ),
773 bit_offset: BitOffset::Regular(
774 RegularBitOffset {
775 offset: 5,
776 },
777 ),
778 bit_size: 1,
779 array: None,
780 enumm: Some(
781 "Pds",
782 ),
783 },
784 Field {
785 name: "sram4pds",
786 description: Some(
787 "SRAM4 power-down in Stop modes (Stop 0, 1, 2, 3)",
788 ),
789 bit_offset: BitOffset::Regular(
790 RegularBitOffset {
791 offset: 6,
792 },
793 ),
794 bit_size: 1,
795 array: None,
796 enumm: Some(
797 "Pds",
798 ),
799 },
800 Field {
801 name: "icrampds",
802 description: Some(
803 "ICACHE SRAM power-down in Stop modes (Stop 0, 1, 2, 3)",
804 ),
805 bit_offset: BitOffset::Regular(
806 RegularBitOffset {
807 offset: 8,
808 },
809 ),
810 bit_size: 1,
811 array: None,
812 enumm: Some(
813 "Pds",
814 ),
815 },
816 Field {
817 name: "dc1rampds",
818 description: Some(
819 "DCACHE1 SRAM power-down in Stop modes (Stop 0, 1, 2, 3)",
820 ),
821 bit_offset: BitOffset::Regular(
822 RegularBitOffset {
823 offset: 9,
824 },
825 ),
826 bit_size: 1,
827 array: None,
828 enumm: Some(
829 "Pds",
830 ),
831 },
832 Field {
833 name: "dma2drampds",
834 description: Some(
835 "DMA2D SRAM power-down in Stop modes (Stop 0, 1, 2, 3)",
836 ),
837 bit_offset: BitOffset::Regular(
838 RegularBitOffset {
839 offset: 10,
840 },
841 ),
842 bit_size: 1,
843 array: None,
844 enumm: Some(
845 "Pds",
846 ),
847 },
848 Field {
849 name: "prampds",
850 description: Some(
851 "FMAC, FDCAN and USB peripherals SRAM power-down in Stop modes (Stop0,1,2,3)",
852 ),
853 bit_offset: BitOffset::Regular(
854 RegularBitOffset {
855 offset: 11,
856 },
857 ),
858 bit_size: 1,
859 array: None,
860 enumm: Some(
861 "Pds",
862 ),
863 },
864 Field {
865 name: "pkarampds",
866 description: Some(
867 "PKA SRAM power-down",
868 ),
869 bit_offset: BitOffset::Regular(
870 RegularBitOffset {
871 offset: 12,
872 },
873 ),
874 bit_size: 1,
875 array: None,
876 enumm: Some(
877 "Pds",
878 ),
879 },
880 Field {
881 name: "sram4fwu",
882 description: Some(
883 "SRAM4 fast wakeup from Stop 0, Stop 1 and Stop 2 modes\r This bit is used to obtain the best trade-off between low-power consumption and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting Stop 0, 1 and 2 modes, and also increases the LPDMA access time to SRAM4 during Stop modes.",
884 ),
885 bit_offset: BitOffset::Regular(
886 RegularBitOffset {
887 offset: 13,
888 },
889 ),
890 bit_size: 1,
891 array: None,
892 enumm: Some(
893 "Sramfwu",
894 ),
895 },
896 Field {
897 name: "flashfwu",
898 description: Some(
899 "Flash memory fast wakeup from Stop 0 and Stop 1 modes\r This bit is used to obtain the best trade-off between low-power consumption and wakeup time when exiting the Stop 0 or Stop 1 modes.\r When this bit is set, the Flash memory remains in normal mode in Stop 0 and Stop 1 modes, which offers a faster startup time with higher consumption.",
900 ),
901 bit_offset: BitOffset::Regular(
902 RegularBitOffset {
903 offset: 14,
904 },
905 ),
906 bit_size: 1,
907 array: None,
908 enumm: Some(
909 "Flashfwu",
910 ),
911 },
912 Field {
913 name: "sram3pds1",
914 description: Some(
915 "SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)",
916 ),
917 bit_offset: BitOffset::Regular(
918 RegularBitOffset {
919 offset: 16,
920 },
921 ),
922 bit_size: 1,
923 array: None,
924 enumm: Some(
925 "Pds",
926 ),
927 },
928 Field {
929 name: "sram3pds2",
930 description: Some(
931 "SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)",
932 ),
933 bit_offset: BitOffset::Regular(
934 RegularBitOffset {
935 offset: 17,
936 },
937 ),
938 bit_size: 1,
939 array: None,
940 enumm: Some(
941 "Pds",
942 ),
943 },
944 Field {
945 name: "sram3pds3",
946 description: Some(
947 "SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)",
948 ),
949 bit_offset: BitOffset::Regular(
950 RegularBitOffset {
951 offset: 18,
952 },
953 ),
954 bit_size: 1,
955 array: None,
956 enumm: Some(
957 "Pds",
958 ),
959 },
960 Field {
961 name: "sram3pds4",
962 description: Some(
963 "SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)",
964 ),
965 bit_offset: BitOffset::Regular(
966 RegularBitOffset {
967 offset: 19,
968 },
969 ),
970 bit_size: 1,
971 array: None,
972 enumm: Some(
973 "Pds",
974 ),
975 },
976 Field {
977 name: "sram3pds5",
978 description: Some(
979 "SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)",
980 ),
981 bit_offset: BitOffset::Regular(
982 RegularBitOffset {
983 offset: 20,
984 },
985 ),
986 bit_size: 1,
987 array: None,
988 enumm: Some(
989 "Pds",
990 ),
991 },
992 Field {
993 name: "sram3pds6",
994 description: Some(
995 "SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)",
996 ),
997 bit_offset: BitOffset::Regular(
998 RegularBitOffset {
999 offset: 21,
1000 },
1001 ),
1002 bit_size: 1,
1003 array: None,
1004 enumm: Some(
1005 "Pds",
1006 ),
1007 },
1008 Field {
1009 name: "sram3pds7",
1010 description: Some(
1011 "SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)",
1012 ),
1013 bit_offset: BitOffset::Regular(
1014 RegularBitOffset {
1015 offset: 22,
1016 },
1017 ),
1018 bit_size: 1,
1019 array: None,
1020 enumm: Some(
1021 "Pds",
1022 ),
1023 },
1024 Field {
1025 name: "sram3pds8",
1026 description: Some(
1027 "SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)",
1028 ),
1029 bit_offset: BitOffset::Regular(
1030 RegularBitOffset {
1031 offset: 23,
1032 },
1033 ),
1034 bit_size: 1,
1035 array: None,
1036 enumm: Some(
1037 "Pds",
1038 ),
1039 },
1040 Field {
1041 name: "srdrun",
1042 description: Some(
1043 "SmartRun domain in Run mode",
1044 ),
1045 bit_offset: BitOffset::Regular(
1046 RegularBitOffset {
1047 offset: 31,
1048 },
1049 ),
1050 bit_size: 1,
1051 array: None,
1052 enumm: None,
1053 },
1054 ],
1055 },
1056 FieldSet {
1057 name: "Cr3",
1058 extends: None,
1059 description: Some(
1060 "control register 3",
1061 ),
1062 bit_size: 32,
1063 fields: &[
1064 Field {
1065 name: "regsel",
1066 description: Some(
1067 "Regulator selection\r Note: REGSEL is reserved and must be kept at reset value in packages without SMPS.",
1068 ),
1069 bit_offset: BitOffset::Regular(
1070 RegularBitOffset {
1071 offset: 1,
1072 },
1073 ),
1074 bit_size: 1,
1075 array: None,
1076 enumm: Some(
1077 "Regsel",
1078 ),
1079 },
1080 Field {
1081 name: "fsten",
1082 description: Some(
1083 "Fast soft start",
1084 ),
1085 bit_offset: BitOffset::Regular(
1086 RegularBitOffset {
1087 offset: 2,
1088 },
1089 ),
1090 bit_size: 1,
1091 array: None,
1092 enumm: None,
1093 },
1094 ],
1095 },
1096 FieldSet {
1097 name: "Dbpcr",
1098 extends: None,
1099 description: Some(
1100 "disable Backup domain register",
1101 ),
1102 bit_size: 32,
1103 fields: &[
1104 Field {
1105 name: "dbp",
1106 description: Some(
1107 "Disable Backup domain write protection\r In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers.",
1108 ),
1109 bit_offset: BitOffset::Regular(
1110 RegularBitOffset {
1111 offset: 0,
1112 },
1113 ),
1114 bit_size: 1,
1115 array: None,
1116 enumm: None,
1117 },
1118 ],
1119 },
1120 FieldSet {
1121 name: "Pcr",
1122 extends: None,
1123 description: Some(
1124 "Power Port pull control register",
1125 ),
1126 bit_size: 32,
1127 fields: &[
1128 Field {
1129 name: "p",
1130 description: Some(
1131 "Port pull bit y (y=0..15)",
1132 ),
1133 bit_offset: BitOffset::Regular(
1134 RegularBitOffset {
1135 offset: 0,
1136 },
1137 ),
1138 bit_size: 1,
1139 array: Some(
1140 Array::Regular(
1141 RegularArray {
1142 len: 16,
1143 stride: 1,
1144 },
1145 ),
1146 ),
1147 enumm: None,
1148 },
1149 ],
1150 },
1151 FieldSet {
1152 name: "Privcfgr",
1153 extends: None,
1154 description: Some(
1155 "privilege control register",
1156 ),
1157 bit_size: 32,
1158 fields: &[
1159 Field {
1160 name: "spriv",
1161 description: Some(
1162 "secure functions privilege configuration\r This bit is set and reset by software. It can be written only by a secure privileged access.",
1163 ),
1164 bit_offset: BitOffset::Regular(
1165 RegularBitOffset {
1166 offset: 0,
1167 },
1168 ),
1169 bit_size: 1,
1170 array: None,
1171 enumm: None,
1172 },
1173 Field {
1174 name: "nspriv",
1175 description: Some(
1176 "non-secure functions privilege configuration\r This bit is set and reset by software. It can be written only by privileged access, secure or non-secure.",
1177 ),
1178 bit_offset: BitOffset::Regular(
1179 RegularBitOffset {
1180 offset: 1,
1181 },
1182 ),
1183 bit_size: 1,
1184 array: None,
1185 enumm: None,
1186 },
1187 ],
1188 },
1189 FieldSet {
1190 name: "Seccfgr",
1191 extends: None,
1192 description: Some(
1193 "security configuration register",
1194 ),
1195 bit_size: 32,
1196 fields: &[
1197 Field {
1198 name: "wup1sec",
1199 description: Some(
1200 "WUP1 secure protection",
1201 ),
1202 bit_offset: BitOffset::Regular(
1203 RegularBitOffset {
1204 offset: 0,
1205 },
1206 ),
1207 bit_size: 1,
1208 array: Some(
1209 Array::Regular(
1210 RegularArray {
1211 len: 8,
1212 stride: 1,
1213 },
1214 ),
1215 ),
1216 enumm: None,
1217 },
1218 Field {
1219 name: "lpmsec",
1220 description: Some(
1221 "Low-power modes secure protection",
1222 ),
1223 bit_offset: BitOffset::Regular(
1224 RegularBitOffset {
1225 offset: 12,
1226 },
1227 ),
1228 bit_size: 1,
1229 array: None,
1230 enumm: None,
1231 },
1232 Field {
1233 name: "vdmsec",
1234 description: Some(
1235 "Voltage detection and monitoring secure protection",
1236 ),
1237 bit_offset: BitOffset::Regular(
1238 RegularBitOffset {
1239 offset: 13,
1240 },
1241 ),
1242 bit_size: 1,
1243 array: None,
1244 enumm: None,
1245 },
1246 Field {
1247 name: "vbsec",
1248 description: Some(
1249 "Backup domain secure protection",
1250 ),
1251 bit_offset: BitOffset::Regular(
1252 RegularBitOffset {
1253 offset: 14,
1254 },
1255 ),
1256 bit_size: 1,
1257 array: None,
1258 enumm: None,
1259 },
1260 Field {
1261 name: "apcsec",
1262 description: Some(
1263 "Pull-up/pull-down secure protection",
1264 ),
1265 bit_offset: BitOffset::Regular(
1266 RegularBitOffset {
1267 offset: 15,
1268 },
1269 ),
1270 bit_size: 1,
1271 array: None,
1272 enumm: None,
1273 },
1274 ],
1275 },
1276 FieldSet {
1277 name: "Sr",
1278 extends: None,
1279 description: Some(
1280 "status register",
1281 ),
1282 bit_size: 32,
1283 fields: &[
1284 Field {
1285 name: "cssf",
1286 description: Some(
1287 "Clear Stop and Standby flags\r This bit is protected against non-secure access when LPMSEC=1 in SECCFGR.\r This bit is protected against unprivileged access when LPMSEC=1 and SPRIV=1 in PRIVCFGR, or when LPMSEC=0 and NSPRIV=1.\r Writing 1 to this bit clears the STOPF and SBF flags.",
1288 ),
1289 bit_offset: BitOffset::Regular(
1290 RegularBitOffset {
1291 offset: 0,
1292 },
1293 ),
1294 bit_size: 1,
1295 array: None,
1296 enumm: None,
1297 },
1298 Field {
1299 name: "stopf",
1300 description: Some(
1301 "Stop flag\r This bit is set by hardware when the device enters a Stop mode, and is cleared by software by writing 1 to the CSSF bit.",
1302 ),
1303 bit_offset: BitOffset::Regular(
1304 RegularBitOffset {
1305 offset: 1,
1306 },
1307 ),
1308 bit_size: 1,
1309 array: None,
1310 enumm: None,
1311 },
1312 Field {
1313 name: "sbf",
1314 description: Some(
1315 "Standby flag\r This bit is set by hardware when the device enters the Standby mode, and is cleared by writing 1 to the CSSF bit, or by a power-on reset. It is not cleared by the system reset.",
1316 ),
1317 bit_offset: BitOffset::Regular(
1318 RegularBitOffset {
1319 offset: 2,
1320 },
1321 ),
1322 bit_size: 1,
1323 array: None,
1324 enumm: None,
1325 },
1326 ],
1327 },
1328 FieldSet {
1329 name: "Svmcr",
1330 extends: None,
1331 description: Some(
1332 "supply voltage monitoring control register",
1333 ),
1334 bit_size: 32,
1335 fields: &[
1336 Field {
1337 name: "pvde",
1338 description: Some(
1339 "Power voltage detector enable",
1340 ),
1341 bit_offset: BitOffset::Regular(
1342 RegularBitOffset {
1343 offset: 4,
1344 },
1345 ),
1346 bit_size: 1,
1347 array: None,
1348 enumm: None,
1349 },
1350 Field {
1351 name: "pvdls",
1352 description: Some(
1353 "Power voltage detector level selection\r These bits select the voltage threshold detected by the power voltage detector:",
1354 ),
1355 bit_offset: BitOffset::Regular(
1356 RegularBitOffset {
1357 offset: 5,
1358 },
1359 ),
1360 bit_size: 3,
1361 array: None,
1362 enumm: Some(
1363 "Pvdls",
1364 ),
1365 },
1366 Field {
1367 name: "uvmen",
1368 description: Some(
1369 "VDDUSB independent USB voltage monitor enable",
1370 ),
1371 bit_offset: BitOffset::Regular(
1372 RegularBitOffset {
1373 offset: 24,
1374 },
1375 ),
1376 bit_size: 1,
1377 array: None,
1378 enumm: None,
1379 },
1380 Field {
1381 name: "io2vmen",
1382 description: Some(
1383 "VDDIO2 independent I/Os voltage monitor enable",
1384 ),
1385 bit_offset: BitOffset::Regular(
1386 RegularBitOffset {
1387 offset: 25,
1388 },
1389 ),
1390 bit_size: 1,
1391 array: None,
1392 enumm: None,
1393 },
1394 Field {
1395 name: "avm1en",
1396 description: Some(
1397 "VDDA independent analog supply voltage monitor 1 enable (1.6V threshold)",
1398 ),
1399 bit_offset: BitOffset::Regular(
1400 RegularBitOffset {
1401 offset: 26,
1402 },
1403 ),
1404 bit_size: 1,
1405 array: None,
1406 enumm: None,
1407 },
1408 Field {
1409 name: "avm2en",
1410 description: Some(
1411 "VDDA independent analog supply voltage monitor 2 enable (1.8V threshold)",
1412 ),
1413 bit_offset: BitOffset::Regular(
1414 RegularBitOffset {
1415 offset: 27,
1416 },
1417 ),
1418 bit_size: 1,
1419 array: None,
1420 enumm: None,
1421 },
1422 Field {
1423 name: "usv",
1424 description: Some(
1425 "VDDUSB independent USB supply valid",
1426 ),
1427 bit_offset: BitOffset::Regular(
1428 RegularBitOffset {
1429 offset: 28,
1430 },
1431 ),
1432 bit_size: 1,
1433 array: None,
1434 enumm: None,
1435 },
1436 Field {
1437 name: "io2sv",
1438 description: Some(
1439 "VDDIO2 independent I/Os supply valid\r This bit is used to validate the VDDIO2 supply for electrical and logical isolation purpose.\r Setting this bit is mandatory to use PG[15:2]. If VDDIO2 is not always present in the application, the VDDIO2 voltage monitor can be used to determine whether this supply is ready or not.",
1440 ),
1441 bit_offset: BitOffset::Regular(
1442 RegularBitOffset {
1443 offset: 29,
1444 },
1445 ),
1446 bit_size: 1,
1447 array: None,
1448 enumm: None,
1449 },
1450 Field {
1451 name: "asv",
1452 description: Some(
1453 "VDDA independent analog supply valid",
1454 ),
1455 bit_offset: BitOffset::Regular(
1456 RegularBitOffset {
1457 offset: 30,
1458 },
1459 ),
1460 bit_size: 1,
1461 array: None,
1462 enumm: None,
1463 },
1464 ],
1465 },
1466 FieldSet {
1467 name: "Svmsr",
1468 extends: None,
1469 description: None,
1470 bit_size: 32,
1471 fields: &[
1472 Field {
1473 name: "regs",
1474 description: Some(
1475 "Regulator selection",
1476 ),
1477 bit_offset: BitOffset::Regular(
1478 RegularBitOffset {
1479 offset: 1,
1480 },
1481 ),
1482 bit_size: 1,
1483 array: None,
1484 enumm: Some(
1485 "Regsel",
1486 ),
1487 },
1488 Field {
1489 name: "pvdo",
1490 description: Some(
1491 "VDD voltage detector output",
1492 ),
1493 bit_offset: BitOffset::Regular(
1494 RegularBitOffset {
1495 offset: 4,
1496 },
1497 ),
1498 bit_size: 1,
1499 array: None,
1500 enumm: Some(
1501 "Pvdo",
1502 ),
1503 },
1504 Field {
1505 name: "actvosrdy",
1506 description: Some(
1507 "Voltage level ready for currently used VOS",
1508 ),
1509 bit_offset: BitOffset::Regular(
1510 RegularBitOffset {
1511 offset: 15,
1512 },
1513 ),
1514 bit_size: 1,
1515 array: None,
1516 enumm: None,
1517 },
1518 Field {
1519 name: "actvos",
1520 description: Some(
1521 "VOS currently applied to VCORE\r This field provides the last VOS value.",
1522 ),
1523 bit_offset: BitOffset::Regular(
1524 RegularBitOffset {
1525 offset: 16,
1526 },
1527 ),
1528 bit_size: 2,
1529 array: None,
1530 enumm: Some(
1531 "Actvos",
1532 ),
1533 },
1534 Field {
1535 name: "vddusbrdy",
1536 description: Some(
1537 "VDDUSB ready",
1538 ),
1539 bit_offset: BitOffset::Regular(
1540 RegularBitOffset {
1541 offset: 24,
1542 },
1543 ),
1544 bit_size: 1,
1545 array: None,
1546 enumm: None,
1547 },
1548 Field {
1549 name: "vddio2rdy",
1550 description: Some(
1551 "VDDIO2 ready",
1552 ),
1553 bit_offset: BitOffset::Regular(
1554 RegularBitOffset {
1555 offset: 25,
1556 },
1557 ),
1558 bit_size: 1,
1559 array: None,
1560 enumm: None,
1561 },
1562 Field {
1563 name: "vdda1rdy",
1564 description: Some(
1565 "VDDA ready versus 1.6V voltage monitor",
1566 ),
1567 bit_offset: BitOffset::Regular(
1568 RegularBitOffset {
1569 offset: 26,
1570 },
1571 ),
1572 bit_size: 1,
1573 array: None,
1574 enumm: None,
1575 },
1576 Field {
1577 name: "vdda2rdy",
1578 description: Some(
1579 "VDDA ready versus 1.8V voltage monitor",
1580 ),
1581 bit_offset: BitOffset::Regular(
1582 RegularBitOffset {
1583 offset: 27,
1584 },
1585 ),
1586 bit_size: 1,
1587 array: None,
1588 enumm: None,
1589 },
1590 ],
1591 },
1592 FieldSet {
1593 name: "Ucpdr",
1594 extends: None,
1595 description: Some(
1596 "USB Type-C™ and Power Delivery register",
1597 ),
1598 bit_size: 32,
1599 fields: &[
1600 Field {
1601 name: "ucpd_dbdis",
1602 description: Some(
1603 "UCPD dead battery disable\r After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to handover control to the UCPD (the UCPD must be initialized before doing the disable).",
1604 ),
1605 bit_offset: BitOffset::Regular(
1606 RegularBitOffset {
1607 offset: 0,
1608 },
1609 ),
1610 bit_size: 1,
1611 array: None,
1612 enumm: None,
1613 },
1614 Field {
1615 name: "ucpd_stby",
1616 description: Some(
1617 "UCPD Standby mode\r When set, this bit is used to memorize the UCPD configuration in Standby mode.\r This bit must be written to 1 just before entering Standby mode when using UCPD.\r It must be written to 0 after exiting the Standby mode and before writing any UCPD registers.",
1618 ),
1619 bit_offset: BitOffset::Regular(
1620 RegularBitOffset {
1621 offset: 1,
1622 },
1623 ),
1624 bit_size: 1,
1625 array: None,
1626 enumm: None,
1627 },
1628 ],
1629 },
1630 FieldSet {
1631 name: "Vosr",
1632 extends: None,
1633 description: Some(
1634 "voltage scaling register",
1635 ),
1636 bit_size: 32,
1637 fields: &[
1638 Field {
1639 name: "usbboostrdy",
1640 description: Some(
1641 "OTG_HS EPOD booster ready\r This bit is set to one by hardware when the power booster startup time is reached. The OTG_HS clock can be provided only after this bit is set.",
1642 ),
1643 bit_offset: BitOffset::Regular(
1644 RegularBitOffset {
1645 offset: 13,
1646 },
1647 ),
1648 bit_size: 1,
1649 array: None,
1650 enumm: None,
1651 },
1652 Field {
1653 name: "boostrdy",
1654 description: Some(
1655 "EPOD booster ready\r This bit is set to 1 by hardware when the power booster startup time is reached. The system clock frequency can be switched higher than 50 MHz only after this bit is set.",
1656 ),
1657 bit_offset: BitOffset::Regular(
1658 RegularBitOffset {
1659 offset: 14,
1660 },
1661 ),
1662 bit_size: 1,
1663 array: None,
1664 enumm: None,
1665 },
1666 Field {
1667 name: "vosrdy",
1668 description: Some(
1669 "Ready bit for VCORE voltage scaling output selection",
1670 ),
1671 bit_offset: BitOffset::Regular(
1672 RegularBitOffset {
1673 offset: 15,
1674 },
1675 ),
1676 bit_size: 1,
1677 array: None,
1678 enumm: None,
1679 },
1680 Field {
1681 name: "vos",
1682 description: Some(
1683 "Voltage scaling range selection\r This field is protected against non-secure access when SYSCLKSEC=1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC=1 in RCC_SECCFGR and SPRIV=1 in PRIVCFGR, or when SYSCLKSEC=0 and NSPRIV=1.",
1684 ),
1685 bit_offset: BitOffset::Regular(
1686 RegularBitOffset {
1687 offset: 16,
1688 },
1689 ),
1690 bit_size: 2,
1691 array: None,
1692 enumm: Some(
1693 "Vos",
1694 ),
1695 },
1696 Field {
1697 name: "boosten",
1698 description: Some(
1699 "EPOD booster enable",
1700 ),
1701 bit_offset: BitOffset::Regular(
1702 RegularBitOffset {
1703 offset: 18,
1704 },
1705 ),
1706 bit_size: 1,
1707 array: None,
1708 enumm: None,
1709 },
1710 Field {
1711 name: "usbpwren",
1712 description: Some(
1713 "OTG_HS power enable",
1714 ),
1715 bit_offset: BitOffset::Regular(
1716 RegularBitOffset {
1717 offset: 19,
1718 },
1719 ),
1720 bit_size: 1,
1721 array: None,
1722 enumm: None,
1723 },
1724 Field {
1725 name: "usbboosten",
1726 description: Some(
1727 "OTG_HS EPOD booster enable",
1728 ),
1729 bit_offset: BitOffset::Regular(
1730 RegularBitOffset {
1731 offset: 20,
1732 },
1733 ),
1734 bit_size: 1,
1735 array: None,
1736 enumm: None,
1737 },
1738 Field {
1739 name: "vdd11usbdis",
1740 description: Some(
1741 "OTG_HS VDD11USB disable",
1742 ),
1743 bit_offset: BitOffset::Regular(
1744 RegularBitOffset {
1745 offset: 21,
1746 },
1747 ),
1748 bit_size: 1,
1749 array: None,
1750 enumm: None,
1751 },
1752 ],
1753 },
1754 FieldSet {
1755 name: "Wucr1",
1756 extends: None,
1757 description: Some(
1758 "wakeup control register 1",
1759 ),
1760 bit_size: 32,
1761 fields: &[
1762 Field {
1763 name: "wupen",
1764 description: Some(
1765 "Wakeup pin WKUP1 enable",
1766 ),
1767 bit_offset: BitOffset::Regular(
1768 RegularBitOffset {
1769 offset: 0,
1770 },
1771 ),
1772 bit_size: 1,
1773 array: Some(
1774 Array::Regular(
1775 RegularArray {
1776 len: 8,
1777 stride: 1,
1778 },
1779 ),
1780 ),
1781 enumm: None,
1782 },
1783 ],
1784 },
1785 FieldSet {
1786 name: "Wucr2",
1787 extends: None,
1788 description: Some(
1789 "wakeup control register 2",
1790 ),
1791 bit_size: 32,
1792 fields: &[
1793 Field {
1794 name: "wupp",
1795 description: Some(
1796 "Wakeup pin WKUP1 polarity.\r This bit must be configured when WUPEN1 = 0.",
1797 ),
1798 bit_offset: BitOffset::Regular(
1799 RegularBitOffset {
1800 offset: 0,
1801 },
1802 ),
1803 bit_size: 1,
1804 array: Some(
1805 Array::Regular(
1806 RegularArray {
1807 len: 8,
1808 stride: 1,
1809 },
1810 ),
1811 ),
1812 enumm: Some(
1813 "Wupp",
1814 ),
1815 },
1816 ],
1817 },
1818 FieldSet {
1819 name: "Wucr3",
1820 extends: None,
1821 description: Some(
1822 "wakeup control register 3",
1823 ),
1824 bit_size: 32,
1825 fields: &[
1826 Field {
1827 name: "wusel1",
1828 description: Some(
1829 "Wakeup pin WKUP1 selection\r This field must be configured when WUPEN1 = 0.",
1830 ),
1831 bit_offset: BitOffset::Regular(
1832 RegularBitOffset {
1833 offset: 0,
1834 },
1835 ),
1836 bit_size: 2,
1837 array: None,
1838 enumm: Some(
1839 "Wusel",
1840 ),
1841 },
1842 Field {
1843 name: "wusel2",
1844 description: Some(
1845 "Wakeup pin WKUP2 selection\r This field must be configured when WUPEN2 = 0.",
1846 ),
1847 bit_offset: BitOffset::Regular(
1848 RegularBitOffset {
1849 offset: 2,
1850 },
1851 ),
1852 bit_size: 2,
1853 array: None,
1854 enumm: Some(
1855 "Wusel",
1856 ),
1857 },
1858 Field {
1859 name: "wusel3",
1860 description: Some(
1861 "Wakeup pin WKUP3 selection\r This field must be configured when WUPEN3 = 0.",
1862 ),
1863 bit_offset: BitOffset::Regular(
1864 RegularBitOffset {
1865 offset: 4,
1866 },
1867 ),
1868 bit_size: 2,
1869 array: None,
1870 enumm: Some(
1871 "Wusel",
1872 ),
1873 },
1874 Field {
1875 name: "wusel4",
1876 description: Some(
1877 "Wakeup pin WKUP4 selection\r This field must be configured when WUPEN4 = 0.",
1878 ),
1879 bit_offset: BitOffset::Regular(
1880 RegularBitOffset {
1881 offset: 6,
1882 },
1883 ),
1884 bit_size: 2,
1885 array: None,
1886 enumm: Some(
1887 "Wusel",
1888 ),
1889 },
1890 Field {
1891 name: "wusel5",
1892 description: Some(
1893 "Wakeup pin WKUP5 selection\r This field must be configured when WUPEN5 = 0.",
1894 ),
1895 bit_offset: BitOffset::Regular(
1896 RegularBitOffset {
1897 offset: 8,
1898 },
1899 ),
1900 bit_size: 2,
1901 array: None,
1902 enumm: Some(
1903 "Wusel",
1904 ),
1905 },
1906 Field {
1907 name: "wusel6",
1908 description: Some(
1909 "Wakeup pin WKUP6 selection\r This field must be configured when WUPEN6 = 0.",
1910 ),
1911 bit_offset: BitOffset::Regular(
1912 RegularBitOffset {
1913 offset: 10,
1914 },
1915 ),
1916 bit_size: 2,
1917 array: None,
1918 enumm: Some(
1919 "Wusel",
1920 ),
1921 },
1922 Field {
1923 name: "wusel7",
1924 description: Some(
1925 "Wakeup pin WKUP7 selection\r This field must be configured when WUPEN7 = 0.",
1926 ),
1927 bit_offset: BitOffset::Regular(
1928 RegularBitOffset {
1929 offset: 12,
1930 },
1931 ),
1932 bit_size: 2,
1933 array: None,
1934 enumm: Some(
1935 "Wusel",
1936 ),
1937 },
1938 Field {
1939 name: "wusel8",
1940 description: Some(
1941 "Wakeup pin WKUP8 selection\r This field must be configured when WUPEN8 = 0.",
1942 ),
1943 bit_offset: BitOffset::Regular(
1944 RegularBitOffset {
1945 offset: 14,
1946 },
1947 ),
1948 bit_size: 2,
1949 array: None,
1950 enumm: Some(
1951 "Wusel",
1952 ),
1953 },
1954 ],
1955 },
1956 FieldSet {
1957 name: "Wuscr",
1958 extends: None,
1959 description: Some(
1960 "wakeup status clear register",
1961 ),
1962 bit_size: 32,
1963 fields: &[
1964 Field {
1965 name: "cwuf1",
1966 description: Some(
1967 "Wakeup flag 1\r Writing 1 to this bit clears the WUF1 flag in WUSR.",
1968 ),
1969 bit_offset: BitOffset::Regular(
1970 RegularBitOffset {
1971 offset: 0,
1972 },
1973 ),
1974 bit_size: 1,
1975 array: None,
1976 enumm: None,
1977 },
1978 Field {
1979 name: "cwuf2",
1980 description: Some(
1981 "Wakeup flag 2\r Writing 1 to this bit clears the WUF2 flag in WUSR.",
1982 ),
1983 bit_offset: BitOffset::Regular(
1984 RegularBitOffset {
1985 offset: 1,
1986 },
1987 ),
1988 bit_size: 1,
1989 array: None,
1990 enumm: None,
1991 },
1992 Field {
1993 name: "cwuf3",
1994 description: Some(
1995 "Wakeup flag 3\r Writing 1 to this bit clears the WUF3 flag in WUSR.",
1996 ),
1997 bit_offset: BitOffset::Regular(
1998 RegularBitOffset {
1999 offset: 2,
2000 },
2001 ),
2002 bit_size: 1,
2003 array: None,
2004 enumm: None,
2005 },
2006 Field {
2007 name: "cwuf4",
2008 description: Some(
2009 "Wakeup flag 4\r Writing 1 to this bit clears the WUF4 flag in WUSR.",
2010 ),
2011 bit_offset: BitOffset::Regular(
2012 RegularBitOffset {
2013 offset: 3,
2014 },
2015 ),
2016 bit_size: 1,
2017 array: None,
2018 enumm: None,
2019 },
2020 Field {
2021 name: "cwuf5",
2022 description: Some(
2023 "Wakeup flag 5\r Writing 1 to this bit clears the WUF5 flag in WUSR.",
2024 ),
2025 bit_offset: BitOffset::Regular(
2026 RegularBitOffset {
2027 offset: 4,
2028 },
2029 ),
2030 bit_size: 1,
2031 array: None,
2032 enumm: None,
2033 },
2034 Field {
2035 name: "cwuf6",
2036 description: Some(
2037 "Wakeup flag 6\r Writing 1 to this bit clears the WUF6 flag in WUSR.",
2038 ),
2039 bit_offset: BitOffset::Regular(
2040 RegularBitOffset {
2041 offset: 5,
2042 },
2043 ),
2044 bit_size: 1,
2045 array: None,
2046 enumm: None,
2047 },
2048 Field {
2049 name: "cwuf7",
2050 description: Some(
2051 "Wakeup flag 7\r Writing 1 to this bit clears the WUF7 flag in WUSR.",
2052 ),
2053 bit_offset: BitOffset::Regular(
2054 RegularBitOffset {
2055 offset: 6,
2056 },
2057 ),
2058 bit_size: 1,
2059 array: None,
2060 enumm: None,
2061 },
2062 Field {
2063 name: "cwuf8",
2064 description: Some(
2065 "Wakeup flag 8\r Writing 1 to this bit clears the WUF8 flag in WUSR.",
2066 ),
2067 bit_offset: BitOffset::Regular(
2068 RegularBitOffset {
2069 offset: 7,
2070 },
2071 ),
2072 bit_size: 1,
2073 array: None,
2074 enumm: None,
2075 },
2076 ],
2077 },
2078 FieldSet {
2079 name: "Wusr",
2080 extends: None,
2081 description: Some(
2082 "wakeup status register",
2083 ),
2084 bit_size: 32,
2085 fields: &[
2086 Field {
2087 name: "wuf1",
2088 description: Some(
2089 "Wakeup flag 1\r This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN1=0.",
2090 ),
2091 bit_offset: BitOffset::Regular(
2092 RegularBitOffset {
2093 offset: 0,
2094 },
2095 ),
2096 bit_size: 1,
2097 array: None,
2098 enumm: None,
2099 },
2100 Field {
2101 name: "wuf2",
2102 description: Some(
2103 "Wakeup flag 2\r This bit is set when a wakeup event is detected on WKUP2 pin. This bit is cleared by writing 1 in the CWUF2 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN2=0.",
2104 ),
2105 bit_offset: BitOffset::Regular(
2106 RegularBitOffset {
2107 offset: 1,
2108 },
2109 ),
2110 bit_size: 1,
2111 array: None,
2112 enumm: None,
2113 },
2114 Field {
2115 name: "wuf3",
2116 description: Some(
2117 "Wakeup flag 3\r This bit is set when a wakeup event is detected on WKUP3 pin. This bit is cleared by writing 1 in the CWUF3 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN3=0.",
2118 ),
2119 bit_offset: BitOffset::Regular(
2120 RegularBitOffset {
2121 offset: 2,
2122 },
2123 ),
2124 bit_size: 1,
2125 array: None,
2126 enumm: None,
2127 },
2128 Field {
2129 name: "wuf4",
2130 description: Some(
2131 "Wakeup flag 4\r This bit is set when a wakeup event is detected on WKUP4 pin. This bit is cleared by writing 1 in the CWUF4 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN4=0.",
2132 ),
2133 bit_offset: BitOffset::Regular(
2134 RegularBitOffset {
2135 offset: 3,
2136 },
2137 ),
2138 bit_size: 1,
2139 array: None,
2140 enumm: None,
2141 },
2142 Field {
2143 name: "wuf5",
2144 description: Some(
2145 "Wakeup flag 5\r This bit is set when a wakeup event is detected on WKUP5 pin. This bit is cleared by writing 1 in the CWUF5 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN5=0.",
2146 ),
2147 bit_offset: BitOffset::Regular(
2148 RegularBitOffset {
2149 offset: 4,
2150 },
2151 ),
2152 bit_size: 1,
2153 array: None,
2154 enumm: None,
2155 },
2156 Field {
2157 name: "wuf6",
2158 description: Some(
2159 "Wakeup flag 6\r This bit is set when a wakeup event is detected on WKUP6 pin. This bit is cleared by writing 1 in the CWUF6 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN6=0.\r If WUSEL=11, this bit is cleared by hardware when all internal wakeup source are cleared.",
2160 ),
2161 bit_offset: BitOffset::Regular(
2162 RegularBitOffset {
2163 offset: 5,
2164 },
2165 ),
2166 bit_size: 1,
2167 array: None,
2168 enumm: None,
2169 },
2170 Field {
2171 name: "wuf7",
2172 description: Some(
2173 "Wakeup flag 7\r This bit is set when a wakeup event is detected on WKUP7 pin. This bit is cleared by writing 1 in the CWUF7 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN7=0.\r If WUSEL=11, this bit is cleared by hardware when all internal wakeup source are cleared.",
2174 ),
2175 bit_offset: BitOffset::Regular(
2176 RegularBitOffset {
2177 offset: 6,
2178 },
2179 ),
2180 bit_size: 1,
2181 array: None,
2182 enumm: None,
2183 },
2184 Field {
2185 name: "wuf8",
2186 description: Some(
2187 "Wakeup flag 8\r This bit is set when a wakeup event is detected on WKUP8 pin. This bit is cleared by writing 1 in the CWUF8 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN8=0.\r If WUSEL=11, this bit is cleared by hardware when all internal wakeup source are cleared.",
2188 ),
2189 bit_offset: BitOffset::Regular(
2190 RegularBitOffset {
2191 offset: 7,
2192 },
2193 ),
2194 bit_size: 1,
2195 array: None,
2196 enumm: None,
2197 },
2198 ],
2199 },
2200 ],
2201 enums: &[
2202 Enum {
2203 name: "Actvos",
2204 description: None,
2205 bit_size: 2,
2206 variants: &[
2207 EnumVariant {
2208 name: "RANGE4",
2209 description: Some(
2210 "Range 4 (lowest power)",
2211 ),
2212 value: 0,
2213 },
2214 EnumVariant {
2215 name: "RANGE3",
2216 description: Some(
2217 "Range 3",
2218 ),
2219 value: 1,
2220 },
2221 EnumVariant {
2222 name: "RANGE2",
2223 description: Some(
2224 "Range 2",
2225 ),
2226 value: 2,
2227 },
2228 EnumVariant {
2229 name: "RANGE1",
2230 description: Some(
2231 "Range 1 (highest frequency)",
2232 ),
2233 value: 3,
2234 },
2235 ],
2236 },
2237 Enum {
2238 name: "Flashfwu",
2239 description: None,
2240 bit_size: 1,
2241 variants: &[
2242 EnumVariant {
2243 name: "LOW_POWER",
2244 description: Some(
2245 "Flash memory enters low-power mode in Stop 0 and Stop 1 modes (lower-power consumption).",
2246 ),
2247 value: 0,
2248 },
2249 EnumVariant {
2250 name: "NORMAL",
2251 description: Some(
2252 "Flash memory remains in normal mode in Stop 0 and Stop 1 modes (faster wakeup time).",
2253 ),
2254 value: 1,
2255 },
2256 ],
2257 },
2258 Enum {
2259 name: "Lpms",
2260 description: None,
2261 bit_size: 3,
2262 variants: &[
2263 EnumVariant {
2264 name: "STOP0",
2265 description: Some(
2266 "Stop 0 mode",
2267 ),
2268 value: 0,
2269 },
2270 EnumVariant {
2271 name: "STOP1",
2272 description: Some(
2273 "Stop 1 mode",
2274 ),
2275 value: 1,
2276 },
2277 EnumVariant {
2278 name: "STOP2",
2279 description: Some(
2280 "Stop 2 mode",
2281 ),
2282 value: 2,
2283 },
2284 EnumVariant {
2285 name: "STOP3",
2286 description: Some(
2287 "Stop 3 mode",
2288 ),
2289 value: 3,
2290 },
2291 ],
2292 },
2293 Enum {
2294 name: "Pds",
2295 description: None,
2296 bit_size: 1,
2297 variants: &[
2298 EnumVariant {
2299 name: "RETAINED",
2300 description: Some(
2301 "Content retained in Stop modes",
2302 ),
2303 value: 0,
2304 },
2305 EnumVariant {
2306 name: "LOST",
2307 description: Some(
2308 "Content lost in Stop modes",
2309 ),
2310 value: 1,
2311 },
2312 ],
2313 },
2314 Enum {
2315 name: "Pvdls",
2316 description: None,
2317 bit_size: 3,
2318 variants: &[
2319 EnumVariant {
2320 name: "V20",
2321 description: Some(
2322 "VPVD0 around 2.0 V",
2323 ),
2324 value: 0,
2325 },
2326 EnumVariant {
2327 name: "V22",
2328 description: Some(
2329 "VPVD1 around 2.2 V",
2330 ),
2331 value: 1,
2332 },
2333 EnumVariant {
2334 name: "V24",
2335 description: Some(
2336 "VPVD2 around 2.4 V",
2337 ),
2338 value: 2,
2339 },
2340 EnumVariant {
2341 name: "V25",
2342 description: Some(
2343 "VPVD3 around 2.5 V",
2344 ),
2345 value: 3,
2346 },
2347 EnumVariant {
2348 name: "V26",
2349 description: Some(
2350 "VPVD4 around 2.6 V",
2351 ),
2352 value: 4,
2353 },
2354 EnumVariant {
2355 name: "V28",
2356 description: Some(
2357 "VPVD5 around 2.8 V",
2358 ),
2359 value: 5,
2360 },
2361 EnumVariant {
2362 name: "V29",
2363 description: Some(
2364 "VPVD6 around 2.9 V",
2365 ),
2366 value: 6,
2367 },
2368 EnumVariant {
2369 name: "PVD_IN",
2370 description: Some(
2371 "External input analog voltage PVD_IN (compared internally to VREFINT)",
2372 ),
2373 value: 7,
2374 },
2375 ],
2376 },
2377 Enum {
2378 name: "Pvdo",
2379 description: None,
2380 bit_size: 1,
2381 variants: &[
2382 EnumVariant {
2383 name: "ABOVE_OR_EQUAL",
2384 description: Some(
2385 "VDD is equal or above the PVD threshold selected by PVDLS[2:0].",
2386 ),
2387 value: 0,
2388 },
2389 EnumVariant {
2390 name: "BELOW",
2391 description: Some(
2392 "VDD is below the PVD threshold selected by PVDLS[2:0].",
2393 ),
2394 value: 1,
2395 },
2396 ],
2397 },
2398 Enum {
2399 name: "Regsel",
2400 description: None,
2401 bit_size: 1,
2402 variants: &[
2403 EnumVariant {
2404 name: "LDO",
2405 description: Some(
2406 "LDO selected",
2407 ),
2408 value: 0,
2409 },
2410 EnumVariant {
2411 name: "SMPS",
2412 description: Some(
2413 "SMPS selected",
2414 ),
2415 value: 1,
2416 },
2417 ],
2418 },
2419 Enum {
2420 name: "Sramfwu",
2421 description: None,
2422 bit_size: 1,
2423 variants: &[
2424 EnumVariant {
2425 name: "B_0X0",
2426 description: Some(
2427 "SRAM4 enters low-power mode in Stop 0, 1 and 2 modes (source biasing for lower-power consumption).",
2428 ),
2429 value: 0,
2430 },
2431 EnumVariant {
2432 name: "B_0X1",
2433 description: Some(
2434 "SRAM4 remains in normal mode in Stop 0, 1 and 2 modes (higher consumption but no SRAM4 wakeup time).",
2435 ),
2436 value: 1,
2437 },
2438 ],
2439 },
2440 Enum {
2441 name: "Srampd",
2442 description: None,
2443 bit_size: 1,
2444 variants: &[
2445 EnumVariant {
2446 name: "POWERED_ON",
2447 description: Some(
2448 "SRAM1 powered on",
2449 ),
2450 value: 0,
2451 },
2452 EnumVariant {
2453 name: "POWERED_OFF",
2454 description: Some(
2455 "SRAM1 powered off",
2456 ),
2457 value: 1,
2458 },
2459 ],
2460 },
2461 Enum {
2462 name: "Temph",
2463 description: None,
2464 bit_size: 1,
2465 variants: &[
2466 EnumVariant {
2467 name: "B_0X0",
2468 description: Some(
2469 "Temperature < high threshold",
2470 ),
2471 value: 0,
2472 },
2473 EnumVariant {
2474 name: "B_0X1",
2475 description: Some(
2476 "Temperature ≥ high threshold",
2477 ),
2478 value: 1,
2479 },
2480 ],
2481 },
2482 Enum {
2483 name: "Templ",
2484 description: None,
2485 bit_size: 1,
2486 variants: &[
2487 EnumVariant {
2488 name: "B_0X0",
2489 description: Some(
2490 "Temperature > low threshold",
2491 ),
2492 value: 0,
2493 },
2494 EnumVariant {
2495 name: "B_0X1",
2496 description: Some(
2497 "Temperature ≤ low threshold",
2498 ),
2499 value: 1,
2500 },
2501 ],
2502 },
2503 Enum {
2504 name: "Vbath",
2505 description: None,
2506 bit_size: 1,
2507 variants: &[
2508 EnumVariant {
2509 name: "B_0X0",
2510 description: Some(
2511 "Backup domain voltage level < high threshold",
2512 ),
2513 value: 0,
2514 },
2515 EnumVariant {
2516 name: "B_0X1",
2517 description: Some(
2518 "Backup domain voltage level ≥ high threshold",
2519 ),
2520 value: 1,
2521 },
2522 ],
2523 },
2524 Enum {
2525 name: "Vbe",
2526 description: None,
2527 bit_size: 1,
2528 variants: &[
2529 EnumVariant {
2530 name: "B_0X0",
2531 description: Some(
2532 "VBAT battery charging disabled",
2533 ),
2534 value: 0,
2535 },
2536 EnumVariant {
2537 name: "B_0X1",
2538 description: Some(
2539 "VBAT battery charging enabled",
2540 ),
2541 value: 1,
2542 },
2543 ],
2544 },
2545 Enum {
2546 name: "Vbrs",
2547 description: None,
2548 bit_size: 1,
2549 variants: &[
2550 EnumVariant {
2551 name: "B_0X0",
2552 description: Some(
2553 "Charge VBAT through a 5 kΩ resistor",
2554 ),
2555 value: 0,
2556 },
2557 EnumVariant {
2558 name: "B_0X1",
2559 description: Some(
2560 "Charge VBAT through a 1.5 kΩ resistor",
2561 ),
2562 value: 1,
2563 },
2564 ],
2565 },
2566 Enum {
2567 name: "Vos",
2568 description: None,
2569 bit_size: 2,
2570 variants: &[
2571 EnumVariant {
2572 name: "RANGE4",
2573 description: Some(
2574 "Range 4 (lowest power)",
2575 ),
2576 value: 0,
2577 },
2578 EnumVariant {
2579 name: "RANGE3",
2580 description: Some(
2581 "Range 3",
2582 ),
2583 value: 1,
2584 },
2585 EnumVariant {
2586 name: "RANGE2",
2587 description: Some(
2588 "Range 2",
2589 ),
2590 value: 2,
2591 },
2592 EnumVariant {
2593 name: "RANGE1",
2594 description: Some(
2595 "Range 1 (highest frequency). This value cannot be written when VCOREMEN = 1 in TAMP_OR register.",
2596 ),
2597 value: 3,
2598 },
2599 ],
2600 },
2601 Enum {
2602 name: "Wupp",
2603 description: None,
2604 bit_size: 1,
2605 variants: &[
2606 EnumVariant {
2607 name: "HIGH",
2608 description: Some(
2609 "Detection on high level (rising edge)",
2610 ),
2611 value: 0,
2612 },
2613 EnumVariant {
2614 name: "LOW",
2615 description: Some(
2616 "Detection on low level (falling edge)",
2617 ),
2618 value: 1,
2619 },
2620 ],
2621 },
2622 Enum {
2623 name: "Wusel",
2624 description: None,
2625 bit_size: 2,
2626 variants: &[
2627 EnumVariant {
2628 name: "B_0X0",
2629 description: Some(
2630 "WKUP7_0",
2631 ),
2632 value: 0,
2633 },
2634 EnumVariant {
2635 name: "B_0X1",
2636 description: Some(
2637 "WKUP7_1",
2638 ),
2639 value: 1,
2640 },
2641 EnumVariant {
2642 name: "B_0X2",
2643 description: Some(
2644 "WKUP7_2",
2645 ),
2646 value: 2,
2647 },
2648 EnumVariant {
2649 name: "B_0X3",
2650 description: Some(
2651 "WKUP7_3",
2652 ),
2653 value: 3,
2654 },
2655 ],
2656 },
2657 ],
2658};
2659