1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Rcc",
7 extends: None,
8 description: Some(
9 "Reset and clock control",
10 ),
11 items: &[
12 BlockItem {
13 name: "cr",
14 description: Some(
15 "RCC clock control register",
16 ),
17 array: None,
18 byte_offset: 0x0,
19 inner: BlockItemInner::Register(
20 Register {
21 access: Access::ReadWrite,
22 bit_size: 32,
23 fieldset: Some(
24 "Cr",
25 ),
26 },
27 ),
28 },
29 BlockItem {
30 name: "icscr1",
31 description: Some(
32 "RCC internal clock sources calibration register 1",
33 ),
34 array: None,
35 byte_offset: 0x8,
36 inner: BlockItemInner::Register(
37 Register {
38 access: Access::ReadWrite,
39 bit_size: 32,
40 fieldset: Some(
41 "Icscr1",
42 ),
43 },
44 ),
45 },
46 BlockItem {
47 name: "icscr2",
48 description: Some(
49 "RCC internal clock sources calibration register 2",
50 ),
51 array: None,
52 byte_offset: 0xc,
53 inner: BlockItemInner::Register(
54 Register {
55 access: Access::ReadWrite,
56 bit_size: 32,
57 fieldset: Some(
58 "Icscr2",
59 ),
60 },
61 ),
62 },
63 BlockItem {
64 name: "icscr3",
65 description: Some(
66 "RCC internal clock sources calibration register 3",
67 ),
68 array: None,
69 byte_offset: 0x10,
70 inner: BlockItemInner::Register(
71 Register {
72 access: Access::ReadWrite,
73 bit_size: 32,
74 fieldset: Some(
75 "Icscr3",
76 ),
77 },
78 ),
79 },
80 BlockItem {
81 name: "crrcr",
82 description: Some(
83 "RCC clock recovery RC register",
84 ),
85 array: None,
86 byte_offset: 0x14,
87 inner: BlockItemInner::Register(
88 Register {
89 access: Access::ReadWrite,
90 bit_size: 32,
91 fieldset: Some(
92 "Crrcr",
93 ),
94 },
95 ),
96 },
97 BlockItem {
98 name: "cfgr1",
99 description: Some(
100 "RCC clock configuration register 1",
101 ),
102 array: None,
103 byte_offset: 0x1c,
104 inner: BlockItemInner::Register(
105 Register {
106 access: Access::ReadWrite,
107 bit_size: 32,
108 fieldset: Some(
109 "Cfgr1",
110 ),
111 },
112 ),
113 },
114 BlockItem {
115 name: "cfgr2",
116 description: Some(
117 "RCC clock configuration register 2",
118 ),
119 array: None,
120 byte_offset: 0x20,
121 inner: BlockItemInner::Register(
122 Register {
123 access: Access::ReadWrite,
124 bit_size: 32,
125 fieldset: Some(
126 "Cfgr2",
127 ),
128 },
129 ),
130 },
131 BlockItem {
132 name: "cfgr3",
133 description: Some(
134 "RCC clock configuration register 3",
135 ),
136 array: None,
137 byte_offset: 0x24,
138 inner: BlockItemInner::Register(
139 Register {
140 access: Access::ReadWrite,
141 bit_size: 32,
142 fieldset: Some(
143 "Cfgr3",
144 ),
145 },
146 ),
147 },
148 BlockItem {
149 name: "pll1cfgr",
150 description: Some(
151 "RCC PLL1 configuration register",
152 ),
153 array: None,
154 byte_offset: 0x28,
155 inner: BlockItemInner::Register(
156 Register {
157 access: Access::ReadWrite,
158 bit_size: 32,
159 fieldset: Some(
160 "Pll1cfgr",
161 ),
162 },
163 ),
164 },
165 BlockItem {
166 name: "pll2cfgr",
167 description: Some(
168 "RCC PLL2 configuration register",
169 ),
170 array: None,
171 byte_offset: 0x2c,
172 inner: BlockItemInner::Register(
173 Register {
174 access: Access::ReadWrite,
175 bit_size: 32,
176 fieldset: Some(
177 "Pll23cfgr",
178 ),
179 },
180 ),
181 },
182 BlockItem {
183 name: "pll3cfgr",
184 description: Some(
185 "RCC PLL3 configuration register",
186 ),
187 array: None,
188 byte_offset: 0x30,
189 inner: BlockItemInner::Register(
190 Register {
191 access: Access::ReadWrite,
192 bit_size: 32,
193 fieldset: Some(
194 "Pll23cfgr",
195 ),
196 },
197 ),
198 },
199 BlockItem {
200 name: "pll1divr",
201 description: Some(
202 "RCC PLL1 dividers register",
203 ),
204 array: None,
205 byte_offset: 0x34,
206 inner: BlockItemInner::Register(
207 Register {
208 access: Access::ReadWrite,
209 bit_size: 32,
210 fieldset: Some(
211 "Plldivr",
212 ),
213 },
214 ),
215 },
216 BlockItem {
217 name: "pll1fracr",
218 description: Some(
219 "RCC PLL1 fractional divider register",
220 ),
221 array: None,
222 byte_offset: 0x38,
223 inner: BlockItemInner::Register(
224 Register {
225 access: Access::ReadWrite,
226 bit_size: 32,
227 fieldset: Some(
228 "Pllfracr",
229 ),
230 },
231 ),
232 },
233 BlockItem {
234 name: "pll2divr",
235 description: Some(
236 "RCC PLL2 dividers configuration register",
237 ),
238 array: None,
239 byte_offset: 0x3c,
240 inner: BlockItemInner::Register(
241 Register {
242 access: Access::ReadWrite,
243 bit_size: 32,
244 fieldset: Some(
245 "Plldivr",
246 ),
247 },
248 ),
249 },
250 BlockItem {
251 name: "pll2fracr",
252 description: Some(
253 "RCC PLL2 fractional divider register",
254 ),
255 array: None,
256 byte_offset: 0x40,
257 inner: BlockItemInner::Register(
258 Register {
259 access: Access::ReadWrite,
260 bit_size: 32,
261 fieldset: Some(
262 "Pllfracr",
263 ),
264 },
265 ),
266 },
267 BlockItem {
268 name: "pll3divr",
269 description: Some(
270 "RCC PLL3 dividers configuration register",
271 ),
272 array: None,
273 byte_offset: 0x44,
274 inner: BlockItemInner::Register(
275 Register {
276 access: Access::ReadWrite,
277 bit_size: 32,
278 fieldset: Some(
279 "Plldivr",
280 ),
281 },
282 ),
283 },
284 BlockItem {
285 name: "pll3fracr",
286 description: Some(
287 "RCC PLL3 fractional divider register",
288 ),
289 array: None,
290 byte_offset: 0x48,
291 inner: BlockItemInner::Register(
292 Register {
293 access: Access::ReadWrite,
294 bit_size: 32,
295 fieldset: Some(
296 "Pllfracr",
297 ),
298 },
299 ),
300 },
301 BlockItem {
302 name: "cier",
303 description: Some(
304 "RCC clock interrupt enable register",
305 ),
306 array: None,
307 byte_offset: 0x50,
308 inner: BlockItemInner::Register(
309 Register {
310 access: Access::ReadWrite,
311 bit_size: 32,
312 fieldset: Some(
313 "Cier",
314 ),
315 },
316 ),
317 },
318 BlockItem {
319 name: "cifr",
320 description: Some(
321 "RCC clock interrupt flag register",
322 ),
323 array: None,
324 byte_offset: 0x54,
325 inner: BlockItemInner::Register(
326 Register {
327 access: Access::ReadWrite,
328 bit_size: 32,
329 fieldset: Some(
330 "Cifr",
331 ),
332 },
333 ),
334 },
335 BlockItem {
336 name: "cicr",
337 description: Some(
338 "RCC clock interrupt clear register",
339 ),
340 array: None,
341 byte_offset: 0x58,
342 inner: BlockItemInner::Register(
343 Register {
344 access: Access::ReadWrite,
345 bit_size: 32,
346 fieldset: Some(
347 "Cicr",
348 ),
349 },
350 ),
351 },
352 BlockItem {
353 name: "ahb1rstr",
354 description: Some(
355 "RCC AHB1 peripheral reset register",
356 ),
357 array: None,
358 byte_offset: 0x60,
359 inner: BlockItemInner::Register(
360 Register {
361 access: Access::ReadWrite,
362 bit_size: 32,
363 fieldset: Some(
364 "Ahb1rstr",
365 ),
366 },
367 ),
368 },
369 BlockItem {
370 name: "ahb2rstr1",
371 description: Some(
372 "RCC AHB2 peripheral reset register 1",
373 ),
374 array: None,
375 byte_offset: 0x64,
376 inner: BlockItemInner::Register(
377 Register {
378 access: Access::ReadWrite,
379 bit_size: 32,
380 fieldset: Some(
381 "Ahb2rstr1",
382 ),
383 },
384 ),
385 },
386 BlockItem {
387 name: "ahb2rstr2",
388 description: Some(
389 "RCC AHB2 peripheral reset register 2",
390 ),
391 array: None,
392 byte_offset: 0x68,
393 inner: BlockItemInner::Register(
394 Register {
395 access: Access::ReadWrite,
396 bit_size: 32,
397 fieldset: Some(
398 "Ahb2rstr2",
399 ),
400 },
401 ),
402 },
403 BlockItem {
404 name: "ahb3rstr",
405 description: Some(
406 "RCC AHB3 peripheral reset register",
407 ),
408 array: None,
409 byte_offset: 0x6c,
410 inner: BlockItemInner::Register(
411 Register {
412 access: Access::ReadWrite,
413 bit_size: 32,
414 fieldset: Some(
415 "Ahb3rstr",
416 ),
417 },
418 ),
419 },
420 BlockItem {
421 name: "apb1rstr1",
422 description: Some(
423 "RCC APB1 peripheral reset register 1",
424 ),
425 array: None,
426 byte_offset: 0x74,
427 inner: BlockItemInner::Register(
428 Register {
429 access: Access::ReadWrite,
430 bit_size: 32,
431 fieldset: Some(
432 "Apb1rstr1",
433 ),
434 },
435 ),
436 },
437 BlockItem {
438 name: "apb1rstr2",
439 description: Some(
440 "RCC APB1 peripheral reset register 2",
441 ),
442 array: None,
443 byte_offset: 0x78,
444 inner: BlockItemInner::Register(
445 Register {
446 access: Access::ReadWrite,
447 bit_size: 32,
448 fieldset: Some(
449 "Apb1rstr2",
450 ),
451 },
452 ),
453 },
454 BlockItem {
455 name: "apb2rstr",
456 description: Some(
457 "RCC APB2 peripheral reset register",
458 ),
459 array: None,
460 byte_offset: 0x7c,
461 inner: BlockItemInner::Register(
462 Register {
463 access: Access::ReadWrite,
464 bit_size: 32,
465 fieldset: Some(
466 "Apb2rstr",
467 ),
468 },
469 ),
470 },
471 BlockItem {
472 name: "apb3rstr",
473 description: Some(
474 "RCC APB3 peripheral reset register",
475 ),
476 array: None,
477 byte_offset: 0x80,
478 inner: BlockItemInner::Register(
479 Register {
480 access: Access::ReadWrite,
481 bit_size: 32,
482 fieldset: Some(
483 "Apb3rstr",
484 ),
485 },
486 ),
487 },
488 BlockItem {
489 name: "ahb1enr",
490 description: Some(
491 "RCC AHB1 peripheral clock enable register",
492 ),
493 array: None,
494 byte_offset: 0x88,
495 inner: BlockItemInner::Register(
496 Register {
497 access: Access::ReadWrite,
498 bit_size: 32,
499 fieldset: Some(
500 "Ahb1enr",
501 ),
502 },
503 ),
504 },
505 BlockItem {
506 name: "ahb2enr1",
507 description: Some(
508 "RCC AHB2 peripheral clock enable register 1",
509 ),
510 array: None,
511 byte_offset: 0x8c,
512 inner: BlockItemInner::Register(
513 Register {
514 access: Access::ReadWrite,
515 bit_size: 32,
516 fieldset: Some(
517 "Ahb2enr1",
518 ),
519 },
520 ),
521 },
522 BlockItem {
523 name: "ahb2enr2",
524 description: Some(
525 "RCC AHB2 peripheral clock enable register 2",
526 ),
527 array: None,
528 byte_offset: 0x90,
529 inner: BlockItemInner::Register(
530 Register {
531 access: Access::ReadWrite,
532 bit_size: 32,
533 fieldset: Some(
534 "Ahb2enr2",
535 ),
536 },
537 ),
538 },
539 BlockItem {
540 name: "ahb3enr",
541 description: Some(
542 "RCC AHB3 peripheral clock enable register",
543 ),
544 array: None,
545 byte_offset: 0x94,
546 inner: BlockItemInner::Register(
547 Register {
548 access: Access::ReadWrite,
549 bit_size: 32,
550 fieldset: Some(
551 "Ahb3enr",
552 ),
553 },
554 ),
555 },
556 BlockItem {
557 name: "apb1enr1",
558 description: Some(
559 "RCC APB1 peripheral clock enable register 1",
560 ),
561 array: None,
562 byte_offset: 0x9c,
563 inner: BlockItemInner::Register(
564 Register {
565 access: Access::ReadWrite,
566 bit_size: 32,
567 fieldset: Some(
568 "Apb1enr1",
569 ),
570 },
571 ),
572 },
573 BlockItem {
574 name: "apb1enr2",
575 description: Some(
576 "RCC APB1 peripheral clock enable register 2",
577 ),
578 array: None,
579 byte_offset: 0xa0,
580 inner: BlockItemInner::Register(
581 Register {
582 access: Access::ReadWrite,
583 bit_size: 32,
584 fieldset: Some(
585 "Apb1enr2",
586 ),
587 },
588 ),
589 },
590 BlockItem {
591 name: "apb2enr",
592 description: Some(
593 "RCC APB2 peripheral clock enable register",
594 ),
595 array: None,
596 byte_offset: 0xa4,
597 inner: BlockItemInner::Register(
598 Register {
599 access: Access::ReadWrite,
600 bit_size: 32,
601 fieldset: Some(
602 "Apb2enr",
603 ),
604 },
605 ),
606 },
607 BlockItem {
608 name: "apb3enr",
609 description: Some(
610 "RCC APB3 peripheral clock enable register",
611 ),
612 array: None,
613 byte_offset: 0xa8,
614 inner: BlockItemInner::Register(
615 Register {
616 access: Access::ReadWrite,
617 bit_size: 32,
618 fieldset: Some(
619 "Apb3enr",
620 ),
621 },
622 ),
623 },
624 BlockItem {
625 name: "ahb1smenr",
626 description: Some(
627 "RCC AHB1 peripheral clocks enable in Sleep and Stop modes register",
628 ),
629 array: None,
630 byte_offset: 0xb0,
631 inner: BlockItemInner::Register(
632 Register {
633 access: Access::ReadWrite,
634 bit_size: 32,
635 fieldset: Some(
636 "Ahb1smenr",
637 ),
638 },
639 ),
640 },
641 BlockItem {
642 name: "ahb2smenr1",
643 description: Some(
644 "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 1",
645 ),
646 array: None,
647 byte_offset: 0xb4,
648 inner: BlockItemInner::Register(
649 Register {
650 access: Access::ReadWrite,
651 bit_size: 32,
652 fieldset: Some(
653 "Ahb2smenr1",
654 ),
655 },
656 ),
657 },
658 BlockItem {
659 name: "ahb2smenr2",
660 description: Some(
661 "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 2",
662 ),
663 array: None,
664 byte_offset: 0xb8,
665 inner: BlockItemInner::Register(
666 Register {
667 access: Access::ReadWrite,
668 bit_size: 32,
669 fieldset: Some(
670 "Ahb2smenr2",
671 ),
672 },
673 ),
674 },
675 BlockItem {
676 name: "ahb3smenr",
677 description: Some(
678 "RCC AHB3 peripheral clocks enable in Sleep and Stop modes register",
679 ),
680 array: None,
681 byte_offset: 0xbc,
682 inner: BlockItemInner::Register(
683 Register {
684 access: Access::ReadWrite,
685 bit_size: 32,
686 fieldset: Some(
687 "Ahb3smenr",
688 ),
689 },
690 ),
691 },
692 BlockItem {
693 name: "apb1smenr1",
694 description: Some(
695 "RCC APB1 peripheral clocks enable in Sleep and Stop modes\tregister 1",
696 ),
697 array: None,
698 byte_offset: 0xc4,
699 inner: BlockItemInner::Register(
700 Register {
701 access: Access::ReadWrite,
702 bit_size: 32,
703 fieldset: Some(
704 "Apb1smenr1",
705 ),
706 },
707 ),
708 },
709 BlockItem {
710 name: "apb1smenr2",
711 description: Some(
712 "RCC APB1 peripheral clocks enable in Sleep and\tStop modes register 2",
713 ),
714 array: None,
715 byte_offset: 0xc8,
716 inner: BlockItemInner::Register(
717 Register {
718 access: Access::ReadWrite,
719 bit_size: 32,
720 fieldset: Some(
721 "Apb1smenr2",
722 ),
723 },
724 ),
725 },
726 BlockItem {
727 name: "apb2smenr",
728 description: Some(
729 "RCC APB2 peripheral clocks enable in Sleep and Stop modes register",
730 ),
731 array: None,
732 byte_offset: 0xcc,
733 inner: BlockItemInner::Register(
734 Register {
735 access: Access::ReadWrite,
736 bit_size: 32,
737 fieldset: Some(
738 "Apb2smenr",
739 ),
740 },
741 ),
742 },
743 BlockItem {
744 name: "apb3smenr",
745 description: Some(
746 "RCC APB3 peripheral clock enable in Sleep and Stop modes register",
747 ),
748 array: None,
749 byte_offset: 0xd0,
750 inner: BlockItemInner::Register(
751 Register {
752 access: Access::ReadWrite,
753 bit_size: 32,
754 fieldset: Some(
755 "Apb3smenr",
756 ),
757 },
758 ),
759 },
760 BlockItem {
761 name: "srdamr",
762 description: Some(
763 "RCC SmartRun domain peripheral autonomous mode register",
764 ),
765 array: None,
766 byte_offset: 0xd8,
767 inner: BlockItemInner::Register(
768 Register {
769 access: Access::ReadWrite,
770 bit_size: 32,
771 fieldset: Some(
772 "Srdamr",
773 ),
774 },
775 ),
776 },
777 BlockItem {
778 name: "ccipr1",
779 description: Some(
780 "RCC peripherals independent clock configuration register 1",
781 ),
782 array: None,
783 byte_offset: 0xe0,
784 inner: BlockItemInner::Register(
785 Register {
786 access: Access::ReadWrite,
787 bit_size: 32,
788 fieldset: Some(
789 "Ccipr1",
790 ),
791 },
792 ),
793 },
794 BlockItem {
795 name: "ccipr2",
796 description: Some(
797 "RCC peripherals independent clock configuration register 2",
798 ),
799 array: None,
800 byte_offset: 0xe4,
801 inner: BlockItemInner::Register(
802 Register {
803 access: Access::ReadWrite,
804 bit_size: 32,
805 fieldset: Some(
806 "Ccipr2",
807 ),
808 },
809 ),
810 },
811 BlockItem {
812 name: "ccipr3",
813 description: Some(
814 "RCC peripherals independent clock configuration register 3",
815 ),
816 array: None,
817 byte_offset: 0xe8,
818 inner: BlockItemInner::Register(
819 Register {
820 access: Access::ReadWrite,
821 bit_size: 32,
822 fieldset: Some(
823 "Ccipr3",
824 ),
825 },
826 ),
827 },
828 BlockItem {
829 name: "bdcr",
830 description: Some(
831 "RCC Backup domain control register",
832 ),
833 array: None,
834 byte_offset: 0xf0,
835 inner: BlockItemInner::Register(
836 Register {
837 access: Access::ReadWrite,
838 bit_size: 32,
839 fieldset: Some(
840 "Bdcr",
841 ),
842 },
843 ),
844 },
845 BlockItem {
846 name: "csr",
847 description: Some(
848 "RCC control/status register",
849 ),
850 array: None,
851 byte_offset: 0xf4,
852 inner: BlockItemInner::Register(
853 Register {
854 access: Access::ReadWrite,
855 bit_size: 32,
856 fieldset: Some(
857 "Csr",
858 ),
859 },
860 ),
861 },
862 BlockItem {
863 name: "seccfgr",
864 description: Some(
865 "RCC secure configuration register",
866 ),
867 array: None,
868 byte_offset: 0x110,
869 inner: BlockItemInner::Register(
870 Register {
871 access: Access::ReadWrite,
872 bit_size: 32,
873 fieldset: Some(
874 "Seccfgr",
875 ),
876 },
877 ),
878 },
879 BlockItem {
880 name: "privcfgr",
881 description: Some(
882 "RCC privilege configuration register",
883 ),
884 array: None,
885 byte_offset: 0x114,
886 inner: BlockItemInner::Register(
887 Register {
888 access: Access::ReadWrite,
889 bit_size: 32,
890 fieldset: Some(
891 "Privcfgr",
892 ),
893 },
894 ),
895 },
896 ],
897 },
898 ],
899 fieldsets: &[
900 FieldSet {
901 name: "Ahb1enr",
902 extends: None,
903 description: Some(
904 "RCC AHB1 peripheral clock enable register",
905 ),
906 bit_size: 32,
907 fields: &[
908 Field {
909 name: "gpdma1en",
910 description: Some(
911 "GPDMA1 clock enable\r Set and cleared by software.",
912 ),
913 bit_offset: BitOffset::Regular(
914 RegularBitOffset {
915 offset: 0,
916 },
917 ),
918 bit_size: 1,
919 array: None,
920 enumm: None,
921 },
922 Field {
923 name: "cordicen",
924 description: Some(
925 "CORDIC clock enable\r Set and cleared by software.",
926 ),
927 bit_offset: BitOffset::Regular(
928 RegularBitOffset {
929 offset: 1,
930 },
931 ),
932 bit_size: 1,
933 array: None,
934 enumm: None,
935 },
936 Field {
937 name: "fmacen",
938 description: Some(
939 "FMAC clock enable\r Set and reset by software.",
940 ),
941 bit_offset: BitOffset::Regular(
942 RegularBitOffset {
943 offset: 2,
944 },
945 ),
946 bit_size: 1,
947 array: None,
948 enumm: None,
949 },
950 Field {
951 name: "mdf1en",
952 description: Some(
953 "MDF1 clock enable\r Set and reset by software.",
954 ),
955 bit_offset: BitOffset::Regular(
956 RegularBitOffset {
957 offset: 3,
958 },
959 ),
960 bit_size: 1,
961 array: None,
962 enumm: None,
963 },
964 Field {
965 name: "flashen",
966 description: Some(
967 "FLASH clock enable\r Set and cleared by software. This bit can be disabled only when the Flash memory is in power down mode.",
968 ),
969 bit_offset: BitOffset::Regular(
970 RegularBitOffset {
971 offset: 8,
972 },
973 ),
974 bit_size: 1,
975 array: None,
976 enumm: None,
977 },
978 Field {
979 name: "crcen",
980 description: Some(
981 "CRC clock enable\r Set and cleared by software.",
982 ),
983 bit_offset: BitOffset::Regular(
984 RegularBitOffset {
985 offset: 12,
986 },
987 ),
988 bit_size: 1,
989 array: None,
990 enumm: None,
991 },
992 Field {
993 name: "jpegen",
994 description: Some(
995 "JPEG clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
996 ),
997 bit_offset: BitOffset::Regular(
998 RegularBitOffset {
999 offset: 15,
1000 },
1001 ),
1002 bit_size: 1,
1003 array: None,
1004 enumm: None,
1005 },
1006 Field {
1007 name: "tscen",
1008 description: Some(
1009 "Touch sensing controller clock enable\r Set and cleared by software.",
1010 ),
1011 bit_offset: BitOffset::Regular(
1012 RegularBitOffset {
1013 offset: 16,
1014 },
1015 ),
1016 bit_size: 1,
1017 array: None,
1018 enumm: None,
1019 },
1020 Field {
1021 name: "ramcfgen",
1022 description: Some(
1023 "RAMCFG clock enable\r Set and cleared by software.",
1024 ),
1025 bit_offset: BitOffset::Regular(
1026 RegularBitOffset {
1027 offset: 17,
1028 },
1029 ),
1030 bit_size: 1,
1031 array: None,
1032 enumm: None,
1033 },
1034 Field {
1035 name: "dma2den",
1036 description: Some(
1037 "DMA2D clock enable\r Set and cleared by software.",
1038 ),
1039 bit_offset: BitOffset::Regular(
1040 RegularBitOffset {
1041 offset: 18,
1042 },
1043 ),
1044 bit_size: 1,
1045 array: None,
1046 enumm: None,
1047 },
1048 Field {
1049 name: "gfxmmuen",
1050 description: Some(
1051 "GFXMMU clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
1052 ),
1053 bit_offset: BitOffset::Regular(
1054 RegularBitOffset {
1055 offset: 19,
1056 },
1057 ),
1058 bit_size: 1,
1059 array: None,
1060 enumm: None,
1061 },
1062 Field {
1063 name: "gpu2den",
1064 description: Some(
1065 "GPU2D clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
1066 ),
1067 bit_offset: BitOffset::Regular(
1068 RegularBitOffset {
1069 offset: 20,
1070 },
1071 ),
1072 bit_size: 1,
1073 array: None,
1074 enumm: None,
1075 },
1076 Field {
1077 name: "dcache2en",
1078 description: Some(
1079 "DCACHE2 clock enable \r This bit is set and reset by software.\r Note: DCACHE2 clock must be enabled to access memories, even if the DCACHE2 is bypassed.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
1080 ),
1081 bit_offset: BitOffset::Regular(
1082 RegularBitOffset {
1083 offset: 21,
1084 },
1085 ),
1086 bit_size: 1,
1087 array: None,
1088 enumm: None,
1089 },
1090 Field {
1091 name: "gtzc1en",
1092 description: Some(
1093 "GTZC1 clock enable\r Set and reset by software.",
1094 ),
1095 bit_offset: BitOffset::Regular(
1096 RegularBitOffset {
1097 offset: 24,
1098 },
1099 ),
1100 bit_size: 1,
1101 array: None,
1102 enumm: None,
1103 },
1104 Field {
1105 name: "bkpsramen",
1106 description: Some(
1107 "BKPSRAM clock enable\r Set and reset by software.",
1108 ),
1109 bit_offset: BitOffset::Regular(
1110 RegularBitOffset {
1111 offset: 28,
1112 },
1113 ),
1114 bit_size: 1,
1115 array: None,
1116 enumm: None,
1117 },
1118 Field {
1119 name: "dcache1en",
1120 description: Some(
1121 "DCACHE1 clock enable\r Set and reset by software.\r Note: DCACHE1 clock must be enabled when external memories are accessed through OCTOSPI1, OCTOSPI2 or FSMC, even if the DCACHE1 is bypassed.",
1122 ),
1123 bit_offset: BitOffset::Regular(
1124 RegularBitOffset {
1125 offset: 30,
1126 },
1127 ),
1128 bit_size: 1,
1129 array: None,
1130 enumm: None,
1131 },
1132 Field {
1133 name: "sram1en",
1134 description: Some(
1135 "SRAM1 clock enable\r Set and reset by software.",
1136 ),
1137 bit_offset: BitOffset::Regular(
1138 RegularBitOffset {
1139 offset: 31,
1140 },
1141 ),
1142 bit_size: 1,
1143 array: None,
1144 enumm: None,
1145 },
1146 ],
1147 },
1148 FieldSet {
1149 name: "Ahb1rstr",
1150 extends: None,
1151 description: Some(
1152 "RCC AHB1 peripheral reset register",
1153 ),
1154 bit_size: 32,
1155 fields: &[
1156 Field {
1157 name: "gpdma1rst",
1158 description: Some(
1159 "GPDMA1 reset\r Set and cleared by software.",
1160 ),
1161 bit_offset: BitOffset::Regular(
1162 RegularBitOffset {
1163 offset: 0,
1164 },
1165 ),
1166 bit_size: 1,
1167 array: None,
1168 enumm: None,
1169 },
1170 Field {
1171 name: "cordicrst",
1172 description: Some(
1173 "CORDIC reset\r Set and cleared by software.",
1174 ),
1175 bit_offset: BitOffset::Regular(
1176 RegularBitOffset {
1177 offset: 1,
1178 },
1179 ),
1180 bit_size: 1,
1181 array: None,
1182 enumm: None,
1183 },
1184 Field {
1185 name: "fmacrst",
1186 description: Some(
1187 "FMAC reset\r Set and cleared by software.",
1188 ),
1189 bit_offset: BitOffset::Regular(
1190 RegularBitOffset {
1191 offset: 2,
1192 },
1193 ),
1194 bit_size: 1,
1195 array: None,
1196 enumm: None,
1197 },
1198 Field {
1199 name: "mdf1rst",
1200 description: Some(
1201 "MDF1 reset\r Set and cleared by software.",
1202 ),
1203 bit_offset: BitOffset::Regular(
1204 RegularBitOffset {
1205 offset: 3,
1206 },
1207 ),
1208 bit_size: 1,
1209 array: None,
1210 enumm: None,
1211 },
1212 Field {
1213 name: "crcrst",
1214 description: Some(
1215 "CRC reset\r Set and cleared by software.",
1216 ),
1217 bit_offset: BitOffset::Regular(
1218 RegularBitOffset {
1219 offset: 12,
1220 },
1221 ),
1222 bit_size: 1,
1223 array: None,
1224 enumm: None,
1225 },
1226 Field {
1227 name: "jpegrst",
1228 description: Some(
1229 "JPEG reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
1230 ),
1231 bit_offset: BitOffset::Regular(
1232 RegularBitOffset {
1233 offset: 15,
1234 },
1235 ),
1236 bit_size: 1,
1237 array: None,
1238 enumm: None,
1239 },
1240 Field {
1241 name: "tscrst",
1242 description: Some(
1243 "TSC reset\r Set and cleared by software.",
1244 ),
1245 bit_offset: BitOffset::Regular(
1246 RegularBitOffset {
1247 offset: 16,
1248 },
1249 ),
1250 bit_size: 1,
1251 array: None,
1252 enumm: None,
1253 },
1254 Field {
1255 name: "ramcfgrst",
1256 description: Some(
1257 "RAMCFG reset\r Set and cleared by software.",
1258 ),
1259 bit_offset: BitOffset::Regular(
1260 RegularBitOffset {
1261 offset: 17,
1262 },
1263 ),
1264 bit_size: 1,
1265 array: None,
1266 enumm: None,
1267 },
1268 Field {
1269 name: "dma2drst",
1270 description: Some(
1271 "DMA2D reset\r Set and cleared by software.",
1272 ),
1273 bit_offset: BitOffset::Regular(
1274 RegularBitOffset {
1275 offset: 18,
1276 },
1277 ),
1278 bit_size: 1,
1279 array: None,
1280 enumm: None,
1281 },
1282 Field {
1283 name: "gfxmmurst",
1284 description: Some(
1285 "GFXMMU reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
1286 ),
1287 bit_offset: BitOffset::Regular(
1288 RegularBitOffset {
1289 offset: 19,
1290 },
1291 ),
1292 bit_size: 1,
1293 array: None,
1294 enumm: None,
1295 },
1296 Field {
1297 name: "gpu2drst",
1298 description: Some(
1299 "GPU2D reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
1300 ),
1301 bit_offset: BitOffset::Regular(
1302 RegularBitOffset {
1303 offset: 20,
1304 },
1305 ),
1306 bit_size: 1,
1307 array: None,
1308 enumm: None,
1309 },
1310 ],
1311 },
1312 FieldSet {
1313 name: "Ahb1smenr",
1314 extends: None,
1315 description: Some(
1316 "RCC AHB1 peripheral clocks enable in Sleep and Stop modes register",
1317 ),
1318 bit_size: 32,
1319 fields: &[
1320 Field {
1321 name: "gpdma1smen",
1322 description: Some(
1323 "GPDMA1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
1324 ),
1325 bit_offset: BitOffset::Regular(
1326 RegularBitOffset {
1327 offset: 0,
1328 },
1329 ),
1330 bit_size: 1,
1331 array: None,
1332 enumm: None,
1333 },
1334 Field {
1335 name: "cordicsmen",
1336 description: Some(
1337 "CORDIC clocks enable during Sleep and Stop modes\r Set and cleared by software during Sleep mode.",
1338 ),
1339 bit_offset: BitOffset::Regular(
1340 RegularBitOffset {
1341 offset: 1,
1342 },
1343 ),
1344 bit_size: 1,
1345 array: None,
1346 enumm: None,
1347 },
1348 Field {
1349 name: "fmacsmen",
1350 description: Some(
1351 "FMAC clocks enable during Sleep and Stop modes.\r Set and cleared by software.",
1352 ),
1353 bit_offset: BitOffset::Regular(
1354 RegularBitOffset {
1355 offset: 2,
1356 },
1357 ),
1358 bit_size: 1,
1359 array: None,
1360 enumm: None,
1361 },
1362 Field {
1363 name: "mdf1smen",
1364 description: Some(
1365 "MDF1 clocks enable during Sleep and Stop modes.\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
1366 ),
1367 bit_offset: BitOffset::Regular(
1368 RegularBitOffset {
1369 offset: 3,
1370 },
1371 ),
1372 bit_size: 1,
1373 array: None,
1374 enumm: None,
1375 },
1376 Field {
1377 name: "flashsmen",
1378 description: Some(
1379 "FLASH clocks enable during Sleep and Stop modes\r Set and cleared by software.",
1380 ),
1381 bit_offset: BitOffset::Regular(
1382 RegularBitOffset {
1383 offset: 8,
1384 },
1385 ),
1386 bit_size: 1,
1387 array: None,
1388 enumm: None,
1389 },
1390 Field {
1391 name: "crcsmen",
1392 description: Some(
1393 "CRC clocks enable during Sleep and Stop modes\r Set and cleared by software.",
1394 ),
1395 bit_offset: BitOffset::Regular(
1396 RegularBitOffset {
1397 offset: 12,
1398 },
1399 ),
1400 bit_size: 1,
1401 array: None,
1402 enumm: None,
1403 },
1404 Field {
1405 name: "jpegsmen",
1406 description: Some(
1407 "JPEG clocks enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
1408 ),
1409 bit_offset: BitOffset::Regular(
1410 RegularBitOffset {
1411 offset: 15,
1412 },
1413 ),
1414 bit_size: 1,
1415 array: None,
1416 enumm: None,
1417 },
1418 Field {
1419 name: "tscsmen",
1420 description: Some(
1421 "TSC clocks enable during Sleep and Stop modes\r Set and cleared by software.",
1422 ),
1423 bit_offset: BitOffset::Regular(
1424 RegularBitOffset {
1425 offset: 16,
1426 },
1427 ),
1428 bit_size: 1,
1429 array: None,
1430 enumm: None,
1431 },
1432 Field {
1433 name: "ramcfgsmen",
1434 description: Some(
1435 "RAMCFG clocks enable during Sleep and Stop modes\r Set and cleared by software.",
1436 ),
1437 bit_offset: BitOffset::Regular(
1438 RegularBitOffset {
1439 offset: 17,
1440 },
1441 ),
1442 bit_size: 1,
1443 array: None,
1444 enumm: None,
1445 },
1446 Field {
1447 name: "dma2dsmen",
1448 description: Some(
1449 "DMA2D clocks enable during Sleep and Stop modes\r Set and cleared by software.",
1450 ),
1451 bit_offset: BitOffset::Regular(
1452 RegularBitOffset {
1453 offset: 18,
1454 },
1455 ),
1456 bit_size: 1,
1457 array: None,
1458 enumm: None,
1459 },
1460 Field {
1461 name: "gfxmmusmen",
1462 description: Some(
1463 "GFXMMU clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
1464 ),
1465 bit_offset: BitOffset::Regular(
1466 RegularBitOffset {
1467 offset: 19,
1468 },
1469 ),
1470 bit_size: 1,
1471 array: None,
1472 enumm: None,
1473 },
1474 Field {
1475 name: "gpu2dsmen",
1476 description: Some(
1477 "GPU2D clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
1478 ),
1479 bit_offset: BitOffset::Regular(
1480 RegularBitOffset {
1481 offset: 20,
1482 },
1483 ),
1484 bit_size: 1,
1485 array: None,
1486 enumm: None,
1487 },
1488 Field {
1489 name: "dcache2smen",
1490 description: Some(
1491 "DCACHE2 clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
1492 ),
1493 bit_offset: BitOffset::Regular(
1494 RegularBitOffset {
1495 offset: 21,
1496 },
1497 ),
1498 bit_size: 1,
1499 array: None,
1500 enumm: None,
1501 },
1502 Field {
1503 name: "gtzc1smen",
1504 description: Some(
1505 "GTZC1 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
1506 ),
1507 bit_offset: BitOffset::Regular(
1508 RegularBitOffset {
1509 offset: 24,
1510 },
1511 ),
1512 bit_size: 1,
1513 array: None,
1514 enumm: None,
1515 },
1516 Field {
1517 name: "bkpsramsmen",
1518 description: Some(
1519 "BKPSRAM clocks enable during Sleep and Stop modes\r Set and cleared by software",
1520 ),
1521 bit_offset: BitOffset::Regular(
1522 RegularBitOffset {
1523 offset: 28,
1524 },
1525 ),
1526 bit_size: 1,
1527 array: None,
1528 enumm: None,
1529 },
1530 Field {
1531 name: "icachesmen",
1532 description: Some(
1533 "ICACHE clocks enable during Sleep and Stop modes\r Set and cleared by software.",
1534 ),
1535 bit_offset: BitOffset::Regular(
1536 RegularBitOffset {
1537 offset: 29,
1538 },
1539 ),
1540 bit_size: 1,
1541 array: None,
1542 enumm: None,
1543 },
1544 Field {
1545 name: "dcache1smen",
1546 description: Some(
1547 "DCACHE1 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
1548 ),
1549 bit_offset: BitOffset::Regular(
1550 RegularBitOffset {
1551 offset: 30,
1552 },
1553 ),
1554 bit_size: 1,
1555 array: None,
1556 enumm: None,
1557 },
1558 Field {
1559 name: "sram1smen",
1560 description: Some(
1561 "SRAM1 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
1562 ),
1563 bit_offset: BitOffset::Regular(
1564 RegularBitOffset {
1565 offset: 31,
1566 },
1567 ),
1568 bit_size: 1,
1569 array: None,
1570 enumm: None,
1571 },
1572 ],
1573 },
1574 FieldSet {
1575 name: "Ahb2enr1",
1576 extends: None,
1577 description: Some(
1578 "RCC AHB2 peripheral clock enable register 1",
1579 ),
1580 bit_size: 32,
1581 fields: &[
1582 Field {
1583 name: "gpioaen",
1584 description: Some(
1585 "IO port A clock enable\r Set and cleared by software.",
1586 ),
1587 bit_offset: BitOffset::Regular(
1588 RegularBitOffset {
1589 offset: 0,
1590 },
1591 ),
1592 bit_size: 1,
1593 array: None,
1594 enumm: None,
1595 },
1596 Field {
1597 name: "gpioben",
1598 description: Some(
1599 "IO port B clock enable\r Set and cleared by software.",
1600 ),
1601 bit_offset: BitOffset::Regular(
1602 RegularBitOffset {
1603 offset: 1,
1604 },
1605 ),
1606 bit_size: 1,
1607 array: None,
1608 enumm: None,
1609 },
1610 Field {
1611 name: "gpiocen",
1612 description: Some(
1613 "IO port C clock enable\r Set and cleared by software.",
1614 ),
1615 bit_offset: BitOffset::Regular(
1616 RegularBitOffset {
1617 offset: 2,
1618 },
1619 ),
1620 bit_size: 1,
1621 array: None,
1622 enumm: None,
1623 },
1624 Field {
1625 name: "gpioden",
1626 description: Some(
1627 "IO port D clock enable\r Set and cleared by software.",
1628 ),
1629 bit_offset: BitOffset::Regular(
1630 RegularBitOffset {
1631 offset: 3,
1632 },
1633 ),
1634 bit_size: 1,
1635 array: None,
1636 enumm: None,
1637 },
1638 Field {
1639 name: "gpioeen",
1640 description: Some(
1641 "IO port E clock enable\r Set and cleared by software.",
1642 ),
1643 bit_offset: BitOffset::Regular(
1644 RegularBitOffset {
1645 offset: 4,
1646 },
1647 ),
1648 bit_size: 1,
1649 array: None,
1650 enumm: None,
1651 },
1652 Field {
1653 name: "gpiofen",
1654 description: Some(
1655 "IO port F clock enable\r Set and cleared by software.",
1656 ),
1657 bit_offset: BitOffset::Regular(
1658 RegularBitOffset {
1659 offset: 5,
1660 },
1661 ),
1662 bit_size: 1,
1663 array: None,
1664 enumm: None,
1665 },
1666 Field {
1667 name: "gpiogen",
1668 description: Some(
1669 "IO port G clock enable\r Set and cleared by software.",
1670 ),
1671 bit_offset: BitOffset::Regular(
1672 RegularBitOffset {
1673 offset: 6,
1674 },
1675 ),
1676 bit_size: 1,
1677 array: None,
1678 enumm: None,
1679 },
1680 Field {
1681 name: "gpiohen",
1682 description: Some(
1683 "IO port H clock enable\r Set and cleared by software.",
1684 ),
1685 bit_offset: BitOffset::Regular(
1686 RegularBitOffset {
1687 offset: 7,
1688 },
1689 ),
1690 bit_size: 1,
1691 array: None,
1692 enumm: None,
1693 },
1694 Field {
1695 name: "gpioien",
1696 description: Some(
1697 "IO port I clock enable\r Set and cleared by software.",
1698 ),
1699 bit_offset: BitOffset::Regular(
1700 RegularBitOffset {
1701 offset: 8,
1702 },
1703 ),
1704 bit_size: 1,
1705 array: None,
1706 enumm: None,
1707 },
1708 Field {
1709 name: "gpiojen",
1710 description: Some(
1711 "I/O port J clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
1712 ),
1713 bit_offset: BitOffset::Regular(
1714 RegularBitOffset {
1715 offset: 9,
1716 },
1717 ),
1718 bit_size: 1,
1719 array: None,
1720 enumm: None,
1721 },
1722 Field {
1723 name: "adc12en",
1724 description: Some(
1725 "ADC1 and ADC2 clock enable\r This bit is set and cleared by software.\r Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx.",
1726 ),
1727 bit_offset: BitOffset::Regular(
1728 RegularBitOffset {
1729 offset: 10,
1730 },
1731 ),
1732 bit_size: 1,
1733 array: None,
1734 enumm: None,
1735 },
1736 Field {
1737 name: "dcmien",
1738 description: Some(
1739 "DCMI and PSSI clock enable\r Set and cleared by software.",
1740 ),
1741 bit_offset: BitOffset::Regular(
1742 RegularBitOffset {
1743 offset: 12,
1744 },
1745 ),
1746 bit_size: 1,
1747 array: None,
1748 enumm: None,
1749 },
1750 Field {
1751 name: "usb_otg_fsen",
1752 description: Some(
1753 "OTG_FS clock enable\r Set and cleared by software.",
1754 ),
1755 bit_offset: BitOffset::Regular(
1756 RegularBitOffset {
1757 offset: 14,
1758 },
1759 ),
1760 bit_size: 1,
1761 array: None,
1762 enumm: None,
1763 },
1764 Field {
1765 name: "usb_otg_hsen",
1766 description: Some(
1767 "OTG_HS clock enable\r Set and cleared by software.",
1768 ),
1769 bit_offset: BitOffset::Regular(
1770 RegularBitOffset {
1771 offset: 14,
1772 },
1773 ),
1774 bit_size: 1,
1775 array: None,
1776 enumm: None,
1777 },
1778 Field {
1779 name: "usb_otg_hs_phyen",
1780 description: Some(
1781 "OTG_HS PHY clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
1782 ),
1783 bit_offset: BitOffset::Regular(
1784 RegularBitOffset {
1785 offset: 15,
1786 },
1787 ),
1788 bit_size: 1,
1789 array: None,
1790 enumm: None,
1791 },
1792 Field {
1793 name: "aesen",
1794 description: Some(
1795 "AES clock enable\r Set and cleared by software.",
1796 ),
1797 bit_offset: BitOffset::Regular(
1798 RegularBitOffset {
1799 offset: 16,
1800 },
1801 ),
1802 bit_size: 1,
1803 array: None,
1804 enumm: None,
1805 },
1806 Field {
1807 name: "hashen",
1808 description: Some(
1809 "HASH clock enable\r Set and cleared by software",
1810 ),
1811 bit_offset: BitOffset::Regular(
1812 RegularBitOffset {
1813 offset: 17,
1814 },
1815 ),
1816 bit_size: 1,
1817 array: None,
1818 enumm: None,
1819 },
1820 Field {
1821 name: "rngen",
1822 description: Some(
1823 "RNG clock enable\r Set and cleared by software.",
1824 ),
1825 bit_offset: BitOffset::Regular(
1826 RegularBitOffset {
1827 offset: 18,
1828 },
1829 ),
1830 bit_size: 1,
1831 array: None,
1832 enumm: None,
1833 },
1834 Field {
1835 name: "pkaen",
1836 description: Some(
1837 "PKA clock enable\r Set and cleared by software.",
1838 ),
1839 bit_offset: BitOffset::Regular(
1840 RegularBitOffset {
1841 offset: 19,
1842 },
1843 ),
1844 bit_size: 1,
1845 array: None,
1846 enumm: None,
1847 },
1848 Field {
1849 name: "saesen",
1850 description: Some(
1851 "SAES clock enable\r Set and cleared by software.",
1852 ),
1853 bit_offset: BitOffset::Regular(
1854 RegularBitOffset {
1855 offset: 20,
1856 },
1857 ),
1858 bit_size: 1,
1859 array: None,
1860 enumm: None,
1861 },
1862 Field {
1863 name: "octospimen",
1864 description: Some(
1865 "OCTOSPIM clock enable\r Set and cleared by software.",
1866 ),
1867 bit_offset: BitOffset::Regular(
1868 RegularBitOffset {
1869 offset: 21,
1870 },
1871 ),
1872 bit_size: 1,
1873 array: None,
1874 enumm: None,
1875 },
1876 Field {
1877 name: "otfdec1en",
1878 description: Some(
1879 "OTFDEC1 clock enable\r Set and cleared by software.",
1880 ),
1881 bit_offset: BitOffset::Regular(
1882 RegularBitOffset {
1883 offset: 23,
1884 },
1885 ),
1886 bit_size: 1,
1887 array: None,
1888 enumm: None,
1889 },
1890 Field {
1891 name: "otfdec2en",
1892 description: Some(
1893 "OTFDEC2 clock enable\r Set and cleared by software.",
1894 ),
1895 bit_offset: BitOffset::Regular(
1896 RegularBitOffset {
1897 offset: 24,
1898 },
1899 ),
1900 bit_size: 1,
1901 array: None,
1902 enumm: None,
1903 },
1904 Field {
1905 name: "sdmmc1en",
1906 description: Some(
1907 "SDMMC1 clock enable\r Set and cleared by software.",
1908 ),
1909 bit_offset: BitOffset::Regular(
1910 RegularBitOffset {
1911 offset: 27,
1912 },
1913 ),
1914 bit_size: 1,
1915 array: None,
1916 enumm: None,
1917 },
1918 Field {
1919 name: "sdmmc2en",
1920 description: Some(
1921 "SDMMC2 clock enable\r Set and cleared by software.",
1922 ),
1923 bit_offset: BitOffset::Regular(
1924 RegularBitOffset {
1925 offset: 28,
1926 },
1927 ),
1928 bit_size: 1,
1929 array: None,
1930 enumm: None,
1931 },
1932 Field {
1933 name: "sram2en",
1934 description: Some(
1935 "SRAM2 clock enable\r Set and reset by software.",
1936 ),
1937 bit_offset: BitOffset::Regular(
1938 RegularBitOffset {
1939 offset: 30,
1940 },
1941 ),
1942 bit_size: 1,
1943 array: None,
1944 enumm: None,
1945 },
1946 Field {
1947 name: "sram3en",
1948 description: Some(
1949 "SRAM3 clock enable\r Set and reset by software.",
1950 ),
1951 bit_offset: BitOffset::Regular(
1952 RegularBitOffset {
1953 offset: 31,
1954 },
1955 ),
1956 bit_size: 1,
1957 array: None,
1958 enumm: None,
1959 },
1960 ],
1961 },
1962 FieldSet {
1963 name: "Ahb2enr2",
1964 extends: None,
1965 description: Some(
1966 "RCC AHB2 peripheral clock enable register 2",
1967 ),
1968 bit_size: 32,
1969 fields: &[
1970 Field {
1971 name: "fsmcen",
1972 description: Some(
1973 "FSMC clock enable\r Set and cleared by software.",
1974 ),
1975 bit_offset: BitOffset::Regular(
1976 RegularBitOffset {
1977 offset: 0,
1978 },
1979 ),
1980 bit_size: 1,
1981 array: None,
1982 enumm: None,
1983 },
1984 Field {
1985 name: "octospi1en",
1986 description: Some(
1987 "OCTOSPI1 clock enable\r Set and cleared by software.",
1988 ),
1989 bit_offset: BitOffset::Regular(
1990 RegularBitOffset {
1991 offset: 4,
1992 },
1993 ),
1994 bit_size: 1,
1995 array: None,
1996 enumm: None,
1997 },
1998 Field {
1999 name: "octospi2en",
2000 description: Some(
2001 "OCTOSPI2 clock enable\r Set and cleared by software.",
2002 ),
2003 bit_offset: BitOffset::Regular(
2004 RegularBitOffset {
2005 offset: 8,
2006 },
2007 ),
2008 bit_size: 1,
2009 array: None,
2010 enumm: None,
2011 },
2012 Field {
2013 name: "hspi1en",
2014 description: Some(
2015 "HSPI1 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
2016 ),
2017 bit_offset: BitOffset::Regular(
2018 RegularBitOffset {
2019 offset: 12,
2020 },
2021 ),
2022 bit_size: 1,
2023 array: None,
2024 enumm: None,
2025 },
2026 Field {
2027 name: "sram6en",
2028 description: Some(
2029 "SRAM6 clock enable \r This bit is set and reset by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
2030 ),
2031 bit_offset: BitOffset::Regular(
2032 RegularBitOffset {
2033 offset: 30,
2034 },
2035 ),
2036 bit_size: 1,
2037 array: None,
2038 enumm: None,
2039 },
2040 Field {
2041 name: "sram5en",
2042 description: Some(
2043 "SRAM5 clock enable \r This bit is set and reset by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
2044 ),
2045 bit_offset: BitOffset::Regular(
2046 RegularBitOffset {
2047 offset: 31,
2048 },
2049 ),
2050 bit_size: 1,
2051 array: None,
2052 enumm: None,
2053 },
2054 ],
2055 },
2056 FieldSet {
2057 name: "Ahb2rstr1",
2058 extends: None,
2059 description: Some(
2060 "RCC AHB2 peripheral reset register 1",
2061 ),
2062 bit_size: 32,
2063 fields: &[
2064 Field {
2065 name: "gpioarst",
2066 description: Some(
2067 "IO port A reset\r Set and cleared by software.",
2068 ),
2069 bit_offset: BitOffset::Regular(
2070 RegularBitOffset {
2071 offset: 0,
2072 },
2073 ),
2074 bit_size: 1,
2075 array: None,
2076 enumm: None,
2077 },
2078 Field {
2079 name: "gpiobrst",
2080 description: Some(
2081 "IO port B reset\r Set and cleared by software.",
2082 ),
2083 bit_offset: BitOffset::Regular(
2084 RegularBitOffset {
2085 offset: 1,
2086 },
2087 ),
2088 bit_size: 1,
2089 array: None,
2090 enumm: None,
2091 },
2092 Field {
2093 name: "gpiocrst",
2094 description: Some(
2095 "IO port C reset\r Set and cleared by software.",
2096 ),
2097 bit_offset: BitOffset::Regular(
2098 RegularBitOffset {
2099 offset: 2,
2100 },
2101 ),
2102 bit_size: 1,
2103 array: None,
2104 enumm: None,
2105 },
2106 Field {
2107 name: "gpiodrst",
2108 description: Some(
2109 "IO port D reset\r Set and cleared by software.",
2110 ),
2111 bit_offset: BitOffset::Regular(
2112 RegularBitOffset {
2113 offset: 3,
2114 },
2115 ),
2116 bit_size: 1,
2117 array: None,
2118 enumm: None,
2119 },
2120 Field {
2121 name: "gpioerst",
2122 description: Some(
2123 "IO port E reset\r Set and cleared by software.",
2124 ),
2125 bit_offset: BitOffset::Regular(
2126 RegularBitOffset {
2127 offset: 4,
2128 },
2129 ),
2130 bit_size: 1,
2131 array: None,
2132 enumm: None,
2133 },
2134 Field {
2135 name: "gpiofrst",
2136 description: Some(
2137 "IO port F reset\r Set and cleared by software.",
2138 ),
2139 bit_offset: BitOffset::Regular(
2140 RegularBitOffset {
2141 offset: 5,
2142 },
2143 ),
2144 bit_size: 1,
2145 array: None,
2146 enumm: None,
2147 },
2148 Field {
2149 name: "gpiogrst",
2150 description: Some(
2151 "IO port G reset\r Set and cleared by software.",
2152 ),
2153 bit_offset: BitOffset::Regular(
2154 RegularBitOffset {
2155 offset: 6,
2156 },
2157 ),
2158 bit_size: 1,
2159 array: None,
2160 enumm: None,
2161 },
2162 Field {
2163 name: "gpiohrst",
2164 description: Some(
2165 "IO port H reset\r Set and cleared by software.",
2166 ),
2167 bit_offset: BitOffset::Regular(
2168 RegularBitOffset {
2169 offset: 7,
2170 },
2171 ),
2172 bit_size: 1,
2173 array: None,
2174 enumm: None,
2175 },
2176 Field {
2177 name: "gpioirst",
2178 description: Some(
2179 "IO port I reset\r Set and cleared by software.",
2180 ),
2181 bit_offset: BitOffset::Regular(
2182 RegularBitOffset {
2183 offset: 8,
2184 },
2185 ),
2186 bit_size: 1,
2187 array: None,
2188 enumm: None,
2189 },
2190 Field {
2191 name: "gpiojrst",
2192 description: Some(
2193 "I/O port J reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
2194 ),
2195 bit_offset: BitOffset::Regular(
2196 RegularBitOffset {
2197 offset: 9,
2198 },
2199 ),
2200 bit_size: 1,
2201 array: None,
2202 enumm: None,
2203 },
2204 Field {
2205 name: "adc12rst",
2206 description: Some(
2207 "ADC1 and ADC2 reset\r This bit is set and cleared by software.\r Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx.",
2208 ),
2209 bit_offset: BitOffset::Regular(
2210 RegularBitOffset {
2211 offset: 10,
2212 },
2213 ),
2214 bit_size: 1,
2215 array: None,
2216 enumm: None,
2217 },
2218 Field {
2219 name: "dcmirst",
2220 description: Some(
2221 "DCMI and PSSI reset\r Set and cleared by software.",
2222 ),
2223 bit_offset: BitOffset::Regular(
2224 RegularBitOffset {
2225 offset: 12,
2226 },
2227 ),
2228 bit_size: 1,
2229 array: None,
2230 enumm: None,
2231 },
2232 Field {
2233 name: "usb_otg_fsrst",
2234 description: Some(
2235 "OTG_FS reset\r Set and cleared by software.",
2236 ),
2237 bit_offset: BitOffset::Regular(
2238 RegularBitOffset {
2239 offset: 14,
2240 },
2241 ),
2242 bit_size: 1,
2243 array: None,
2244 enumm: None,
2245 },
2246 Field {
2247 name: "usb_otg_hsrst",
2248 description: Some(
2249 "OTG_HS reset\r Set and cleared by software.",
2250 ),
2251 bit_offset: BitOffset::Regular(
2252 RegularBitOffset {
2253 offset: 14,
2254 },
2255 ),
2256 bit_size: 1,
2257 array: None,
2258 enumm: None,
2259 },
2260 Field {
2261 name: "aesrst",
2262 description: Some(
2263 "AES hardware accelerator reset\r Set and cleared by software.",
2264 ),
2265 bit_offset: BitOffset::Regular(
2266 RegularBitOffset {
2267 offset: 16,
2268 },
2269 ),
2270 bit_size: 1,
2271 array: None,
2272 enumm: None,
2273 },
2274 Field {
2275 name: "hashrst",
2276 description: Some(
2277 "Hash reset\r Set and cleared by software.",
2278 ),
2279 bit_offset: BitOffset::Regular(
2280 RegularBitOffset {
2281 offset: 17,
2282 },
2283 ),
2284 bit_size: 1,
2285 array: None,
2286 enumm: None,
2287 },
2288 Field {
2289 name: "rngrst",
2290 description: Some(
2291 "Random number generator reset\r Set and cleared by software.",
2292 ),
2293 bit_offset: BitOffset::Regular(
2294 RegularBitOffset {
2295 offset: 18,
2296 },
2297 ),
2298 bit_size: 1,
2299 array: None,
2300 enumm: None,
2301 },
2302 Field {
2303 name: "pkarst",
2304 description: Some(
2305 "PKA reset\r Set and cleared by software.",
2306 ),
2307 bit_offset: BitOffset::Regular(
2308 RegularBitOffset {
2309 offset: 19,
2310 },
2311 ),
2312 bit_size: 1,
2313 array: None,
2314 enumm: None,
2315 },
2316 Field {
2317 name: "saesrst",
2318 description: Some(
2319 "SAES hardware accelerator reset\r Set and cleared by software.",
2320 ),
2321 bit_offset: BitOffset::Regular(
2322 RegularBitOffset {
2323 offset: 20,
2324 },
2325 ),
2326 bit_size: 1,
2327 array: None,
2328 enumm: None,
2329 },
2330 Field {
2331 name: "octospimrst",
2332 description: Some(
2333 "OCTOSPIM reset\r Set and cleared by software.",
2334 ),
2335 bit_offset: BitOffset::Regular(
2336 RegularBitOffset {
2337 offset: 21,
2338 },
2339 ),
2340 bit_size: 1,
2341 array: None,
2342 enumm: None,
2343 },
2344 Field {
2345 name: "otfdec1rst",
2346 description: Some(
2347 "OTFDEC1 reset\r Set and cleared by software.",
2348 ),
2349 bit_offset: BitOffset::Regular(
2350 RegularBitOffset {
2351 offset: 23,
2352 },
2353 ),
2354 bit_size: 1,
2355 array: None,
2356 enumm: None,
2357 },
2358 Field {
2359 name: "otfdec2rst",
2360 description: Some(
2361 "OTFDEC2 reset\r Set and cleared by software.",
2362 ),
2363 bit_offset: BitOffset::Regular(
2364 RegularBitOffset {
2365 offset: 24,
2366 },
2367 ),
2368 bit_size: 1,
2369 array: None,
2370 enumm: None,
2371 },
2372 Field {
2373 name: "sdmmc1rst",
2374 description: Some(
2375 "SDMMC1 reset\r Set and cleared by software.",
2376 ),
2377 bit_offset: BitOffset::Regular(
2378 RegularBitOffset {
2379 offset: 27,
2380 },
2381 ),
2382 bit_size: 1,
2383 array: None,
2384 enumm: None,
2385 },
2386 Field {
2387 name: "sdmmc2rst",
2388 description: Some(
2389 "SDMMC2 reset\r Set and cleared by software.",
2390 ),
2391 bit_offset: BitOffset::Regular(
2392 RegularBitOffset {
2393 offset: 28,
2394 },
2395 ),
2396 bit_size: 1,
2397 array: None,
2398 enumm: None,
2399 },
2400 ],
2401 },
2402 FieldSet {
2403 name: "Ahb2rstr2",
2404 extends: None,
2405 description: Some(
2406 "RCC AHB2 peripheral reset register 2",
2407 ),
2408 bit_size: 32,
2409 fields: &[
2410 Field {
2411 name: "fsmcrst",
2412 description: Some(
2413 "Flexible memory controller reset\r Set and cleared by software.",
2414 ),
2415 bit_offset: BitOffset::Regular(
2416 RegularBitOffset {
2417 offset: 0,
2418 },
2419 ),
2420 bit_size: 1,
2421 array: None,
2422 enumm: None,
2423 },
2424 Field {
2425 name: "octospi1rst",
2426 description: Some(
2427 "OCTOSPI1 reset\r Set and cleared by software.",
2428 ),
2429 bit_offset: BitOffset::Regular(
2430 RegularBitOffset {
2431 offset: 4,
2432 },
2433 ),
2434 bit_size: 1,
2435 array: None,
2436 enumm: None,
2437 },
2438 Field {
2439 name: "octospi2rst",
2440 description: Some(
2441 "OCTOSPI2 reset\r Set and cleared by software.",
2442 ),
2443 bit_offset: BitOffset::Regular(
2444 RegularBitOffset {
2445 offset: 8,
2446 },
2447 ),
2448 bit_size: 1,
2449 array: None,
2450 enumm: None,
2451 },
2452 Field {
2453 name: "hspi1rst",
2454 description: Some(
2455 "HSPI1 reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
2456 ),
2457 bit_offset: BitOffset::Regular(
2458 RegularBitOffset {
2459 offset: 12,
2460 },
2461 ),
2462 bit_size: 1,
2463 array: None,
2464 enumm: None,
2465 },
2466 ],
2467 },
2468 FieldSet {
2469 name: "Ahb2smenr1",
2470 extends: None,
2471 description: Some(
2472 "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 1",
2473 ),
2474 bit_size: 32,
2475 fields: &[
2476 Field {
2477 name: "gpioasmen",
2478 description: Some(
2479 "IO port A clocks enable during Sleep and Stop modes\r Set and cleared by software.",
2480 ),
2481 bit_offset: BitOffset::Regular(
2482 RegularBitOffset {
2483 offset: 0,
2484 },
2485 ),
2486 bit_size: 1,
2487 array: None,
2488 enumm: None,
2489 },
2490 Field {
2491 name: "gpiobsmen",
2492 description: Some(
2493 "IO port B clocks enable during Sleep and Stop modes\r Set and cleared by software.",
2494 ),
2495 bit_offset: BitOffset::Regular(
2496 RegularBitOffset {
2497 offset: 1,
2498 },
2499 ),
2500 bit_size: 1,
2501 array: None,
2502 enumm: None,
2503 },
2504 Field {
2505 name: "gpiocsmen",
2506 description: Some(
2507 "IO port C clocks enable during Sleep and Stop modes\r Set and cleared by software.",
2508 ),
2509 bit_offset: BitOffset::Regular(
2510 RegularBitOffset {
2511 offset: 2,
2512 },
2513 ),
2514 bit_size: 1,
2515 array: None,
2516 enumm: None,
2517 },
2518 Field {
2519 name: "gpiodsmen",
2520 description: Some(
2521 "IO port D clocks enable during Sleep and Stop modes\r Set and cleared by software.",
2522 ),
2523 bit_offset: BitOffset::Regular(
2524 RegularBitOffset {
2525 offset: 3,
2526 },
2527 ),
2528 bit_size: 1,
2529 array: None,
2530 enumm: None,
2531 },
2532 Field {
2533 name: "gpioesmen",
2534 description: Some(
2535 "IO port E clocks enable during Sleep and Stop modes\r Set and cleared by software.",
2536 ),
2537 bit_offset: BitOffset::Regular(
2538 RegularBitOffset {
2539 offset: 4,
2540 },
2541 ),
2542 bit_size: 1,
2543 array: None,
2544 enumm: None,
2545 },
2546 Field {
2547 name: "gpiofsmen",
2548 description: Some(
2549 "IO port F clocks enable during Sleep and Stop modes\r Set and cleared by software.",
2550 ),
2551 bit_offset: BitOffset::Regular(
2552 RegularBitOffset {
2553 offset: 5,
2554 },
2555 ),
2556 bit_size: 1,
2557 array: None,
2558 enumm: None,
2559 },
2560 Field {
2561 name: "gpiogsmen",
2562 description: Some(
2563 "IO port G clocks enable during Sleep and Stop modes\r Set and cleared by software.",
2564 ),
2565 bit_offset: BitOffset::Regular(
2566 RegularBitOffset {
2567 offset: 6,
2568 },
2569 ),
2570 bit_size: 1,
2571 array: None,
2572 enumm: None,
2573 },
2574 Field {
2575 name: "gpiohsmen",
2576 description: Some(
2577 "IO port H clocks enable during Sleep and Stop modes\r Set and cleared by software.",
2578 ),
2579 bit_offset: BitOffset::Regular(
2580 RegularBitOffset {
2581 offset: 7,
2582 },
2583 ),
2584 bit_size: 1,
2585 array: None,
2586 enumm: None,
2587 },
2588 Field {
2589 name: "gpioismen",
2590 description: Some(
2591 "IO port I clocks enable during Sleep and Stop modes\r Set and cleared by software.",
2592 ),
2593 bit_offset: BitOffset::Regular(
2594 RegularBitOffset {
2595 offset: 8,
2596 },
2597 ),
2598 bit_size: 1,
2599 array: None,
2600 enumm: None,
2601 },
2602 Field {
2603 name: "gpiojsmen",
2604 description: Some(
2605 "I/O port J clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
2606 ),
2607 bit_offset: BitOffset::Regular(
2608 RegularBitOffset {
2609 offset: 9,
2610 },
2611 ),
2612 bit_size: 1,
2613 array: None,
2614 enumm: None,
2615 },
2616 Field {
2617 name: "adc12smen",
2618 description: Some(
2619 "ADC1 and ADC2 clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit impacts ADC1 in STM32U535/545/575/585 and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx.",
2620 ),
2621 bit_offset: BitOffset::Regular(
2622 RegularBitOffset {
2623 offset: 10,
2624 },
2625 ),
2626 bit_size: 1,
2627 array: None,
2628 enumm: None,
2629 },
2630 Field {
2631 name: "dcmismen",
2632 description: Some(
2633 "DCMI and PSSI clocks enable during Sleep and Stop modes\r Set and cleared by software.",
2634 ),
2635 bit_offset: BitOffset::Regular(
2636 RegularBitOffset {
2637 offset: 12,
2638 },
2639 ),
2640 bit_size: 1,
2641 array: None,
2642 enumm: None,
2643 },
2644 Field {
2645 name: "usb_otg_fssmen",
2646 description: Some(
2647 "OTG_FS clocks enable during Sleep and Stop modes\r Set and cleared by software.",
2648 ),
2649 bit_offset: BitOffset::Regular(
2650 RegularBitOffset {
2651 offset: 14,
2652 },
2653 ),
2654 bit_size: 1,
2655 array: None,
2656 enumm: None,
2657 },
2658 Field {
2659 name: "usb_otg_hssmen",
2660 description: Some(
2661 "OTG_HS clocks enable during Sleep and Stop modes\r Set and cleared by software.",
2662 ),
2663 bit_offset: BitOffset::Regular(
2664 RegularBitOffset {
2665 offset: 14,
2666 },
2667 ),
2668 bit_size: 1,
2669 array: None,
2670 enumm: None,
2671 },
2672 Field {
2673 name: "usb_otg_hs_physmen",
2674 description: Some(
2675 "OTG_HS PHY clock enable during Sleep and Stop modes\r This bit is set and cleared by software\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
2676 ),
2677 bit_offset: BitOffset::Regular(
2678 RegularBitOffset {
2679 offset: 15,
2680 },
2681 ),
2682 bit_size: 1,
2683 array: None,
2684 enumm: None,
2685 },
2686 Field {
2687 name: "aessmen",
2688 description: Some(
2689 "AES clock enable during Sleep and Stop modes\r Set and cleared by software",
2690 ),
2691 bit_offset: BitOffset::Regular(
2692 RegularBitOffset {
2693 offset: 16,
2694 },
2695 ),
2696 bit_size: 1,
2697 array: None,
2698 enumm: None,
2699 },
2700 Field {
2701 name: "hashsmen",
2702 description: Some(
2703 "HASH clock enable during Sleep and Stop modes\r Set and cleared by software",
2704 ),
2705 bit_offset: BitOffset::Regular(
2706 RegularBitOffset {
2707 offset: 17,
2708 },
2709 ),
2710 bit_size: 1,
2711 array: None,
2712 enumm: None,
2713 },
2714 Field {
2715 name: "rngsmen",
2716 description: Some(
2717 "Random number generator (RNG) clocks enable during Sleep and Stop modes\r Set and cleared by software.",
2718 ),
2719 bit_offset: BitOffset::Regular(
2720 RegularBitOffset {
2721 offset: 18,
2722 },
2723 ),
2724 bit_size: 1,
2725 array: None,
2726 enumm: None,
2727 },
2728 Field {
2729 name: "pkasmen",
2730 description: Some(
2731 "PKA clocks enable during Sleep and Stop modes\r Set and cleared by software.",
2732 ),
2733 bit_offset: BitOffset::Regular(
2734 RegularBitOffset {
2735 offset: 19,
2736 },
2737 ),
2738 bit_size: 1,
2739 array: None,
2740 enumm: None,
2741 },
2742 Field {
2743 name: "saessmen",
2744 description: Some(
2745 "SAES accelerator clocks enable during Sleep and Stop modes\r Set and cleared by software.",
2746 ),
2747 bit_offset: BitOffset::Regular(
2748 RegularBitOffset {
2749 offset: 20,
2750 },
2751 ),
2752 bit_size: 1,
2753 array: None,
2754 enumm: None,
2755 },
2756 Field {
2757 name: "octospimsmen",
2758 description: Some(
2759 "OCTOSPIM clocks enable during Sleep and Stop modes\r Set and cleared by software.",
2760 ),
2761 bit_offset: BitOffset::Regular(
2762 RegularBitOffset {
2763 offset: 21,
2764 },
2765 ),
2766 bit_size: 1,
2767 array: None,
2768 enumm: None,
2769 },
2770 Field {
2771 name: "otfdec1smen",
2772 description: Some(
2773 "OTFDEC1 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
2774 ),
2775 bit_offset: BitOffset::Regular(
2776 RegularBitOffset {
2777 offset: 23,
2778 },
2779 ),
2780 bit_size: 1,
2781 array: None,
2782 enumm: None,
2783 },
2784 Field {
2785 name: "otfdec2smen",
2786 description: Some(
2787 "OTFDEC2 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
2788 ),
2789 bit_offset: BitOffset::Regular(
2790 RegularBitOffset {
2791 offset: 24,
2792 },
2793 ),
2794 bit_size: 1,
2795 array: None,
2796 enumm: None,
2797 },
2798 Field {
2799 name: "sdmmc1smen",
2800 description: Some(
2801 "SDMMC1 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
2802 ),
2803 bit_offset: BitOffset::Regular(
2804 RegularBitOffset {
2805 offset: 27,
2806 },
2807 ),
2808 bit_size: 1,
2809 array: None,
2810 enumm: None,
2811 },
2812 Field {
2813 name: "sdmmc2smen",
2814 description: Some(
2815 "SDMMC2 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
2816 ),
2817 bit_offset: BitOffset::Regular(
2818 RegularBitOffset {
2819 offset: 28,
2820 },
2821 ),
2822 bit_size: 1,
2823 array: None,
2824 enumm: None,
2825 },
2826 Field {
2827 name: "sram2smen",
2828 description: Some(
2829 "SRAM2 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
2830 ),
2831 bit_offset: BitOffset::Regular(
2832 RegularBitOffset {
2833 offset: 30,
2834 },
2835 ),
2836 bit_size: 1,
2837 array: None,
2838 enumm: None,
2839 },
2840 Field {
2841 name: "sram3smen",
2842 description: Some(
2843 "SRAM3 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
2844 ),
2845 bit_offset: BitOffset::Regular(
2846 RegularBitOffset {
2847 offset: 31,
2848 },
2849 ),
2850 bit_size: 1,
2851 array: None,
2852 enumm: None,
2853 },
2854 ],
2855 },
2856 FieldSet {
2857 name: "Ahb2smenr2",
2858 extends: None,
2859 description: Some(
2860 "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 2",
2861 ),
2862 bit_size: 32,
2863 fields: &[
2864 Field {
2865 name: "fsmcsmen",
2866 description: Some(
2867 "FSMC clocks enable during Sleep and Stop modes\r Set and cleared by software.",
2868 ),
2869 bit_offset: BitOffset::Regular(
2870 RegularBitOffset {
2871 offset: 0,
2872 },
2873 ),
2874 bit_size: 1,
2875 array: None,
2876 enumm: None,
2877 },
2878 Field {
2879 name: "octospi1smen",
2880 description: Some(
2881 "OCTOSPI1 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
2882 ),
2883 bit_offset: BitOffset::Regular(
2884 RegularBitOffset {
2885 offset: 4,
2886 },
2887 ),
2888 bit_size: 1,
2889 array: None,
2890 enumm: None,
2891 },
2892 Field {
2893 name: "octospi2smen",
2894 description: Some(
2895 "OCTOSPI2 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
2896 ),
2897 bit_offset: BitOffset::Regular(
2898 RegularBitOffset {
2899 offset: 8,
2900 },
2901 ),
2902 bit_size: 1,
2903 array: None,
2904 enumm: None,
2905 },
2906 Field {
2907 name: "hspi1smen",
2908 description: Some(
2909 "HSPI1 clock enable during Sleep and Stop modes \r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
2910 ),
2911 bit_offset: BitOffset::Regular(
2912 RegularBitOffset {
2913 offset: 12,
2914 },
2915 ),
2916 bit_size: 1,
2917 array: None,
2918 enumm: None,
2919 },
2920 Field {
2921 name: "sram6smen",
2922 description: Some(
2923 "SRAM6 clock enable during Sleep and Stop modes \r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
2924 ),
2925 bit_offset: BitOffset::Regular(
2926 RegularBitOffset {
2927 offset: 30,
2928 },
2929 ),
2930 bit_size: 1,
2931 array: None,
2932 enumm: None,
2933 },
2934 Field {
2935 name: "sram5smen",
2936 description: Some(
2937 "SRAM5 clock enable during Sleep and Stop modes \r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
2938 ),
2939 bit_offset: BitOffset::Regular(
2940 RegularBitOffset {
2941 offset: 31,
2942 },
2943 ),
2944 bit_size: 1,
2945 array: None,
2946 enumm: None,
2947 },
2948 ],
2949 },
2950 FieldSet {
2951 name: "Ahb3enr",
2952 extends: None,
2953 description: Some(
2954 "RCC AHB3 peripheral clock enable register",
2955 ),
2956 bit_size: 32,
2957 fields: &[
2958 Field {
2959 name: "lpgpio1en",
2960 description: Some(
2961 "LPGPIO1 enable\r Set and cleared by software.",
2962 ),
2963 bit_offset: BitOffset::Regular(
2964 RegularBitOffset {
2965 offset: 0,
2966 },
2967 ),
2968 bit_size: 1,
2969 array: None,
2970 enumm: None,
2971 },
2972 Field {
2973 name: "pwren",
2974 description: Some(
2975 "PWR clock enable\r Set and cleared by software.",
2976 ),
2977 bit_offset: BitOffset::Regular(
2978 RegularBitOffset {
2979 offset: 2,
2980 },
2981 ),
2982 bit_size: 1,
2983 array: None,
2984 enumm: None,
2985 },
2986 Field {
2987 name: "adc4en",
2988 description: Some(
2989 "ADC4 clock enable\r Set and cleared by software.",
2990 ),
2991 bit_offset: BitOffset::Regular(
2992 RegularBitOffset {
2993 offset: 5,
2994 },
2995 ),
2996 bit_size: 1,
2997 array: None,
2998 enumm: None,
2999 },
3000 Field {
3001 name: "dac1en",
3002 description: Some(
3003 "DAC1 clock enable\r Set and cleared by software.",
3004 ),
3005 bit_offset: BitOffset::Regular(
3006 RegularBitOffset {
3007 offset: 6,
3008 },
3009 ),
3010 bit_size: 1,
3011 array: None,
3012 enumm: None,
3013 },
3014 Field {
3015 name: "lpdma1en",
3016 description: Some(
3017 "LPDMA1 clock enable\r Set and cleared by software.",
3018 ),
3019 bit_offset: BitOffset::Regular(
3020 RegularBitOffset {
3021 offset: 9,
3022 },
3023 ),
3024 bit_size: 1,
3025 array: None,
3026 enumm: None,
3027 },
3028 Field {
3029 name: "adf1en",
3030 description: Some(
3031 "ADF1 clock enable\r Set and cleared by software.",
3032 ),
3033 bit_offset: BitOffset::Regular(
3034 RegularBitOffset {
3035 offset: 10,
3036 },
3037 ),
3038 bit_size: 1,
3039 array: None,
3040 enumm: None,
3041 },
3042 Field {
3043 name: "gtzc2en",
3044 description: Some(
3045 "GTZC2 clock enable\r Set and cleared by software.",
3046 ),
3047 bit_offset: BitOffset::Regular(
3048 RegularBitOffset {
3049 offset: 12,
3050 },
3051 ),
3052 bit_size: 1,
3053 array: None,
3054 enumm: None,
3055 },
3056 Field {
3057 name: "sram4en",
3058 description: Some(
3059 "SRAM4 clock enable\r Set and reset by software.",
3060 ),
3061 bit_offset: BitOffset::Regular(
3062 RegularBitOffset {
3063 offset: 31,
3064 },
3065 ),
3066 bit_size: 1,
3067 array: None,
3068 enumm: None,
3069 },
3070 ],
3071 },
3072 FieldSet {
3073 name: "Ahb3rstr",
3074 extends: None,
3075 description: Some(
3076 "RCC AHB3 peripheral reset register",
3077 ),
3078 bit_size: 32,
3079 fields: &[
3080 Field {
3081 name: "lpgpio1rst",
3082 description: Some(
3083 "LPGPIO1 reset\r Set and cleared by software.",
3084 ),
3085 bit_offset: BitOffset::Regular(
3086 RegularBitOffset {
3087 offset: 0,
3088 },
3089 ),
3090 bit_size: 1,
3091 array: None,
3092 enumm: None,
3093 },
3094 Field {
3095 name: "adc4rst",
3096 description: Some(
3097 "ADC4 reset\r Set and cleared by software.",
3098 ),
3099 bit_offset: BitOffset::Regular(
3100 RegularBitOffset {
3101 offset: 5,
3102 },
3103 ),
3104 bit_size: 1,
3105 array: None,
3106 enumm: None,
3107 },
3108 Field {
3109 name: "dac1rst",
3110 description: Some(
3111 "DAC1 reset\r Set and cleared by software.",
3112 ),
3113 bit_offset: BitOffset::Regular(
3114 RegularBitOffset {
3115 offset: 6,
3116 },
3117 ),
3118 bit_size: 1,
3119 array: None,
3120 enumm: None,
3121 },
3122 Field {
3123 name: "lpdma1rst",
3124 description: Some(
3125 "LPDMA1 reset\r Set and cleared by software.",
3126 ),
3127 bit_offset: BitOffset::Regular(
3128 RegularBitOffset {
3129 offset: 9,
3130 },
3131 ),
3132 bit_size: 1,
3133 array: None,
3134 enumm: None,
3135 },
3136 Field {
3137 name: "adf1rst",
3138 description: Some(
3139 "ADF1 reset\r Set and cleared by software.",
3140 ),
3141 bit_offset: BitOffset::Regular(
3142 RegularBitOffset {
3143 offset: 10,
3144 },
3145 ),
3146 bit_size: 1,
3147 array: None,
3148 enumm: None,
3149 },
3150 ],
3151 },
3152 FieldSet {
3153 name: "Ahb3smenr",
3154 extends: None,
3155 description: Some(
3156 "RCC AHB3 peripheral clocks enable in Sleep and Stop modes register",
3157 ),
3158 bit_size: 32,
3159 fields: &[
3160 Field {
3161 name: "lpgpio1smen",
3162 description: Some(
3163 "LPGPIO1 enable during Sleep and Stop modes\r Set and cleared by software.",
3164 ),
3165 bit_offset: BitOffset::Regular(
3166 RegularBitOffset {
3167 offset: 0,
3168 },
3169 ),
3170 bit_size: 1,
3171 array: None,
3172 enumm: None,
3173 },
3174 Field {
3175 name: "pwrsmen",
3176 description: Some(
3177 "PWR clock enable during Sleep and Stop modes\r Set and cleared by software.",
3178 ),
3179 bit_offset: BitOffset::Regular(
3180 RegularBitOffset {
3181 offset: 2,
3182 },
3183 ),
3184 bit_size: 1,
3185 array: None,
3186 enumm: None,
3187 },
3188 Field {
3189 name: "adc4smen",
3190 description: Some(
3191 "ADC4 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
3192 ),
3193 bit_offset: BitOffset::Regular(
3194 RegularBitOffset {
3195 offset: 5,
3196 },
3197 ),
3198 bit_size: 1,
3199 array: None,
3200 enumm: None,
3201 },
3202 Field {
3203 name: "dac1smen",
3204 description: Some(
3205 "DAC1 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
3206 ),
3207 bit_offset: BitOffset::Regular(
3208 RegularBitOffset {
3209 offset: 6,
3210 },
3211 ),
3212 bit_size: 1,
3213 array: None,
3214 enumm: None,
3215 },
3216 Field {
3217 name: "lpdma1smen",
3218 description: Some(
3219 "LPDMA1 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
3220 ),
3221 bit_offset: BitOffset::Regular(
3222 RegularBitOffset {
3223 offset: 9,
3224 },
3225 ),
3226 bit_size: 1,
3227 array: None,
3228 enumm: None,
3229 },
3230 Field {
3231 name: "adf1smen",
3232 description: Some(
3233 "ADF1 clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
3234 ),
3235 bit_offset: BitOffset::Regular(
3236 RegularBitOffset {
3237 offset: 10,
3238 },
3239 ),
3240 bit_size: 1,
3241 array: None,
3242 enumm: None,
3243 },
3244 Field {
3245 name: "gtzc2smen",
3246 description: Some(
3247 "GTZC2 clock enable during Sleep and Stop modes\r Set and cleared by software.",
3248 ),
3249 bit_offset: BitOffset::Regular(
3250 RegularBitOffset {
3251 offset: 12,
3252 },
3253 ),
3254 bit_size: 1,
3255 array: None,
3256 enumm: None,
3257 },
3258 Field {
3259 name: "sram4smen",
3260 description: Some(
3261 "SRAM4 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
3262 ),
3263 bit_offset: BitOffset::Regular(
3264 RegularBitOffset {
3265 offset: 31,
3266 },
3267 ),
3268 bit_size: 1,
3269 array: None,
3270 enumm: None,
3271 },
3272 ],
3273 },
3274 FieldSet {
3275 name: "Apb1enr1",
3276 extends: None,
3277 description: Some(
3278 "RCC APB1 peripheral clock enable register 1",
3279 ),
3280 bit_size: 32,
3281 fields: &[
3282 Field {
3283 name: "tim2en",
3284 description: Some(
3285 "TIM2 clock enable\r Set and cleared by software.",
3286 ),
3287 bit_offset: BitOffset::Regular(
3288 RegularBitOffset {
3289 offset: 0,
3290 },
3291 ),
3292 bit_size: 1,
3293 array: None,
3294 enumm: None,
3295 },
3296 Field {
3297 name: "tim3en",
3298 description: Some(
3299 "TIM3 clock enable\r Set and cleared by software.",
3300 ),
3301 bit_offset: BitOffset::Regular(
3302 RegularBitOffset {
3303 offset: 1,
3304 },
3305 ),
3306 bit_size: 1,
3307 array: None,
3308 enumm: None,
3309 },
3310 Field {
3311 name: "tim4en",
3312 description: Some(
3313 "TIM4 clock enable\r Set and cleared by software.",
3314 ),
3315 bit_offset: BitOffset::Regular(
3316 RegularBitOffset {
3317 offset: 2,
3318 },
3319 ),
3320 bit_size: 1,
3321 array: None,
3322 enumm: None,
3323 },
3324 Field {
3325 name: "tim5en",
3326 description: Some(
3327 "TIM5 clock enable\r Set and cleared by software.",
3328 ),
3329 bit_offset: BitOffset::Regular(
3330 RegularBitOffset {
3331 offset: 3,
3332 },
3333 ),
3334 bit_size: 1,
3335 array: None,
3336 enumm: None,
3337 },
3338 Field {
3339 name: "tim6en",
3340 description: Some(
3341 "TIM6 clock enable\r Set and cleared by software.",
3342 ),
3343 bit_offset: BitOffset::Regular(
3344 RegularBitOffset {
3345 offset: 4,
3346 },
3347 ),
3348 bit_size: 1,
3349 array: None,
3350 enumm: None,
3351 },
3352 Field {
3353 name: "tim7en",
3354 description: Some(
3355 "TIM7 clock enable\r Set and cleared by software.",
3356 ),
3357 bit_offset: BitOffset::Regular(
3358 RegularBitOffset {
3359 offset: 5,
3360 },
3361 ),
3362 bit_size: 1,
3363 array: None,
3364 enumm: None,
3365 },
3366 Field {
3367 name: "wwdgen",
3368 description: Some(
3369 "WWDG clock enable\r Set by software to enable the window watchdog clock. Reset by hardware system reset.\r This bit can also be set by hardware if the WWDG_SW option bit is reset.",
3370 ),
3371 bit_offset: BitOffset::Regular(
3372 RegularBitOffset {
3373 offset: 11,
3374 },
3375 ),
3376 bit_size: 1,
3377 array: None,
3378 enumm: None,
3379 },
3380 Field {
3381 name: "spi2en",
3382 description: Some(
3383 "SPI2 clock enable\r Set and cleared by software.",
3384 ),
3385 bit_offset: BitOffset::Regular(
3386 RegularBitOffset {
3387 offset: 14,
3388 },
3389 ),
3390 bit_size: 1,
3391 array: None,
3392 enumm: None,
3393 },
3394 Field {
3395 name: "usart2en",
3396 description: Some(
3397 "USART2 clock enable\r Set and cleared by software.",
3398 ),
3399 bit_offset: BitOffset::Regular(
3400 RegularBitOffset {
3401 offset: 17,
3402 },
3403 ),
3404 bit_size: 1,
3405 array: None,
3406 enumm: None,
3407 },
3408 Field {
3409 name: "usart3en",
3410 description: Some(
3411 "USART3 clock enable\r Set and cleared by software.",
3412 ),
3413 bit_offset: BitOffset::Regular(
3414 RegularBitOffset {
3415 offset: 18,
3416 },
3417 ),
3418 bit_size: 1,
3419 array: None,
3420 enumm: None,
3421 },
3422 Field {
3423 name: "uart4en",
3424 description: Some(
3425 "UART4 clock enable\r Set and cleared by software.",
3426 ),
3427 bit_offset: BitOffset::Regular(
3428 RegularBitOffset {
3429 offset: 19,
3430 },
3431 ),
3432 bit_size: 1,
3433 array: None,
3434 enumm: None,
3435 },
3436 Field {
3437 name: "uart5en",
3438 description: Some(
3439 "UART5 clock enable\r Set and cleared by software.",
3440 ),
3441 bit_offset: BitOffset::Regular(
3442 RegularBitOffset {
3443 offset: 20,
3444 },
3445 ),
3446 bit_size: 1,
3447 array: None,
3448 enumm: None,
3449 },
3450 Field {
3451 name: "i2c1en",
3452 description: Some(
3453 "I2C1 clock enable\r Set and cleared by software.",
3454 ),
3455 bit_offset: BitOffset::Regular(
3456 RegularBitOffset {
3457 offset: 21,
3458 },
3459 ),
3460 bit_size: 1,
3461 array: None,
3462 enumm: None,
3463 },
3464 Field {
3465 name: "i2c2en",
3466 description: Some(
3467 "I2C2 clock enable\r Set and cleared by software.",
3468 ),
3469 bit_offset: BitOffset::Regular(
3470 RegularBitOffset {
3471 offset: 22,
3472 },
3473 ),
3474 bit_size: 1,
3475 array: None,
3476 enumm: None,
3477 },
3478 Field {
3479 name: "crsen",
3480 description: Some(
3481 "CRS clock enable\r Set and cleared by software.",
3482 ),
3483 bit_offset: BitOffset::Regular(
3484 RegularBitOffset {
3485 offset: 24,
3486 },
3487 ),
3488 bit_size: 1,
3489 array: None,
3490 enumm: None,
3491 },
3492 Field {
3493 name: "usart6en",
3494 description: Some(
3495 "USART6 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
3496 ),
3497 bit_offset: BitOffset::Regular(
3498 RegularBitOffset {
3499 offset: 25,
3500 },
3501 ),
3502 bit_size: 1,
3503 array: None,
3504 enumm: None,
3505 },
3506 ],
3507 },
3508 FieldSet {
3509 name: "Apb1enr2",
3510 extends: None,
3511 description: Some(
3512 "RCC APB1 peripheral clock enable register 2",
3513 ),
3514 bit_size: 32,
3515 fields: &[
3516 Field {
3517 name: "i2c4en",
3518 description: Some(
3519 "I2C4 clock enable\r Set and cleared by software",
3520 ),
3521 bit_offset: BitOffset::Regular(
3522 RegularBitOffset {
3523 offset: 1,
3524 },
3525 ),
3526 bit_size: 1,
3527 array: None,
3528 enumm: None,
3529 },
3530 Field {
3531 name: "lptim2en",
3532 description: Some(
3533 "LPTIM2 clock enable\r Set and cleared by software.",
3534 ),
3535 bit_offset: BitOffset::Regular(
3536 RegularBitOffset {
3537 offset: 5,
3538 },
3539 ),
3540 bit_size: 1,
3541 array: None,
3542 enumm: None,
3543 },
3544 Field {
3545 name: "i2c5en",
3546 description: Some(
3547 "I2C5 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
3548 ),
3549 bit_offset: BitOffset::Regular(
3550 RegularBitOffset {
3551 offset: 6,
3552 },
3553 ),
3554 bit_size: 1,
3555 array: None,
3556 enumm: None,
3557 },
3558 Field {
3559 name: "i2c6en",
3560 description: Some(
3561 "I2C6 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
3562 ),
3563 bit_offset: BitOffset::Regular(
3564 RegularBitOffset {
3565 offset: 7,
3566 },
3567 ),
3568 bit_size: 1,
3569 array: None,
3570 enumm: None,
3571 },
3572 Field {
3573 name: "fdcan1en",
3574 description: Some(
3575 "FDCAN1 clock enable\r Set and cleared by software.",
3576 ),
3577 bit_offset: BitOffset::Regular(
3578 RegularBitOffset {
3579 offset: 9,
3580 },
3581 ),
3582 bit_size: 1,
3583 array: None,
3584 enumm: None,
3585 },
3586 Field {
3587 name: "ucpd1en",
3588 description: Some(
3589 "UCPD1 clock enable\r Set and cleared by software.",
3590 ),
3591 bit_offset: BitOffset::Regular(
3592 RegularBitOffset {
3593 offset: 23,
3594 },
3595 ),
3596 bit_size: 1,
3597 array: None,
3598 enumm: None,
3599 },
3600 ],
3601 },
3602 FieldSet {
3603 name: "Apb1rstr1",
3604 extends: None,
3605 description: Some(
3606 "RCC APB1 peripheral reset register 1",
3607 ),
3608 bit_size: 32,
3609 fields: &[
3610 Field {
3611 name: "tim2rst",
3612 description: Some(
3613 "TIM2 reset\r Set and cleared by software.",
3614 ),
3615 bit_offset: BitOffset::Regular(
3616 RegularBitOffset {
3617 offset: 0,
3618 },
3619 ),
3620 bit_size: 1,
3621 array: None,
3622 enumm: None,
3623 },
3624 Field {
3625 name: "tim3rst",
3626 description: Some(
3627 "TIM3 reset\r Set and cleared by software.",
3628 ),
3629 bit_offset: BitOffset::Regular(
3630 RegularBitOffset {
3631 offset: 1,
3632 },
3633 ),
3634 bit_size: 1,
3635 array: None,
3636 enumm: None,
3637 },
3638 Field {
3639 name: "tim4rst",
3640 description: Some(
3641 "TIM4 reset\r Set and cleared by software.",
3642 ),
3643 bit_offset: BitOffset::Regular(
3644 RegularBitOffset {
3645 offset: 2,
3646 },
3647 ),
3648 bit_size: 1,
3649 array: None,
3650 enumm: None,
3651 },
3652 Field {
3653 name: "tim5rst",
3654 description: Some(
3655 "TIM5 reset\r Set and cleared by software.",
3656 ),
3657 bit_offset: BitOffset::Regular(
3658 RegularBitOffset {
3659 offset: 3,
3660 },
3661 ),
3662 bit_size: 1,
3663 array: None,
3664 enumm: None,
3665 },
3666 Field {
3667 name: "tim6rst",
3668 description: Some(
3669 "TIM6 reset\r Set and cleared by software.",
3670 ),
3671 bit_offset: BitOffset::Regular(
3672 RegularBitOffset {
3673 offset: 4,
3674 },
3675 ),
3676 bit_size: 1,
3677 array: None,
3678 enumm: None,
3679 },
3680 Field {
3681 name: "tim7rst",
3682 description: Some(
3683 "TIM7 reset\r Set and cleared by software.",
3684 ),
3685 bit_offset: BitOffset::Regular(
3686 RegularBitOffset {
3687 offset: 5,
3688 },
3689 ),
3690 bit_size: 1,
3691 array: None,
3692 enumm: None,
3693 },
3694 Field {
3695 name: "spi2rst",
3696 description: Some(
3697 "SPI2 reset\r Set and cleared by software.",
3698 ),
3699 bit_offset: BitOffset::Regular(
3700 RegularBitOffset {
3701 offset: 14,
3702 },
3703 ),
3704 bit_size: 1,
3705 array: None,
3706 enumm: None,
3707 },
3708 Field {
3709 name: "usart2rst",
3710 description: Some(
3711 "USART2 reset\r Set and cleared by software.",
3712 ),
3713 bit_offset: BitOffset::Regular(
3714 RegularBitOffset {
3715 offset: 17,
3716 },
3717 ),
3718 bit_size: 1,
3719 array: None,
3720 enumm: None,
3721 },
3722 Field {
3723 name: "usart3rst",
3724 description: Some(
3725 "USART3 reset\r Set and cleared by software.",
3726 ),
3727 bit_offset: BitOffset::Regular(
3728 RegularBitOffset {
3729 offset: 18,
3730 },
3731 ),
3732 bit_size: 1,
3733 array: None,
3734 enumm: None,
3735 },
3736 Field {
3737 name: "uart4rst",
3738 description: Some(
3739 "UART4 reset\r Set and cleared by software.",
3740 ),
3741 bit_offset: BitOffset::Regular(
3742 RegularBitOffset {
3743 offset: 19,
3744 },
3745 ),
3746 bit_size: 1,
3747 array: None,
3748 enumm: None,
3749 },
3750 Field {
3751 name: "uart5rst",
3752 description: Some(
3753 "UART5 reset\r Set and cleared by software.",
3754 ),
3755 bit_offset: BitOffset::Regular(
3756 RegularBitOffset {
3757 offset: 20,
3758 },
3759 ),
3760 bit_size: 1,
3761 array: None,
3762 enumm: None,
3763 },
3764 Field {
3765 name: "i2c1rst",
3766 description: Some(
3767 "I2C1 reset\r Set and cleared by software.",
3768 ),
3769 bit_offset: BitOffset::Regular(
3770 RegularBitOffset {
3771 offset: 21,
3772 },
3773 ),
3774 bit_size: 1,
3775 array: None,
3776 enumm: None,
3777 },
3778 Field {
3779 name: "i2c2rst",
3780 description: Some(
3781 "I2C2 reset\r Set and cleared by software.",
3782 ),
3783 bit_offset: BitOffset::Regular(
3784 RegularBitOffset {
3785 offset: 22,
3786 },
3787 ),
3788 bit_size: 1,
3789 array: None,
3790 enumm: None,
3791 },
3792 Field {
3793 name: "crsrst",
3794 description: Some(
3795 "CRS reset\r Set and cleared by software.",
3796 ),
3797 bit_offset: BitOffset::Regular(
3798 RegularBitOffset {
3799 offset: 24,
3800 },
3801 ),
3802 bit_size: 1,
3803 array: None,
3804 enumm: None,
3805 },
3806 Field {
3807 name: "usart6rst",
3808 description: Some(
3809 "USART6 reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
3810 ),
3811 bit_offset: BitOffset::Regular(
3812 RegularBitOffset {
3813 offset: 25,
3814 },
3815 ),
3816 bit_size: 1,
3817 array: None,
3818 enumm: None,
3819 },
3820 ],
3821 },
3822 FieldSet {
3823 name: "Apb1rstr2",
3824 extends: None,
3825 description: Some(
3826 "RCC APB1 peripheral reset register 2",
3827 ),
3828 bit_size: 32,
3829 fields: &[
3830 Field {
3831 name: "i2c4rst",
3832 description: Some(
3833 "I2C4 reset\r Set and cleared by software",
3834 ),
3835 bit_offset: BitOffset::Regular(
3836 RegularBitOffset {
3837 offset: 1,
3838 },
3839 ),
3840 bit_size: 1,
3841 array: None,
3842 enumm: None,
3843 },
3844 Field {
3845 name: "lptim2rst",
3846 description: Some(
3847 "LPTIM2 reset\r Set and cleared by software.",
3848 ),
3849 bit_offset: BitOffset::Regular(
3850 RegularBitOffset {
3851 offset: 5,
3852 },
3853 ),
3854 bit_size: 1,
3855 array: None,
3856 enumm: None,
3857 },
3858 Field {
3859 name: "i2c5rst",
3860 description: Some(
3861 "I2C5 reset\r This bit is set and cleared by software\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
3862 ),
3863 bit_offset: BitOffset::Regular(
3864 RegularBitOffset {
3865 offset: 6,
3866 },
3867 ),
3868 bit_size: 1,
3869 array: None,
3870 enumm: None,
3871 },
3872 Field {
3873 name: "i2c6rst",
3874 description: Some(
3875 "I2C6 reset\r This bit is set and cleared by software\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
3876 ),
3877 bit_offset: BitOffset::Regular(
3878 RegularBitOffset {
3879 offset: 7,
3880 },
3881 ),
3882 bit_size: 1,
3883 array: None,
3884 enumm: None,
3885 },
3886 Field {
3887 name: "fdcan1rst",
3888 description: Some(
3889 "FDCAN1 reset\r Set and cleared by software.",
3890 ),
3891 bit_offset: BitOffset::Regular(
3892 RegularBitOffset {
3893 offset: 9,
3894 },
3895 ),
3896 bit_size: 1,
3897 array: None,
3898 enumm: None,
3899 },
3900 Field {
3901 name: "ucpd1rst",
3902 description: Some(
3903 "UCPD1 reset\r Set and cleared by software.",
3904 ),
3905 bit_offset: BitOffset::Regular(
3906 RegularBitOffset {
3907 offset: 23,
3908 },
3909 ),
3910 bit_size: 1,
3911 array: None,
3912 enumm: None,
3913 },
3914 ],
3915 },
3916 FieldSet {
3917 name: "Apb1smenr1",
3918 extends: None,
3919 description: Some(
3920 "RCC APB1 peripheral clocks enable in Sleep and Stop modes\tregister 1",
3921 ),
3922 bit_size: 32,
3923 fields: &[
3924 Field {
3925 name: "tim2smen",
3926 description: Some(
3927 "TIM2 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
3928 ),
3929 bit_offset: BitOffset::Regular(
3930 RegularBitOffset {
3931 offset: 0,
3932 },
3933 ),
3934 bit_size: 1,
3935 array: None,
3936 enumm: None,
3937 },
3938 Field {
3939 name: "tim3smen",
3940 description: Some(
3941 "TIM3 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
3942 ),
3943 bit_offset: BitOffset::Regular(
3944 RegularBitOffset {
3945 offset: 1,
3946 },
3947 ),
3948 bit_size: 1,
3949 array: None,
3950 enumm: None,
3951 },
3952 Field {
3953 name: "tim4smen",
3954 description: Some(
3955 "TIM4 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
3956 ),
3957 bit_offset: BitOffset::Regular(
3958 RegularBitOffset {
3959 offset: 2,
3960 },
3961 ),
3962 bit_size: 1,
3963 array: None,
3964 enumm: None,
3965 },
3966 Field {
3967 name: "tim5smen",
3968 description: Some(
3969 "TIM5 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
3970 ),
3971 bit_offset: BitOffset::Regular(
3972 RegularBitOffset {
3973 offset: 3,
3974 },
3975 ),
3976 bit_size: 1,
3977 array: None,
3978 enumm: None,
3979 },
3980 Field {
3981 name: "tim6smen",
3982 description: Some(
3983 "TIM6 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
3984 ),
3985 bit_offset: BitOffset::Regular(
3986 RegularBitOffset {
3987 offset: 4,
3988 },
3989 ),
3990 bit_size: 1,
3991 array: None,
3992 enumm: None,
3993 },
3994 Field {
3995 name: "tim7smen",
3996 description: Some(
3997 "TIM7 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
3998 ),
3999 bit_offset: BitOffset::Regular(
4000 RegularBitOffset {
4001 offset: 5,
4002 },
4003 ),
4004 bit_size: 1,
4005 array: None,
4006 enumm: None,
4007 },
4008 Field {
4009 name: "wwdgsmen",
4010 description: Some(
4011 "Window watchdog clocks enable during Sleep and Stop modes\r Set and cleared by software. This bit is forced to 1 by hardware when the hardware WWDG option is activated.",
4012 ),
4013 bit_offset: BitOffset::Regular(
4014 RegularBitOffset {
4015 offset: 11,
4016 },
4017 ),
4018 bit_size: 1,
4019 array: None,
4020 enumm: None,
4021 },
4022 Field {
4023 name: "spi2smen",
4024 description: Some(
4025 "SPI2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
4026 ),
4027 bit_offset: BitOffset::Regular(
4028 RegularBitOffset {
4029 offset: 14,
4030 },
4031 ),
4032 bit_size: 1,
4033 array: None,
4034 enumm: None,
4035 },
4036 Field {
4037 name: "usart2smen",
4038 description: Some(
4039 "USART2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
4040 ),
4041 bit_offset: BitOffset::Regular(
4042 RegularBitOffset {
4043 offset: 17,
4044 },
4045 ),
4046 bit_size: 1,
4047 array: None,
4048 enumm: None,
4049 },
4050 Field {
4051 name: "usart3smen",
4052 description: Some(
4053 "USART3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
4054 ),
4055 bit_offset: BitOffset::Regular(
4056 RegularBitOffset {
4057 offset: 18,
4058 },
4059 ),
4060 bit_size: 1,
4061 array: None,
4062 enumm: None,
4063 },
4064 Field {
4065 name: "uart4smen",
4066 description: Some(
4067 "UART4 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
4068 ),
4069 bit_offset: BitOffset::Regular(
4070 RegularBitOffset {
4071 offset: 19,
4072 },
4073 ),
4074 bit_size: 1,
4075 array: None,
4076 enumm: None,
4077 },
4078 Field {
4079 name: "uart5smen",
4080 description: Some(
4081 "UART5 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
4082 ),
4083 bit_offset: BitOffset::Regular(
4084 RegularBitOffset {
4085 offset: 20,
4086 },
4087 ),
4088 bit_size: 1,
4089 array: None,
4090 enumm: None,
4091 },
4092 Field {
4093 name: "i2c1smen",
4094 description: Some(
4095 "I2C1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
4096 ),
4097 bit_offset: BitOffset::Regular(
4098 RegularBitOffset {
4099 offset: 21,
4100 },
4101 ),
4102 bit_size: 1,
4103 array: None,
4104 enumm: None,
4105 },
4106 Field {
4107 name: "i2c2smen",
4108 description: Some(
4109 "I2C2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
4110 ),
4111 bit_offset: BitOffset::Regular(
4112 RegularBitOffset {
4113 offset: 22,
4114 },
4115 ),
4116 bit_size: 1,
4117 array: None,
4118 enumm: None,
4119 },
4120 Field {
4121 name: "crssmen",
4122 description: Some(
4123 "CRS clock enable during Sleep and Stop modes\r Set and cleared by software.",
4124 ),
4125 bit_offset: BitOffset::Regular(
4126 RegularBitOffset {
4127 offset: 24,
4128 },
4129 ),
4130 bit_size: 1,
4131 array: None,
4132 enumm: None,
4133 },
4134 Field {
4135 name: "usart6smen",
4136 description: Some(
4137 "USART6 clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
4138 ),
4139 bit_offset: BitOffset::Regular(
4140 RegularBitOffset {
4141 offset: 25,
4142 },
4143 ),
4144 bit_size: 1,
4145 array: None,
4146 enumm: None,
4147 },
4148 ],
4149 },
4150 FieldSet {
4151 name: "Apb1smenr2",
4152 extends: None,
4153 description: Some(
4154 "RCC APB1 peripheral clocks enable in Sleep and\tStop modes register 2",
4155 ),
4156 bit_size: 32,
4157 fields: &[
4158 Field {
4159 name: "i2c4smen",
4160 description: Some(
4161 "I2C4 clocks enable during Sleep and Stop modes\r Set and cleared by software\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
4162 ),
4163 bit_offset: BitOffset::Regular(
4164 RegularBitOffset {
4165 offset: 1,
4166 },
4167 ),
4168 bit_size: 1,
4169 array: None,
4170 enumm: None,
4171 },
4172 Field {
4173 name: "lptim2smen",
4174 description: Some(
4175 "LPTIM2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
4176 ),
4177 bit_offset: BitOffset::Regular(
4178 RegularBitOffset {
4179 offset: 5,
4180 },
4181 ),
4182 bit_size: 1,
4183 array: None,
4184 enumm: None,
4185 },
4186 Field {
4187 name: "i2c5smen",
4188 description: Some(
4189 "I2C5 clock enable during Sleep and Stop modes\r This bit is set and cleared by software\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
4190 ),
4191 bit_offset: BitOffset::Regular(
4192 RegularBitOffset {
4193 offset: 6,
4194 },
4195 ),
4196 bit_size: 1,
4197 array: None,
4198 enumm: None,
4199 },
4200 Field {
4201 name: "i2c6smen",
4202 description: Some(
4203 "I2C6 clock enable during Sleep and Stop modes\r This bit is set and cleared by software\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
4204 ),
4205 bit_offset: BitOffset::Regular(
4206 RegularBitOffset {
4207 offset: 7,
4208 },
4209 ),
4210 bit_size: 1,
4211 array: None,
4212 enumm: None,
4213 },
4214 Field {
4215 name: "fdcan1smen",
4216 description: Some(
4217 "FDCAN1 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
4218 ),
4219 bit_offset: BitOffset::Regular(
4220 RegularBitOffset {
4221 offset: 9,
4222 },
4223 ),
4224 bit_size: 1,
4225 array: None,
4226 enumm: None,
4227 },
4228 Field {
4229 name: "ucpd1smen",
4230 description: Some(
4231 "UCPD1 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
4232 ),
4233 bit_offset: BitOffset::Regular(
4234 RegularBitOffset {
4235 offset: 23,
4236 },
4237 ),
4238 bit_size: 1,
4239 array: None,
4240 enumm: None,
4241 },
4242 ],
4243 },
4244 FieldSet {
4245 name: "Apb2enr",
4246 extends: None,
4247 description: Some(
4248 "RCC APB2 peripheral clock enable register",
4249 ),
4250 bit_size: 32,
4251 fields: &[
4252 Field {
4253 name: "tim1en",
4254 description: Some(
4255 "TIM1 clock enable\r Set and cleared by software.",
4256 ),
4257 bit_offset: BitOffset::Regular(
4258 RegularBitOffset {
4259 offset: 11,
4260 },
4261 ),
4262 bit_size: 1,
4263 array: None,
4264 enumm: None,
4265 },
4266 Field {
4267 name: "spi1en",
4268 description: Some(
4269 "SPI1 clock enable\r Set and cleared by software.",
4270 ),
4271 bit_offset: BitOffset::Regular(
4272 RegularBitOffset {
4273 offset: 12,
4274 },
4275 ),
4276 bit_size: 1,
4277 array: None,
4278 enumm: None,
4279 },
4280 Field {
4281 name: "tim8en",
4282 description: Some(
4283 "TIM8 clock enable\r Set and cleared by software.",
4284 ),
4285 bit_offset: BitOffset::Regular(
4286 RegularBitOffset {
4287 offset: 13,
4288 },
4289 ),
4290 bit_size: 1,
4291 array: None,
4292 enumm: None,
4293 },
4294 Field {
4295 name: "usart1en",
4296 description: Some(
4297 "USART1clock enable\r Set and cleared by software.",
4298 ),
4299 bit_offset: BitOffset::Regular(
4300 RegularBitOffset {
4301 offset: 14,
4302 },
4303 ),
4304 bit_size: 1,
4305 array: None,
4306 enumm: None,
4307 },
4308 Field {
4309 name: "tim15en",
4310 description: Some(
4311 "TIM15 clock enable\r Set and cleared by software.",
4312 ),
4313 bit_offset: BitOffset::Regular(
4314 RegularBitOffset {
4315 offset: 16,
4316 },
4317 ),
4318 bit_size: 1,
4319 array: None,
4320 enumm: None,
4321 },
4322 Field {
4323 name: "tim16en",
4324 description: Some(
4325 "TIM16 clock enable\r Set and cleared by software.",
4326 ),
4327 bit_offset: BitOffset::Regular(
4328 RegularBitOffset {
4329 offset: 17,
4330 },
4331 ),
4332 bit_size: 1,
4333 array: None,
4334 enumm: None,
4335 },
4336 Field {
4337 name: "tim17en",
4338 description: Some(
4339 "TIM17 clock enable\r Set and cleared by software.",
4340 ),
4341 bit_offset: BitOffset::Regular(
4342 RegularBitOffset {
4343 offset: 18,
4344 },
4345 ),
4346 bit_size: 1,
4347 array: None,
4348 enumm: None,
4349 },
4350 Field {
4351 name: "sai1en",
4352 description: Some(
4353 "SAI1 clock enable\r Set and cleared by software.",
4354 ),
4355 bit_offset: BitOffset::Regular(
4356 RegularBitOffset {
4357 offset: 21,
4358 },
4359 ),
4360 bit_size: 1,
4361 array: None,
4362 enumm: None,
4363 },
4364 Field {
4365 name: "sai2en",
4366 description: Some(
4367 "SAI2 clock enable\r Set and cleared by software.",
4368 ),
4369 bit_offset: BitOffset::Regular(
4370 RegularBitOffset {
4371 offset: 22,
4372 },
4373 ),
4374 bit_size: 1,
4375 array: None,
4376 enumm: None,
4377 },
4378 Field {
4379 name: "usben",
4380 description: Some(
4381 "USB clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
4382 ),
4383 bit_offset: BitOffset::Regular(
4384 RegularBitOffset {
4385 offset: 24,
4386 },
4387 ),
4388 bit_size: 1,
4389 array: None,
4390 enumm: None,
4391 },
4392 Field {
4393 name: "gfxtimen",
4394 description: Some(
4395 "GFXTIM clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
4396 ),
4397 bit_offset: BitOffset::Regular(
4398 RegularBitOffset {
4399 offset: 25,
4400 },
4401 ),
4402 bit_size: 1,
4403 array: None,
4404 enumm: None,
4405 },
4406 Field {
4407 name: "ltdcen",
4408 description: Some(
4409 "LTDC clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
4410 ),
4411 bit_offset: BitOffset::Regular(
4412 RegularBitOffset {
4413 offset: 26,
4414 },
4415 ),
4416 bit_size: 1,
4417 array: None,
4418 enumm: None,
4419 },
4420 Field {
4421 name: "dsien",
4422 description: Some(
4423 "DSI clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
4424 ),
4425 bit_offset: BitOffset::Regular(
4426 RegularBitOffset {
4427 offset: 27,
4428 },
4429 ),
4430 bit_size: 1,
4431 array: None,
4432 enumm: None,
4433 },
4434 ],
4435 },
4436 FieldSet {
4437 name: "Apb2rstr",
4438 extends: None,
4439 description: Some(
4440 "RCC APB2 peripheral reset register",
4441 ),
4442 bit_size: 32,
4443 fields: &[
4444 Field {
4445 name: "tim1rst",
4446 description: Some(
4447 "TIM1 reset\r Set and cleared by software.",
4448 ),
4449 bit_offset: BitOffset::Regular(
4450 RegularBitOffset {
4451 offset: 11,
4452 },
4453 ),
4454 bit_size: 1,
4455 array: None,
4456 enumm: None,
4457 },
4458 Field {
4459 name: "spi1rst",
4460 description: Some(
4461 "SPI1 reset\r Set and cleared by software.",
4462 ),
4463 bit_offset: BitOffset::Regular(
4464 RegularBitOffset {
4465 offset: 12,
4466 },
4467 ),
4468 bit_size: 1,
4469 array: None,
4470 enumm: None,
4471 },
4472 Field {
4473 name: "tim8rst",
4474 description: Some(
4475 "TIM8 reset\r Set and cleared by software.",
4476 ),
4477 bit_offset: BitOffset::Regular(
4478 RegularBitOffset {
4479 offset: 13,
4480 },
4481 ),
4482 bit_size: 1,
4483 array: None,
4484 enumm: None,
4485 },
4486 Field {
4487 name: "usart1rst",
4488 description: Some(
4489 "USART1 reset\r Set and cleared by software.",
4490 ),
4491 bit_offset: BitOffset::Regular(
4492 RegularBitOffset {
4493 offset: 14,
4494 },
4495 ),
4496 bit_size: 1,
4497 array: None,
4498 enumm: None,
4499 },
4500 Field {
4501 name: "tim15rst",
4502 description: Some(
4503 "TIM15 reset\r Set and cleared by software.",
4504 ),
4505 bit_offset: BitOffset::Regular(
4506 RegularBitOffset {
4507 offset: 16,
4508 },
4509 ),
4510 bit_size: 1,
4511 array: None,
4512 enumm: None,
4513 },
4514 Field {
4515 name: "tim16rst",
4516 description: Some(
4517 "TIM16 reset\r Set and cleared by software.",
4518 ),
4519 bit_offset: BitOffset::Regular(
4520 RegularBitOffset {
4521 offset: 17,
4522 },
4523 ),
4524 bit_size: 1,
4525 array: None,
4526 enumm: None,
4527 },
4528 Field {
4529 name: "tim17rst",
4530 description: Some(
4531 "TIM17 reset\r Set and cleared by software.",
4532 ),
4533 bit_offset: BitOffset::Regular(
4534 RegularBitOffset {
4535 offset: 18,
4536 },
4537 ),
4538 bit_size: 1,
4539 array: None,
4540 enumm: None,
4541 },
4542 Field {
4543 name: "sai1rst",
4544 description: Some(
4545 "SAI1 reset\r Set and cleared by software.",
4546 ),
4547 bit_offset: BitOffset::Regular(
4548 RegularBitOffset {
4549 offset: 21,
4550 },
4551 ),
4552 bit_size: 1,
4553 array: None,
4554 enumm: None,
4555 },
4556 Field {
4557 name: "sai2rst",
4558 description: Some(
4559 "SAI2 reset\r Set and cleared by software.",
4560 ),
4561 bit_offset: BitOffset::Regular(
4562 RegularBitOffset {
4563 offset: 22,
4564 },
4565 ),
4566 bit_size: 1,
4567 array: None,
4568 enumm: None,
4569 },
4570 Field {
4571 name: "usbrst",
4572 description: Some(
4573 "USB reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
4574 ),
4575 bit_offset: BitOffset::Regular(
4576 RegularBitOffset {
4577 offset: 24,
4578 },
4579 ),
4580 bit_size: 1,
4581 array: None,
4582 enumm: None,
4583 },
4584 Field {
4585 name: "gfxtimrst",
4586 description: Some(
4587 "GFXTIM reset\r This bit is set and cleared by software.\r Note: .This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
4588 ),
4589 bit_offset: BitOffset::Regular(
4590 RegularBitOffset {
4591 offset: 25,
4592 },
4593 ),
4594 bit_size: 1,
4595 array: None,
4596 enumm: None,
4597 },
4598 Field {
4599 name: "ltdcrst",
4600 description: Some(
4601 "LTDC reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
4602 ),
4603 bit_offset: BitOffset::Regular(
4604 RegularBitOffset {
4605 offset: 26,
4606 },
4607 ),
4608 bit_size: 1,
4609 array: None,
4610 enumm: None,
4611 },
4612 Field {
4613 name: "dsirst",
4614 description: Some(
4615 "DSI reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
4616 ),
4617 bit_offset: BitOffset::Regular(
4618 RegularBitOffset {
4619 offset: 27,
4620 },
4621 ),
4622 bit_size: 1,
4623 array: None,
4624 enumm: None,
4625 },
4626 ],
4627 },
4628 FieldSet {
4629 name: "Apb2smenr",
4630 extends: None,
4631 description: Some(
4632 "RCC APB2 peripheral clocks enable in Sleep and Stop modes register",
4633 ),
4634 bit_size: 32,
4635 fields: &[
4636 Field {
4637 name: "tim1smen",
4638 description: Some(
4639 "TIM1 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
4640 ),
4641 bit_offset: BitOffset::Regular(
4642 RegularBitOffset {
4643 offset: 11,
4644 },
4645 ),
4646 bit_size: 1,
4647 array: None,
4648 enumm: None,
4649 },
4650 Field {
4651 name: "spi1smen",
4652 description: Some(
4653 "SPI1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
4654 ),
4655 bit_offset: BitOffset::Regular(
4656 RegularBitOffset {
4657 offset: 12,
4658 },
4659 ),
4660 bit_size: 1,
4661 array: None,
4662 enumm: None,
4663 },
4664 Field {
4665 name: "tim8smen",
4666 description: Some(
4667 "TIM8 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
4668 ),
4669 bit_offset: BitOffset::Regular(
4670 RegularBitOffset {
4671 offset: 13,
4672 },
4673 ),
4674 bit_size: 1,
4675 array: None,
4676 enumm: None,
4677 },
4678 Field {
4679 name: "usart1smen",
4680 description: Some(
4681 "USART1clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
4682 ),
4683 bit_offset: BitOffset::Regular(
4684 RegularBitOffset {
4685 offset: 14,
4686 },
4687 ),
4688 bit_size: 1,
4689 array: None,
4690 enumm: None,
4691 },
4692 Field {
4693 name: "tim15smen",
4694 description: Some(
4695 "TIM15 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
4696 ),
4697 bit_offset: BitOffset::Regular(
4698 RegularBitOffset {
4699 offset: 16,
4700 },
4701 ),
4702 bit_size: 1,
4703 array: None,
4704 enumm: None,
4705 },
4706 Field {
4707 name: "tim16smen",
4708 description: Some(
4709 "TIM16 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
4710 ),
4711 bit_offset: BitOffset::Regular(
4712 RegularBitOffset {
4713 offset: 17,
4714 },
4715 ),
4716 bit_size: 1,
4717 array: None,
4718 enumm: None,
4719 },
4720 Field {
4721 name: "tim17smen",
4722 description: Some(
4723 "TIM17 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
4724 ),
4725 bit_offset: BitOffset::Regular(
4726 RegularBitOffset {
4727 offset: 18,
4728 },
4729 ),
4730 bit_size: 1,
4731 array: None,
4732 enumm: None,
4733 },
4734 Field {
4735 name: "sai1smen",
4736 description: Some(
4737 "SAI1 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
4738 ),
4739 bit_offset: BitOffset::Regular(
4740 RegularBitOffset {
4741 offset: 21,
4742 },
4743 ),
4744 bit_size: 1,
4745 array: None,
4746 enumm: None,
4747 },
4748 Field {
4749 name: "sai2smen",
4750 description: Some(
4751 "SAI2 clocks enable during Sleep and Stop modes\r Set and cleared by software.",
4752 ),
4753 bit_offset: BitOffset::Regular(
4754 RegularBitOffset {
4755 offset: 22,
4756 },
4757 ),
4758 bit_size: 1,
4759 array: None,
4760 enumm: None,
4761 },
4762 Field {
4763 name: "usbsmen",
4764 description: Some(
4765 "USB clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
4766 ),
4767 bit_offset: BitOffset::Regular(
4768 RegularBitOffset {
4769 offset: 24,
4770 },
4771 ),
4772 bit_size: 1,
4773 array: None,
4774 enumm: None,
4775 },
4776 Field {
4777 name: "gfxtimsmen",
4778 description: Some(
4779 "GFXTIM clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
4780 ),
4781 bit_offset: BitOffset::Regular(
4782 RegularBitOffset {
4783 offset: 25,
4784 },
4785 ),
4786 bit_size: 1,
4787 array: None,
4788 enumm: None,
4789 },
4790 Field {
4791 name: "ltdcsmen",
4792 description: Some(
4793 "LTDC clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
4794 ),
4795 bit_offset: BitOffset::Regular(
4796 RegularBitOffset {
4797 offset: 26,
4798 },
4799 ),
4800 bit_size: 1,
4801 array: None,
4802 enumm: None,
4803 },
4804 Field {
4805 name: "dsismen",
4806 description: Some(
4807 "DSI clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
4808 ),
4809 bit_offset: BitOffset::Regular(
4810 RegularBitOffset {
4811 offset: 27,
4812 },
4813 ),
4814 bit_size: 1,
4815 array: None,
4816 enumm: None,
4817 },
4818 ],
4819 },
4820 FieldSet {
4821 name: "Apb3enr",
4822 extends: None,
4823 description: Some(
4824 "RCC APB3 peripheral clock enable register",
4825 ),
4826 bit_size: 32,
4827 fields: &[
4828 Field {
4829 name: "syscfgen",
4830 description: Some(
4831 "SYSCFG clock enable\r Set and cleared by software.",
4832 ),
4833 bit_offset: BitOffset::Regular(
4834 RegularBitOffset {
4835 offset: 1,
4836 },
4837 ),
4838 bit_size: 1,
4839 array: None,
4840 enumm: None,
4841 },
4842 Field {
4843 name: "spi3en",
4844 description: Some(
4845 "SPI3 clock enable\r Set and cleared by software.",
4846 ),
4847 bit_offset: BitOffset::Regular(
4848 RegularBitOffset {
4849 offset: 5,
4850 },
4851 ),
4852 bit_size: 1,
4853 array: None,
4854 enumm: None,
4855 },
4856 Field {
4857 name: "lpuart1en",
4858 description: Some(
4859 "LPUART1 clock enable\r Set and cleared by software.",
4860 ),
4861 bit_offset: BitOffset::Regular(
4862 RegularBitOffset {
4863 offset: 6,
4864 },
4865 ),
4866 bit_size: 1,
4867 array: None,
4868 enumm: None,
4869 },
4870 Field {
4871 name: "i2c3en",
4872 description: Some(
4873 "I2C3 clock enable\r Set and cleared by software.",
4874 ),
4875 bit_offset: BitOffset::Regular(
4876 RegularBitOffset {
4877 offset: 7,
4878 },
4879 ),
4880 bit_size: 1,
4881 array: None,
4882 enumm: None,
4883 },
4884 Field {
4885 name: "lptim1en",
4886 description: Some(
4887 "LPTIM1 clock enable\r Set and cleared by software.",
4888 ),
4889 bit_offset: BitOffset::Regular(
4890 RegularBitOffset {
4891 offset: 11,
4892 },
4893 ),
4894 bit_size: 1,
4895 array: None,
4896 enumm: None,
4897 },
4898 Field {
4899 name: "lptim3en",
4900 description: Some(
4901 "LPTIM3 clock enable\r Set and cleared by software.",
4902 ),
4903 bit_offset: BitOffset::Regular(
4904 RegularBitOffset {
4905 offset: 12,
4906 },
4907 ),
4908 bit_size: 1,
4909 array: None,
4910 enumm: None,
4911 },
4912 Field {
4913 name: "lptim4en",
4914 description: Some(
4915 "LPTIM4 clock enable\r Set and cleared by software.",
4916 ),
4917 bit_offset: BitOffset::Regular(
4918 RegularBitOffset {
4919 offset: 13,
4920 },
4921 ),
4922 bit_size: 1,
4923 array: None,
4924 enumm: None,
4925 },
4926 Field {
4927 name: "opampen",
4928 description: Some(
4929 "OPAMP clock enable\r Set and cleared by software.",
4930 ),
4931 bit_offset: BitOffset::Regular(
4932 RegularBitOffset {
4933 offset: 14,
4934 },
4935 ),
4936 bit_size: 1,
4937 array: None,
4938 enumm: None,
4939 },
4940 Field {
4941 name: "compen",
4942 description: Some(
4943 "COMP clock enable\r Set and cleared by software.",
4944 ),
4945 bit_offset: BitOffset::Regular(
4946 RegularBitOffset {
4947 offset: 15,
4948 },
4949 ),
4950 bit_size: 1,
4951 array: None,
4952 enumm: None,
4953 },
4954 Field {
4955 name: "vrefen",
4956 description: Some(
4957 "VREFBUF clock enable\r Set and cleared by software.",
4958 ),
4959 bit_offset: BitOffset::Regular(
4960 RegularBitOffset {
4961 offset: 20,
4962 },
4963 ),
4964 bit_size: 1,
4965 array: None,
4966 enumm: None,
4967 },
4968 Field {
4969 name: "rtcapben",
4970 description: Some(
4971 "RTC and TAMP APB clock enable\r Set and cleared by software.",
4972 ),
4973 bit_offset: BitOffset::Regular(
4974 RegularBitOffset {
4975 offset: 21,
4976 },
4977 ),
4978 bit_size: 1,
4979 array: None,
4980 enumm: None,
4981 },
4982 ],
4983 },
4984 FieldSet {
4985 name: "Apb3rstr",
4986 extends: None,
4987 description: Some(
4988 "RCC APB3 peripheral reset register",
4989 ),
4990 bit_size: 32,
4991 fields: &[
4992 Field {
4993 name: "syscfgrst",
4994 description: Some(
4995 "SYSCFG reset\r Set and cleared by software.",
4996 ),
4997 bit_offset: BitOffset::Regular(
4998 RegularBitOffset {
4999 offset: 1,
5000 },
5001 ),
5002 bit_size: 1,
5003 array: None,
5004 enumm: None,
5005 },
5006 Field {
5007 name: "spi3rst",
5008 description: Some(
5009 "SPI3 reset\r Set and cleared by software.",
5010 ),
5011 bit_offset: BitOffset::Regular(
5012 RegularBitOffset {
5013 offset: 5,
5014 },
5015 ),
5016 bit_size: 1,
5017 array: None,
5018 enumm: None,
5019 },
5020 Field {
5021 name: "lpuart1rst",
5022 description: Some(
5023 "LPUART1 reset\r Set and cleared by software.",
5024 ),
5025 bit_offset: BitOffset::Regular(
5026 RegularBitOffset {
5027 offset: 6,
5028 },
5029 ),
5030 bit_size: 1,
5031 array: None,
5032 enumm: None,
5033 },
5034 Field {
5035 name: "i2c3rst",
5036 description: Some(
5037 "I2C3 reset\r Set and cleared by software.",
5038 ),
5039 bit_offset: BitOffset::Regular(
5040 RegularBitOffset {
5041 offset: 7,
5042 },
5043 ),
5044 bit_size: 1,
5045 array: None,
5046 enumm: None,
5047 },
5048 Field {
5049 name: "lptim1rst",
5050 description: Some(
5051 "LPTIM1 reset\r Set and cleared by software.",
5052 ),
5053 bit_offset: BitOffset::Regular(
5054 RegularBitOffset {
5055 offset: 11,
5056 },
5057 ),
5058 bit_size: 1,
5059 array: None,
5060 enumm: None,
5061 },
5062 Field {
5063 name: "lptim3rst",
5064 description: Some(
5065 "LPTIM3 reset\r Set and cleared by software.",
5066 ),
5067 bit_offset: BitOffset::Regular(
5068 RegularBitOffset {
5069 offset: 12,
5070 },
5071 ),
5072 bit_size: 1,
5073 array: None,
5074 enumm: None,
5075 },
5076 Field {
5077 name: "lptim4rst",
5078 description: Some(
5079 "LPTIM4 reset\r Set and cleared by software.",
5080 ),
5081 bit_offset: BitOffset::Regular(
5082 RegularBitOffset {
5083 offset: 13,
5084 },
5085 ),
5086 bit_size: 1,
5087 array: None,
5088 enumm: None,
5089 },
5090 Field {
5091 name: "opamprst",
5092 description: Some(
5093 "OPAMP reset\r Set and cleared by software.",
5094 ),
5095 bit_offset: BitOffset::Regular(
5096 RegularBitOffset {
5097 offset: 14,
5098 },
5099 ),
5100 bit_size: 1,
5101 array: None,
5102 enumm: None,
5103 },
5104 Field {
5105 name: "comprst",
5106 description: Some(
5107 "COMP reset\r Set and cleared by software.",
5108 ),
5109 bit_offset: BitOffset::Regular(
5110 RegularBitOffset {
5111 offset: 15,
5112 },
5113 ),
5114 bit_size: 1,
5115 array: None,
5116 enumm: None,
5117 },
5118 Field {
5119 name: "vrefrst",
5120 description: Some(
5121 "VREFBUF reset\r Set and cleared by software.",
5122 ),
5123 bit_offset: BitOffset::Regular(
5124 RegularBitOffset {
5125 offset: 20,
5126 },
5127 ),
5128 bit_size: 1,
5129 array: None,
5130 enumm: None,
5131 },
5132 ],
5133 },
5134 FieldSet {
5135 name: "Apb3smenr",
5136 extends: None,
5137 description: Some(
5138 "RCC APB3 peripheral clock enable in Sleep and Stop modes register",
5139 ),
5140 bit_size: 32,
5141 fields: &[
5142 Field {
5143 name: "syscfgsmen",
5144 description: Some(
5145 "SYSCFG clocks enable during Sleep and Stop modes\r Set and cleared by software.",
5146 ),
5147 bit_offset: BitOffset::Regular(
5148 RegularBitOffset {
5149 offset: 1,
5150 },
5151 ),
5152 bit_size: 1,
5153 array: None,
5154 enumm: None,
5155 },
5156 Field {
5157 name: "spi3smen",
5158 description: Some(
5159 "SPI3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
5160 ),
5161 bit_offset: BitOffset::Regular(
5162 RegularBitOffset {
5163 offset: 5,
5164 },
5165 ),
5166 bit_size: 1,
5167 array: None,
5168 enumm: None,
5169 },
5170 Field {
5171 name: "lpuart1smen",
5172 description: Some(
5173 "LPUART1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
5174 ),
5175 bit_offset: BitOffset::Regular(
5176 RegularBitOffset {
5177 offset: 6,
5178 },
5179 ),
5180 bit_size: 1,
5181 array: None,
5182 enumm: None,
5183 },
5184 Field {
5185 name: "i2c3smen",
5186 description: Some(
5187 "I2C3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
5188 ),
5189 bit_offset: BitOffset::Regular(
5190 RegularBitOffset {
5191 offset: 7,
5192 },
5193 ),
5194 bit_size: 1,
5195 array: None,
5196 enumm: None,
5197 },
5198 Field {
5199 name: "lptim1smen",
5200 description: Some(
5201 "LPTIM1 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
5202 ),
5203 bit_offset: BitOffset::Regular(
5204 RegularBitOffset {
5205 offset: 11,
5206 },
5207 ),
5208 bit_size: 1,
5209 array: None,
5210 enumm: None,
5211 },
5212 Field {
5213 name: "lptim3smen",
5214 description: Some(
5215 "LPTIM3 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
5216 ),
5217 bit_offset: BitOffset::Regular(
5218 RegularBitOffset {
5219 offset: 12,
5220 },
5221 ),
5222 bit_size: 1,
5223 array: None,
5224 enumm: None,
5225 },
5226 Field {
5227 name: "lptim4smen",
5228 description: Some(
5229 "LPTIM4 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
5230 ),
5231 bit_offset: BitOffset::Regular(
5232 RegularBitOffset {
5233 offset: 13,
5234 },
5235 ),
5236 bit_size: 1,
5237 array: None,
5238 enumm: None,
5239 },
5240 Field {
5241 name: "opampsmen",
5242 description: Some(
5243 "OPAMP clocks enable during Sleep and Stop modes\r Set and cleared by software.",
5244 ),
5245 bit_offset: BitOffset::Regular(
5246 RegularBitOffset {
5247 offset: 14,
5248 },
5249 ),
5250 bit_size: 1,
5251 array: None,
5252 enumm: None,
5253 },
5254 Field {
5255 name: "compsmen",
5256 description: Some(
5257 "COMP clocks enable during Sleep and Stop modes\r Set and cleared by software.",
5258 ),
5259 bit_offset: BitOffset::Regular(
5260 RegularBitOffset {
5261 offset: 15,
5262 },
5263 ),
5264 bit_size: 1,
5265 array: None,
5266 enumm: None,
5267 },
5268 Field {
5269 name: "vrefsmen",
5270 description: Some(
5271 "VREFBUF clocks enable during Sleep and Stop modes\r Set and cleared by software.",
5272 ),
5273 bit_offset: BitOffset::Regular(
5274 RegularBitOffset {
5275 offset: 20,
5276 },
5277 ),
5278 bit_size: 1,
5279 array: None,
5280 enumm: None,
5281 },
5282 Field {
5283 name: "rtcapbsmen",
5284 description: Some(
5285 "RTC and TAMP APB clock enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
5286 ),
5287 bit_offset: BitOffset::Regular(
5288 RegularBitOffset {
5289 offset: 21,
5290 },
5291 ),
5292 bit_size: 1,
5293 array: None,
5294 enumm: None,
5295 },
5296 ],
5297 },
5298 FieldSet {
5299 name: "Bdcr",
5300 extends: None,
5301 description: Some(
5302 "RCC Backup domain control register",
5303 ),
5304 bit_size: 32,
5305 fields: &[
5306 Field {
5307 name: "lseon",
5308 description: Some(
5309 "LSE oscillator enable\r Set and cleared by software.",
5310 ),
5311 bit_offset: BitOffset::Regular(
5312 RegularBitOffset {
5313 offset: 0,
5314 },
5315 ),
5316 bit_size: 1,
5317 array: None,
5318 enumm: None,
5319 },
5320 Field {
5321 name: "lserdy",
5322 description: Some(
5323 "LSE oscillator ready\r Set and cleared by hardware to indicate when the external 32\u{a0}kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles.",
5324 ),
5325 bit_offset: BitOffset::Regular(
5326 RegularBitOffset {
5327 offset: 1,
5328 },
5329 ),
5330 bit_size: 1,
5331 array: None,
5332 enumm: None,
5333 },
5334 Field {
5335 name: "lsebyp",
5336 description: Some(
5337 "LSE oscillator bypass\r Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32\u{a0}kHz oscillator is disabled (LSEON = 0 and LSERDY = 0).",
5338 ),
5339 bit_offset: BitOffset::Regular(
5340 RegularBitOffset {
5341 offset: 2,
5342 },
5343 ),
5344 bit_size: 1,
5345 array: None,
5346 enumm: None,
5347 },
5348 Field {
5349 name: "lsedrv",
5350 description: Some(
5351 "LSE oscillator drive capability\r Set by software to modulate the drive capability of the LSE oscillator. This field can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0).\r Note: The oscillator is in 'Xtal mode when it is not in bypass mode.",
5352 ),
5353 bit_offset: BitOffset::Regular(
5354 RegularBitOffset {
5355 offset: 3,
5356 },
5357 ),
5358 bit_size: 2,
5359 array: None,
5360 enumm: Some(
5361 "Lsedrv",
5362 ),
5363 },
5364 Field {
5365 name: "lsecsson",
5366 description: Some(
5367 "CSS on LSE enable\r Set by software to enable the CSS on LSE. LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected.\r Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD\u{a0}=\u{a0}1). In that case, the software must disable the LSECSSON bit.",
5368 ),
5369 bit_offset: BitOffset::Regular(
5370 RegularBitOffset {
5371 offset: 5,
5372 },
5373 ),
5374 bit_size: 1,
5375 array: None,
5376 enumm: None,
5377 },
5378 Field {
5379 name: "lsecssd",
5380 description: Some(
5381 "CSS on LSE failure Detection\r Set by hardware to indicate when a failure is detected by the CCS on the external 32\u{a0}kHz oscillator (LSE).",
5382 ),
5383 bit_offset: BitOffset::Regular(
5384 RegularBitOffset {
5385 offset: 6,
5386 },
5387 ),
5388 bit_size: 1,
5389 array: None,
5390 enumm: None,
5391 },
5392 Field {
5393 name: "lsesysen",
5394 description: Some(
5395 "LSE system clock (LSESYS) enable\r Set by software to enable always the LSE system clock generated by RCC. This clock can be used by any peripheral when its source clock is the LSE or at system level in case of one of the LSCOSEL, MCO, MSI PLL mode or CSS on LSE is needed.\r The LSESYS clock can be generated even if LSESYSEN= 0 if the LSE clock is requested by the CSS on LSE, by a peripheral or any other source clock using LSE.",
5396 ),
5397 bit_offset: BitOffset::Regular(
5398 RegularBitOffset {
5399 offset: 7,
5400 },
5401 ),
5402 bit_size: 1,
5403 array: None,
5404 enumm: None,
5405 },
5406 Field {
5407 name: "rtcsel",
5408 description: Some(
5409 "RTC and TAMP clock source selection\r Set by software to select the clock source for the RTC and TAMP . Once the RTC and TAMP clock source has been selected, it cannot be changed anymore unless the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them.",
5410 ),
5411 bit_offset: BitOffset::Regular(
5412 RegularBitOffset {
5413 offset: 8,
5414 },
5415 ),
5416 bit_size: 2,
5417 array: None,
5418 enumm: Some(
5419 "Rtcsel",
5420 ),
5421 },
5422 Field {
5423 name: "lsesysrdy",
5424 description: Some(
5425 "LSE system clock (LSESYS) ready\r Set and cleared by hardware to indicate when the LSE system clock is stable.When the LSESYSEN bit is set, the LSESYSRDY flag is set after two LSE clock cycles.\r The LSE clock must be already enabled and stable (LSEON and LSERDY are set).\r When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles.",
5426 ),
5427 bit_offset: BitOffset::Regular(
5428 RegularBitOffset {
5429 offset: 11,
5430 },
5431 ),
5432 bit_size: 1,
5433 array: None,
5434 enumm: None,
5435 },
5436 Field {
5437 name: "lsegfon",
5438 description: Some(
5439 "LSE clock glitch filter enable\r Set and cleared by hardware to enable the LSE glitch filter. This bit can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0)",
5440 ),
5441 bit_offset: BitOffset::Regular(
5442 RegularBitOffset {
5443 offset: 12,
5444 },
5445 ),
5446 bit_size: 1,
5447 array: None,
5448 enumm: None,
5449 },
5450 Field {
5451 name: "rtcen",
5452 description: Some(
5453 "RTC and TAMP clock enable\r Set and cleared by software.",
5454 ),
5455 bit_offset: BitOffset::Regular(
5456 RegularBitOffset {
5457 offset: 15,
5458 },
5459 ),
5460 bit_size: 1,
5461 array: None,
5462 enumm: None,
5463 },
5464 Field {
5465 name: "bdrst",
5466 description: Some(
5467 "Backup domain software reset\r Set and cleared by software.",
5468 ),
5469 bit_offset: BitOffset::Regular(
5470 RegularBitOffset {
5471 offset: 16,
5472 },
5473 ),
5474 bit_size: 1,
5475 array: None,
5476 enumm: None,
5477 },
5478 Field {
5479 name: "lscoen",
5480 description: Some(
5481 "Low-speed clock output (LSCO) enable\r Set and cleared by software.",
5482 ),
5483 bit_offset: BitOffset::Regular(
5484 RegularBitOffset {
5485 offset: 24,
5486 },
5487 ),
5488 bit_size: 1,
5489 array: None,
5490 enumm: None,
5491 },
5492 Field {
5493 name: "lscosel",
5494 description: Some(
5495 "Low-speed clock output selection\r Set and cleared by software.",
5496 ),
5497 bit_offset: BitOffset::Regular(
5498 RegularBitOffset {
5499 offset: 25,
5500 },
5501 ),
5502 bit_size: 1,
5503 array: None,
5504 enumm: Some(
5505 "Lscosel",
5506 ),
5507 },
5508 Field {
5509 name: "lsion",
5510 description: Some(
5511 "LSI oscillator enable\r Set and cleared by software.",
5512 ),
5513 bit_offset: BitOffset::Regular(
5514 RegularBitOffset {
5515 offset: 26,
5516 },
5517 ),
5518 bit_size: 1,
5519 array: None,
5520 enumm: None,
5521 },
5522 Field {
5523 name: "lsirdy",
5524 description: Some(
5525 "LSI oscillator ready\r Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0.",
5526 ),
5527 bit_offset: BitOffset::Regular(
5528 RegularBitOffset {
5529 offset: 27,
5530 },
5531 ),
5532 bit_size: 1,
5533 array: None,
5534 enumm: None,
5535 },
5536 Field {
5537 name: "lsiprediv",
5538 description: Some(
5539 "Low-speed clock divider configuration\r Set and cleared by software to enable the LSI division. This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). If the LSI was previously enabled, it is necessary to wait for at least 60 μs after clearing LSION bit (synchronization time for LSI to be really disabled), before writing LSIPREDIV. The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC.",
5540 ),
5541 bit_offset: BitOffset::Regular(
5542 RegularBitOffset {
5543 offset: 28,
5544 },
5545 ),
5546 bit_size: 1,
5547 array: None,
5548 enumm: Some(
5549 "Lsiprediv",
5550 ),
5551 },
5552 ],
5553 },
5554 FieldSet {
5555 name: "Ccipr1",
5556 extends: None,
5557 description: Some(
5558 "RCC peripherals independent clock configuration register 1",
5559 ),
5560 bit_size: 32,
5561 fields: &[
5562 Field {
5563 name: "usart1sel",
5564 description: Some(
5565 "USART1 kernel clock source selection\r This bits are used to select the USART1 kernel clock source.\r Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE.",
5566 ),
5567 bit_offset: BitOffset::Regular(
5568 RegularBitOffset {
5569 offset: 0,
5570 },
5571 ),
5572 bit_size: 2,
5573 array: None,
5574 enumm: Some(
5575 "Usart1sel",
5576 ),
5577 },
5578 Field {
5579 name: "usart2sel",
5580 description: Some(
5581 "USART2 kernel clock source selection\r This bits are used to select the USART2 kernel clock source.\r Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE.",
5582 ),
5583 bit_offset: BitOffset::Regular(
5584 RegularBitOffset {
5585 offset: 2,
5586 },
5587 ),
5588 bit_size: 2,
5589 array: None,
5590 enumm: Some(
5591 "Usartsel",
5592 ),
5593 },
5594 Field {
5595 name: "usart3sel",
5596 description: Some(
5597 "USART3 kernel clock source selection\r This bits are used to select the USART3 kernel clock source.\r Note: The USART3 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE.",
5598 ),
5599 bit_offset: BitOffset::Regular(
5600 RegularBitOffset {
5601 offset: 4,
5602 },
5603 ),
5604 bit_size: 2,
5605 array: None,
5606 enumm: Some(
5607 "Usartsel",
5608 ),
5609 },
5610 Field {
5611 name: "uart4sel",
5612 description: Some(
5613 "UART4 kernel clock source selection\r This bits are used to select the UART4 kernel clock source.\r Note: The UART4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE.",
5614 ),
5615 bit_offset: BitOffset::Regular(
5616 RegularBitOffset {
5617 offset: 6,
5618 },
5619 ),
5620 bit_size: 2,
5621 array: None,
5622 enumm: Some(
5623 "Usartsel",
5624 ),
5625 },
5626 Field {
5627 name: "uart5sel",
5628 description: Some(
5629 "UART5 kernel clock source selection\r These bits are used to select the UART5 kernel clock source.\r Note: The UART5 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or LSE.",
5630 ),
5631 bit_offset: BitOffset::Regular(
5632 RegularBitOffset {
5633 offset: 8,
5634 },
5635 ),
5636 bit_size: 2,
5637 array: None,
5638 enumm: Some(
5639 "Usartsel",
5640 ),
5641 },
5642 Field {
5643 name: "i2c1sel",
5644 description: Some(
5645 "I2C1 kernel clock source selection\r These bits are used to select the I2C1 kernel clock source.\r Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK.",
5646 ),
5647 bit_offset: BitOffset::Regular(
5648 RegularBitOffset {
5649 offset: 10,
5650 },
5651 ),
5652 bit_size: 2,
5653 array: None,
5654 enumm: Some(
5655 "I2csel",
5656 ),
5657 },
5658 Field {
5659 name: "i2c2sel",
5660 description: Some(
5661 "I2C2 kernel clock source selection\r These bits are used to select the I2C2 kernel clock source.\r Note: The I2C2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK.",
5662 ),
5663 bit_offset: BitOffset::Regular(
5664 RegularBitOffset {
5665 offset: 12,
5666 },
5667 ),
5668 bit_size: 2,
5669 array: None,
5670 enumm: Some(
5671 "I2csel",
5672 ),
5673 },
5674 Field {
5675 name: "i2c4sel",
5676 description: Some(
5677 "I2C4 kernel clock source selection\r These bits are used to select the I2C4 kernel clock source.\r Note: The I2C4 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK.",
5678 ),
5679 bit_offset: BitOffset::Regular(
5680 RegularBitOffset {
5681 offset: 14,
5682 },
5683 ),
5684 bit_size: 2,
5685 array: None,
5686 enumm: Some(
5687 "I2csel",
5688 ),
5689 },
5690 Field {
5691 name: "spi2sel",
5692 description: Some(
5693 "SPI2 kernel clock source selection\r These bits are used to select the SPI2 kernel clock source.\r Note: The SPI2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK.",
5694 ),
5695 bit_offset: BitOffset::Regular(
5696 RegularBitOffset {
5697 offset: 16,
5698 },
5699 ),
5700 bit_size: 2,
5701 array: None,
5702 enumm: Some(
5703 "Spi2sel",
5704 ),
5705 },
5706 Field {
5707 name: "lptim2sel",
5708 description: Some(
5709 "Low-power timer 2 kernel clock source selection\r These bits are used to select the LPTIM2 kernel clock source.\r Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI if HSIKERON = 1.",
5710 ),
5711 bit_offset: BitOffset::Regular(
5712 RegularBitOffset {
5713 offset: 18,
5714 },
5715 ),
5716 bit_size: 2,
5717 array: None,
5718 enumm: Some(
5719 "Lptim2sel",
5720 ),
5721 },
5722 Field {
5723 name: "spi1sel",
5724 description: Some(
5725 "SPI1 kernel clock source selection\r These bits are used to select the SPI1 kernel clock source.\r Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI or MSIK.",
5726 ),
5727 bit_offset: BitOffset::Regular(
5728 RegularBitOffset {
5729 offset: 20,
5730 },
5731 ),
5732 bit_size: 2,
5733 array: None,
5734 enumm: Some(
5735 "Spi1sel",
5736 ),
5737 },
5738 Field {
5739 name: "systicksel",
5740 description: Some(
5741 "SysTick clock source selection\r These bits are used to select the SysTick clock source.\r Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one HCLK cycle is introduced, due to the LSE or LSI sampling with HCLK in the SysTick circuitry.",
5742 ),
5743 bit_offset: BitOffset::Regular(
5744 RegularBitOffset {
5745 offset: 22,
5746 },
5747 ),
5748 bit_size: 2,
5749 array: None,
5750 enumm: Some(
5751 "Systicksel",
5752 ),
5753 },
5754 Field {
5755 name: "fdcan1sel",
5756 description: Some(
5757 "FDCAN1 kernel clock source selection\r These bits are used to select the FDCAN1 kernel clock source.",
5758 ),
5759 bit_offset: BitOffset::Regular(
5760 RegularBitOffset {
5761 offset: 24,
5762 },
5763 ),
5764 bit_size: 2,
5765 array: None,
5766 enumm: Some(
5767 "Fdcansel",
5768 ),
5769 },
5770 Field {
5771 name: "iclksel",
5772 description: Some(
5773 "intermediate clock source selection\r These bits are used to select the clock source used by OTG_FS and SDMMC.",
5774 ),
5775 bit_offset: BitOffset::Regular(
5776 RegularBitOffset {
5777 offset: 26,
5778 },
5779 ),
5780 bit_size: 2,
5781 array: None,
5782 enumm: Some(
5783 "Iclksel",
5784 ),
5785 },
5786 Field {
5787 name: "timicsel",
5788 description: Some(
5789 "Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture\r When the TIMICSEL2 bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected either to HSI/256, MSI/4 or MSI/1024. Depending on TIMICSEL[1:0] value, MSI is either MSIK or MSIS.\r When TIMICSEL2 is cleared, the HSI, MSIK and MSIS clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture.\r 0xx: HSI, MSIK and MSIS dividers disabled\r Note: The clock division must be disabled (TIMICSEL configured to 0xx) before selecting or changing a clock sources division.",
5790 ),
5791 bit_offset: BitOffset::Regular(
5792 RegularBitOffset {
5793 offset: 29,
5794 },
5795 ),
5796 bit_size: 3,
5797 array: None,
5798 enumm: Some(
5799 "Timicsel",
5800 ),
5801 },
5802 ],
5803 },
5804 FieldSet {
5805 name: "Ccipr2",
5806 extends: None,
5807 description: Some(
5808 "RCC peripherals independent clock configuration register 2",
5809 ),
5810 bit_size: 32,
5811 fields: &[
5812 Field {
5813 name: "mdf1sel",
5814 description: Some(
5815 "MDF1 kernel clock source selection\r These bits are used to select the MDF1 kernel clock source.\r others: reserved",
5816 ),
5817 bit_offset: BitOffset::Regular(
5818 RegularBitOffset {
5819 offset: 0,
5820 },
5821 ),
5822 bit_size: 3,
5823 array: None,
5824 enumm: Some(
5825 "Mdfsel",
5826 ),
5827 },
5828 Field {
5829 name: "sai1sel",
5830 description: Some(
5831 "SAI1 kernel clock source selection\r These bits are used to select the SAI1 kernel clock source.\r others: reserved\r Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible.",
5832 ),
5833 bit_offset: BitOffset::Regular(
5834 RegularBitOffset {
5835 offset: 5,
5836 },
5837 ),
5838 bit_size: 3,
5839 array: None,
5840 enumm: Some(
5841 "Saisel",
5842 ),
5843 },
5844 Field {
5845 name: "sai2sel",
5846 description: Some(
5847 "SAI2 kernel clock source selection\r These bits are used to select the SAI2 kernel clock source.\r others: reserved\r Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible.",
5848 ),
5849 bit_offset: BitOffset::Regular(
5850 RegularBitOffset {
5851 offset: 8,
5852 },
5853 ),
5854 bit_size: 3,
5855 array: None,
5856 enumm: Some(
5857 "Saisel",
5858 ),
5859 },
5860 Field {
5861 name: "saessel",
5862 description: Some(
5863 "SAES kernel clock source selection\r This bit is used to select the SAES kernel clock source.",
5864 ),
5865 bit_offset: BitOffset::Regular(
5866 RegularBitOffset {
5867 offset: 11,
5868 },
5869 ),
5870 bit_size: 1,
5871 array: None,
5872 enumm: Some(
5873 "Saessel",
5874 ),
5875 },
5876 Field {
5877 name: "rngsel",
5878 description: Some(
5879 "RNGSEL kernel clock source selection\r These bits are used to select the RNG kernel clock source.",
5880 ),
5881 bit_offset: BitOffset::Regular(
5882 RegularBitOffset {
5883 offset: 12,
5884 },
5885 ),
5886 bit_size: 2,
5887 array: None,
5888 enumm: Some(
5889 "Rngsel",
5890 ),
5891 },
5892 Field {
5893 name: "sdmmcsel",
5894 description: Some(
5895 "SDMMC1 and SDMMC2 kernel clock source selection\r This bit is used to select the SDMMC kernel clock source. It is recommended to change this bit only after reset and before enabling the SDMMC.",
5896 ),
5897 bit_offset: BitOffset::Regular(
5898 RegularBitOffset {
5899 offset: 14,
5900 },
5901 ),
5902 bit_size: 1,
5903 array: None,
5904 enumm: Some(
5905 "Sdmmcsel",
5906 ),
5907 },
5908 Field {
5909 name: "dsisel",
5910 description: Some(
5911 "DSI kernel clock source selection\r This bit is used to select the DSI kernel clock source.\r This bit is only available on some devices in the STM32U5 Series. \r Refer to the device datasheet for availability of its associated peripheral. \r Note: If not present, consider this bit as reserved and keep it at reset value.",
5912 ),
5913 bit_offset: BitOffset::Regular(
5914 RegularBitOffset {
5915 offset: 15,
5916 },
5917 ),
5918 bit_size: 1,
5919 array: None,
5920 enumm: Some(
5921 "Dsisel",
5922 ),
5923 },
5924 Field {
5925 name: "usart6sel",
5926 description: Some(
5927 "USART6 kernel clock source selection\r These bits are used to select the USART6 kernel clock source.\r The USART6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI or LSE.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value.",
5928 ),
5929 bit_offset: BitOffset::Regular(
5930 RegularBitOffset {
5931 offset: 16,
5932 },
5933 ),
5934 bit_size: 2,
5935 array: None,
5936 enumm: Some(
5937 "Usartsel",
5938 ),
5939 },
5940 Field {
5941 name: "ltdcsel",
5942 description: Some(
5943 "LTDC kernel clock source selection\r This bit is used to select the LTDC kernel clock source.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.",
5944 ),
5945 bit_offset: BitOffset::Regular(
5946 RegularBitOffset {
5947 offset: 18,
5948 },
5949 ),
5950 bit_size: 1,
5951 array: None,
5952 enumm: Some(
5953 "Ltdcsel",
5954 ),
5955 },
5956 Field {
5957 name: "octospisel",
5958 description: Some(
5959 "OCTOSPI1 and OCTOSPI2 kernel clock source selection\r These bits are used to select the OCTOSPI1 and OCTOSPI2 kernel clock source.",
5960 ),
5961 bit_offset: BitOffset::Regular(
5962 RegularBitOffset {
5963 offset: 20,
5964 },
5965 ),
5966 bit_size: 2,
5967 array: None,
5968 enumm: Some(
5969 "Octospisel",
5970 ),
5971 },
5972 Field {
5973 name: "hspi1sel",
5974 description: Some(
5975 "HSPI1 kernel clock source selection\r These bits are used to select the HSPI1 kernel clock source.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value.",
5976 ),
5977 bit_offset: BitOffset::Regular(
5978 RegularBitOffset {
5979 offset: 22,
5980 },
5981 ),
5982 bit_size: 2,
5983 array: None,
5984 enumm: Some(
5985 "Hspisel",
5986 ),
5987 },
5988 Field {
5989 name: "i2c5sel",
5990 description: Some(
5991 "I2C5 kernel clock source selection\r These bits are used to select the I2C5 kernel clock source.\r The I2C5 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI�or MSIK.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value.",
5992 ),
5993 bit_offset: BitOffset::Regular(
5994 RegularBitOffset {
5995 offset: 24,
5996 },
5997 ),
5998 bit_size: 2,
5999 array: None,
6000 enumm: Some(
6001 "I2csel",
6002 ),
6003 },
6004 Field {
6005 name: "i2c6sel",
6006 description: Some(
6007 "I2C6 kernel clock source selection\r These bits are used to select the I2C6 kernel clock source.\r The I2C6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI�or MSIK.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value.",
6008 ),
6009 bit_offset: BitOffset::Regular(
6010 RegularBitOffset {
6011 offset: 26,
6012 },
6013 ),
6014 bit_size: 2,
6015 array: None,
6016 enumm: Some(
6017 "I2csel",
6018 ),
6019 },
6020 Field {
6021 name: "otghssel",
6022 description: Some(
6023 "OTG_HS PHY kernel clock source selection\r These bits are used to select the OTG_HS PHY kernel clock source.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value.",
6024 ),
6025 bit_offset: BitOffset::Regular(
6026 RegularBitOffset {
6027 offset: 30,
6028 },
6029 ),
6030 bit_size: 2,
6031 array: None,
6032 enumm: Some(
6033 "Otghssel",
6034 ),
6035 },
6036 ],
6037 },
6038 FieldSet {
6039 name: "Ccipr3",
6040 extends: None,
6041 description: Some(
6042 "RCC peripherals independent clock configuration register 3",
6043 ),
6044 bit_size: 32,
6045 fields: &[
6046 Field {
6047 name: "lpuart1sel",
6048 description: Some(
6049 "LPUART1 kernel clock source selection\r These bits are used to select the LPUART1 kernel clock source.\r others: reserved\r Note: The LPUART1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI, LSE or MSIK.",
6050 ),
6051 bit_offset: BitOffset::Regular(
6052 RegularBitOffset {
6053 offset: 0,
6054 },
6055 ),
6056 bit_size: 3,
6057 array: None,
6058 enumm: Some(
6059 "Lpusartsel",
6060 ),
6061 },
6062 Field {
6063 name: "spi3sel",
6064 description: Some(
6065 "SPI3 kernel clock source selection\r These bits are used to select the SPI3 kernel clock source.\r Note: The SPI3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK.",
6066 ),
6067 bit_offset: BitOffset::Regular(
6068 RegularBitOffset {
6069 offset: 3,
6070 },
6071 ),
6072 bit_size: 2,
6073 array: None,
6074 enumm: Some(
6075 "Spi3sel",
6076 ),
6077 },
6078 Field {
6079 name: "i2c3sel",
6080 description: Some(
6081 "I2C3 kernel clock source selection\r These bits are used to select the I2C3 kernel clock source.\r Note: The I2C3 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK.",
6082 ),
6083 bit_offset: BitOffset::Regular(
6084 RegularBitOffset {
6085 offset: 6,
6086 },
6087 ),
6088 bit_size: 2,
6089 array: None,
6090 enumm: Some(
6091 "I2c3sel",
6092 ),
6093 },
6094 Field {
6095 name: "lptim34sel",
6096 description: Some(
6097 "LPTIM3 and LPTIM4 kernel clock source selection\r These bits are used to select the LPTIM3 and LPTIM4 kernel clock source.\r Note: The LPTIM3 and LPTIM4 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI with HSIKERON = 1 or MSIK with MSIKERON\u{a0}=\u{a0}1.",
6098 ),
6099 bit_offset: BitOffset::Regular(
6100 RegularBitOffset {
6101 offset: 8,
6102 },
6103 ),
6104 bit_size: 2,
6105 array: None,
6106 enumm: Some(
6107 "Lptimsel",
6108 ),
6109 },
6110 Field {
6111 name: "lptim1sel",
6112 description: Some(
6113 "LPTIM1 kernel clock source selection\r These bits are used to select the LPTIM1 kernel clock source.\r Note: The LPTIM1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is LSI, LSE, HSI with HSIKERON = 1 or MSIK with MSIKERON = 1.",
6114 ),
6115 bit_offset: BitOffset::Regular(
6116 RegularBitOffset {
6117 offset: 10,
6118 },
6119 ),
6120 bit_size: 2,
6121 array: None,
6122 enumm: Some(
6123 "Lptimsel",
6124 ),
6125 },
6126 Field {
6127 name: "adcdacsel",
6128 description: Some(
6129 "ADC1, ADC4 and DAC1 kernel clock source selection\r These bits are used to select the ADC1, ADC4 and DAC1 kernel clock source.\r others: reserved\r Note: The ADC1, ADC4 and DAC1 are functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is HSI or MSIK (only ADC4 and DAC1 are functional in Stop 2 mode).",
6130 ),
6131 bit_offset: BitOffset::Regular(
6132 RegularBitOffset {
6133 offset: 12,
6134 },
6135 ),
6136 bit_size: 3,
6137 array: None,
6138 enumm: Some(
6139 "Adcdacsel",
6140 ),
6141 },
6142 Field {
6143 name: "dac1sel",
6144 description: Some(
6145 "DAC1 sample and hold clock source selection\r This bit is used to select the DAC1 sample and hold clock source.",
6146 ),
6147 bit_offset: BitOffset::Regular(
6148 RegularBitOffset {
6149 offset: 15,
6150 },
6151 ),
6152 bit_size: 1,
6153 array: None,
6154 enumm: Some(
6155 "Dacsel",
6156 ),
6157 },
6158 Field {
6159 name: "adf1sel",
6160 description: Some(
6161 "ADF1 kernel clock source selection\r These bits are used to select the ADF1 kernel clock source.\r others: reserved\r Note: The ADF1 is functional in Stop 0, Stop 1 and Stop 2 modes only when the kernel clock is AUDIOCLK or MSIK.",
6162 ),
6163 bit_offset: BitOffset::Regular(
6164 RegularBitOffset {
6165 offset: 16,
6166 },
6167 ),
6168 bit_size: 3,
6169 array: None,
6170 enumm: Some(
6171 "Adfsel",
6172 ),
6173 },
6174 ],
6175 },
6176 FieldSet {
6177 name: "Cfgr1",
6178 extends: None,
6179 description: Some(
6180 "RCC clock configuration register 1",
6181 ),
6182 bit_size: 32,
6183 fields: &[
6184 Field {
6185 name: "sw",
6186 description: Some(
6187 "system clock switch\r Set and cleared by software to select system clock source (SYSCLK).\r Configured by hardware to force MSIS oscillator selection when exiting Standby or Shutdown mode. Configured by hardware to force MSIS or HSI oscillator selection when exiting Stop mode or in case of HSE oscillator failure, depending on STOPWUCK value.",
6188 ),
6189 bit_offset: BitOffset::Regular(
6190 RegularBitOffset {
6191 offset: 0,
6192 },
6193 ),
6194 bit_size: 2,
6195 array: None,
6196 enumm: Some(
6197 "Sw",
6198 ),
6199 },
6200 Field {
6201 name: "sws",
6202 description: Some(
6203 "system clock switch status\r Set and cleared by hardware to indicate which clock source is used as system clock.",
6204 ),
6205 bit_offset: BitOffset::Regular(
6206 RegularBitOffset {
6207 offset: 2,
6208 },
6209 ),
6210 bit_size: 2,
6211 array: None,
6212 enumm: Some(
6213 "Sw",
6214 ),
6215 },
6216 Field {
6217 name: "stopwuck",
6218 description: Some(
6219 "wakeup from Stop and CSS backup clock selection\r Set and cleared by software to select the system clock used when exiting Stop mode.\r The selected clock is also used as emergency clock for the clock security system on HSE. Warning: STOPWUCK must not be modified when the CSS is enabled by HSECSSON bit in RCC_CR and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW\u{a0}=\u{a0}10).",
6220 ),
6221 bit_offset: BitOffset::Regular(
6222 RegularBitOffset {
6223 offset: 4,
6224 },
6225 ),
6226 bit_size: 1,
6227 array: None,
6228 enumm: Some(
6229 "Stopwuck",
6230 ),
6231 },
6232 Field {
6233 name: "stopkerwuck",
6234 description: Some(
6235 "wakeup from Stop kernel clock automatic enable selection\r Set and cleared by software to enable automatically another oscillator when exiting Stop mode. This oscillator can be used as independent kernel clock by peripherals.",
6236 ),
6237 bit_offset: BitOffset::Regular(
6238 RegularBitOffset {
6239 offset: 5,
6240 },
6241 ),
6242 bit_size: 1,
6243 array: None,
6244 enumm: Some(
6245 "Stopkerwuck",
6246 ),
6247 },
6248 Field {
6249 name: "mcosel",
6250 description: Some(
6251 "microcontroller clock output\r Set and cleared by software.\r Others: reserved\r Note: This clock output may have some truncated cycles at startup or during MCO clock source switching.",
6252 ),
6253 bit_offset: BitOffset::Regular(
6254 RegularBitOffset {
6255 offset: 24,
6256 },
6257 ),
6258 bit_size: 4,
6259 array: None,
6260 enumm: Some(
6261 "Mcosel",
6262 ),
6263 },
6264 Field {
6265 name: "mcopre",
6266 description: Some(
6267 "microcontroller clock output prescaler\r Set and cleared by software.\r It is highly recommended to change this prescaler before MCO output is enabled.\r Others: not allowed",
6268 ),
6269 bit_offset: BitOffset::Regular(
6270 RegularBitOffset {
6271 offset: 28,
6272 },
6273 ),
6274 bit_size: 3,
6275 array: None,
6276 enumm: Some(
6277 "Mcopre",
6278 ),
6279 },
6280 ],
6281 },
6282 FieldSet {
6283 name: "Cfgr2",
6284 extends: None,
6285 description: Some(
6286 "RCC clock configuration register 2",
6287 ),
6288 bit_size: 32,
6289 fields: &[
6290 Field {
6291 name: "hpre",
6292 description: Some(
6293 "AHB prescaler\r Set and cleared by software to control the division factor of the AHB clock (HCLK).\r Depending on the device voltage range, the software must set these bits correctly to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to ). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account.\r 0xxx: SYSCLK not divided",
6294 ),
6295 bit_offset: BitOffset::Regular(
6296 RegularBitOffset {
6297 offset: 0,
6298 },
6299 ),
6300 bit_size: 4,
6301 array: None,
6302 enumm: Some(
6303 "Hpre",
6304 ),
6305 },
6306 Field {
6307 name: "ppre1",
6308 description: Some(
6309 "APB1 prescaler\r Set and cleared by software to control the division factor of the APB1 clock (PCLK1).\r 0xx: HCLK not divided",
6310 ),
6311 bit_offset: BitOffset::Regular(
6312 RegularBitOffset {
6313 offset: 4,
6314 },
6315 ),
6316 bit_size: 3,
6317 array: None,
6318 enumm: Some(
6319 "Ppre",
6320 ),
6321 },
6322 Field {
6323 name: "ppre2",
6324 description: Some(
6325 "APB2 prescaler\r Set and cleared by software to control the division factor of the APB2 clock (PCLK2).\r 0xx: HCLK not divided",
6326 ),
6327 bit_offset: BitOffset::Regular(
6328 RegularBitOffset {
6329 offset: 8,
6330 },
6331 ),
6332 bit_size: 3,
6333 array: None,
6334 enumm: Some(
6335 "Ppre",
6336 ),
6337 },
6338 Field {
6339 name: "dpre",
6340 description: Some(
6341 "DSI PHY prescaler\r This bitfiled is set and cleared by software to control the division factor of DSI PHY bus clock (DCLK).\r 0xx: DCLK not divided\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value.",
6342 ),
6343 bit_offset: BitOffset::Regular(
6344 RegularBitOffset {
6345 offset: 12,
6346 },
6347 ),
6348 bit_size: 3,
6349 array: None,
6350 enumm: Some(
6351 "Dpre",
6352 ),
6353 },
6354 Field {
6355 name: "ahb1dis",
6356 description: Some(
6357 "AHB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals (except those listed hereafter) are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks are off, except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1.",
6358 ),
6359 bit_offset: BitOffset::Regular(
6360 RegularBitOffset {
6361 offset: 16,
6362 },
6363 ),
6364 bit_size: 1,
6365 array: None,
6366 enumm: None,
6367 },
6368 Field {
6369 name: "ahb2dis1",
6370 description: Some(
6371 "AHB2_1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR1 (except SRAM2 and SRAM3) are used and when their clocks are disabled in RCC_AHB2ENR1. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR1 are off, except for SRAM2 and SRAM3.",
6372 ),
6373 bit_offset: BitOffset::Regular(
6374 RegularBitOffset {
6375 offset: 17,
6376 },
6377 ),
6378 bit_size: 1,
6379 array: None,
6380 enumm: None,
6381 },
6382 Field {
6383 name: "ahb2dis2",
6384 description: Some(
6385 "AHB2_2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR2 are used and when their clocks are disabled in RCC_AHB2ENR2. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2EBNR2 are off.",
6386 ),
6387 bit_offset: BitOffset::Regular(
6388 RegularBitOffset {
6389 offset: 18,
6390 },
6391 ),
6392 bit_size: 1,
6393 array: None,
6394 enumm: None,
6395 },
6396 Field {
6397 name: "apb1dis",
6398 description: Some(
6399 "APB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG.",
6400 ),
6401 bit_offset: BitOffset::Regular(
6402 RegularBitOffset {
6403 offset: 19,
6404 },
6405 ),
6406 bit_size: 1,
6407 array: None,
6408 enumm: None,
6409 },
6410 Field {
6411 name: "apb2dis",
6412 description: Some(
6413 "APB2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all the APB2 peripherals clocks are off.",
6414 ),
6415 bit_offset: BitOffset::Regular(
6416 RegularBitOffset {
6417 offset: 20,
6418 },
6419 ),
6420 bit_size: 1,
6421 array: None,
6422 enumm: None,
6423 },
6424 ],
6425 },
6426 FieldSet {
6427 name: "Cfgr3",
6428 extends: None,
6429 description: Some(
6430 "RCC clock configuration register 3",
6431 ),
6432 bit_size: 32,
6433 fields: &[
6434 Field {
6435 name: "ppre3",
6436 description: Some(
6437 "APB3 prescaler\r Set and cleared by software to control the division factor of the APB3 clock (PCLK3).\r 0xx: HCLK not divided",
6438 ),
6439 bit_offset: BitOffset::Regular(
6440 RegularBitOffset {
6441 offset: 4,
6442 },
6443 ),
6444 bit_size: 3,
6445 array: None,
6446 enumm: Some(
6447 "Ppre",
6448 ),
6449 },
6450 Field {
6451 name: "ahb3dis",
6452 description: Some(
6453 "AHB3 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB3 peripherals (except SRAM4) are used and when their clocks are disabled in RCC_AHB3ENR. When this bit is set, all the AHB3 peripherals clocks are off, except for SRAM4.",
6454 ),
6455 bit_offset: BitOffset::Regular(
6456 RegularBitOffset {
6457 offset: 16,
6458 },
6459 ),
6460 bit_size: 1,
6461 array: None,
6462 enumm: None,
6463 },
6464 Field {
6465 name: "apb3dis",
6466 description: Some(
6467 "APB3 clock disable\r This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals from RCC_APB3ENR are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off.",
6468 ),
6469 bit_offset: BitOffset::Regular(
6470 RegularBitOffset {
6471 offset: 17,
6472 },
6473 ),
6474 bit_size: 1,
6475 array: None,
6476 enumm: None,
6477 },
6478 ],
6479 },
6480 FieldSet {
6481 name: "Cicr",
6482 extends: None,
6483 description: Some(
6484 "RCC clock interrupt clear register",
6485 ),
6486 bit_size: 32,
6487 fields: &[
6488 Field {
6489 name: "lsirdyc",
6490 description: Some(
6491 "LSI ready interrupt clear\r Writing this bit to 1 clears the LSIRDYF flag. Writing 0 has no effect.",
6492 ),
6493 bit_offset: BitOffset::Regular(
6494 RegularBitOffset {
6495 offset: 0,
6496 },
6497 ),
6498 bit_size: 1,
6499 array: None,
6500 enumm: None,
6501 },
6502 Field {
6503 name: "lserdyc",
6504 description: Some(
6505 "LSE ready interrupt clear\r Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect.",
6506 ),
6507 bit_offset: BitOffset::Regular(
6508 RegularBitOffset {
6509 offset: 1,
6510 },
6511 ),
6512 bit_size: 1,
6513 array: None,
6514 enumm: None,
6515 },
6516 Field {
6517 name: "msisrdyc",
6518 description: Some(
6519 "MSIS ready interrupt clear\r Writing this bit to 1 clears the MSISRDYF flag. Writing 0 has no effect.",
6520 ),
6521 bit_offset: BitOffset::Regular(
6522 RegularBitOffset {
6523 offset: 2,
6524 },
6525 ),
6526 bit_size: 1,
6527 array: None,
6528 enumm: None,
6529 },
6530 Field {
6531 name: "hsirdyc",
6532 description: Some(
6533 "HSI ready interrupt clear\r Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect.",
6534 ),
6535 bit_offset: BitOffset::Regular(
6536 RegularBitOffset {
6537 offset: 3,
6538 },
6539 ),
6540 bit_size: 1,
6541 array: None,
6542 enumm: None,
6543 },
6544 Field {
6545 name: "hserdyc",
6546 description: Some(
6547 "HSE ready interrupt clear\r Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect.",
6548 ),
6549 bit_offset: BitOffset::Regular(
6550 RegularBitOffset {
6551 offset: 4,
6552 },
6553 ),
6554 bit_size: 1,
6555 array: None,
6556 enumm: None,
6557 },
6558 Field {
6559 name: "hsi48rdyc",
6560 description: Some(
6561 "HSI48 ready interrupt clear\r Writing this bit to 1 clears the HSI48RDYF flag. Writing 0 has no effect.",
6562 ),
6563 bit_offset: BitOffset::Regular(
6564 RegularBitOffset {
6565 offset: 5,
6566 },
6567 ),
6568 bit_size: 1,
6569 array: None,
6570 enumm: None,
6571 },
6572 Field {
6573 name: "pllrdyc",
6574 description: Some(
6575 "PLL1 ready interrupt clear\r Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect.",
6576 ),
6577 bit_offset: BitOffset::Regular(
6578 RegularBitOffset {
6579 offset: 6,
6580 },
6581 ),
6582 bit_size: 1,
6583 array: Some(
6584 Array::Regular(
6585 RegularArray {
6586 len: 3,
6587 stride: 1,
6588 },
6589 ),
6590 ),
6591 enumm: None,
6592 },
6593 Field {
6594 name: "cssc",
6595 description: Some(
6596 "Clock security system interrupt clear\r Writing this bit to 1 clears the CSSF flag. Writing 0 has no effect.",
6597 ),
6598 bit_offset: BitOffset::Regular(
6599 RegularBitOffset {
6600 offset: 10,
6601 },
6602 ),
6603 bit_size: 1,
6604 array: None,
6605 enumm: None,
6606 },
6607 Field {
6608 name: "msikrdyc",
6609 description: Some(
6610 "MSIK oscillator ready interrupt clear\r Writing this bit to 1 clears the MSIKRDYF flag. Writing 0 has no effect.",
6611 ),
6612 bit_offset: BitOffset::Regular(
6613 RegularBitOffset {
6614 offset: 11,
6615 },
6616 ),
6617 bit_size: 1,
6618 array: None,
6619 enumm: None,
6620 },
6621 Field {
6622 name: "shsirdyc",
6623 description: Some(
6624 "SHSI oscillator ready interrupt clear\r Writing this bit to 1 clears the SHSIRDYF flag. Writing 0 has no effect.",
6625 ),
6626 bit_offset: BitOffset::Regular(
6627 RegularBitOffset {
6628 offset: 12,
6629 },
6630 ),
6631 bit_size: 1,
6632 array: None,
6633 enumm: None,
6634 },
6635 ],
6636 },
6637 FieldSet {
6638 name: "Cier",
6639 extends: None,
6640 description: Some(
6641 "RCC clock interrupt enable register",
6642 ),
6643 bit_size: 32,
6644 fields: &[
6645 Field {
6646 name: "lsirdyie",
6647 description: Some(
6648 "LSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization.",
6649 ),
6650 bit_offset: BitOffset::Regular(
6651 RegularBitOffset {
6652 offset: 0,
6653 },
6654 ),
6655 bit_size: 1,
6656 array: None,
6657 enumm: None,
6658 },
6659 Field {
6660 name: "lserdyie",
6661 description: Some(
6662 "LSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization.",
6663 ),
6664 bit_offset: BitOffset::Regular(
6665 RegularBitOffset {
6666 offset: 1,
6667 },
6668 ),
6669 bit_size: 1,
6670 array: None,
6671 enumm: None,
6672 },
6673 Field {
6674 name: "msisrdyie",
6675 description: Some(
6676 "MSIS ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the MSIS oscillator stabilization.",
6677 ),
6678 bit_offset: BitOffset::Regular(
6679 RegularBitOffset {
6680 offset: 2,
6681 },
6682 ),
6683 bit_size: 1,
6684 array: None,
6685 enumm: None,
6686 },
6687 Field {
6688 name: "hsirdyie",
6689 description: Some(
6690 "HSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization.",
6691 ),
6692 bit_offset: BitOffset::Regular(
6693 RegularBitOffset {
6694 offset: 3,
6695 },
6696 ),
6697 bit_size: 1,
6698 array: None,
6699 enumm: None,
6700 },
6701 Field {
6702 name: "hserdyie",
6703 description: Some(
6704 "HSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization.",
6705 ),
6706 bit_offset: BitOffset::Regular(
6707 RegularBitOffset {
6708 offset: 4,
6709 },
6710 ),
6711 bit_size: 1,
6712 array: None,
6713 enumm: None,
6714 },
6715 Field {
6716 name: "hsi48rdyie",
6717 description: Some(
6718 "HSI48 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI48 oscillator stabilization.",
6719 ),
6720 bit_offset: BitOffset::Regular(
6721 RegularBitOffset {
6722 offset: 5,
6723 },
6724 ),
6725 bit_size: 1,
6726 array: None,
6727 enumm: None,
6728 },
6729 Field {
6730 name: "pllrdyie",
6731 description: Some(
6732 "PLL ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by PLL1 lock.",
6733 ),
6734 bit_offset: BitOffset::Regular(
6735 RegularBitOffset {
6736 offset: 6,
6737 },
6738 ),
6739 bit_size: 1,
6740 array: Some(
6741 Array::Regular(
6742 RegularArray {
6743 len: 3,
6744 stride: 1,
6745 },
6746 ),
6747 ),
6748 enumm: None,
6749 },
6750 Field {
6751 name: "msikrdyie",
6752 description: Some(
6753 "MSIK ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the MSIK oscillator stabilization.",
6754 ),
6755 bit_offset: BitOffset::Regular(
6756 RegularBitOffset {
6757 offset: 11,
6758 },
6759 ),
6760 bit_size: 1,
6761 array: None,
6762 enumm: None,
6763 },
6764 Field {
6765 name: "shsirdyie",
6766 description: Some(
6767 "SHSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the SHSI oscillator stabilization.",
6768 ),
6769 bit_offset: BitOffset::Regular(
6770 RegularBitOffset {
6771 offset: 12,
6772 },
6773 ),
6774 bit_size: 1,
6775 array: None,
6776 enumm: None,
6777 },
6778 ],
6779 },
6780 FieldSet {
6781 name: "Cifr",
6782 extends: None,
6783 description: Some(
6784 "RCC clock interrupt flag register",
6785 ),
6786 bit_size: 32,
6787 fields: &[
6788 Field {
6789 name: "lsirdyf",
6790 description: Some(
6791 "LSI ready interrupt flag\r Set by hardware when the LSI clock becomes stable and LSIRDYIE is set.\r Cleared by software setting the LSIRDYC bit.",
6792 ),
6793 bit_offset: BitOffset::Regular(
6794 RegularBitOffset {
6795 offset: 0,
6796 },
6797 ),
6798 bit_size: 1,
6799 array: None,
6800 enumm: None,
6801 },
6802 Field {
6803 name: "lserdyf",
6804 description: Some(
6805 "LSE ready interrupt flag\r Set by hardware when the LSE clock becomes stable and LSERDYIE is set.\r Cleared by software setting the LSERDYC bit.",
6806 ),
6807 bit_offset: BitOffset::Regular(
6808 RegularBitOffset {
6809 offset: 1,
6810 },
6811 ),
6812 bit_size: 1,
6813 array: None,
6814 enumm: None,
6815 },
6816 Field {
6817 name: "msisrdyf",
6818 description: Some(
6819 "MSIS ready interrupt flag\r Set by hardware when the MSIS clock becomes stable and MSISRDYIE is set.\r Cleared by software setting the MSISRDYC bit.",
6820 ),
6821 bit_offset: BitOffset::Regular(
6822 RegularBitOffset {
6823 offset: 2,
6824 },
6825 ),
6826 bit_size: 1,
6827 array: None,
6828 enumm: None,
6829 },
6830 Field {
6831 name: "hsirdyf",
6832 description: Some(
6833 "HSI ready interrupt flag\r Set by hardware when the HSI clock becomes stable and HSIRDYIE is set in a response to setting the HSION (see RCC_CR). When HSION is not set but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.\r Cleared by software setting the HSIRDYC bit.",
6834 ),
6835 bit_offset: BitOffset::Regular(
6836 RegularBitOffset {
6837 offset: 3,
6838 },
6839 ),
6840 bit_size: 1,
6841 array: None,
6842 enumm: None,
6843 },
6844 Field {
6845 name: "hserdyf",
6846 description: Some(
6847 "HSE ready interrupt flag\r Set by hardware when the HSE clock becomes stable and HSERDYIE is set.\r Cleared by software setting the HSERDYC bit.",
6848 ),
6849 bit_offset: BitOffset::Regular(
6850 RegularBitOffset {
6851 offset: 4,
6852 },
6853 ),
6854 bit_size: 1,
6855 array: None,
6856 enumm: None,
6857 },
6858 Field {
6859 name: "hsi48rdyf",
6860 description: Some(
6861 "HSI48 ready interrupt flag\r Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set.\r Cleared by software setting the HSI48RDYC bit.",
6862 ),
6863 bit_offset: BitOffset::Regular(
6864 RegularBitOffset {
6865 offset: 5,
6866 },
6867 ),
6868 bit_size: 1,
6869 array: None,
6870 enumm: None,
6871 },
6872 Field {
6873 name: "pllrdyf",
6874 description: Some(
6875 "PLL1 ready interrupt flag\r Set by hardware when the PLL1 locks and PLL1RDYIE is set.\r Cleared by software setting the PLL1RDYC bit.",
6876 ),
6877 bit_offset: BitOffset::Regular(
6878 RegularBitOffset {
6879 offset: 6,
6880 },
6881 ),
6882 bit_size: 1,
6883 array: Some(
6884 Array::Regular(
6885 RegularArray {
6886 len: 3,
6887 stride: 1,
6888 },
6889 ),
6890 ),
6891 enumm: None,
6892 },
6893 Field {
6894 name: "cssf",
6895 description: Some(
6896 "Clock security system interrupt flag\r Set by hardware when a failure is detected in the HSE oscillator.\r Cleared by software setting the CSSC bit.",
6897 ),
6898 bit_offset: BitOffset::Regular(
6899 RegularBitOffset {
6900 offset: 10,
6901 },
6902 ),
6903 bit_size: 1,
6904 array: None,
6905 enumm: None,
6906 },
6907 Field {
6908 name: "msikrdyf",
6909 description: Some(
6910 "MSIK ready interrupt flag\r Set by hardware when the MSIK clock becomes stable and MSIKRDYIE is set.\r Cleared by software setting the MSIKRDYC bit.",
6911 ),
6912 bit_offset: BitOffset::Regular(
6913 RegularBitOffset {
6914 offset: 11,
6915 },
6916 ),
6917 bit_size: 1,
6918 array: None,
6919 enumm: None,
6920 },
6921 Field {
6922 name: "shsirdyf",
6923 description: Some(
6924 "SHSI ready interrupt flag\r Set by hardware when the SHSI clock becomes stable and SHSIRDYIE is set.\r Cleared by software setting the SHSIRDYC bit.",
6925 ),
6926 bit_offset: BitOffset::Regular(
6927 RegularBitOffset {
6928 offset: 12,
6929 },
6930 ),
6931 bit_size: 1,
6932 array: None,
6933 enumm: None,
6934 },
6935 ],
6936 },
6937 FieldSet {
6938 name: "Cr",
6939 extends: None,
6940 description: Some(
6941 "RCC clock control register",
6942 ),
6943 bit_size: 32,
6944 fields: &[
6945 Field {
6946 name: "msison",
6947 description: Some(
6948 "MSIS clock enable\r Set and cleared by software.\r Cleared by hardware to stop the MSIS oscillator when entering Stop, Standby or Shutdown mode.\r Set by hardware to force the MSIS oscillator ON when exiting Standby or Shutdown mode.\r Set by hardware to force the MSIS oscillator ON when STOPWUCK = 0 when exiting Stop modes or in case of a failure of the HSE oscillator.\r Set by hardware when used directly or indirectly as system clock.",
6949 ),
6950 bit_offset: BitOffset::Regular(
6951 RegularBitOffset {
6952 offset: 0,
6953 },
6954 ),
6955 bit_size: 1,
6956 array: None,
6957 enumm: None,
6958 },
6959 Field {
6960 name: "msikeron",
6961 description: Some(
6962 "MSI enable for some peripheral kernels\r Set and cleared by software to force MSI ON even in Stop modes. Keeping the MSI ON in Stop mode allows the communication speed not to be reduced by the MSI startup time. This bit has no effect on MSISON and MSIKON values (see autonomous mode for more details).\r The MSIKERON must be configured at 0 before entering Stop 3 mode.",
6963 ),
6964 bit_offset: BitOffset::Regular(
6965 RegularBitOffset {
6966 offset: 1,
6967 },
6968 ),
6969 bit_size: 1,
6970 array: None,
6971 enumm: None,
6972 },
6973 Field {
6974 name: "msisrdy",
6975 description: Some(
6976 "MSIS clock ready flag\r Set by hardware to indicate that the MSIS oscillator is stable. This bit is set only when MSIS is enabled by software by setting MSISON.\r Note: Once the MSISON bit is cleared, MSISRDY goes low after six MSIS clock cycles.",
6977 ),
6978 bit_offset: BitOffset::Regular(
6979 RegularBitOffset {
6980 offset: 2,
6981 },
6982 ),
6983 bit_size: 1,
6984 array: None,
6985 enumm: None,
6986 },
6987 Field {
6988 name: "msipllen",
6989 description: Some(
6990 "MSI clock PLL-mode enable\r Set and cleared by software to enable/disable the PLL part of the MSI clock source.\r MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware). A hardware protection prevents from enabling MSIPLLEN if LSE is not ready.\r This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the CSS on LSE detects a LSE failure (see RCC_CSR).",
6991 ),
6992 bit_offset: BitOffset::Regular(
6993 RegularBitOffset {
6994 offset: 3,
6995 },
6996 ),
6997 bit_size: 1,
6998 array: None,
6999 enumm: None,
7000 },
7001 Field {
7002 name: "msikon",
7003 description: Some(
7004 "MSIK clock enable\r Set and cleared by software.\r Cleared by hardware to stop the MSIK when entering Stop, Standby or Shutdown mode.\r Set by hardware to force the MSIK oscillator ON when exiting Standby or Shutdown mode.\r Set by hardware to force the MSIK oscillator ON when STOPWUCK = 0 or STOPKERWUCK\u{a0}=\u{a0}0 when exiting Stop modes or in case of a failure of the HSE oscillator.",
7005 ),
7006 bit_offset: BitOffset::Regular(
7007 RegularBitOffset {
7008 offset: 4,
7009 },
7010 ),
7011 bit_size: 1,
7012 array: None,
7013 enumm: None,
7014 },
7015 Field {
7016 name: "msikrdy",
7017 description: Some(
7018 "MSIK clock ready flag\r Set by hardware to indicate that the MSIK is stable. This bit is set only when MSI kernel oscillator is enabled by software by setting MSIKON.\r Note: Once the MSIKON bit is cleared, MSIKRDY goes low after six MSIK oscillator clock cycles.",
7019 ),
7020 bit_offset: BitOffset::Regular(
7021 RegularBitOffset {
7022 offset: 5,
7023 },
7024 ),
7025 bit_size: 1,
7026 array: None,
7027 enumm: None,
7028 },
7029 Field {
7030 name: "msipllsel",
7031 description: Some(
7032 "MSI clock with PLL mode selection\r Set and cleared by software to select which MSI output clock uses the PLL mode. This bit can be written only when the MSI PLL mode is disabled (MSIPLLEN = 0).\r Note: If the MSI kernel clock output uses the same oscillator source than the MSI system clock output, then the PLL mode is applied to the both clocks outputs.",
7033 ),
7034 bit_offset: BitOffset::Regular(
7035 RegularBitOffset {
7036 offset: 6,
7037 },
7038 ),
7039 bit_size: 1,
7040 array: None,
7041 enumm: Some(
7042 "Msipllsel",
7043 ),
7044 },
7045 Field {
7046 name: "msipllfast",
7047 description: Some(
7048 "MSI PLL mode fast startup\r Set and reset by software to enable/disable the fast PLL mode start-up of the MSI clock\r source. This bit is used only if PLL mode is selected (MSIPLLEN = 1).\r The fast start-up feature is not active the first time the PLL mode is selected. The fast start-up is active when the MSI in PLL mode returns from switch off.",
7049 ),
7050 bit_offset: BitOffset::Regular(
7051 RegularBitOffset {
7052 offset: 7,
7053 },
7054 ),
7055 bit_size: 1,
7056 array: None,
7057 enumm: Some(
7058 "Msipllfast",
7059 ),
7060 },
7061 Field {
7062 name: "hsion",
7063 description: Some(
7064 "HSI clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSI oscillator when entering Stop, Standby or Shutdown mode.\r Set by hardware to force the HSI oscillator ON when STOPWUCK = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator.\r This bit is set by hardware if the HSI is used directly or indirectly as system clock.",
7065 ),
7066 bit_offset: BitOffset::Regular(
7067 RegularBitOffset {
7068 offset: 8,
7069 },
7070 ),
7071 bit_size: 1,
7072 array: None,
7073 enumm: None,
7074 },
7075 Field {
7076 name: "hsikeron",
7077 description: Some(
7078 "HSI enable for some peripheral kernels\r Set and cleared by software to force HSI ON even in Stop modes. Keeping the HSI ON in Stop mode allows the communication speed not to be reduced by the HSI startup time. This bit has no effect on HSION value.\r Refer to for more details.\r The HSIKERON must be configured at 0 before entering Stop 3 mode.",
7079 ),
7080 bit_offset: BitOffset::Regular(
7081 RegularBitOffset {
7082 offset: 9,
7083 },
7084 ),
7085 bit_size: 1,
7086 array: None,
7087 enumm: None,
7088 },
7089 Field {
7090 name: "hsirdy",
7091 description: Some(
7092 "HSI clock ready flag\r Set by hardware to indicate that HSI oscillator is stable. This bit is set only when HSI is enabled by software by setting HSION.\r Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI clock cycles.",
7093 ),
7094 bit_offset: BitOffset::Regular(
7095 RegularBitOffset {
7096 offset: 10,
7097 },
7098 ),
7099 bit_size: 1,
7100 array: None,
7101 enumm: None,
7102 },
7103 Field {
7104 name: "hsi48on",
7105 description: Some(
7106 "HSI48 clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes.",
7107 ),
7108 bit_offset: BitOffset::Regular(
7109 RegularBitOffset {
7110 offset: 12,
7111 },
7112 ),
7113 bit_size: 1,
7114 array: None,
7115 enumm: None,
7116 },
7117 Field {
7118 name: "hsi48rdy",
7119 description: Some(
7120 "HSI48 clock ready flag\r Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON.",
7121 ),
7122 bit_offset: BitOffset::Regular(
7123 RegularBitOffset {
7124 offset: 13,
7125 },
7126 ),
7127 bit_size: 1,
7128 array: None,
7129 enumm: None,
7130 },
7131 Field {
7132 name: "shsion",
7133 description: Some(
7134 "SHSI clock enable\r Set and cleared by software.\r Cleared by hardware to stop the SHSI when entering in Stop, Standby or Shutdown modes.",
7135 ),
7136 bit_offset: BitOffset::Regular(
7137 RegularBitOffset {
7138 offset: 14,
7139 },
7140 ),
7141 bit_size: 1,
7142 array: None,
7143 enumm: None,
7144 },
7145 Field {
7146 name: "shsirdy",
7147 description: Some(
7148 "SHSI clock ready flag\r Set by hardware to indicate that the SHSI oscillator is stable. This bit is set only when SHSI is enabled by software by setting SHSION.\r Note: Once the SHSION bit is cleared, SHSIRDY goes low after six SHSI clock cycles.",
7149 ),
7150 bit_offset: BitOffset::Regular(
7151 RegularBitOffset {
7152 offset: 15,
7153 },
7154 ),
7155 bit_size: 1,
7156 array: None,
7157 enumm: None,
7158 },
7159 Field {
7160 name: "hseon",
7161 description: Some(
7162 "HSE clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.",
7163 ),
7164 bit_offset: BitOffset::Regular(
7165 RegularBitOffset {
7166 offset: 16,
7167 },
7168 ),
7169 bit_size: 1,
7170 array: None,
7171 enumm: None,
7172 },
7173 Field {
7174 name: "hserdy",
7175 description: Some(
7176 "HSE clock ready flag\r Set by hardware to indicate that the HSE oscillator is stable.\r Note: Once the HSEON bit is cleared, HSERDY goes low after six HSE clock cycles.",
7177 ),
7178 bit_offset: BitOffset::Regular(
7179 RegularBitOffset {
7180 offset: 17,
7181 },
7182 ),
7183 bit_size: 1,
7184 array: None,
7185 enumm: None,
7186 },
7187 Field {
7188 name: "hsebyp",
7189 description: Some(
7190 "HSE crystal oscillator bypass\r Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled.",
7191 ),
7192 bit_offset: BitOffset::Regular(
7193 RegularBitOffset {
7194 offset: 18,
7195 },
7196 ),
7197 bit_size: 1,
7198 array: None,
7199 enumm: None,
7200 },
7201 Field {
7202 name: "csson",
7203 description: Some(
7204 "Clock security system enable\r Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset.",
7205 ),
7206 bit_offset: BitOffset::Regular(
7207 RegularBitOffset {
7208 offset: 19,
7209 },
7210 ),
7211 bit_size: 1,
7212 array: None,
7213 enumm: None,
7214 },
7215 Field {
7216 name: "hseext",
7217 description: Some(
7218 "HSE external clock bypass mode\r Set and reset by software to select the external clock mode in bypass mode. External clock mode must be configured with HSEON bit to be used by the device. This bit can be written only if the HSE oscillator is disabled. This bit is active only if the HSE bypass mode is enabled.",
7219 ),
7220 bit_offset: BitOffset::Regular(
7221 RegularBitOffset {
7222 offset: 20,
7223 },
7224 ),
7225 bit_size: 1,
7226 array: None,
7227 enumm: Some(
7228 "Hseext",
7229 ),
7230 },
7231 Field {
7232 name: "pllon",
7233 description: Some(
7234 "PLL1 enable\r Set and cleared by software to enable the main PLL.\r Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL1 clock is used as the system clock.",
7235 ),
7236 bit_offset: BitOffset::Regular(
7237 RegularBitOffset {
7238 offset: 24,
7239 },
7240 ),
7241 bit_size: 1,
7242 array: Some(
7243 Array::Regular(
7244 RegularArray {
7245 len: 3,
7246 stride: 2,
7247 },
7248 ),
7249 ),
7250 enumm: None,
7251 },
7252 Field {
7253 name: "pllrdy",
7254 description: Some(
7255 "PLL1 clock ready flag\r Set by hardware to indicate that the PLL1 is locked.",
7256 ),
7257 bit_offset: BitOffset::Regular(
7258 RegularBitOffset {
7259 offset: 25,
7260 },
7261 ),
7262 bit_size: 1,
7263 array: Some(
7264 Array::Regular(
7265 RegularArray {
7266 len: 3,
7267 stride: 2,
7268 },
7269 ),
7270 ),
7271 enumm: None,
7272 },
7273 ],
7274 },
7275 FieldSet {
7276 name: "Crrcr",
7277 extends: None,
7278 description: Some(
7279 "RCC clock recovery RC register",
7280 ),
7281 bit_size: 32,
7282 fields: &[
7283 Field {
7284 name: "hsi48cal",
7285 description: Some(
7286 "HSI48 clock calibration\r These bits are initialized at startup with the factory-programmed HSI48 calibration trim value.",
7287 ),
7288 bit_offset: BitOffset::Regular(
7289 RegularBitOffset {
7290 offset: 0,
7291 },
7292 ),
7293 bit_size: 9,
7294 array: None,
7295 enumm: None,
7296 },
7297 ],
7298 },
7299 FieldSet {
7300 name: "Csr",
7301 extends: None,
7302 description: Some(
7303 "RCC control/status register",
7304 ),
7305 bit_size: 32,
7306 fields: &[
7307 Field {
7308 name: "msiksrange",
7309 description: Some(
7310 "MSIK range after Standby mode\r Set by software to chose the MSIK frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4\u{a0}MHz. MSIKSRANGE can be written only when MSIRGSEL = 1.\r others: reserved\r Note: Changing the MSIKSRANGE does not change the current MSIK frequency.",
7311 ),
7312 bit_offset: BitOffset::Regular(
7313 RegularBitOffset {
7314 offset: 8,
7315 },
7316 ),
7317 bit_size: 4,
7318 array: None,
7319 enumm: Some(
7320 "Msixsrange",
7321 ),
7322 },
7323 Field {
7324 name: "msissrange",
7325 description: Some(
7326 "MSIS range after Standby mode\r Set by software to chose the MSIS frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4\u{a0}MHz. MSISSRANGE can be written only when MSIRGSEL = 1.\r others: reserved\r Note: Changing the MSISSRANGE does not change the current MSIS frequency.",
7327 ),
7328 bit_offset: BitOffset::Regular(
7329 RegularBitOffset {
7330 offset: 12,
7331 },
7332 ),
7333 bit_size: 4,
7334 array: None,
7335 enumm: Some(
7336 "Msixsrange",
7337 ),
7338 },
7339 Field {
7340 name: "rmvf",
7341 description: Some(
7342 "Remove reset flag\r Set by software to clear the reset flags.",
7343 ),
7344 bit_offset: BitOffset::Regular(
7345 RegularBitOffset {
7346 offset: 23,
7347 },
7348 ),
7349 bit_size: 1,
7350 array: None,
7351 enumm: None,
7352 },
7353 Field {
7354 name: "oblrstf",
7355 description: Some(
7356 "Option byte loader reset flag\r Set by hardware when a reset from the option byte loading occurs.\r Cleared by writing to the RMVF bit.",
7357 ),
7358 bit_offset: BitOffset::Regular(
7359 RegularBitOffset {
7360 offset: 25,
7361 },
7362 ),
7363 bit_size: 1,
7364 array: None,
7365 enumm: None,
7366 },
7367 Field {
7368 name: "pinrstf",
7369 description: Some(
7370 "NRST pin reset flag\r Set by hardware when a reset from the NRST pin occurs.\r Cleared by writing to the RMVF bit.",
7371 ),
7372 bit_offset: BitOffset::Regular(
7373 RegularBitOffset {
7374 offset: 26,
7375 },
7376 ),
7377 bit_size: 1,
7378 array: None,
7379 enumm: None,
7380 },
7381 Field {
7382 name: "borrstf",
7383 description: Some(
7384 "BOR flag\r Set by hardware when a BOR occurs.\r Cleared by writing to the RMVF bit.",
7385 ),
7386 bit_offset: BitOffset::Regular(
7387 RegularBitOffset {
7388 offset: 27,
7389 },
7390 ),
7391 bit_size: 1,
7392 array: None,
7393 enumm: None,
7394 },
7395 Field {
7396 name: "sftrstf",
7397 description: Some(
7398 "Software reset flag\r Set by hardware when a software reset occurs.\r Cleared by writing to the RMVF bit.",
7399 ),
7400 bit_offset: BitOffset::Regular(
7401 RegularBitOffset {
7402 offset: 28,
7403 },
7404 ),
7405 bit_size: 1,
7406 array: None,
7407 enumm: None,
7408 },
7409 Field {
7410 name: "iwdgrstf",
7411 description: Some(
7412 "Independent watchdog reset flag\r Set by hardware when an independent watchdog reset domain occurs.\r Cleared by writing to the RMVF bit.",
7413 ),
7414 bit_offset: BitOffset::Regular(
7415 RegularBitOffset {
7416 offset: 29,
7417 },
7418 ),
7419 bit_size: 1,
7420 array: None,
7421 enumm: None,
7422 },
7423 Field {
7424 name: "wwdgrstf",
7425 description: Some(
7426 "Window watchdog reset flag\r Set by hardware when a window watchdog reset occurs.\r Cleared by writing to the RMVF bit.",
7427 ),
7428 bit_offset: BitOffset::Regular(
7429 RegularBitOffset {
7430 offset: 30,
7431 },
7432 ),
7433 bit_size: 1,
7434 array: None,
7435 enumm: None,
7436 },
7437 Field {
7438 name: "lpwrrstf",
7439 description: Some(
7440 "Low-power reset flag\r Set by hardware when a reset occurs due to Stop, Standby or Shutdown mode entry, whereas the corresponding nRST_STOP, nRST_STBY or nRST_SHDW option bit is cleared.\r Cleared by writing to the RMVF bit.",
7441 ),
7442 bit_offset: BitOffset::Regular(
7443 RegularBitOffset {
7444 offset: 31,
7445 },
7446 ),
7447 bit_size: 1,
7448 array: None,
7449 enumm: None,
7450 },
7451 ],
7452 },
7453 FieldSet {
7454 name: "Icscr1",
7455 extends: None,
7456 description: Some(
7457 "RCC internal clock sources calibration register 1",
7458 ),
7459 bit_size: 32,
7460 fields: &[
7461 Field {
7462 name: "msical3",
7463 description: Some(
7464 "MSIRC3 clock calibration for MSI ranges 12 to 15\r These bits are initialized at startup with the factory-programmed MSIRC3 calibration trim value for ranges 12 to 15. When MSITRIM3 is written, MSICAL3 is updated with the sum of MSITRIM3[4:0] and the factory calibration trim value MSIRC2[4:0].\r There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level.",
7465 ),
7466 bit_offset: BitOffset::Regular(
7467 RegularBitOffset {
7468 offset: 0,
7469 },
7470 ),
7471 bit_size: 5,
7472 array: None,
7473 enumm: None,
7474 },
7475 Field {
7476 name: "msical2",
7477 description: Some(
7478 "MSIRC2 clock calibration for MSI ranges 8 to 11\r These bits are initialized at startup with the factory-programmed MSIRC2 calibration trim value for ranges 8 to 11. When MSITRIM2 is written, MSICAL2 is updated with the sum of MSITRIM2[4:0] and the factory calibration trim value MSIRC2[4:0].\r There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level.",
7479 ),
7480 bit_offset: BitOffset::Regular(
7481 RegularBitOffset {
7482 offset: 5,
7483 },
7484 ),
7485 bit_size: 5,
7486 array: None,
7487 enumm: None,
7488 },
7489 Field {
7490 name: "msical1",
7491 description: Some(
7492 "MSIRC1 clock calibration for MSI ranges 4 to 7\r These bits are initialized at startup with the factory-programmed MSIRC1 calibration trim value for ranges 4 to 7. When MSITRIM1 is written, MSICAL1 is updated with the sum of MSITRIM1[4:0] and the factory calibration trim value MSIRC1[4:0].\r There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level.",
7493 ),
7494 bit_offset: BitOffset::Regular(
7495 RegularBitOffset {
7496 offset: 10,
7497 },
7498 ),
7499 bit_size: 5,
7500 array: None,
7501 enumm: None,
7502 },
7503 Field {
7504 name: "msical0",
7505 description: Some(
7506 "MSIRC0 clock calibration for MSI ranges 0 to 3\r These bits are initialized at startup with the factory-programmed MSIRC0 calibration trim value for ranges 0 to 3. When MSITRIM0 is written, MSICAL0 is updated with the sum of MSITRIM0[4:0] and the factory-programmed calibration trim value MSIRC0[4:0].",
7507 ),
7508 bit_offset: BitOffset::Regular(
7509 RegularBitOffset {
7510 offset: 15,
7511 },
7512 ),
7513 bit_size: 5,
7514 array: None,
7515 enumm: None,
7516 },
7517 Field {
7518 name: "msibias",
7519 description: Some(
7520 "MSI bias mode selection\r Set by software to select the MSI bias mode. By default, the MSI bias is in continuous mode in order to maintain the output clocks accuracy. Setting this bit reduces the MSI consumption under range 4 but decrease its accuracy.",
7521 ),
7522 bit_offset: BitOffset::Regular(
7523 RegularBitOffset {
7524 offset: 22,
7525 },
7526 ),
7527 bit_size: 1,
7528 array: None,
7529 enumm: Some(
7530 "Msibias",
7531 ),
7532 },
7533 Field {
7534 name: "msirgsel",
7535 description: Some(
7536 "MSI clock range selection\r Set by software to select the MSIS and MSIK clocks range with MSISRANGE[3:0] and MSIKRANGE[3:0]. Write 0 has no effect.\r After exiting Standby or Shutdown mode, or after a reset, this bit is at 0 and the MSIS and MSIK ranges are provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR.",
7537 ),
7538 bit_offset: BitOffset::Regular(
7539 RegularBitOffset {
7540 offset: 23,
7541 },
7542 ),
7543 bit_size: 1,
7544 array: None,
7545 enumm: Some(
7546 "Msirgsel",
7547 ),
7548 },
7549 Field {
7550 name: "msikrange",
7551 description: Some(
7552 "MSIK clock ranges\r These bits are configured by software to choose the frequency range of MSIK oscillator when MSIRGSEL is set. 16 frequency ranges are available:\r Note: MSIKRANGE can be modified when MSIK is OFF (MSISON = 0) or when MSIK is ready (MSIKRDY\u{a0}=\u{a0}1). MSIKRANGE must NOT be modified when MSIK is ON and NOT ready (MSIKON = 1 and MSIKRDY = 0)\r MSIKRANGE is kept when the device wakes up from Stop mode, except when the MSIK range is above 24 MHz. In this case MSIKRANGE is changed by hardware into Range 2 (24 MHz).",
7553 ),
7554 bit_offset: BitOffset::Regular(
7555 RegularBitOffset {
7556 offset: 24,
7557 },
7558 ),
7559 bit_size: 4,
7560 array: None,
7561 enumm: Some(
7562 "Msirange",
7563 ),
7564 },
7565 Field {
7566 name: "msisrange",
7567 description: Some(
7568 "MSIS clock ranges\r These bits are configured by software to choose the frequency range of MSIS oscillator when MSIRGSEL is set. 16 frequency ranges are available:\r Note: MSISRANGE can be modified when MSIS is OFF (MSISON = 0) or when MSIS is ready (MSISRDY\u{a0}=\u{a0}1). MSISRANGE must NOT be modified when MSIS is ON and NOT ready (MSISON\u{a0}=\u{a0}1 and MSISRDY\u{a0}=\u{a0}0)\r MSISRANGE is kept when the device wakes up from Stop mode, except when the MSIS range is above 24 MHz. In this case MSISRANGE is changed by hardware into Range 2 (24 MHz).",
7569 ),
7570 bit_offset: BitOffset::Regular(
7571 RegularBitOffset {
7572 offset: 28,
7573 },
7574 ),
7575 bit_size: 4,
7576 array: None,
7577 enumm: Some(
7578 "Msirange",
7579 ),
7580 },
7581 ],
7582 },
7583 FieldSet {
7584 name: "Icscr2",
7585 extends: None,
7586 description: Some(
7587 "RCC internal clock sources calibration register 2",
7588 ),
7589 bit_size: 32,
7590 fields: &[
7591 Field {
7592 name: "msitrim3",
7593 description: Some(
7594 "MSI clock trimming for ranges 12 to 15\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC3[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI.",
7595 ),
7596 bit_offset: BitOffset::Regular(
7597 RegularBitOffset {
7598 offset: 0,
7599 },
7600 ),
7601 bit_size: 5,
7602 array: None,
7603 enumm: None,
7604 },
7605 Field {
7606 name: "msitrim2",
7607 description: Some(
7608 "MSI clock trimming for ranges 8 to 11\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC2[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI.",
7609 ),
7610 bit_offset: BitOffset::Regular(
7611 RegularBitOffset {
7612 offset: 5,
7613 },
7614 ),
7615 bit_size: 5,
7616 array: None,
7617 enumm: None,
7618 },
7619 Field {
7620 name: "msitrim1",
7621 description: Some(
7622 "MSI clock trimming for ranges 4 to 7\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC1[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI.",
7623 ),
7624 bit_offset: BitOffset::Regular(
7625 RegularBitOffset {
7626 offset: 10,
7627 },
7628 ),
7629 bit_size: 5,
7630 array: None,
7631 enumm: None,
7632 },
7633 Field {
7634 name: "msitrim0",
7635 description: Some(
7636 "MSI clock trimming for ranges 0 to 3\r These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC0[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI.",
7637 ),
7638 bit_offset: BitOffset::Regular(
7639 RegularBitOffset {
7640 offset: 15,
7641 },
7642 ),
7643 bit_size: 5,
7644 array: None,
7645 enumm: None,
7646 },
7647 ],
7648 },
7649 FieldSet {
7650 name: "Icscr3",
7651 extends: None,
7652 description: Some(
7653 "RCC internal clock sources calibration register 3",
7654 ),
7655 bit_size: 32,
7656 fields: &[
7657 Field {
7658 name: "hsical",
7659 description: Some(
7660 "HSI clock calibration\r These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value.",
7661 ),
7662 bit_offset: BitOffset::Regular(
7663 RegularBitOffset {
7664 offset: 0,
7665 },
7666 ),
7667 bit_size: 12,
7668 array: None,
7669 enumm: None,
7670 },
7671 Field {
7672 name: "hsitrim",
7673 description: Some(
7674 "HSI clock trimming\r These bits provide an additional user-programmable trimming value that is added to the HSICAL[11:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI.",
7675 ),
7676 bit_offset: BitOffset::Regular(
7677 RegularBitOffset {
7678 offset: 16,
7679 },
7680 ),
7681 bit_size: 5,
7682 array: None,
7683 enumm: None,
7684 },
7685 ],
7686 },
7687 FieldSet {
7688 name: "Pll1cfgr",
7689 extends: None,
7690 description: Some(
7691 "RCC PLL configuration register",
7692 ),
7693 bit_size: 32,
7694 fields: &[
7695 Field {
7696 name: "pllsrc",
7697 description: Some(
7698 "PLL entry clock source\r Set and cleared by software to select PLL clock source. These bits can be written only when the PLL is disabled.\r In order to save power, when no PLL is used, the value of PLLSRC must be 0.",
7699 ),
7700 bit_offset: BitOffset::Regular(
7701 RegularBitOffset {
7702 offset: 0,
7703 },
7704 ),
7705 bit_size: 2,
7706 array: None,
7707 enumm: Some(
7708 "Pllsrc",
7709 ),
7710 },
7711 Field {
7712 name: "pllrge",
7713 description: Some(
7714 "PLL input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL.\r This bit must be written before enabling the PLL.\r 00-01-10: PLL input (ref1_ck) clock range frequency between 4 and 8 MHz",
7715 ),
7716 bit_offset: BitOffset::Regular(
7717 RegularBitOffset {
7718 offset: 2,
7719 },
7720 ),
7721 bit_size: 2,
7722 array: None,
7723 enumm: Some(
7724 "Pllrge",
7725 ),
7726 },
7727 Field {
7728 name: "pllfracen",
7729 description: Some(
7730 "PLL fractional latch enable\r Set and reset by software to latch the content of PLLFRACN into the ΣΠmodulator.\r In order to latch the PLLFRACN value into the ΣΠmodulator, PLLFRACEN must be set\u{a0}to\u{a0}0, then set to 1: the transition 0 to 1 transfers the content of PLLFRACN into the modulator (see for details).",
7731 ),
7732 bit_offset: BitOffset::Regular(
7733 RegularBitOffset {
7734 offset: 4,
7735 },
7736 ),
7737 bit_size: 1,
7738 array: None,
7739 enumm: None,
7740 },
7741 Field {
7742 name: "pllm",
7743 description: Some(
7744 "Prescaler for PLL\r Set and cleared by software to configure the prescaler of the PLL. The VCO1 input frequency is PLL input clock frequency/PLLM.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0).\r ...",
7745 ),
7746 bit_offset: BitOffset::Regular(
7747 RegularBitOffset {
7748 offset: 8,
7749 },
7750 ),
7751 bit_size: 4,
7752 array: None,
7753 enumm: Some(
7754 "Pllm",
7755 ),
7756 },
7757 Field {
7758 name: "pllmboost",
7759 description: Some(
7760 "Prescaler for EPOD booster input clock\r Set and cleared by software to configure the prescaler of the PLL, used for the EPOD booster. The EPOD booster input frequency is PLL input clock frequency/PLLMBOOST.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0) and EPOD Boost mode is disabled (see ).\r others: reserved",
7761 ),
7762 bit_offset: BitOffset::Regular(
7763 RegularBitOffset {
7764 offset: 12,
7765 },
7766 ),
7767 bit_size: 4,
7768 array: None,
7769 enumm: Some(
7770 "Pllmboost",
7771 ),
7772 },
7773 Field {
7774 name: "pllpen",
7775 description: Some(
7776 "PLL DIVP divider output enable\r Set and reset by software to enable the PLL_p_ck output of the PLL.\r To save power, PLLPEN and PLLP bits must be set to 0 when the PLL_p_ck is not used.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0).",
7777 ),
7778 bit_offset: BitOffset::Regular(
7779 RegularBitOffset {
7780 offset: 16,
7781 },
7782 ),
7783 bit_size: 1,
7784 array: None,
7785 enumm: None,
7786 },
7787 Field {
7788 name: "pllqen",
7789 description: Some(
7790 "PLL DIVQ divider output enable\r Set and reset by software to enable the PLL_q_ck output of the PLL.\r To save power, PLLQEN and PLLQ bits must be set to 0 when the PLL_q_ck is not used.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0).",
7791 ),
7792 bit_offset: BitOffset::Regular(
7793 RegularBitOffset {
7794 offset: 17,
7795 },
7796 ),
7797 bit_size: 1,
7798 array: None,
7799 enumm: None,
7800 },
7801 Field {
7802 name: "pllren",
7803 description: Some(
7804 "PLL DIVR divider output enable\r Set and reset by software to enable the PLL_r_ck output of the PLL.\r To save power, PLLRENPLL2REN and PLLR bits must be set to 0 when the PLL_r_ck is not used.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0).",
7805 ),
7806 bit_offset: BitOffset::Regular(
7807 RegularBitOffset {
7808 offset: 18,
7809 },
7810 ),
7811 bit_size: 1,
7812 array: None,
7813 enumm: None,
7814 },
7815 ],
7816 },
7817 FieldSet {
7818 name: "Pll23cfgr",
7819 extends: None,
7820 description: Some(
7821 "RCC PLL configuration register",
7822 ),
7823 bit_size: 32,
7824 fields: &[
7825 Field {
7826 name: "pllsrc",
7827 description: Some(
7828 "PLL entry clock source\r Set and cleared by software to select PLL clock source. These bits can be written only when the PLL is disabled.\r In order to save power, when no PLL is used, the value of PLLSRC must be 0.",
7829 ),
7830 bit_offset: BitOffset::Regular(
7831 RegularBitOffset {
7832 offset: 0,
7833 },
7834 ),
7835 bit_size: 2,
7836 array: None,
7837 enumm: Some(
7838 "Pllsrc",
7839 ),
7840 },
7841 Field {
7842 name: "pllrge",
7843 description: Some(
7844 "PLL input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL.\r This bit must be written before enabling the PLL.\r 00-01-10: PLL input (ref1_ck) clock range frequency between 4 and 8 MHz",
7845 ),
7846 bit_offset: BitOffset::Regular(
7847 RegularBitOffset {
7848 offset: 2,
7849 },
7850 ),
7851 bit_size: 2,
7852 array: None,
7853 enumm: Some(
7854 "Pllrge",
7855 ),
7856 },
7857 Field {
7858 name: "pllfracen",
7859 description: Some(
7860 "PLL fractional latch enable\r Set and reset by software to latch the content of PLLFRACN into the ΣΠmodulator.\r In order to latch the PLLFRACN value into the ΣΠmodulator, PLLFRACEN must be set\u{a0}to\u{a0}0, then set to 1: the transition 0 to 1 transfers the content of PLLFRACN into the modulator (see for details).",
7861 ),
7862 bit_offset: BitOffset::Regular(
7863 RegularBitOffset {
7864 offset: 4,
7865 },
7866 ),
7867 bit_size: 1,
7868 array: None,
7869 enumm: None,
7870 },
7871 Field {
7872 name: "pllm",
7873 description: Some(
7874 "Prescaler for PLL\r Set and cleared by software to configure the prescaler of the PLL. The VCO1 input frequency is PLL input clock frequency/PLLM.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0).\r ...",
7875 ),
7876 bit_offset: BitOffset::Regular(
7877 RegularBitOffset {
7878 offset: 8,
7879 },
7880 ),
7881 bit_size: 4,
7882 array: None,
7883 enumm: Some(
7884 "Pllm",
7885 ),
7886 },
7887 Field {
7888 name: "pllpen",
7889 description: Some(
7890 "PLL DIVP divider output enable\r Set and reset by software to enable the PLL_p_ck output of the PLL.\r To save power, PLLPEN and PLLP bits must be set to 0 when the PLL_p_ck is not used.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0).",
7891 ),
7892 bit_offset: BitOffset::Regular(
7893 RegularBitOffset {
7894 offset: 16,
7895 },
7896 ),
7897 bit_size: 1,
7898 array: None,
7899 enumm: None,
7900 },
7901 Field {
7902 name: "pllqen",
7903 description: Some(
7904 "PLL DIVQ divider output enable\r Set and reset by software to enable the PLL_q_ck output of the PLL.\r To save power, PLLQEN and PLLQ bits must be set to 0 when the PLL_q_ck is not used.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0).",
7905 ),
7906 bit_offset: BitOffset::Regular(
7907 RegularBitOffset {
7908 offset: 17,
7909 },
7910 ),
7911 bit_size: 1,
7912 array: None,
7913 enumm: None,
7914 },
7915 Field {
7916 name: "pllren",
7917 description: Some(
7918 "PLL DIVR divider output enable\r Set and reset by software to enable the PLL_r_ck output of the PLL.\r To save power, PLLRENPLL2REN and PLLR bits must be set to 0 when the PLL_r_ck is not used.\r This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0).",
7919 ),
7920 bit_offset: BitOffset::Regular(
7921 RegularBitOffset {
7922 offset: 18,
7923 },
7924 ),
7925 bit_size: 1,
7926 array: None,
7927 enumm: None,
7928 },
7929 ],
7930 },
7931 FieldSet {
7932 name: "Plldivr",
7933 extends: None,
7934 description: Some(
7935 "RCC PLL1 dividers register",
7936 ),
7937 bit_size: 32,
7938 fields: &[
7939 Field {
7940 name: "plln",
7941 description: Some(
7942 "Multiplication factor for PLL1 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ...\r ...\r Others: reserved\r VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded into PLL1FRACN, with:\r PLL1N between 4 and 512\r input frequency Fref1_ck between 4 and 16\u{a0}MHz",
7943 ),
7944 bit_offset: BitOffset::Regular(
7945 RegularBitOffset {
7946 offset: 0,
7947 },
7948 ),
7949 bit_size: 9,
7950 array: None,
7951 enumm: Some(
7952 "Plln",
7953 ),
7954 },
7955 Field {
7956 name: "pllp",
7957 description: Some(
7958 "PLL1 DIVP division factor\r Set and reset by software to control the frequency of the pll1_p_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r Note that odd division factors are not allowed.\r ...",
7959 ),
7960 bit_offset: BitOffset::Regular(
7961 RegularBitOffset {
7962 offset: 9,
7963 },
7964 ),
7965 bit_size: 7,
7966 array: None,
7967 enumm: Some(
7968 "Plldiv",
7969 ),
7970 },
7971 Field {
7972 name: "pllq",
7973 description: Some(
7974 "PLL1 DIVQ division factor\r Set and reset by software to control the frequency of the pll1_q_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ...",
7975 ),
7976 bit_offset: BitOffset::Regular(
7977 RegularBitOffset {
7978 offset: 16,
7979 },
7980 ),
7981 bit_size: 7,
7982 array: None,
7983 enumm: Some(
7984 "Plldiv",
7985 ),
7986 },
7987 Field {
7988 name: "pllr",
7989 description: Some(
7990 "PLL1 DIVR division factor\r Set and reset by software to control the frequency of the pll1_r_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ...",
7991 ),
7992 bit_offset: BitOffset::Regular(
7993 RegularBitOffset {
7994 offset: 24,
7995 },
7996 ),
7997 bit_size: 7,
7998 array: None,
7999 enumm: Some(
8000 "Plldiv",
8001 ),
8002 },
8003 ],
8004 },
8005 FieldSet {
8006 name: "Pllfracr",
8007 extends: None,
8008 description: Some(
8009 "RCC PLL1 fractional divider register",
8010 ),
8011 bit_size: 32,
8012 fields: &[
8013 Field {
8014 name: "pllfracn",
8015 description: Some(
8016 "Fractional part of the multiplication factor for PLL1 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.\r VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with:\r PLL1N must be between 4 and 512.\r PLL1FRACN can be between 0 and 213- 1.\r The input frequency Fref1_ck must be between 4 and 16 MHz.\r To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r Set the bit PLL1FRACEN to 0.\r Write the new fractional value into PLL1FRACN.\r Set the bit PLL1FRACEN to 1.",
8017 ),
8018 bit_offset: BitOffset::Regular(
8019 RegularBitOffset {
8020 offset: 3,
8021 },
8022 ),
8023 bit_size: 13,
8024 array: None,
8025 enumm: None,
8026 },
8027 ],
8028 },
8029 FieldSet {
8030 name: "Privcfgr",
8031 extends: None,
8032 description: Some(
8033 "RCC privilege configuration register",
8034 ),
8035 bit_size: 32,
8036 fields: &[
8037 Field {
8038 name: "spriv",
8039 description: Some(
8040 "RCC secure functions privilege configuration\r Set and reset by software. This bit can be written only by a secure privileged access.",
8041 ),
8042 bit_offset: BitOffset::Regular(
8043 RegularBitOffset {
8044 offset: 0,
8045 },
8046 ),
8047 bit_size: 1,
8048 array: None,
8049 enumm: None,
8050 },
8051 Field {
8052 name: "nspriv",
8053 description: Some(
8054 "RCC non-secure functions privilege configuration\r Set and reset by software. This bit can be written only by privileged access, secure or non-secure.",
8055 ),
8056 bit_offset: BitOffset::Regular(
8057 RegularBitOffset {
8058 offset: 1,
8059 },
8060 ),
8061 bit_size: 1,
8062 array: None,
8063 enumm: None,
8064 },
8065 ],
8066 },
8067 FieldSet {
8068 name: "Seccfgr",
8069 extends: None,
8070 description: Some(
8071 "RCC secure configuration register",
8072 ),
8073 bit_size: 32,
8074 fields: &[
8075 Field {
8076 name: "hsisec",
8077 description: Some(
8078 "HSI clock configuration and status bits security\r Set and reset by software.",
8079 ),
8080 bit_offset: BitOffset::Regular(
8081 RegularBitOffset {
8082 offset: 0,
8083 },
8084 ),
8085 bit_size: 1,
8086 array: None,
8087 enumm: Some(
8088 "Security",
8089 ),
8090 },
8091 Field {
8092 name: "hsesec",
8093 description: Some(
8094 "HSE clock configuration bits, status bits and HSE_CSS security\r Set and reset by software.",
8095 ),
8096 bit_offset: BitOffset::Regular(
8097 RegularBitOffset {
8098 offset: 1,
8099 },
8100 ),
8101 bit_size: 1,
8102 array: None,
8103 enumm: Some(
8104 "Security",
8105 ),
8106 },
8107 Field {
8108 name: "msisec",
8109 description: Some(
8110 "MSI clock configuration and status bits security\r Set and reset by software.",
8111 ),
8112 bit_offset: BitOffset::Regular(
8113 RegularBitOffset {
8114 offset: 2,
8115 },
8116 ),
8117 bit_size: 1,
8118 array: None,
8119 enumm: Some(
8120 "Security",
8121 ),
8122 },
8123 Field {
8124 name: "lsisec",
8125 description: Some(
8126 "LSI clock configuration and status bits security\r Set and reset by software.",
8127 ),
8128 bit_offset: BitOffset::Regular(
8129 RegularBitOffset {
8130 offset: 3,
8131 },
8132 ),
8133 bit_size: 1,
8134 array: None,
8135 enumm: Some(
8136 "Security",
8137 ),
8138 },
8139 Field {
8140 name: "lsesec",
8141 description: Some(
8142 "LSE clock configuration and status bits security\r Set and reset by software.",
8143 ),
8144 bit_offset: BitOffset::Regular(
8145 RegularBitOffset {
8146 offset: 4,
8147 },
8148 ),
8149 bit_size: 1,
8150 array: None,
8151 enumm: Some(
8152 "Security",
8153 ),
8154 },
8155 Field {
8156 name: "sysclksec",
8157 description: Some(
8158 "SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security\r Set and reset by software.",
8159 ),
8160 bit_offset: BitOffset::Regular(
8161 RegularBitOffset {
8162 offset: 5,
8163 },
8164 ),
8165 bit_size: 1,
8166 array: None,
8167 enumm: Some(
8168 "Security",
8169 ),
8170 },
8171 Field {
8172 name: "prescsec",
8173 description: Some(
8174 "AHBx/APBx prescaler configuration bits security\r Set and reset by software.",
8175 ),
8176 bit_offset: BitOffset::Regular(
8177 RegularBitOffset {
8178 offset: 6,
8179 },
8180 ),
8181 bit_size: 1,
8182 array: None,
8183 enumm: Some(
8184 "Security",
8185 ),
8186 },
8187 Field {
8188 name: "pllsec",
8189 description: Some(
8190 "PLL1 clock configuration and status bits security\r Set and reset by software.",
8191 ),
8192 bit_offset: BitOffset::Regular(
8193 RegularBitOffset {
8194 offset: 7,
8195 },
8196 ),
8197 bit_size: 1,
8198 array: Some(
8199 Array::Regular(
8200 RegularArray {
8201 len: 3,
8202 stride: 1,
8203 },
8204 ),
8205 ),
8206 enumm: Some(
8207 "Security",
8208 ),
8209 },
8210 Field {
8211 name: "iclksec",
8212 description: Some(
8213 "intermediate clock source selection security\r Set and reset by software.",
8214 ),
8215 bit_offset: BitOffset::Regular(
8216 RegularBitOffset {
8217 offset: 10,
8218 },
8219 ),
8220 bit_size: 1,
8221 array: None,
8222 enumm: Some(
8223 "Security",
8224 ),
8225 },
8226 Field {
8227 name: "hsi48sec",
8228 description: Some(
8229 "HSI48 clock configuration and status bits security\r Set and reset by software.",
8230 ),
8231 bit_offset: BitOffset::Regular(
8232 RegularBitOffset {
8233 offset: 11,
8234 },
8235 ),
8236 bit_size: 1,
8237 array: None,
8238 enumm: Some(
8239 "Security",
8240 ),
8241 },
8242 Field {
8243 name: "rmvfsec",
8244 description: Some(
8245 "Remove reset flag security\r Set and reset by software.",
8246 ),
8247 bit_offset: BitOffset::Regular(
8248 RegularBitOffset {
8249 offset: 12,
8250 },
8251 ),
8252 bit_size: 1,
8253 array: None,
8254 enumm: Some(
8255 "Security",
8256 ),
8257 },
8258 ],
8259 },
8260 FieldSet {
8261 name: "Srdamr",
8262 extends: None,
8263 description: Some(
8264 "RCC SmartRun domain peripheral autonomous mode register",
8265 ),
8266 bit_size: 32,
8267 fields: &[
8268 Field {
8269 name: "spi3amen",
8270 description: Some(
8271 "SPI3 autonomous mode enable in Stop 0,1, 2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
8272 ),
8273 bit_offset: BitOffset::Regular(
8274 RegularBitOffset {
8275 offset: 5,
8276 },
8277 ),
8278 bit_size: 1,
8279 array: None,
8280 enumm: None,
8281 },
8282 Field {
8283 name: "lpuart1amen",
8284 description: Some(
8285 "LPUART1 autonomous mode enable in Stop 0,1, 2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
8286 ),
8287 bit_offset: BitOffset::Regular(
8288 RegularBitOffset {
8289 offset: 6,
8290 },
8291 ),
8292 bit_size: 1,
8293 array: None,
8294 enumm: None,
8295 },
8296 Field {
8297 name: "i2c3amen",
8298 description: Some(
8299 "I2C3 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
8300 ),
8301 bit_offset: BitOffset::Regular(
8302 RegularBitOffset {
8303 offset: 7,
8304 },
8305 ),
8306 bit_size: 1,
8307 array: None,
8308 enumm: None,
8309 },
8310 Field {
8311 name: "lptim1amen",
8312 description: Some(
8313 "LPTIM1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
8314 ),
8315 bit_offset: BitOffset::Regular(
8316 RegularBitOffset {
8317 offset: 11,
8318 },
8319 ),
8320 bit_size: 1,
8321 array: None,
8322 enumm: None,
8323 },
8324 Field {
8325 name: "lptim3amen",
8326 description: Some(
8327 "LPTIM3 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
8328 ),
8329 bit_offset: BitOffset::Regular(
8330 RegularBitOffset {
8331 offset: 12,
8332 },
8333 ),
8334 bit_size: 1,
8335 array: None,
8336 enumm: None,
8337 },
8338 Field {
8339 name: "lptim4amen",
8340 description: Some(
8341 "LPTIM4 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
8342 ),
8343 bit_offset: BitOffset::Regular(
8344 RegularBitOffset {
8345 offset: 13,
8346 },
8347 ),
8348 bit_size: 1,
8349 array: None,
8350 enumm: None,
8351 },
8352 Field {
8353 name: "opampamen",
8354 description: Some(
8355 "OPAMP autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.",
8356 ),
8357 bit_offset: BitOffset::Regular(
8358 RegularBitOffset {
8359 offset: 14,
8360 },
8361 ),
8362 bit_size: 1,
8363 array: None,
8364 enumm: None,
8365 },
8366 Field {
8367 name: "compamen",
8368 description: Some(
8369 "COMP autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.",
8370 ),
8371 bit_offset: BitOffset::Regular(
8372 RegularBitOffset {
8373 offset: 15,
8374 },
8375 ),
8376 bit_size: 1,
8377 array: None,
8378 enumm: None,
8379 },
8380 Field {
8381 name: "vrefamen",
8382 description: Some(
8383 "VREFBUF autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.",
8384 ),
8385 bit_offset: BitOffset::Regular(
8386 RegularBitOffset {
8387 offset: 20,
8388 },
8389 ),
8390 bit_size: 1,
8391 array: None,
8392 enumm: None,
8393 },
8394 Field {
8395 name: "rtcapbamen",
8396 description: Some(
8397 "RTC and TAMP autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
8398 ),
8399 bit_offset: BitOffset::Regular(
8400 RegularBitOffset {
8401 offset: 21,
8402 },
8403 ),
8404 bit_size: 1,
8405 array: None,
8406 enumm: None,
8407 },
8408 Field {
8409 name: "adc4amen",
8410 description: Some(
8411 "ADC4 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
8412 ),
8413 bit_offset: BitOffset::Regular(
8414 RegularBitOffset {
8415 offset: 25,
8416 },
8417 ),
8418 bit_size: 1,
8419 array: None,
8420 enumm: None,
8421 },
8422 Field {
8423 name: "lpgpio1amen",
8424 description: Some(
8425 "LPGPIO1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.",
8426 ),
8427 bit_offset: BitOffset::Regular(
8428 RegularBitOffset {
8429 offset: 26,
8430 },
8431 ),
8432 bit_size: 1,
8433 array: None,
8434 enumm: None,
8435 },
8436 Field {
8437 name: "dac1amen",
8438 description: Some(
8439 "DAC1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
8440 ),
8441 bit_offset: BitOffset::Regular(
8442 RegularBitOffset {
8443 offset: 27,
8444 },
8445 ),
8446 bit_size: 1,
8447 array: None,
8448 enumm: None,
8449 },
8450 Field {
8451 name: "lpdma1amen",
8452 description: Some(
8453 "LPDMA1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
8454 ),
8455 bit_offset: BitOffset::Regular(
8456 RegularBitOffset {
8457 offset: 28,
8458 },
8459 ),
8460 bit_size: 1,
8461 array: None,
8462 enumm: None,
8463 },
8464 Field {
8465 name: "adf1amen",
8466 description: Some(
8467 "ADF1 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.",
8468 ),
8469 bit_offset: BitOffset::Regular(
8470 RegularBitOffset {
8471 offset: 29,
8472 },
8473 ),
8474 bit_size: 1,
8475 array: None,
8476 enumm: None,
8477 },
8478 Field {
8479 name: "sram4amen",
8480 description: Some(
8481 "SRAM4 autonomous mode enable in Stop 0,1,2 mode\r Set and cleared by software.",
8482 ),
8483 bit_offset: BitOffset::Regular(
8484 RegularBitOffset {
8485 offset: 31,
8486 },
8487 ),
8488 bit_size: 1,
8489 array: None,
8490 enumm: None,
8491 },
8492 ],
8493 },
8494 ],
8495 enums: &[
8496 Enum {
8497 name: "Adcdacsel",
8498 description: None,
8499 bit_size: 3,
8500 variants: &[
8501 EnumVariant {
8502 name: "HCLK1",
8503 description: Some(
8504 "HCLK clock selected",
8505 ),
8506 value: 0,
8507 },
8508 EnumVariant {
8509 name: "SYS",
8510 description: Some(
8511 "SYSCLK selected",
8512 ),
8513 value: 1,
8514 },
8515 EnumVariant {
8516 name: "PLL2_R",
8517 description: Some(
8518 "PLL2 R (pll2_r_ck) selected",
8519 ),
8520 value: 2,
8521 },
8522 EnumVariant {
8523 name: "HSE",
8524 description: Some(
8525 "HSE clock selected",
8526 ),
8527 value: 3,
8528 },
8529 EnumVariant {
8530 name: "HSI",
8531 description: Some(
8532 "HSI clock selected",
8533 ),
8534 value: 4,
8535 },
8536 EnumVariant {
8537 name: "MSIK",
8538 description: Some(
8539 "MSIK clock selected",
8540 ),
8541 value: 5,
8542 },
8543 ],
8544 },
8545 Enum {
8546 name: "Adfsel",
8547 description: None,
8548 bit_size: 3,
8549 variants: &[
8550 EnumVariant {
8551 name: "HCLK3",
8552 description: Some(
8553 "HCLK selected",
8554 ),
8555 value: 0,
8556 },
8557 EnumVariant {
8558 name: "PLL1_P",
8559 description: Some(
8560 "PLL1 P (pll1_p_ck) selected",
8561 ),
8562 value: 1,
8563 },
8564 EnumVariant {
8565 name: "PLL3_Q",
8566 description: Some(
8567 "PLL3 Q (pll3_q_ck) selected",
8568 ),
8569 value: 2,
8570 },
8571 EnumVariant {
8572 name: "AUDIOCLK",
8573 description: Some(
8574 "input pin AUDIOCLK selected",
8575 ),
8576 value: 3,
8577 },
8578 EnumVariant {
8579 name: "MSIK",
8580 description: Some(
8581 "MSIK clock selected",
8582 ),
8583 value: 4,
8584 },
8585 ],
8586 },
8587 Enum {
8588 name: "Dacsel",
8589 description: None,
8590 bit_size: 1,
8591 variants: &[
8592 EnumVariant {
8593 name: "LSE",
8594 description: Some(
8595 "LSE selected",
8596 ),
8597 value: 0,
8598 },
8599 EnumVariant {
8600 name: "LSI",
8601 description: Some(
8602 "LSI selected",
8603 ),
8604 value: 1,
8605 },
8606 ],
8607 },
8608 Enum {
8609 name: "Dpre",
8610 description: None,
8611 bit_size: 3,
8612 variants: &[
8613 EnumVariant {
8614 name: "DIV1",
8615 description: Some(
8616 "DCLK not divided",
8617 ),
8618 value: 0,
8619 },
8620 EnumVariant {
8621 name: "DIV2",
8622 description: Some(
8623 "DCLK divided by 2",
8624 ),
8625 value: 4,
8626 },
8627 EnumVariant {
8628 name: "DIV4",
8629 description: Some(
8630 "DCLK divided by 4",
8631 ),
8632 value: 5,
8633 },
8634 EnumVariant {
8635 name: "DIV8",
8636 description: Some(
8637 "DCLK divided by 8",
8638 ),
8639 value: 6,
8640 },
8641 EnumVariant {
8642 name: "DIV16",
8643 description: Some(
8644 "DCLK divided by 16",
8645 ),
8646 value: 7,
8647 },
8648 ],
8649 },
8650 Enum {
8651 name: "Dsisel",
8652 description: None,
8653 bit_size: 1,
8654 variants: &[
8655 EnumVariant {
8656 name: "PLL3_P",
8657 description: Some(
8658 "PLL3 “P” (pll3_p_ck) selected",
8659 ),
8660 value: 0,
8661 },
8662 EnumVariant {
8663 name: "DSI_PHY",
8664 description: Some(
8665 "DSI PHY PLL output selected (formerly called DCLK, renamed to DSI_PHY to match other chip families)",
8666 ),
8667 value: 1,
8668 },
8669 ],
8670 },
8671 Enum {
8672 name: "Fdcansel",
8673 description: None,
8674 bit_size: 2,
8675 variants: &[
8676 EnumVariant {
8677 name: "HSE",
8678 description: Some(
8679 "HSE clock selected",
8680 ),
8681 value: 0,
8682 },
8683 EnumVariant {
8684 name: "PLL1_Q",
8685 description: Some(
8686 "PLL1 Q (pll1_q_ck) selected",
8687 ),
8688 value: 1,
8689 },
8690 EnumVariant {
8691 name: "PLL2_P",
8692 description: Some(
8693 "PLL2 P (pll2_p_ck) selected",
8694 ),
8695 value: 2,
8696 },
8697 ],
8698 },
8699 Enum {
8700 name: "Hpre",
8701 description: None,
8702 bit_size: 4,
8703 variants: &[
8704 EnumVariant {
8705 name: "DIV1",
8706 description: Some(
8707 "SYSCLK not divided",
8708 ),
8709 value: 0,
8710 },
8711 EnumVariant {
8712 name: "DIV2",
8713 description: Some(
8714 "SYSCLK divided by 2",
8715 ),
8716 value: 8,
8717 },
8718 EnumVariant {
8719 name: "DIV4",
8720 description: Some(
8721 "SYSCLK divided by 4",
8722 ),
8723 value: 9,
8724 },
8725 EnumVariant {
8726 name: "DIV8",
8727 description: Some(
8728 "SYSCLK divided by 8",
8729 ),
8730 value: 10,
8731 },
8732 EnumVariant {
8733 name: "DIV16",
8734 description: Some(
8735 "SYSCLK divided by 16",
8736 ),
8737 value: 11,
8738 },
8739 EnumVariant {
8740 name: "DIV64",
8741 description: Some(
8742 "SYSCLK divided by 64",
8743 ),
8744 value: 12,
8745 },
8746 EnumVariant {
8747 name: "DIV128",
8748 description: Some(
8749 "SYSCLK divided by 128",
8750 ),
8751 value: 13,
8752 },
8753 EnumVariant {
8754 name: "DIV256",
8755 description: Some(
8756 "SYSCLK divided by 256",
8757 ),
8758 value: 14,
8759 },
8760 EnumVariant {
8761 name: "DIV512",
8762 description: Some(
8763 "SYSCLK divided by 512",
8764 ),
8765 value: 15,
8766 },
8767 ],
8768 },
8769 Enum {
8770 name: "Hseext",
8771 description: None,
8772 bit_size: 1,
8773 variants: &[
8774 EnumVariant {
8775 name: "ANALOG",
8776 description: Some(
8777 "external HSE clock analog mode",
8778 ),
8779 value: 0,
8780 },
8781 EnumVariant {
8782 name: "DIGITAL",
8783 description: Some(
8784 "external HSE clock digital mode (through I/O Schmitt trigger)",
8785 ),
8786 value: 1,
8787 },
8788 ],
8789 },
8790 Enum {
8791 name: "Hspisel",
8792 description: None,
8793 bit_size: 2,
8794 variants: &[
8795 EnumVariant {
8796 name: "SYS",
8797 description: Some(
8798 "SYSCLK selected",
8799 ),
8800 value: 0,
8801 },
8802 EnumVariant {
8803 name: "PLL1_Q",
8804 description: Some(
8805 "PLL1 “Q” (pll1_q_ck) selected, can be up to 200 MHz",
8806 ),
8807 value: 1,
8808 },
8809 EnumVariant {
8810 name: "PLL2_Q",
8811 description: Some(
8812 "PLL2 “Q” (pll2_q_ck) selected, can be up to 200 MHz",
8813 ),
8814 value: 2,
8815 },
8816 EnumVariant {
8817 name: "PLL3_R",
8818 description: Some(
8819 "PLL3 “R” (pll3_r_ck) selected, can be up to 200 MHz",
8820 ),
8821 value: 3,
8822 },
8823 ],
8824 },
8825 Enum {
8826 name: "I2c3sel",
8827 description: None,
8828 bit_size: 2,
8829 variants: &[
8830 EnumVariant {
8831 name: "PCLK3",
8832 description: Some(
8833 "PCLK3 selected",
8834 ),
8835 value: 0,
8836 },
8837 EnumVariant {
8838 name: "SYS",
8839 description: Some(
8840 "SYSCLK selected",
8841 ),
8842 value: 1,
8843 },
8844 EnumVariant {
8845 name: "HSI",
8846 description: Some(
8847 "HSI selected",
8848 ),
8849 value: 2,
8850 },
8851 EnumVariant {
8852 name: "MSIK",
8853 description: Some(
8854 "MSIK selected",
8855 ),
8856 value: 3,
8857 },
8858 ],
8859 },
8860 Enum {
8861 name: "I2csel",
8862 description: None,
8863 bit_size: 2,
8864 variants: &[
8865 EnumVariant {
8866 name: "PCLK1",
8867 description: Some(
8868 "PCLK1 selected",
8869 ),
8870 value: 0,
8871 },
8872 EnumVariant {
8873 name: "SYS",
8874 description: Some(
8875 "SYSCLK selected",
8876 ),
8877 value: 1,
8878 },
8879 EnumVariant {
8880 name: "HSI",
8881 description: Some(
8882 "HSI selected",
8883 ),
8884 value: 2,
8885 },
8886 EnumVariant {
8887 name: "MSIK",
8888 description: Some(
8889 "MSIK selected",
8890 ),
8891 value: 3,
8892 },
8893 ],
8894 },
8895 Enum {
8896 name: "Iclksel",
8897 description: None,
8898 bit_size: 2,
8899 variants: &[
8900 EnumVariant {
8901 name: "HSI48",
8902 description: Some(
8903 "HSI48 clock selected",
8904 ),
8905 value: 0,
8906 },
8907 EnumVariant {
8908 name: "PLL2_Q",
8909 description: Some(
8910 "PLL2 Q (pll2_q_ck) selected",
8911 ),
8912 value: 1,
8913 },
8914 EnumVariant {
8915 name: "PLL1_Q",
8916 description: Some(
8917 "PLL1 Q (pll1_q_ck) selected",
8918 ),
8919 value: 2,
8920 },
8921 EnumVariant {
8922 name: "MSIK",
8923 description: Some(
8924 "MSIK clock selected",
8925 ),
8926 value: 3,
8927 },
8928 ],
8929 },
8930 Enum {
8931 name: "Lptim2sel",
8932 description: None,
8933 bit_size: 2,
8934 variants: &[
8935 EnumVariant {
8936 name: "PCLK1",
8937 description: Some(
8938 "PCLK1 selected",
8939 ),
8940 value: 0,
8941 },
8942 EnumVariant {
8943 name: "LSI",
8944 description: Some(
8945 "LSI selected",
8946 ),
8947 value: 1,
8948 },
8949 EnumVariant {
8950 name: "HSI",
8951 description: Some(
8952 "HSI selected",
8953 ),
8954 value: 2,
8955 },
8956 EnumVariant {
8957 name: "LSE",
8958 description: Some(
8959 "LSE selected",
8960 ),
8961 value: 3,
8962 },
8963 ],
8964 },
8965 Enum {
8966 name: "Lptimsel",
8967 description: None,
8968 bit_size: 2,
8969 variants: &[
8970 EnumVariant {
8971 name: "MSIK",
8972 description: Some(
8973 "MSIK selected",
8974 ),
8975 value: 0,
8976 },
8977 EnumVariant {
8978 name: "LSI",
8979 description: Some(
8980 "LSI selected",
8981 ),
8982 value: 1,
8983 },
8984 EnumVariant {
8985 name: "HSI",
8986 description: Some(
8987 "HSI selected",
8988 ),
8989 value: 2,
8990 },
8991 EnumVariant {
8992 name: "LSE",
8993 description: Some(
8994 "LSE selected",
8995 ),
8996 value: 3,
8997 },
8998 ],
8999 },
9000 Enum {
9001 name: "Lpusartsel",
9002 description: None,
9003 bit_size: 3,
9004 variants: &[
9005 EnumVariant {
9006 name: "PCLK3",
9007 description: Some(
9008 "PCLK3 selected",
9009 ),
9010 value: 0,
9011 },
9012 EnumVariant {
9013 name: "SYS",
9014 description: Some(
9015 "SYSCLK selected",
9016 ),
9017 value: 1,
9018 },
9019 EnumVariant {
9020 name: "HSI",
9021 description: Some(
9022 "HSI selected",
9023 ),
9024 value: 2,
9025 },
9026 EnumVariant {
9027 name: "LSE",
9028 description: Some(
9029 "LSE selected",
9030 ),
9031 value: 3,
9032 },
9033 EnumVariant {
9034 name: "MSIK",
9035 description: Some(
9036 "MSIK selected",
9037 ),
9038 value: 4,
9039 },
9040 ],
9041 },
9042 Enum {
9043 name: "Lscosel",
9044 description: None,
9045 bit_size: 1,
9046 variants: &[
9047 EnumVariant {
9048 name: "LSI",
9049 description: Some(
9050 "LSI clock selected",
9051 ),
9052 value: 0,
9053 },
9054 EnumVariant {
9055 name: "LSE",
9056 description: Some(
9057 "LSE clock selected",
9058 ),
9059 value: 1,
9060 },
9061 ],
9062 },
9063 Enum {
9064 name: "Lsedrv",
9065 description: None,
9066 bit_size: 2,
9067 variants: &[
9068 EnumVariant {
9069 name: "LOW",
9070 description: Some(
9071 "Low driving capability",
9072 ),
9073 value: 0,
9074 },
9075 EnumVariant {
9076 name: "MEDIUM_LOW",
9077 description: Some(
9078 "Medium low driving capability",
9079 ),
9080 value: 1,
9081 },
9082 EnumVariant {
9083 name: "MEDIUM_HIGH",
9084 description: Some(
9085 "Medium high driving capability",
9086 ),
9087 value: 2,
9088 },
9089 EnumVariant {
9090 name: "HIGH",
9091 description: Some(
9092 "High driving capability",
9093 ),
9094 value: 3,
9095 },
9096 ],
9097 },
9098 Enum {
9099 name: "Lsiprediv",
9100 description: None,
9101 bit_size: 1,
9102 variants: &[
9103 EnumVariant {
9104 name: "DIV1",
9105 description: Some(
9106 "LSI not divided",
9107 ),
9108 value: 0,
9109 },
9110 EnumVariant {
9111 name: "DIV128",
9112 description: Some(
9113 "LSI divided by 128",
9114 ),
9115 value: 1,
9116 },
9117 ],
9118 },
9119 Enum {
9120 name: "Ltdcsel",
9121 description: None,
9122 bit_size: 1,
9123 variants: &[
9124 EnumVariant {
9125 name: "PLL3_R",
9126 description: Some(
9127 "PLL3 “R” (pll3_r_ck) selected",
9128 ),
9129 value: 0,
9130 },
9131 EnumVariant {
9132 name: "PLL2_R",
9133 description: Some(
9134 "PLL2 “R” (pll2_r_ck) selected",
9135 ),
9136 value: 1,
9137 },
9138 ],
9139 },
9140 Enum {
9141 name: "Mcopre",
9142 description: None,
9143 bit_size: 3,
9144 variants: &[
9145 EnumVariant {
9146 name: "DIV1",
9147 description: Some(
9148 "MCO divided by 1",
9149 ),
9150 value: 0,
9151 },
9152 EnumVariant {
9153 name: "DIV2",
9154 description: Some(
9155 "MCO divided by 2",
9156 ),
9157 value: 1,
9158 },
9159 EnumVariant {
9160 name: "DIV4",
9161 description: Some(
9162 "MCO divided by 4",
9163 ),
9164 value: 2,
9165 },
9166 EnumVariant {
9167 name: "DIV8",
9168 description: Some(
9169 "MCO divided by 8",
9170 ),
9171 value: 3,
9172 },
9173 EnumVariant {
9174 name: "DIV16",
9175 description: Some(
9176 "MCO divided by 16",
9177 ),
9178 value: 4,
9179 },
9180 ],
9181 },
9182 Enum {
9183 name: "Mcosel",
9184 description: None,
9185 bit_size: 4,
9186 variants: &[
9187 EnumVariant {
9188 name: "DISABLE",
9189 description: Some(
9190 "MCO output disabled, no clock on MCO",
9191 ),
9192 value: 0,
9193 },
9194 EnumVariant {
9195 name: "SYS",
9196 description: Some(
9197 "SYSCLK system clock selected",
9198 ),
9199 value: 1,
9200 },
9201 EnumVariant {
9202 name: "MSIS",
9203 description: Some(
9204 "MSIS clock selected",
9205 ),
9206 value: 2,
9207 },
9208 EnumVariant {
9209 name: "HSI",
9210 description: Some(
9211 "HSI clock selected",
9212 ),
9213 value: 3,
9214 },
9215 EnumVariant {
9216 name: "HSE",
9217 description: Some(
9218 "HSE clock selected",
9219 ),
9220 value: 4,
9221 },
9222 EnumVariant {
9223 name: "PLL1_R",
9224 description: Some(
9225 "Main PLL clock pll1_r_ck selected",
9226 ),
9227 value: 5,
9228 },
9229 EnumVariant {
9230 name: "LSI",
9231 description: Some(
9232 "LSI clock selected",
9233 ),
9234 value: 6,
9235 },
9236 EnumVariant {
9237 name: "LSE",
9238 description: Some(
9239 "LSE clock selected",
9240 ),
9241 value: 7,
9242 },
9243 EnumVariant {
9244 name: "HSI48",
9245 description: Some(
9246 "Internal HSI48 clock selected",
9247 ),
9248 value: 8,
9249 },
9250 EnumVariant {
9251 name: "MSIK",
9252 description: Some(
9253 "MSIK clock selected",
9254 ),
9255 value: 9,
9256 },
9257 ],
9258 },
9259 Enum {
9260 name: "Mdfsel",
9261 description: None,
9262 bit_size: 3,
9263 variants: &[
9264 EnumVariant {
9265 name: "HCLK1",
9266 description: Some(
9267 "HCLK selected",
9268 ),
9269 value: 0,
9270 },
9271 EnumVariant {
9272 name: "PLL1_P",
9273 description: Some(
9274 "PLL1 P (pll1_p_ck) selected",
9275 ),
9276 value: 1,
9277 },
9278 EnumVariant {
9279 name: "PLL3_Q",
9280 description: Some(
9281 "PLL3 Q (pll3_q_ck) selected",
9282 ),
9283 value: 2,
9284 },
9285 EnumVariant {
9286 name: "AUDIOCLK",
9287 description: Some(
9288 "input pin AUDIOCLK selected",
9289 ),
9290 value: 3,
9291 },
9292 EnumVariant {
9293 name: "MSIK",
9294 description: Some(
9295 "MSIK clock selected",
9296 ),
9297 value: 4,
9298 },
9299 ],
9300 },
9301 Enum {
9302 name: "Msibias",
9303 description: None,
9304 bit_size: 1,
9305 variants: &[
9306 EnumVariant {
9307 name: "CONTINUOUS",
9308 description: Some(
9309 "MSI bias continuous mode (clock accuracy fast settling time)",
9310 ),
9311 value: 0,
9312 },
9313 EnumVariant {
9314 name: "SAMPLING",
9315 description: Some(
9316 "MSI bias sampling mode (ultra-low-power mode)",
9317 ),
9318 value: 1,
9319 },
9320 ],
9321 },
9322 Enum {
9323 name: "Msipllfast",
9324 description: None,
9325 bit_size: 1,
9326 variants: &[
9327 EnumVariant {
9328 name: "NORMAL",
9329 description: Some(
9330 "MSI PLL normal start-up",
9331 ),
9332 value: 0,
9333 },
9334 EnumVariant {
9335 name: "FAST",
9336 description: Some(
9337 "MSI PLL fast start-up",
9338 ),
9339 value: 1,
9340 },
9341 ],
9342 },
9343 Enum {
9344 name: "Msipllsel",
9345 description: None,
9346 bit_size: 1,
9347 variants: &[
9348 EnumVariant {
9349 name: "MSIK",
9350 description: Some(
9351 "PLL mode applied to MSIK (MSI kernel) clock output",
9352 ),
9353 value: 0,
9354 },
9355 EnumVariant {
9356 name: "MSIS",
9357 description: Some(
9358 "PLL mode applied to MSIS (MSI system) clock output",
9359 ),
9360 value: 1,
9361 },
9362 ],
9363 },
9364 Enum {
9365 name: "Msirange",
9366 description: None,
9367 bit_size: 4,
9368 variants: &[
9369 EnumVariant {
9370 name: "RANGE_48MHZ",
9371 description: Some(
9372 "range 0 around 48 MHz",
9373 ),
9374 value: 0,
9375 },
9376 EnumVariant {
9377 name: "RANGE_24MHZ",
9378 description: Some(
9379 "range 1 around 24 MHz",
9380 ),
9381 value: 1,
9382 },
9383 EnumVariant {
9384 name: "RANGE_16MHZ",
9385 description: Some(
9386 "range 2 around 16 MHz",
9387 ),
9388 value: 2,
9389 },
9390 EnumVariant {
9391 name: "RANGE_12MHZ",
9392 description: Some(
9393 "range 3 around 12 MHz",
9394 ),
9395 value: 3,
9396 },
9397 EnumVariant {
9398 name: "RANGE_4MHZ",
9399 description: Some(
9400 "range 4 around 4 MHz (reset value)",
9401 ),
9402 value: 4,
9403 },
9404 EnumVariant {
9405 name: "RANGE_2MHZ",
9406 description: Some(
9407 "range 5 around 2 MHz",
9408 ),
9409 value: 5,
9410 },
9411 EnumVariant {
9412 name: "RANGE_1_33MHZ",
9413 description: Some(
9414 "range 6 around 1.33 MHz",
9415 ),
9416 value: 6,
9417 },
9418 EnumVariant {
9419 name: "RANGE_1MHZ",
9420 description: Some(
9421 "range 7 around 1 MHz",
9422 ),
9423 value: 7,
9424 },
9425 EnumVariant {
9426 name: "RANGE_3_072MHZ",
9427 description: Some(
9428 "range 8 around 3.072 MHz",
9429 ),
9430 value: 8,
9431 },
9432 EnumVariant {
9433 name: "RANGE_1_536MHZ",
9434 description: Some(
9435 "range 9 around 1.536 MHz",
9436 ),
9437 value: 9,
9438 },
9439 EnumVariant {
9440 name: "RANGE_1_024MHZ",
9441 description: Some(
9442 "range 10 around 1.024 MHz",
9443 ),
9444 value: 10,
9445 },
9446 EnumVariant {
9447 name: "RANGE_768KHZ",
9448 description: Some(
9449 "range 11 around 768 kHz",
9450 ),
9451 value: 11,
9452 },
9453 EnumVariant {
9454 name: "RANGE_400KHZ",
9455 description: Some(
9456 "range 12 around 400 kHz",
9457 ),
9458 value: 12,
9459 },
9460 EnumVariant {
9461 name: "RANGE_200KHZ",
9462 description: Some(
9463 "range 13 around 200 kHz",
9464 ),
9465 value: 13,
9466 },
9467 EnumVariant {
9468 name: "RANGE_133KHZ",
9469 description: Some(
9470 "range 14 around 133 kHz",
9471 ),
9472 value: 14,
9473 },
9474 EnumVariant {
9475 name: "RANGE_100KHZ",
9476 description: Some(
9477 "range 15 around 100 kHz",
9478 ),
9479 value: 15,
9480 },
9481 ],
9482 },
9483 Enum {
9484 name: "Msirgsel",
9485 description: None,
9486 bit_size: 1,
9487 variants: &[
9488 EnumVariant {
9489 name: "CSR",
9490 description: Some(
9491 "MSIS/MSIK ranges provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR",
9492 ),
9493 value: 0,
9494 },
9495 EnumVariant {
9496 name: "ICSCR1",
9497 description: Some(
9498 "MSIS/MSIK ranges provided by MSISRANGE[3:0] and MSIKRANGE[3:0] in RCC_ICSCR1",
9499 ),
9500 value: 1,
9501 },
9502 ],
9503 },
9504 Enum {
9505 name: "Msixsrange",
9506 description: None,
9507 bit_size: 4,
9508 variants: &[
9509 EnumVariant {
9510 name: "RANGE_4MHZ",
9511 description: Some(
9512 "range 4 around 4M Hz (reset value)",
9513 ),
9514 value: 4,
9515 },
9516 EnumVariant {
9517 name: "RANGE_2MHZ",
9518 description: Some(
9519 "range 5 around 2 MHz",
9520 ),
9521 value: 5,
9522 },
9523 EnumVariant {
9524 name: "RANGE_1_5MHZ",
9525 description: Some(
9526 "range 6 around 1.5 MHz",
9527 ),
9528 value: 6,
9529 },
9530 EnumVariant {
9531 name: "RANGE_1MHZ",
9532 description: Some(
9533 "range 7 around 1 MHz",
9534 ),
9535 value: 7,
9536 },
9537 EnumVariant {
9538 name: "RANGE_3_072MHZ",
9539 description: Some(
9540 "range 8 around 3.072 MHz",
9541 ),
9542 value: 8,
9543 },
9544 ],
9545 },
9546 Enum {
9547 name: "Octospisel",
9548 description: None,
9549 bit_size: 2,
9550 variants: &[
9551 EnumVariant {
9552 name: "SYS",
9553 description: Some(
9554 "SYSCLK selected",
9555 ),
9556 value: 0,
9557 },
9558 EnumVariant {
9559 name: "MSIK",
9560 description: Some(
9561 "MSIK selected",
9562 ),
9563 value: 1,
9564 },
9565 EnumVariant {
9566 name: "PLL1_Q",
9567 description: Some(
9568 "PLL1 Q (pll1_q_ck) selected, can be up to 200 MHz",
9569 ),
9570 value: 2,
9571 },
9572 EnumVariant {
9573 name: "PLL2_Q",
9574 description: Some(
9575 "PLL2 Q (pll2_q_ck) selected, can be up to 200 MHz",
9576 ),
9577 value: 3,
9578 },
9579 ],
9580 },
9581 Enum {
9582 name: "Otghssel",
9583 description: None,
9584 bit_size: 2,
9585 variants: &[
9586 EnumVariant {
9587 name: "HSE",
9588 description: Some(
9589 "HSE selected",
9590 ),
9591 value: 0,
9592 },
9593 EnumVariant {
9594 name: "PLL1_P",
9595 description: Some(
9596 "PLL1 “P” (pll1_q_ck) selected,",
9597 ),
9598 value: 1,
9599 },
9600 EnumVariant {
9601 name: "HSE_DIV_2",
9602 description: Some(
9603 "HSE/2 selected",
9604 ),
9605 value: 2,
9606 },
9607 EnumVariant {
9608 name: "PLL1_P_DIV_2",
9609 description: Some(
9610 "PLL1 “P” divided by 2 (pll1_p_ck/2) selected",
9611 ),
9612 value: 3,
9613 },
9614 ],
9615 },
9616 Enum {
9617 name: "Plldiv",
9618 description: None,
9619 bit_size: 7,
9620 variants: &[
9621 EnumVariant {
9622 name: "DIV1",
9623 description: None,
9624 value: 0,
9625 },
9626 EnumVariant {
9627 name: "DIV2",
9628 description: None,
9629 value: 1,
9630 },
9631 EnumVariant {
9632 name: "DIV3",
9633 description: None,
9634 value: 2,
9635 },
9636 EnumVariant {
9637 name: "DIV4",
9638 description: None,
9639 value: 3,
9640 },
9641 EnumVariant {
9642 name: "DIV5",
9643 description: None,
9644 value: 4,
9645 },
9646 EnumVariant {
9647 name: "DIV6",
9648 description: None,
9649 value: 5,
9650 },
9651 EnumVariant {
9652 name: "DIV7",
9653 description: None,
9654 value: 6,
9655 },
9656 EnumVariant {
9657 name: "DIV8",
9658 description: None,
9659 value: 7,
9660 },
9661 EnumVariant {
9662 name: "DIV9",
9663 description: None,
9664 value: 8,
9665 },
9666 EnumVariant {
9667 name: "DIV10",
9668 description: None,
9669 value: 9,
9670 },
9671 EnumVariant {
9672 name: "DIV11",
9673 description: None,
9674 value: 10,
9675 },
9676 EnumVariant {
9677 name: "DIV12",
9678 description: None,
9679 value: 11,
9680 },
9681 EnumVariant {
9682 name: "DIV13",
9683 description: None,
9684 value: 12,
9685 },
9686 EnumVariant {
9687 name: "DIV14",
9688 description: None,
9689 value: 13,
9690 },
9691 EnumVariant {
9692 name: "DIV15",
9693 description: None,
9694 value: 14,
9695 },
9696 EnumVariant {
9697 name: "DIV16",
9698 description: None,
9699 value: 15,
9700 },
9701 EnumVariant {
9702 name: "DIV17",
9703 description: None,
9704 value: 16,
9705 },
9706 EnumVariant {
9707 name: "DIV18",
9708 description: None,
9709 value: 17,
9710 },
9711 EnumVariant {
9712 name: "DIV19",
9713 description: None,
9714 value: 18,
9715 },
9716 EnumVariant {
9717 name: "DIV20",
9718 description: None,
9719 value: 19,
9720 },
9721 EnumVariant {
9722 name: "DIV21",
9723 description: None,
9724 value: 20,
9725 },
9726 EnumVariant {
9727 name: "DIV22",
9728 description: None,
9729 value: 21,
9730 },
9731 EnumVariant {
9732 name: "DIV23",
9733 description: None,
9734 value: 22,
9735 },
9736 EnumVariant {
9737 name: "DIV24",
9738 description: None,
9739 value: 23,
9740 },
9741 EnumVariant {
9742 name: "DIV25",
9743 description: None,
9744 value: 24,
9745 },
9746 EnumVariant {
9747 name: "DIV26",
9748 description: None,
9749 value: 25,
9750 },
9751 EnumVariant {
9752 name: "DIV27",
9753 description: None,
9754 value: 26,
9755 },
9756 EnumVariant {
9757 name: "DIV28",
9758 description: None,
9759 value: 27,
9760 },
9761 EnumVariant {
9762 name: "DIV29",
9763 description: None,
9764 value: 28,
9765 },
9766 EnumVariant {
9767 name: "DIV30",
9768 description: None,
9769 value: 29,
9770 },
9771 EnumVariant {
9772 name: "DIV31",
9773 description: None,
9774 value: 30,
9775 },
9776 EnumVariant {
9777 name: "DIV32",
9778 description: None,
9779 value: 31,
9780 },
9781 EnumVariant {
9782 name: "DIV33",
9783 description: None,
9784 value: 32,
9785 },
9786 EnumVariant {
9787 name: "DIV34",
9788 description: None,
9789 value: 33,
9790 },
9791 EnumVariant {
9792 name: "DIV35",
9793 description: None,
9794 value: 34,
9795 },
9796 EnumVariant {
9797 name: "DIV36",
9798 description: None,
9799 value: 35,
9800 },
9801 EnumVariant {
9802 name: "DIV37",
9803 description: None,
9804 value: 36,
9805 },
9806 EnumVariant {
9807 name: "DIV38",
9808 description: None,
9809 value: 37,
9810 },
9811 EnumVariant {
9812 name: "DIV39",
9813 description: None,
9814 value: 38,
9815 },
9816 EnumVariant {
9817 name: "DIV40",
9818 description: None,
9819 value: 39,
9820 },
9821 EnumVariant {
9822 name: "DIV41",
9823 description: None,
9824 value: 40,
9825 },
9826 EnumVariant {
9827 name: "DIV42",
9828 description: None,
9829 value: 41,
9830 },
9831 EnumVariant {
9832 name: "DIV43",
9833 description: None,
9834 value: 42,
9835 },
9836 EnumVariant {
9837 name: "DIV44",
9838 description: None,
9839 value: 43,
9840 },
9841 EnumVariant {
9842 name: "DIV45",
9843 description: None,
9844 value: 44,
9845 },
9846 EnumVariant {
9847 name: "DIV46",
9848 description: None,
9849 value: 45,
9850 },
9851 EnumVariant {
9852 name: "DIV47",
9853 description: None,
9854 value: 46,
9855 },
9856 EnumVariant {
9857 name: "DIV48",
9858 description: None,
9859 value: 47,
9860 },
9861 EnumVariant {
9862 name: "DIV49",
9863 description: None,
9864 value: 48,
9865 },
9866 EnumVariant {
9867 name: "DIV50",
9868 description: None,
9869 value: 49,
9870 },
9871 EnumVariant {
9872 name: "DIV51",
9873 description: None,
9874 value: 50,
9875 },
9876 EnumVariant {
9877 name: "DIV52",
9878 description: None,
9879 value: 51,
9880 },
9881 EnumVariant {
9882 name: "DIV53",
9883 description: None,
9884 value: 52,
9885 },
9886 EnumVariant {
9887 name: "DIV54",
9888 description: None,
9889 value: 53,
9890 },
9891 EnumVariant {
9892 name: "DIV55",
9893 description: None,
9894 value: 54,
9895 },
9896 EnumVariant {
9897 name: "DIV56",
9898 description: None,
9899 value: 55,
9900 },
9901 EnumVariant {
9902 name: "DIV57",
9903 description: None,
9904 value: 56,
9905 },
9906 EnumVariant {
9907 name: "DIV58",
9908 description: None,
9909 value: 57,
9910 },
9911 EnumVariant {
9912 name: "DIV59",
9913 description: None,
9914 value: 58,
9915 },
9916 EnumVariant {
9917 name: "DIV60",
9918 description: None,
9919 value: 59,
9920 },
9921 EnumVariant {
9922 name: "DIV61",
9923 description: None,
9924 value: 60,
9925 },
9926 EnumVariant {
9927 name: "DIV62",
9928 description: None,
9929 value: 61,
9930 },
9931 EnumVariant {
9932 name: "DIV63",
9933 description: None,
9934 value: 62,
9935 },
9936 EnumVariant {
9937 name: "DIV64",
9938 description: None,
9939 value: 63,
9940 },
9941 EnumVariant {
9942 name: "DIV65",
9943 description: None,
9944 value: 64,
9945 },
9946 EnumVariant {
9947 name: "DIV66",
9948 description: None,
9949 value: 65,
9950 },
9951 EnumVariant {
9952 name: "DIV67",
9953 description: None,
9954 value: 66,
9955 },
9956 EnumVariant {
9957 name: "DIV68",
9958 description: None,
9959 value: 67,
9960 },
9961 EnumVariant {
9962 name: "DIV69",
9963 description: None,
9964 value: 68,
9965 },
9966 EnumVariant {
9967 name: "DIV70",
9968 description: None,
9969 value: 69,
9970 },
9971 EnumVariant {
9972 name: "DIV71",
9973 description: None,
9974 value: 70,
9975 },
9976 EnumVariant {
9977 name: "DIV72",
9978 description: None,
9979 value: 71,
9980 },
9981 EnumVariant {
9982 name: "DIV73",
9983 description: None,
9984 value: 72,
9985 },
9986 EnumVariant {
9987 name: "DIV74",
9988 description: None,
9989 value: 73,
9990 },
9991 EnumVariant {
9992 name: "DIV75",
9993 description: None,
9994 value: 74,
9995 },
9996 EnumVariant {
9997 name: "DIV76",
9998 description: None,
9999 value: 75,
10000 },
10001 EnumVariant {
10002 name: "DIV77",
10003 description: None,
10004 value: 76,
10005 },
10006 EnumVariant {
10007 name: "DIV78",
10008 description: None,
10009 value: 77,
10010 },
10011 EnumVariant {
10012 name: "DIV79",
10013 description: None,
10014 value: 78,
10015 },
10016 EnumVariant {
10017 name: "DIV80",
10018 description: None,
10019 value: 79,
10020 },
10021 EnumVariant {
10022 name: "DIV81",
10023 description: None,
10024 value: 80,
10025 },
10026 EnumVariant {
10027 name: "DIV82",
10028 description: None,
10029 value: 81,
10030 },
10031 EnumVariant {
10032 name: "DIV83",
10033 description: None,
10034 value: 82,
10035 },
10036 EnumVariant {
10037 name: "DIV84",
10038 description: None,
10039 value: 83,
10040 },
10041 EnumVariant {
10042 name: "DIV85",
10043 description: None,
10044 value: 84,
10045 },
10046 EnumVariant {
10047 name: "DIV86",
10048 description: None,
10049 value: 85,
10050 },
10051 EnumVariant {
10052 name: "DIV87",
10053 description: None,
10054 value: 86,
10055 },
10056 EnumVariant {
10057 name: "DIV88",
10058 description: None,
10059 value: 87,
10060 },
10061 EnumVariant {
10062 name: "DIV89",
10063 description: None,
10064 value: 88,
10065 },
10066 EnumVariant {
10067 name: "DIV90",
10068 description: None,
10069 value: 89,
10070 },
10071 EnumVariant {
10072 name: "DIV91",
10073 description: None,
10074 value: 90,
10075 },
10076 EnumVariant {
10077 name: "DIV92",
10078 description: None,
10079 value: 91,
10080 },
10081 EnumVariant {
10082 name: "DIV93",
10083 description: None,
10084 value: 92,
10085 },
10086 EnumVariant {
10087 name: "DIV94",
10088 description: None,
10089 value: 93,
10090 },
10091 EnumVariant {
10092 name: "DIV95",
10093 description: None,
10094 value: 94,
10095 },
10096 EnumVariant {
10097 name: "DIV96",
10098 description: None,
10099 value: 95,
10100 },
10101 EnumVariant {
10102 name: "DIV97",
10103 description: None,
10104 value: 96,
10105 },
10106 EnumVariant {
10107 name: "DIV98",
10108 description: None,
10109 value: 97,
10110 },
10111 EnumVariant {
10112 name: "DIV99",
10113 description: None,
10114 value: 98,
10115 },
10116 EnumVariant {
10117 name: "DIV100",
10118 description: None,
10119 value: 99,
10120 },
10121 EnumVariant {
10122 name: "DIV101",
10123 description: None,
10124 value: 100,
10125 },
10126 EnumVariant {
10127 name: "DIV102",
10128 description: None,
10129 value: 101,
10130 },
10131 EnumVariant {
10132 name: "DIV103",
10133 description: None,
10134 value: 102,
10135 },
10136 EnumVariant {
10137 name: "DIV104",
10138 description: None,
10139 value: 103,
10140 },
10141 EnumVariant {
10142 name: "DIV105",
10143 description: None,
10144 value: 104,
10145 },
10146 EnumVariant {
10147 name: "DIV106",
10148 description: None,
10149 value: 105,
10150 },
10151 EnumVariant {
10152 name: "DIV107",
10153 description: None,
10154 value: 106,
10155 },
10156 EnumVariant {
10157 name: "DIV108",
10158 description: None,
10159 value: 107,
10160 },
10161 EnumVariant {
10162 name: "DIV109",
10163 description: None,
10164 value: 108,
10165 },
10166 EnumVariant {
10167 name: "DIV110",
10168 description: None,
10169 value: 109,
10170 },
10171 EnumVariant {
10172 name: "DIV111",
10173 description: None,
10174 value: 110,
10175 },
10176 EnumVariant {
10177 name: "DIV112",
10178 description: None,
10179 value: 111,
10180 },
10181 EnumVariant {
10182 name: "DIV113",
10183 description: None,
10184 value: 112,
10185 },
10186 EnumVariant {
10187 name: "DIV114",
10188 description: None,
10189 value: 113,
10190 },
10191 EnumVariant {
10192 name: "DIV115",
10193 description: None,
10194 value: 114,
10195 },
10196 EnumVariant {
10197 name: "DIV116",
10198 description: None,
10199 value: 115,
10200 },
10201 EnumVariant {
10202 name: "DIV117",
10203 description: None,
10204 value: 116,
10205 },
10206 EnumVariant {
10207 name: "DIV118",
10208 description: None,
10209 value: 117,
10210 },
10211 EnumVariant {
10212 name: "DIV119",
10213 description: None,
10214 value: 118,
10215 },
10216 EnumVariant {
10217 name: "DIV120",
10218 description: None,
10219 value: 119,
10220 },
10221 EnumVariant {
10222 name: "DIV121",
10223 description: None,
10224 value: 120,
10225 },
10226 EnumVariant {
10227 name: "DIV122",
10228 description: None,
10229 value: 121,
10230 },
10231 EnumVariant {
10232 name: "DIV123",
10233 description: None,
10234 value: 122,
10235 },
10236 EnumVariant {
10237 name: "DIV124",
10238 description: None,
10239 value: 123,
10240 },
10241 EnumVariant {
10242 name: "DIV125",
10243 description: None,
10244 value: 124,
10245 },
10246 EnumVariant {
10247 name: "DIV126",
10248 description: None,
10249 value: 125,
10250 },
10251 EnumVariant {
10252 name: "DIV127",
10253 description: None,
10254 value: 126,
10255 },
10256 EnumVariant {
10257 name: "DIV128",
10258 description: None,
10259 value: 127,
10260 },
10261 ],
10262 },
10263 Enum {
10264 name: "Pllm",
10265 description: None,
10266 bit_size: 4,
10267 variants: &[
10268 EnumVariant {
10269 name: "DIV1",
10270 description: None,
10271 value: 0,
10272 },
10273 EnumVariant {
10274 name: "DIV2",
10275 description: None,
10276 value: 1,
10277 },
10278 EnumVariant {
10279 name: "DIV3",
10280 description: None,
10281 value: 2,
10282 },
10283 EnumVariant {
10284 name: "DIV4",
10285 description: None,
10286 value: 3,
10287 },
10288 EnumVariant {
10289 name: "DIV5",
10290 description: None,
10291 value: 4,
10292 },
10293 EnumVariant {
10294 name: "DIV6",
10295 description: None,
10296 value: 5,
10297 },
10298 EnumVariant {
10299 name: "DIV7",
10300 description: None,
10301 value: 6,
10302 },
10303 EnumVariant {
10304 name: "DIV8",
10305 description: None,
10306 value: 7,
10307 },
10308 EnumVariant {
10309 name: "DIV9",
10310 description: None,
10311 value: 8,
10312 },
10313 EnumVariant {
10314 name: "DIV10",
10315 description: None,
10316 value: 9,
10317 },
10318 EnumVariant {
10319 name: "DIV11",
10320 description: None,
10321 value: 10,
10322 },
10323 EnumVariant {
10324 name: "DIV12",
10325 description: None,
10326 value: 11,
10327 },
10328 EnumVariant {
10329 name: "DIV13",
10330 description: None,
10331 value: 12,
10332 },
10333 EnumVariant {
10334 name: "DIV14",
10335 description: None,
10336 value: 13,
10337 },
10338 EnumVariant {
10339 name: "DIV15",
10340 description: None,
10341 value: 14,
10342 },
10343 EnumVariant {
10344 name: "DIV16",
10345 description: None,
10346 value: 15,
10347 },
10348 ],
10349 },
10350 Enum {
10351 name: "Pllmboost",
10352 description: None,
10353 bit_size: 4,
10354 variants: &[
10355 EnumVariant {
10356 name: "DIV1",
10357 description: Some(
10358 "division by 1 (bypass)",
10359 ),
10360 value: 0,
10361 },
10362 EnumVariant {
10363 name: "DIV2",
10364 description: Some(
10365 "division by 2",
10366 ),
10367 value: 1,
10368 },
10369 EnumVariant {
10370 name: "DIV4",
10371 description: Some(
10372 "division by 4",
10373 ),
10374 value: 2,
10375 },
10376 EnumVariant {
10377 name: "DIV6",
10378 description: Some(
10379 "division by 6",
10380 ),
10381 value: 3,
10382 },
10383 EnumVariant {
10384 name: "DIV8",
10385 description: Some(
10386 "division by 8",
10387 ),
10388 value: 4,
10389 },
10390 EnumVariant {
10391 name: "DIV10",
10392 description: Some(
10393 "division by 10",
10394 ),
10395 value: 5,
10396 },
10397 EnumVariant {
10398 name: "DIV12",
10399 description: Some(
10400 "division by 12",
10401 ),
10402 value: 6,
10403 },
10404 EnumVariant {
10405 name: "DIV14",
10406 description: Some(
10407 "division by 14",
10408 ),
10409 value: 7,
10410 },
10411 EnumVariant {
10412 name: "DIV16",
10413 description: Some(
10414 "division by 16",
10415 ),
10416 value: 8,
10417 },
10418 ],
10419 },
10420 Enum {
10421 name: "Plln",
10422 description: None,
10423 bit_size: 9,
10424 variants: &[
10425 EnumVariant {
10426 name: "MUL4",
10427 description: None,
10428 value: 3,
10429 },
10430 EnumVariant {
10431 name: "MUL5",
10432 description: None,
10433 value: 4,
10434 },
10435 EnumVariant {
10436 name: "MUL6",
10437 description: None,
10438 value: 5,
10439 },
10440 EnumVariant {
10441 name: "MUL7",
10442 description: None,
10443 value: 6,
10444 },
10445 EnumVariant {
10446 name: "MUL8",
10447 description: None,
10448 value: 7,
10449 },
10450 EnumVariant {
10451 name: "MUL9",
10452 description: None,
10453 value: 8,
10454 },
10455 EnumVariant {
10456 name: "MUL10",
10457 description: None,
10458 value: 9,
10459 },
10460 EnumVariant {
10461 name: "MUL11",
10462 description: None,
10463 value: 10,
10464 },
10465 EnumVariant {
10466 name: "MUL12",
10467 description: None,
10468 value: 11,
10469 },
10470 EnumVariant {
10471 name: "MUL13",
10472 description: None,
10473 value: 12,
10474 },
10475 EnumVariant {
10476 name: "MUL14",
10477 description: None,
10478 value: 13,
10479 },
10480 EnumVariant {
10481 name: "MUL15",
10482 description: None,
10483 value: 14,
10484 },
10485 EnumVariant {
10486 name: "MUL16",
10487 description: None,
10488 value: 15,
10489 },
10490 EnumVariant {
10491 name: "MUL17",
10492 description: None,
10493 value: 16,
10494 },
10495 EnumVariant {
10496 name: "MUL18",
10497 description: None,
10498 value: 17,
10499 },
10500 EnumVariant {
10501 name: "MUL19",
10502 description: None,
10503 value: 18,
10504 },
10505 EnumVariant {
10506 name: "MUL20",
10507 description: None,
10508 value: 19,
10509 },
10510 EnumVariant {
10511 name: "MUL21",
10512 description: None,
10513 value: 20,
10514 },
10515 EnumVariant {
10516 name: "MUL22",
10517 description: None,
10518 value: 21,
10519 },
10520 EnumVariant {
10521 name: "MUL23",
10522 description: None,
10523 value: 22,
10524 },
10525 EnumVariant {
10526 name: "MUL24",
10527 description: None,
10528 value: 23,
10529 },
10530 EnumVariant {
10531 name: "MUL25",
10532 description: None,
10533 value: 24,
10534 },
10535 EnumVariant {
10536 name: "MUL26",
10537 description: None,
10538 value: 25,
10539 },
10540 EnumVariant {
10541 name: "MUL27",
10542 description: None,
10543 value: 26,
10544 },
10545 EnumVariant {
10546 name: "MUL28",
10547 description: None,
10548 value: 27,
10549 },
10550 EnumVariant {
10551 name: "MUL29",
10552 description: None,
10553 value: 28,
10554 },
10555 EnumVariant {
10556 name: "MUL30",
10557 description: None,
10558 value: 29,
10559 },
10560 EnumVariant {
10561 name: "MUL31",
10562 description: None,
10563 value: 30,
10564 },
10565 EnumVariant {
10566 name: "MUL32",
10567 description: None,
10568 value: 31,
10569 },
10570 EnumVariant {
10571 name: "MUL33",
10572 description: None,
10573 value: 32,
10574 },
10575 EnumVariant {
10576 name: "MUL34",
10577 description: None,
10578 value: 33,
10579 },
10580 EnumVariant {
10581 name: "MUL35",
10582 description: None,
10583 value: 34,
10584 },
10585 EnumVariant {
10586 name: "MUL36",
10587 description: None,
10588 value: 35,
10589 },
10590 EnumVariant {
10591 name: "MUL37",
10592 description: None,
10593 value: 36,
10594 },
10595 EnumVariant {
10596 name: "MUL38",
10597 description: None,
10598 value: 37,
10599 },
10600 EnumVariant {
10601 name: "MUL39",
10602 description: None,
10603 value: 38,
10604 },
10605 EnumVariant {
10606 name: "MUL40",
10607 description: None,
10608 value: 39,
10609 },
10610 EnumVariant {
10611 name: "MUL41",
10612 description: None,
10613 value: 40,
10614 },
10615 EnumVariant {
10616 name: "MUL42",
10617 description: None,
10618 value: 41,
10619 },
10620 EnumVariant {
10621 name: "MUL43",
10622 description: None,
10623 value: 42,
10624 },
10625 EnumVariant {
10626 name: "MUL44",
10627 description: None,
10628 value: 43,
10629 },
10630 EnumVariant {
10631 name: "MUL45",
10632 description: None,
10633 value: 44,
10634 },
10635 EnumVariant {
10636 name: "MUL46",
10637 description: None,
10638 value: 45,
10639 },
10640 EnumVariant {
10641 name: "MUL47",
10642 description: None,
10643 value: 46,
10644 },
10645 EnumVariant {
10646 name: "MUL48",
10647 description: None,
10648 value: 47,
10649 },
10650 EnumVariant {
10651 name: "MUL49",
10652 description: None,
10653 value: 48,
10654 },
10655 EnumVariant {
10656 name: "MUL50",
10657 description: None,
10658 value: 49,
10659 },
10660 EnumVariant {
10661 name: "MUL51",
10662 description: None,
10663 value: 50,
10664 },
10665 EnumVariant {
10666 name: "MUL52",
10667 description: None,
10668 value: 51,
10669 },
10670 EnumVariant {
10671 name: "MUL53",
10672 description: None,
10673 value: 52,
10674 },
10675 EnumVariant {
10676 name: "MUL54",
10677 description: None,
10678 value: 53,
10679 },
10680 EnumVariant {
10681 name: "MUL55",
10682 description: None,
10683 value: 54,
10684 },
10685 EnumVariant {
10686 name: "MUL56",
10687 description: None,
10688 value: 55,
10689 },
10690 EnumVariant {
10691 name: "MUL57",
10692 description: None,
10693 value: 56,
10694 },
10695 EnumVariant {
10696 name: "MUL58",
10697 description: None,
10698 value: 57,
10699 },
10700 EnumVariant {
10701 name: "MUL59",
10702 description: None,
10703 value: 58,
10704 },
10705 EnumVariant {
10706 name: "MUL60",
10707 description: None,
10708 value: 59,
10709 },
10710 EnumVariant {
10711 name: "MUL61",
10712 description: None,
10713 value: 60,
10714 },
10715 EnumVariant {
10716 name: "MUL62",
10717 description: None,
10718 value: 61,
10719 },
10720 EnumVariant {
10721 name: "MUL63",
10722 description: None,
10723 value: 62,
10724 },
10725 EnumVariant {
10726 name: "MUL64",
10727 description: None,
10728 value: 63,
10729 },
10730 EnumVariant {
10731 name: "MUL65",
10732 description: None,
10733 value: 64,
10734 },
10735 EnumVariant {
10736 name: "MUL66",
10737 description: None,
10738 value: 65,
10739 },
10740 EnumVariant {
10741 name: "MUL67",
10742 description: None,
10743 value: 66,
10744 },
10745 EnumVariant {
10746 name: "MUL68",
10747 description: None,
10748 value: 67,
10749 },
10750 EnumVariant {
10751 name: "MUL69",
10752 description: None,
10753 value: 68,
10754 },
10755 EnumVariant {
10756 name: "MUL70",
10757 description: None,
10758 value: 69,
10759 },
10760 EnumVariant {
10761 name: "MUL71",
10762 description: None,
10763 value: 70,
10764 },
10765 EnumVariant {
10766 name: "MUL72",
10767 description: None,
10768 value: 71,
10769 },
10770 EnumVariant {
10771 name: "MUL73",
10772 description: None,
10773 value: 72,
10774 },
10775 EnumVariant {
10776 name: "MUL74",
10777 description: None,
10778 value: 73,
10779 },
10780 EnumVariant {
10781 name: "MUL75",
10782 description: None,
10783 value: 74,
10784 },
10785 EnumVariant {
10786 name: "MUL76",
10787 description: None,
10788 value: 75,
10789 },
10790 EnumVariant {
10791 name: "MUL77",
10792 description: None,
10793 value: 76,
10794 },
10795 EnumVariant {
10796 name: "MUL78",
10797 description: None,
10798 value: 77,
10799 },
10800 EnumVariant {
10801 name: "MUL79",
10802 description: None,
10803 value: 78,
10804 },
10805 EnumVariant {
10806 name: "MUL80",
10807 description: None,
10808 value: 79,
10809 },
10810 EnumVariant {
10811 name: "MUL81",
10812 description: None,
10813 value: 80,
10814 },
10815 EnumVariant {
10816 name: "MUL82",
10817 description: None,
10818 value: 81,
10819 },
10820 EnumVariant {
10821 name: "MUL83",
10822 description: None,
10823 value: 82,
10824 },
10825 EnumVariant {
10826 name: "MUL84",
10827 description: None,
10828 value: 83,
10829 },
10830 EnumVariant {
10831 name: "MUL85",
10832 description: None,
10833 value: 84,
10834 },
10835 EnumVariant {
10836 name: "MUL86",
10837 description: None,
10838 value: 85,
10839 },
10840 EnumVariant {
10841 name: "MUL87",
10842 description: None,
10843 value: 86,
10844 },
10845 EnumVariant {
10846 name: "MUL88",
10847 description: None,
10848 value: 87,
10849 },
10850 EnumVariant {
10851 name: "MUL89",
10852 description: None,
10853 value: 88,
10854 },
10855 EnumVariant {
10856 name: "MUL90",
10857 description: None,
10858 value: 89,
10859 },
10860 EnumVariant {
10861 name: "MUL91",
10862 description: None,
10863 value: 90,
10864 },
10865 EnumVariant {
10866 name: "MUL92",
10867 description: None,
10868 value: 91,
10869 },
10870 EnumVariant {
10871 name: "MUL93",
10872 description: None,
10873 value: 92,
10874 },
10875 EnumVariant {
10876 name: "MUL94",
10877 description: None,
10878 value: 93,
10879 },
10880 EnumVariant {
10881 name: "MUL95",
10882 description: None,
10883 value: 94,
10884 },
10885 EnumVariant {
10886 name: "MUL96",
10887 description: None,
10888 value: 95,
10889 },
10890 EnumVariant {
10891 name: "MUL97",
10892 description: None,
10893 value: 96,
10894 },
10895 EnumVariant {
10896 name: "MUL98",
10897 description: None,
10898 value: 97,
10899 },
10900 EnumVariant {
10901 name: "MUL99",
10902 description: None,
10903 value: 98,
10904 },
10905 EnumVariant {
10906 name: "MUL100",
10907 description: None,
10908 value: 99,
10909 },
10910 EnumVariant {
10911 name: "MUL101",
10912 description: None,
10913 value: 100,
10914 },
10915 EnumVariant {
10916 name: "MUL102",
10917 description: None,
10918 value: 101,
10919 },
10920 EnumVariant {
10921 name: "MUL103",
10922 description: None,
10923 value: 102,
10924 },
10925 EnumVariant {
10926 name: "MUL104",
10927 description: None,
10928 value: 103,
10929 },
10930 EnumVariant {
10931 name: "MUL105",
10932 description: None,
10933 value: 104,
10934 },
10935 EnumVariant {
10936 name: "MUL106",
10937 description: None,
10938 value: 105,
10939 },
10940 EnumVariant {
10941 name: "MUL107",
10942 description: None,
10943 value: 106,
10944 },
10945 EnumVariant {
10946 name: "MUL108",
10947 description: None,
10948 value: 107,
10949 },
10950 EnumVariant {
10951 name: "MUL109",
10952 description: None,
10953 value: 108,
10954 },
10955 EnumVariant {
10956 name: "MUL110",
10957 description: None,
10958 value: 109,
10959 },
10960 EnumVariant {
10961 name: "MUL111",
10962 description: None,
10963 value: 110,
10964 },
10965 EnumVariant {
10966 name: "MUL112",
10967 description: None,
10968 value: 111,
10969 },
10970 EnumVariant {
10971 name: "MUL113",
10972 description: None,
10973 value: 112,
10974 },
10975 EnumVariant {
10976 name: "MUL114",
10977 description: None,
10978 value: 113,
10979 },
10980 EnumVariant {
10981 name: "MUL115",
10982 description: None,
10983 value: 114,
10984 },
10985 EnumVariant {
10986 name: "MUL116",
10987 description: None,
10988 value: 115,
10989 },
10990 EnumVariant {
10991 name: "MUL117",
10992 description: None,
10993 value: 116,
10994 },
10995 EnumVariant {
10996 name: "MUL118",
10997 description: None,
10998 value: 117,
10999 },
11000 EnumVariant {
11001 name: "MUL119",
11002 description: None,
11003 value: 118,
11004 },
11005 EnumVariant {
11006 name: "MUL120",
11007 description: None,
11008 value: 119,
11009 },
11010 EnumVariant {
11011 name: "MUL121",
11012 description: None,
11013 value: 120,
11014 },
11015 EnumVariant {
11016 name: "MUL122",
11017 description: None,
11018 value: 121,
11019 },
11020 EnumVariant {
11021 name: "MUL123",
11022 description: None,
11023 value: 122,
11024 },
11025 EnumVariant {
11026 name: "MUL124",
11027 description: None,
11028 value: 123,
11029 },
11030 EnumVariant {
11031 name: "MUL125",
11032 description: None,
11033 value: 124,
11034 },
11035 EnumVariant {
11036 name: "MUL126",
11037 description: None,
11038 value: 125,
11039 },
11040 EnumVariant {
11041 name: "MUL127",
11042 description: None,
11043 value: 126,
11044 },
11045 EnumVariant {
11046 name: "MUL128",
11047 description: None,
11048 value: 127,
11049 },
11050 EnumVariant {
11051 name: "MUL129",
11052 description: None,
11053 value: 128,
11054 },
11055 EnumVariant {
11056 name: "MUL130",
11057 description: None,
11058 value: 129,
11059 },
11060 EnumVariant {
11061 name: "MUL131",
11062 description: None,
11063 value: 130,
11064 },
11065 EnumVariant {
11066 name: "MUL132",
11067 description: None,
11068 value: 131,
11069 },
11070 EnumVariant {
11071 name: "MUL133",
11072 description: None,
11073 value: 132,
11074 },
11075 EnumVariant {
11076 name: "MUL134",
11077 description: None,
11078 value: 133,
11079 },
11080 EnumVariant {
11081 name: "MUL135",
11082 description: None,
11083 value: 134,
11084 },
11085 EnumVariant {
11086 name: "MUL136",
11087 description: None,
11088 value: 135,
11089 },
11090 EnumVariant {
11091 name: "MUL137",
11092 description: None,
11093 value: 136,
11094 },
11095 EnumVariant {
11096 name: "MUL138",
11097 description: None,
11098 value: 137,
11099 },
11100 EnumVariant {
11101 name: "MUL139",
11102 description: None,
11103 value: 138,
11104 },
11105 EnumVariant {
11106 name: "MUL140",
11107 description: None,
11108 value: 139,
11109 },
11110 EnumVariant {
11111 name: "MUL141",
11112 description: None,
11113 value: 140,
11114 },
11115 EnumVariant {
11116 name: "MUL142",
11117 description: None,
11118 value: 141,
11119 },
11120 EnumVariant {
11121 name: "MUL143",
11122 description: None,
11123 value: 142,
11124 },
11125 EnumVariant {
11126 name: "MUL144",
11127 description: None,
11128 value: 143,
11129 },
11130 EnumVariant {
11131 name: "MUL145",
11132 description: None,
11133 value: 144,
11134 },
11135 EnumVariant {
11136 name: "MUL146",
11137 description: None,
11138 value: 145,
11139 },
11140 EnumVariant {
11141 name: "MUL147",
11142 description: None,
11143 value: 146,
11144 },
11145 EnumVariant {
11146 name: "MUL148",
11147 description: None,
11148 value: 147,
11149 },
11150 EnumVariant {
11151 name: "MUL149",
11152 description: None,
11153 value: 148,
11154 },
11155 EnumVariant {
11156 name: "MUL150",
11157 description: None,
11158 value: 149,
11159 },
11160 EnumVariant {
11161 name: "MUL151",
11162 description: None,
11163 value: 150,
11164 },
11165 EnumVariant {
11166 name: "MUL152",
11167 description: None,
11168 value: 151,
11169 },
11170 EnumVariant {
11171 name: "MUL153",
11172 description: None,
11173 value: 152,
11174 },
11175 EnumVariant {
11176 name: "MUL154",
11177 description: None,
11178 value: 153,
11179 },
11180 EnumVariant {
11181 name: "MUL155",
11182 description: None,
11183 value: 154,
11184 },
11185 EnumVariant {
11186 name: "MUL156",
11187 description: None,
11188 value: 155,
11189 },
11190 EnumVariant {
11191 name: "MUL157",
11192 description: None,
11193 value: 156,
11194 },
11195 EnumVariant {
11196 name: "MUL158",
11197 description: None,
11198 value: 157,
11199 },
11200 EnumVariant {
11201 name: "MUL159",
11202 description: None,
11203 value: 158,
11204 },
11205 EnumVariant {
11206 name: "MUL160",
11207 description: None,
11208 value: 159,
11209 },
11210 EnumVariant {
11211 name: "MUL161",
11212 description: None,
11213 value: 160,
11214 },
11215 EnumVariant {
11216 name: "MUL162",
11217 description: None,
11218 value: 161,
11219 },
11220 EnumVariant {
11221 name: "MUL163",
11222 description: None,
11223 value: 162,
11224 },
11225 EnumVariant {
11226 name: "MUL164",
11227 description: None,
11228 value: 163,
11229 },
11230 EnumVariant {
11231 name: "MUL165",
11232 description: None,
11233 value: 164,
11234 },
11235 EnumVariant {
11236 name: "MUL166",
11237 description: None,
11238 value: 165,
11239 },
11240 EnumVariant {
11241 name: "MUL167",
11242 description: None,
11243 value: 166,
11244 },
11245 EnumVariant {
11246 name: "MUL168",
11247 description: None,
11248 value: 167,
11249 },
11250 EnumVariant {
11251 name: "MUL169",
11252 description: None,
11253 value: 168,
11254 },
11255 EnumVariant {
11256 name: "MUL170",
11257 description: None,
11258 value: 169,
11259 },
11260 EnumVariant {
11261 name: "MUL171",
11262 description: None,
11263 value: 170,
11264 },
11265 EnumVariant {
11266 name: "MUL172",
11267 description: None,
11268 value: 171,
11269 },
11270 EnumVariant {
11271 name: "MUL173",
11272 description: None,
11273 value: 172,
11274 },
11275 EnumVariant {
11276 name: "MUL174",
11277 description: None,
11278 value: 173,
11279 },
11280 EnumVariant {
11281 name: "MUL175",
11282 description: None,
11283 value: 174,
11284 },
11285 EnumVariant {
11286 name: "MUL176",
11287 description: None,
11288 value: 175,
11289 },
11290 EnumVariant {
11291 name: "MUL177",
11292 description: None,
11293 value: 176,
11294 },
11295 EnumVariant {
11296 name: "MUL178",
11297 description: None,
11298 value: 177,
11299 },
11300 EnumVariant {
11301 name: "MUL179",
11302 description: None,
11303 value: 178,
11304 },
11305 EnumVariant {
11306 name: "MUL180",
11307 description: None,
11308 value: 179,
11309 },
11310 EnumVariant {
11311 name: "MUL181",
11312 description: None,
11313 value: 180,
11314 },
11315 EnumVariant {
11316 name: "MUL182",
11317 description: None,
11318 value: 181,
11319 },
11320 EnumVariant {
11321 name: "MUL183",
11322 description: None,
11323 value: 182,
11324 },
11325 EnumVariant {
11326 name: "MUL184",
11327 description: None,
11328 value: 183,
11329 },
11330 EnumVariant {
11331 name: "MUL185",
11332 description: None,
11333 value: 184,
11334 },
11335 EnumVariant {
11336 name: "MUL186",
11337 description: None,
11338 value: 185,
11339 },
11340 EnumVariant {
11341 name: "MUL187",
11342 description: None,
11343 value: 186,
11344 },
11345 EnumVariant {
11346 name: "MUL188",
11347 description: None,
11348 value: 187,
11349 },
11350 EnumVariant {
11351 name: "MUL189",
11352 description: None,
11353 value: 188,
11354 },
11355 EnumVariant {
11356 name: "MUL190",
11357 description: None,
11358 value: 189,
11359 },
11360 EnumVariant {
11361 name: "MUL191",
11362 description: None,
11363 value: 190,
11364 },
11365 EnumVariant {
11366 name: "MUL192",
11367 description: None,
11368 value: 191,
11369 },
11370 EnumVariant {
11371 name: "MUL193",
11372 description: None,
11373 value: 192,
11374 },
11375 EnumVariant {
11376 name: "MUL194",
11377 description: None,
11378 value: 193,
11379 },
11380 EnumVariant {
11381 name: "MUL195",
11382 description: None,
11383 value: 194,
11384 },
11385 EnumVariant {
11386 name: "MUL196",
11387 description: None,
11388 value: 195,
11389 },
11390 EnumVariant {
11391 name: "MUL197",
11392 description: None,
11393 value: 196,
11394 },
11395 EnumVariant {
11396 name: "MUL198",
11397 description: None,
11398 value: 197,
11399 },
11400 EnumVariant {
11401 name: "MUL199",
11402 description: None,
11403 value: 198,
11404 },
11405 EnumVariant {
11406 name: "MUL200",
11407 description: None,
11408 value: 199,
11409 },
11410 EnumVariant {
11411 name: "MUL201",
11412 description: None,
11413 value: 200,
11414 },
11415 EnumVariant {
11416 name: "MUL202",
11417 description: None,
11418 value: 201,
11419 },
11420 EnumVariant {
11421 name: "MUL203",
11422 description: None,
11423 value: 202,
11424 },
11425 EnumVariant {
11426 name: "MUL204",
11427 description: None,
11428 value: 203,
11429 },
11430 EnumVariant {
11431 name: "MUL205",
11432 description: None,
11433 value: 204,
11434 },
11435 EnumVariant {
11436 name: "MUL206",
11437 description: None,
11438 value: 205,
11439 },
11440 EnumVariant {
11441 name: "MUL207",
11442 description: None,
11443 value: 206,
11444 },
11445 EnumVariant {
11446 name: "MUL208",
11447 description: None,
11448 value: 207,
11449 },
11450 EnumVariant {
11451 name: "MUL209",
11452 description: None,
11453 value: 208,
11454 },
11455 EnumVariant {
11456 name: "MUL210",
11457 description: None,
11458 value: 209,
11459 },
11460 EnumVariant {
11461 name: "MUL211",
11462 description: None,
11463 value: 210,
11464 },
11465 EnumVariant {
11466 name: "MUL212",
11467 description: None,
11468 value: 211,
11469 },
11470 EnumVariant {
11471 name: "MUL213",
11472 description: None,
11473 value: 212,
11474 },
11475 EnumVariant {
11476 name: "MUL214",
11477 description: None,
11478 value: 213,
11479 },
11480 EnumVariant {
11481 name: "MUL215",
11482 description: None,
11483 value: 214,
11484 },
11485 EnumVariant {
11486 name: "MUL216",
11487 description: None,
11488 value: 215,
11489 },
11490 EnumVariant {
11491 name: "MUL217",
11492 description: None,
11493 value: 216,
11494 },
11495 EnumVariant {
11496 name: "MUL218",
11497 description: None,
11498 value: 217,
11499 },
11500 EnumVariant {
11501 name: "MUL219",
11502 description: None,
11503 value: 218,
11504 },
11505 EnumVariant {
11506 name: "MUL220",
11507 description: None,
11508 value: 219,
11509 },
11510 EnumVariant {
11511 name: "MUL221",
11512 description: None,
11513 value: 220,
11514 },
11515 EnumVariant {
11516 name: "MUL222",
11517 description: None,
11518 value: 221,
11519 },
11520 EnumVariant {
11521 name: "MUL223",
11522 description: None,
11523 value: 222,
11524 },
11525 EnumVariant {
11526 name: "MUL224",
11527 description: None,
11528 value: 223,
11529 },
11530 EnumVariant {
11531 name: "MUL225",
11532 description: None,
11533 value: 224,
11534 },
11535 EnumVariant {
11536 name: "MUL226",
11537 description: None,
11538 value: 225,
11539 },
11540 EnumVariant {
11541 name: "MUL227",
11542 description: None,
11543 value: 226,
11544 },
11545 EnumVariant {
11546 name: "MUL228",
11547 description: None,
11548 value: 227,
11549 },
11550 EnumVariant {
11551 name: "MUL229",
11552 description: None,
11553 value: 228,
11554 },
11555 EnumVariant {
11556 name: "MUL230",
11557 description: None,
11558 value: 229,
11559 },
11560 EnumVariant {
11561 name: "MUL231",
11562 description: None,
11563 value: 230,
11564 },
11565 EnumVariant {
11566 name: "MUL232",
11567 description: None,
11568 value: 231,
11569 },
11570 EnumVariant {
11571 name: "MUL233",
11572 description: None,
11573 value: 232,
11574 },
11575 EnumVariant {
11576 name: "MUL234",
11577 description: None,
11578 value: 233,
11579 },
11580 EnumVariant {
11581 name: "MUL235",
11582 description: None,
11583 value: 234,
11584 },
11585 EnumVariant {
11586 name: "MUL236",
11587 description: None,
11588 value: 235,
11589 },
11590 EnumVariant {
11591 name: "MUL237",
11592 description: None,
11593 value: 236,
11594 },
11595 EnumVariant {
11596 name: "MUL238",
11597 description: None,
11598 value: 237,
11599 },
11600 EnumVariant {
11601 name: "MUL239",
11602 description: None,
11603 value: 238,
11604 },
11605 EnumVariant {
11606 name: "MUL240",
11607 description: None,
11608 value: 239,
11609 },
11610 EnumVariant {
11611 name: "MUL241",
11612 description: None,
11613 value: 240,
11614 },
11615 EnumVariant {
11616 name: "MUL242",
11617 description: None,
11618 value: 241,
11619 },
11620 EnumVariant {
11621 name: "MUL243",
11622 description: None,
11623 value: 242,
11624 },
11625 EnumVariant {
11626 name: "MUL244",
11627 description: None,
11628 value: 243,
11629 },
11630 EnumVariant {
11631 name: "MUL245",
11632 description: None,
11633 value: 244,
11634 },
11635 EnumVariant {
11636 name: "MUL246",
11637 description: None,
11638 value: 245,
11639 },
11640 EnumVariant {
11641 name: "MUL247",
11642 description: None,
11643 value: 246,
11644 },
11645 EnumVariant {
11646 name: "MUL248",
11647 description: None,
11648 value: 247,
11649 },
11650 EnumVariant {
11651 name: "MUL249",
11652 description: None,
11653 value: 248,
11654 },
11655 EnumVariant {
11656 name: "MUL250",
11657 description: None,
11658 value: 249,
11659 },
11660 EnumVariant {
11661 name: "MUL251",
11662 description: None,
11663 value: 250,
11664 },
11665 EnumVariant {
11666 name: "MUL252",
11667 description: None,
11668 value: 251,
11669 },
11670 EnumVariant {
11671 name: "MUL253",
11672 description: None,
11673 value: 252,
11674 },
11675 EnumVariant {
11676 name: "MUL254",
11677 description: None,
11678 value: 253,
11679 },
11680 EnumVariant {
11681 name: "MUL255",
11682 description: None,
11683 value: 254,
11684 },
11685 EnumVariant {
11686 name: "MUL256",
11687 description: None,
11688 value: 255,
11689 },
11690 EnumVariant {
11691 name: "MUL257",
11692 description: None,
11693 value: 256,
11694 },
11695 EnumVariant {
11696 name: "MUL258",
11697 description: None,
11698 value: 257,
11699 },
11700 EnumVariant {
11701 name: "MUL259",
11702 description: None,
11703 value: 258,
11704 },
11705 EnumVariant {
11706 name: "MUL260",
11707 description: None,
11708 value: 259,
11709 },
11710 EnumVariant {
11711 name: "MUL261",
11712 description: None,
11713 value: 260,
11714 },
11715 EnumVariant {
11716 name: "MUL262",
11717 description: None,
11718 value: 261,
11719 },
11720 EnumVariant {
11721 name: "MUL263",
11722 description: None,
11723 value: 262,
11724 },
11725 EnumVariant {
11726 name: "MUL264",
11727 description: None,
11728 value: 263,
11729 },
11730 EnumVariant {
11731 name: "MUL265",
11732 description: None,
11733 value: 264,
11734 },
11735 EnumVariant {
11736 name: "MUL266",
11737 description: None,
11738 value: 265,
11739 },
11740 EnumVariant {
11741 name: "MUL267",
11742 description: None,
11743 value: 266,
11744 },
11745 EnumVariant {
11746 name: "MUL268",
11747 description: None,
11748 value: 267,
11749 },
11750 EnumVariant {
11751 name: "MUL269",
11752 description: None,
11753 value: 268,
11754 },
11755 EnumVariant {
11756 name: "MUL270",
11757 description: None,
11758 value: 269,
11759 },
11760 EnumVariant {
11761 name: "MUL271",
11762 description: None,
11763 value: 270,
11764 },
11765 EnumVariant {
11766 name: "MUL272",
11767 description: None,
11768 value: 271,
11769 },
11770 EnumVariant {
11771 name: "MUL273",
11772 description: None,
11773 value: 272,
11774 },
11775 EnumVariant {
11776 name: "MUL274",
11777 description: None,
11778 value: 273,
11779 },
11780 EnumVariant {
11781 name: "MUL275",
11782 description: None,
11783 value: 274,
11784 },
11785 EnumVariant {
11786 name: "MUL276",
11787 description: None,
11788 value: 275,
11789 },
11790 EnumVariant {
11791 name: "MUL277",
11792 description: None,
11793 value: 276,
11794 },
11795 EnumVariant {
11796 name: "MUL278",
11797 description: None,
11798 value: 277,
11799 },
11800 EnumVariant {
11801 name: "MUL279",
11802 description: None,
11803 value: 278,
11804 },
11805 EnumVariant {
11806 name: "MUL280",
11807 description: None,
11808 value: 279,
11809 },
11810 EnumVariant {
11811 name: "MUL281",
11812 description: None,
11813 value: 280,
11814 },
11815 EnumVariant {
11816 name: "MUL282",
11817 description: None,
11818 value: 281,
11819 },
11820 EnumVariant {
11821 name: "MUL283",
11822 description: None,
11823 value: 282,
11824 },
11825 EnumVariant {
11826 name: "MUL284",
11827 description: None,
11828 value: 283,
11829 },
11830 EnumVariant {
11831 name: "MUL285",
11832 description: None,
11833 value: 284,
11834 },
11835 EnumVariant {
11836 name: "MUL286",
11837 description: None,
11838 value: 285,
11839 },
11840 EnumVariant {
11841 name: "MUL287",
11842 description: None,
11843 value: 286,
11844 },
11845 EnumVariant {
11846 name: "MUL288",
11847 description: None,
11848 value: 287,
11849 },
11850 EnumVariant {
11851 name: "MUL289",
11852 description: None,
11853 value: 288,
11854 },
11855 EnumVariant {
11856 name: "MUL290",
11857 description: None,
11858 value: 289,
11859 },
11860 EnumVariant {
11861 name: "MUL291",
11862 description: None,
11863 value: 290,
11864 },
11865 EnumVariant {
11866 name: "MUL292",
11867 description: None,
11868 value: 291,
11869 },
11870 EnumVariant {
11871 name: "MUL293",
11872 description: None,
11873 value: 292,
11874 },
11875 EnumVariant {
11876 name: "MUL294",
11877 description: None,
11878 value: 293,
11879 },
11880 EnumVariant {
11881 name: "MUL295",
11882 description: None,
11883 value: 294,
11884 },
11885 EnumVariant {
11886 name: "MUL296",
11887 description: None,
11888 value: 295,
11889 },
11890 EnumVariant {
11891 name: "MUL297",
11892 description: None,
11893 value: 296,
11894 },
11895 EnumVariant {
11896 name: "MUL298",
11897 description: None,
11898 value: 297,
11899 },
11900 EnumVariant {
11901 name: "MUL299",
11902 description: None,
11903 value: 298,
11904 },
11905 EnumVariant {
11906 name: "MUL300",
11907 description: None,
11908 value: 299,
11909 },
11910 EnumVariant {
11911 name: "MUL301",
11912 description: None,
11913 value: 300,
11914 },
11915 EnumVariant {
11916 name: "MUL302",
11917 description: None,
11918 value: 301,
11919 },
11920 EnumVariant {
11921 name: "MUL303",
11922 description: None,
11923 value: 302,
11924 },
11925 EnumVariant {
11926 name: "MUL304",
11927 description: None,
11928 value: 303,
11929 },
11930 EnumVariant {
11931 name: "MUL305",
11932 description: None,
11933 value: 304,
11934 },
11935 EnumVariant {
11936 name: "MUL306",
11937 description: None,
11938 value: 305,
11939 },
11940 EnumVariant {
11941 name: "MUL307",
11942 description: None,
11943 value: 306,
11944 },
11945 EnumVariant {
11946 name: "MUL308",
11947 description: None,
11948 value: 307,
11949 },
11950 EnumVariant {
11951 name: "MUL309",
11952 description: None,
11953 value: 308,
11954 },
11955 EnumVariant {
11956 name: "MUL310",
11957 description: None,
11958 value: 309,
11959 },
11960 EnumVariant {
11961 name: "MUL311",
11962 description: None,
11963 value: 310,
11964 },
11965 EnumVariant {
11966 name: "MUL312",
11967 description: None,
11968 value: 311,
11969 },
11970 EnumVariant {
11971 name: "MUL313",
11972 description: None,
11973 value: 312,
11974 },
11975 EnumVariant {
11976 name: "MUL314",
11977 description: None,
11978 value: 313,
11979 },
11980 EnumVariant {
11981 name: "MUL315",
11982 description: None,
11983 value: 314,
11984 },
11985 EnumVariant {
11986 name: "MUL316",
11987 description: None,
11988 value: 315,
11989 },
11990 EnumVariant {
11991 name: "MUL317",
11992 description: None,
11993 value: 316,
11994 },
11995 EnumVariant {
11996 name: "MUL318",
11997 description: None,
11998 value: 317,
11999 },
12000 EnumVariant {
12001 name: "MUL319",
12002 description: None,
12003 value: 318,
12004 },
12005 EnumVariant {
12006 name: "MUL320",
12007 description: None,
12008 value: 319,
12009 },
12010 EnumVariant {
12011 name: "MUL321",
12012 description: None,
12013 value: 320,
12014 },
12015 EnumVariant {
12016 name: "MUL322",
12017 description: None,
12018 value: 321,
12019 },
12020 EnumVariant {
12021 name: "MUL323",
12022 description: None,
12023 value: 322,
12024 },
12025 EnumVariant {
12026 name: "MUL324",
12027 description: None,
12028 value: 323,
12029 },
12030 EnumVariant {
12031 name: "MUL325",
12032 description: None,
12033 value: 324,
12034 },
12035 EnumVariant {
12036 name: "MUL326",
12037 description: None,
12038 value: 325,
12039 },
12040 EnumVariant {
12041 name: "MUL327",
12042 description: None,
12043 value: 326,
12044 },
12045 EnumVariant {
12046 name: "MUL328",
12047 description: None,
12048 value: 327,
12049 },
12050 EnumVariant {
12051 name: "MUL329",
12052 description: None,
12053 value: 328,
12054 },
12055 EnumVariant {
12056 name: "MUL330",
12057 description: None,
12058 value: 329,
12059 },
12060 EnumVariant {
12061 name: "MUL331",
12062 description: None,
12063 value: 330,
12064 },
12065 EnumVariant {
12066 name: "MUL332",
12067 description: None,
12068 value: 331,
12069 },
12070 EnumVariant {
12071 name: "MUL333",
12072 description: None,
12073 value: 332,
12074 },
12075 EnumVariant {
12076 name: "MUL334",
12077 description: None,
12078 value: 333,
12079 },
12080 EnumVariant {
12081 name: "MUL335",
12082 description: None,
12083 value: 334,
12084 },
12085 EnumVariant {
12086 name: "MUL336",
12087 description: None,
12088 value: 335,
12089 },
12090 EnumVariant {
12091 name: "MUL337",
12092 description: None,
12093 value: 336,
12094 },
12095 EnumVariant {
12096 name: "MUL338",
12097 description: None,
12098 value: 337,
12099 },
12100 EnumVariant {
12101 name: "MUL339",
12102 description: None,
12103 value: 338,
12104 },
12105 EnumVariant {
12106 name: "MUL340",
12107 description: None,
12108 value: 339,
12109 },
12110 EnumVariant {
12111 name: "MUL341",
12112 description: None,
12113 value: 340,
12114 },
12115 EnumVariant {
12116 name: "MUL342",
12117 description: None,
12118 value: 341,
12119 },
12120 EnumVariant {
12121 name: "MUL343",
12122 description: None,
12123 value: 342,
12124 },
12125 EnumVariant {
12126 name: "MUL344",
12127 description: None,
12128 value: 343,
12129 },
12130 EnumVariant {
12131 name: "MUL345",
12132 description: None,
12133 value: 344,
12134 },
12135 EnumVariant {
12136 name: "MUL346",
12137 description: None,
12138 value: 345,
12139 },
12140 EnumVariant {
12141 name: "MUL347",
12142 description: None,
12143 value: 346,
12144 },
12145 EnumVariant {
12146 name: "MUL348",
12147 description: None,
12148 value: 347,
12149 },
12150 EnumVariant {
12151 name: "MUL349",
12152 description: None,
12153 value: 348,
12154 },
12155 EnumVariant {
12156 name: "MUL350",
12157 description: None,
12158 value: 349,
12159 },
12160 EnumVariant {
12161 name: "MUL351",
12162 description: None,
12163 value: 350,
12164 },
12165 EnumVariant {
12166 name: "MUL352",
12167 description: None,
12168 value: 351,
12169 },
12170 EnumVariant {
12171 name: "MUL353",
12172 description: None,
12173 value: 352,
12174 },
12175 EnumVariant {
12176 name: "MUL354",
12177 description: None,
12178 value: 353,
12179 },
12180 EnumVariant {
12181 name: "MUL355",
12182 description: None,
12183 value: 354,
12184 },
12185 EnumVariant {
12186 name: "MUL356",
12187 description: None,
12188 value: 355,
12189 },
12190 EnumVariant {
12191 name: "MUL357",
12192 description: None,
12193 value: 356,
12194 },
12195 EnumVariant {
12196 name: "MUL358",
12197 description: None,
12198 value: 357,
12199 },
12200 EnumVariant {
12201 name: "MUL359",
12202 description: None,
12203 value: 358,
12204 },
12205 EnumVariant {
12206 name: "MUL360",
12207 description: None,
12208 value: 359,
12209 },
12210 EnumVariant {
12211 name: "MUL361",
12212 description: None,
12213 value: 360,
12214 },
12215 EnumVariant {
12216 name: "MUL362",
12217 description: None,
12218 value: 361,
12219 },
12220 EnumVariant {
12221 name: "MUL363",
12222 description: None,
12223 value: 362,
12224 },
12225 EnumVariant {
12226 name: "MUL364",
12227 description: None,
12228 value: 363,
12229 },
12230 EnumVariant {
12231 name: "MUL365",
12232 description: None,
12233 value: 364,
12234 },
12235 EnumVariant {
12236 name: "MUL366",
12237 description: None,
12238 value: 365,
12239 },
12240 EnumVariant {
12241 name: "MUL367",
12242 description: None,
12243 value: 366,
12244 },
12245 EnumVariant {
12246 name: "MUL368",
12247 description: None,
12248 value: 367,
12249 },
12250 EnumVariant {
12251 name: "MUL369",
12252 description: None,
12253 value: 368,
12254 },
12255 EnumVariant {
12256 name: "MUL370",
12257 description: None,
12258 value: 369,
12259 },
12260 EnumVariant {
12261 name: "MUL371",
12262 description: None,
12263 value: 370,
12264 },
12265 EnumVariant {
12266 name: "MUL372",
12267 description: None,
12268 value: 371,
12269 },
12270 EnumVariant {
12271 name: "MUL373",
12272 description: None,
12273 value: 372,
12274 },
12275 EnumVariant {
12276 name: "MUL374",
12277 description: None,
12278 value: 373,
12279 },
12280 EnumVariant {
12281 name: "MUL375",
12282 description: None,
12283 value: 374,
12284 },
12285 EnumVariant {
12286 name: "MUL376",
12287 description: None,
12288 value: 375,
12289 },
12290 EnumVariant {
12291 name: "MUL377",
12292 description: None,
12293 value: 376,
12294 },
12295 EnumVariant {
12296 name: "MUL378",
12297 description: None,
12298 value: 377,
12299 },
12300 EnumVariant {
12301 name: "MUL379",
12302 description: None,
12303 value: 378,
12304 },
12305 EnumVariant {
12306 name: "MUL380",
12307 description: None,
12308 value: 379,
12309 },
12310 EnumVariant {
12311 name: "MUL381",
12312 description: None,
12313 value: 380,
12314 },
12315 EnumVariant {
12316 name: "MUL382",
12317 description: None,
12318 value: 381,
12319 },
12320 EnumVariant {
12321 name: "MUL383",
12322 description: None,
12323 value: 382,
12324 },
12325 EnumVariant {
12326 name: "MUL384",
12327 description: None,
12328 value: 383,
12329 },
12330 EnumVariant {
12331 name: "MUL385",
12332 description: None,
12333 value: 384,
12334 },
12335 EnumVariant {
12336 name: "MUL386",
12337 description: None,
12338 value: 385,
12339 },
12340 EnumVariant {
12341 name: "MUL387",
12342 description: None,
12343 value: 386,
12344 },
12345 EnumVariant {
12346 name: "MUL388",
12347 description: None,
12348 value: 387,
12349 },
12350 EnumVariant {
12351 name: "MUL389",
12352 description: None,
12353 value: 388,
12354 },
12355 EnumVariant {
12356 name: "MUL390",
12357 description: None,
12358 value: 389,
12359 },
12360 EnumVariant {
12361 name: "MUL391",
12362 description: None,
12363 value: 390,
12364 },
12365 EnumVariant {
12366 name: "MUL392",
12367 description: None,
12368 value: 391,
12369 },
12370 EnumVariant {
12371 name: "MUL393",
12372 description: None,
12373 value: 392,
12374 },
12375 EnumVariant {
12376 name: "MUL394",
12377 description: None,
12378 value: 393,
12379 },
12380 EnumVariant {
12381 name: "MUL395",
12382 description: None,
12383 value: 394,
12384 },
12385 EnumVariant {
12386 name: "MUL396",
12387 description: None,
12388 value: 395,
12389 },
12390 EnumVariant {
12391 name: "MUL397",
12392 description: None,
12393 value: 396,
12394 },
12395 EnumVariant {
12396 name: "MUL398",
12397 description: None,
12398 value: 397,
12399 },
12400 EnumVariant {
12401 name: "MUL399",
12402 description: None,
12403 value: 398,
12404 },
12405 EnumVariant {
12406 name: "MUL400",
12407 description: None,
12408 value: 399,
12409 },
12410 EnumVariant {
12411 name: "MUL401",
12412 description: None,
12413 value: 400,
12414 },
12415 EnumVariant {
12416 name: "MUL402",
12417 description: None,
12418 value: 401,
12419 },
12420 EnumVariant {
12421 name: "MUL403",
12422 description: None,
12423 value: 402,
12424 },
12425 EnumVariant {
12426 name: "MUL404",
12427 description: None,
12428 value: 403,
12429 },
12430 EnumVariant {
12431 name: "MUL405",
12432 description: None,
12433 value: 404,
12434 },
12435 EnumVariant {
12436 name: "MUL406",
12437 description: None,
12438 value: 405,
12439 },
12440 EnumVariant {
12441 name: "MUL407",
12442 description: None,
12443 value: 406,
12444 },
12445 EnumVariant {
12446 name: "MUL408",
12447 description: None,
12448 value: 407,
12449 },
12450 EnumVariant {
12451 name: "MUL409",
12452 description: None,
12453 value: 408,
12454 },
12455 EnumVariant {
12456 name: "MUL410",
12457 description: None,
12458 value: 409,
12459 },
12460 EnumVariant {
12461 name: "MUL411",
12462 description: None,
12463 value: 410,
12464 },
12465 EnumVariant {
12466 name: "MUL412",
12467 description: None,
12468 value: 411,
12469 },
12470 EnumVariant {
12471 name: "MUL413",
12472 description: None,
12473 value: 412,
12474 },
12475 EnumVariant {
12476 name: "MUL414",
12477 description: None,
12478 value: 413,
12479 },
12480 EnumVariant {
12481 name: "MUL415",
12482 description: None,
12483 value: 414,
12484 },
12485 EnumVariant {
12486 name: "MUL416",
12487 description: None,
12488 value: 415,
12489 },
12490 EnumVariant {
12491 name: "MUL417",
12492 description: None,
12493 value: 416,
12494 },
12495 EnumVariant {
12496 name: "MUL418",
12497 description: None,
12498 value: 417,
12499 },
12500 EnumVariant {
12501 name: "MUL419",
12502 description: None,
12503 value: 418,
12504 },
12505 EnumVariant {
12506 name: "MUL420",
12507 description: None,
12508 value: 419,
12509 },
12510 EnumVariant {
12511 name: "MUL421",
12512 description: None,
12513 value: 420,
12514 },
12515 EnumVariant {
12516 name: "MUL422",
12517 description: None,
12518 value: 421,
12519 },
12520 EnumVariant {
12521 name: "MUL423",
12522 description: None,
12523 value: 422,
12524 },
12525 EnumVariant {
12526 name: "MUL424",
12527 description: None,
12528 value: 423,
12529 },
12530 EnumVariant {
12531 name: "MUL425",
12532 description: None,
12533 value: 424,
12534 },
12535 EnumVariant {
12536 name: "MUL426",
12537 description: None,
12538 value: 425,
12539 },
12540 EnumVariant {
12541 name: "MUL427",
12542 description: None,
12543 value: 426,
12544 },
12545 EnumVariant {
12546 name: "MUL428",
12547 description: None,
12548 value: 427,
12549 },
12550 EnumVariant {
12551 name: "MUL429",
12552 description: None,
12553 value: 428,
12554 },
12555 EnumVariant {
12556 name: "MUL430",
12557 description: None,
12558 value: 429,
12559 },
12560 EnumVariant {
12561 name: "MUL431",
12562 description: None,
12563 value: 430,
12564 },
12565 EnumVariant {
12566 name: "MUL432",
12567 description: None,
12568 value: 431,
12569 },
12570 EnumVariant {
12571 name: "MUL433",
12572 description: None,
12573 value: 432,
12574 },
12575 EnumVariant {
12576 name: "MUL434",
12577 description: None,
12578 value: 433,
12579 },
12580 EnumVariant {
12581 name: "MUL435",
12582 description: None,
12583 value: 434,
12584 },
12585 EnumVariant {
12586 name: "MUL436",
12587 description: None,
12588 value: 435,
12589 },
12590 EnumVariant {
12591 name: "MUL437",
12592 description: None,
12593 value: 436,
12594 },
12595 EnumVariant {
12596 name: "MUL438",
12597 description: None,
12598 value: 437,
12599 },
12600 EnumVariant {
12601 name: "MUL439",
12602 description: None,
12603 value: 438,
12604 },
12605 EnumVariant {
12606 name: "MUL440",
12607 description: None,
12608 value: 439,
12609 },
12610 EnumVariant {
12611 name: "MUL441",
12612 description: None,
12613 value: 440,
12614 },
12615 EnumVariant {
12616 name: "MUL442",
12617 description: None,
12618 value: 441,
12619 },
12620 EnumVariant {
12621 name: "MUL443",
12622 description: None,
12623 value: 442,
12624 },
12625 EnumVariant {
12626 name: "MUL444",
12627 description: None,
12628 value: 443,
12629 },
12630 EnumVariant {
12631 name: "MUL445",
12632 description: None,
12633 value: 444,
12634 },
12635 EnumVariant {
12636 name: "MUL446",
12637 description: None,
12638 value: 445,
12639 },
12640 EnumVariant {
12641 name: "MUL447",
12642 description: None,
12643 value: 446,
12644 },
12645 EnumVariant {
12646 name: "MUL448",
12647 description: None,
12648 value: 447,
12649 },
12650 EnumVariant {
12651 name: "MUL449",
12652 description: None,
12653 value: 448,
12654 },
12655 EnumVariant {
12656 name: "MUL450",
12657 description: None,
12658 value: 449,
12659 },
12660 EnumVariant {
12661 name: "MUL451",
12662 description: None,
12663 value: 450,
12664 },
12665 EnumVariant {
12666 name: "MUL452",
12667 description: None,
12668 value: 451,
12669 },
12670 EnumVariant {
12671 name: "MUL453",
12672 description: None,
12673 value: 452,
12674 },
12675 EnumVariant {
12676 name: "MUL454",
12677 description: None,
12678 value: 453,
12679 },
12680 EnumVariant {
12681 name: "MUL455",
12682 description: None,
12683 value: 454,
12684 },
12685 EnumVariant {
12686 name: "MUL456",
12687 description: None,
12688 value: 455,
12689 },
12690 EnumVariant {
12691 name: "MUL457",
12692 description: None,
12693 value: 456,
12694 },
12695 EnumVariant {
12696 name: "MUL458",
12697 description: None,
12698 value: 457,
12699 },
12700 EnumVariant {
12701 name: "MUL459",
12702 description: None,
12703 value: 458,
12704 },
12705 EnumVariant {
12706 name: "MUL460",
12707 description: None,
12708 value: 459,
12709 },
12710 EnumVariant {
12711 name: "MUL461",
12712 description: None,
12713 value: 460,
12714 },
12715 EnumVariant {
12716 name: "MUL462",
12717 description: None,
12718 value: 461,
12719 },
12720 EnumVariant {
12721 name: "MUL463",
12722 description: None,
12723 value: 462,
12724 },
12725 EnumVariant {
12726 name: "MUL464",
12727 description: None,
12728 value: 463,
12729 },
12730 EnumVariant {
12731 name: "MUL465",
12732 description: None,
12733 value: 464,
12734 },
12735 EnumVariant {
12736 name: "MUL466",
12737 description: None,
12738 value: 465,
12739 },
12740 EnumVariant {
12741 name: "MUL467",
12742 description: None,
12743 value: 466,
12744 },
12745 EnumVariant {
12746 name: "MUL468",
12747 description: None,
12748 value: 467,
12749 },
12750 EnumVariant {
12751 name: "MUL469",
12752 description: None,
12753 value: 468,
12754 },
12755 EnumVariant {
12756 name: "MUL470",
12757 description: None,
12758 value: 469,
12759 },
12760 EnumVariant {
12761 name: "MUL471",
12762 description: None,
12763 value: 470,
12764 },
12765 EnumVariant {
12766 name: "MUL472",
12767 description: None,
12768 value: 471,
12769 },
12770 EnumVariant {
12771 name: "MUL473",
12772 description: None,
12773 value: 472,
12774 },
12775 EnumVariant {
12776 name: "MUL474",
12777 description: None,
12778 value: 473,
12779 },
12780 EnumVariant {
12781 name: "MUL475",
12782 description: None,
12783 value: 474,
12784 },
12785 EnumVariant {
12786 name: "MUL476",
12787 description: None,
12788 value: 475,
12789 },
12790 EnumVariant {
12791 name: "MUL477",
12792 description: None,
12793 value: 476,
12794 },
12795 EnumVariant {
12796 name: "MUL478",
12797 description: None,
12798 value: 477,
12799 },
12800 EnumVariant {
12801 name: "MUL479",
12802 description: None,
12803 value: 478,
12804 },
12805 EnumVariant {
12806 name: "MUL480",
12807 description: None,
12808 value: 479,
12809 },
12810 EnumVariant {
12811 name: "MUL481",
12812 description: None,
12813 value: 480,
12814 },
12815 EnumVariant {
12816 name: "MUL482",
12817 description: None,
12818 value: 481,
12819 },
12820 EnumVariant {
12821 name: "MUL483",
12822 description: None,
12823 value: 482,
12824 },
12825 EnumVariant {
12826 name: "MUL484",
12827 description: None,
12828 value: 483,
12829 },
12830 EnumVariant {
12831 name: "MUL485",
12832 description: None,
12833 value: 484,
12834 },
12835 EnumVariant {
12836 name: "MUL486",
12837 description: None,
12838 value: 485,
12839 },
12840 EnumVariant {
12841 name: "MUL487",
12842 description: None,
12843 value: 486,
12844 },
12845 EnumVariant {
12846 name: "MUL488",
12847 description: None,
12848 value: 487,
12849 },
12850 EnumVariant {
12851 name: "MUL489",
12852 description: None,
12853 value: 488,
12854 },
12855 EnumVariant {
12856 name: "MUL490",
12857 description: None,
12858 value: 489,
12859 },
12860 EnumVariant {
12861 name: "MUL491",
12862 description: None,
12863 value: 490,
12864 },
12865 EnumVariant {
12866 name: "MUL492",
12867 description: None,
12868 value: 491,
12869 },
12870 EnumVariant {
12871 name: "MUL493",
12872 description: None,
12873 value: 492,
12874 },
12875 EnumVariant {
12876 name: "MUL494",
12877 description: None,
12878 value: 493,
12879 },
12880 EnumVariant {
12881 name: "MUL495",
12882 description: None,
12883 value: 494,
12884 },
12885 EnumVariant {
12886 name: "MUL496",
12887 description: None,
12888 value: 495,
12889 },
12890 EnumVariant {
12891 name: "MUL497",
12892 description: None,
12893 value: 496,
12894 },
12895 EnumVariant {
12896 name: "MUL498",
12897 description: None,
12898 value: 497,
12899 },
12900 EnumVariant {
12901 name: "MUL499",
12902 description: None,
12903 value: 498,
12904 },
12905 EnumVariant {
12906 name: "MUL500",
12907 description: None,
12908 value: 499,
12909 },
12910 EnumVariant {
12911 name: "MUL501",
12912 description: None,
12913 value: 500,
12914 },
12915 EnumVariant {
12916 name: "MUL502",
12917 description: None,
12918 value: 501,
12919 },
12920 EnumVariant {
12921 name: "MUL503",
12922 description: None,
12923 value: 502,
12924 },
12925 EnumVariant {
12926 name: "MUL504",
12927 description: None,
12928 value: 503,
12929 },
12930 EnumVariant {
12931 name: "MUL505",
12932 description: None,
12933 value: 504,
12934 },
12935 EnumVariant {
12936 name: "MUL506",
12937 description: None,
12938 value: 505,
12939 },
12940 EnumVariant {
12941 name: "MUL507",
12942 description: None,
12943 value: 506,
12944 },
12945 EnumVariant {
12946 name: "MUL508",
12947 description: None,
12948 value: 507,
12949 },
12950 EnumVariant {
12951 name: "MUL509",
12952 description: None,
12953 value: 508,
12954 },
12955 EnumVariant {
12956 name: "MUL510",
12957 description: None,
12958 value: 509,
12959 },
12960 EnumVariant {
12961 name: "MUL511",
12962 description: None,
12963 value: 510,
12964 },
12965 EnumVariant {
12966 name: "MUL512",
12967 description: None,
12968 value: 511,
12969 },
12970 ],
12971 },
12972 Enum {
12973 name: "Pllrge",
12974 description: None,
12975 bit_size: 2,
12976 variants: &[
12977 EnumVariant {
12978 name: "FREQ_4TO8MHZ",
12979 description: Some(
12980 "PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz",
12981 ),
12982 value: 0,
12983 },
12984 EnumVariant {
12985 name: "FREQ_8TO16MHZ",
12986 description: Some(
12987 "PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz",
12988 ),
12989 value: 3,
12990 },
12991 ],
12992 },
12993 Enum {
12994 name: "Pllsrc",
12995 description: None,
12996 bit_size: 2,
12997 variants: &[
12998 EnumVariant {
12999 name: "DISABLE",
13000 description: Some(
13001 "No clock sent to PLL3",
13002 ),
13003 value: 0,
13004 },
13005 EnumVariant {
13006 name: "MSIS",
13007 description: Some(
13008 "MSIS clock selected as PLL3 clock entry",
13009 ),
13010 value: 1,
13011 },
13012 EnumVariant {
13013 name: "HSI",
13014 description: Some(
13015 "HSI clock selected as PLL3 clock entry",
13016 ),
13017 value: 2,
13018 },
13019 EnumVariant {
13020 name: "HSE",
13021 description: Some(
13022 "HSE clock selected as PLL3 clock entry",
13023 ),
13024 value: 3,
13025 },
13026 ],
13027 },
13028 Enum {
13029 name: "Ppre",
13030 description: None,
13031 bit_size: 3,
13032 variants: &[
13033 EnumVariant {
13034 name: "DIV1",
13035 description: Some(
13036 "HCLK not divided",
13037 ),
13038 value: 0,
13039 },
13040 EnumVariant {
13041 name: "DIV2",
13042 description: Some(
13043 "HCLK divided by 2",
13044 ),
13045 value: 4,
13046 },
13047 EnumVariant {
13048 name: "DIV4",
13049 description: Some(
13050 "HCLK divided by 4",
13051 ),
13052 value: 5,
13053 },
13054 EnumVariant {
13055 name: "DIV8",
13056 description: Some(
13057 "HCLK divided by 8",
13058 ),
13059 value: 6,
13060 },
13061 EnumVariant {
13062 name: "DIV16",
13063 description: Some(
13064 "HCLK divided by 16",
13065 ),
13066 value: 7,
13067 },
13068 ],
13069 },
13070 Enum {
13071 name: "Rngsel",
13072 description: None,
13073 bit_size: 2,
13074 variants: &[
13075 EnumVariant {
13076 name: "HSI48",
13077 description: Some(
13078 "HSI48 selected",
13079 ),
13080 value: 0,
13081 },
13082 EnumVariant {
13083 name: "HSI48_DIV_2",
13084 description: Some(
13085 "HSI48 / 2 selected, can be used in Range 4",
13086 ),
13087 value: 1,
13088 },
13089 EnumVariant {
13090 name: "HSI",
13091 description: Some(
13092 "HSI selected",
13093 ),
13094 value: 2,
13095 },
13096 ],
13097 },
13098 Enum {
13099 name: "Rtcsel",
13100 description: None,
13101 bit_size: 2,
13102 variants: &[
13103 EnumVariant {
13104 name: "DISABLE",
13105 description: Some(
13106 "No clock selected",
13107 ),
13108 value: 0,
13109 },
13110 EnumVariant {
13111 name: "LSE",
13112 description: Some(
13113 "LSE oscillator clock selected",
13114 ),
13115 value: 1,
13116 },
13117 EnumVariant {
13118 name: "LSI",
13119 description: Some(
13120 "LSI oscillator clock selected",
13121 ),
13122 value: 2,
13123 },
13124 EnumVariant {
13125 name: "HSE",
13126 description: Some(
13127 "HSE oscillator clock divided by 32 selected",
13128 ),
13129 value: 3,
13130 },
13131 ],
13132 },
13133 Enum {
13134 name: "Saessel",
13135 description: None,
13136 bit_size: 1,
13137 variants: &[
13138 EnumVariant {
13139 name: "SHSI",
13140 description: Some(
13141 "SHSI selected",
13142 ),
13143 value: 0,
13144 },
13145 EnumVariant {
13146 name: "SHSI_DIV_2",
13147 description: Some(
13148 "SHSI / 2 selected, can be used in Range 4",
13149 ),
13150 value: 1,
13151 },
13152 ],
13153 },
13154 Enum {
13155 name: "Saisel",
13156 description: None,
13157 bit_size: 3,
13158 variants: &[
13159 EnumVariant {
13160 name: "PLL2_P",
13161 description: Some(
13162 "PLL2 P (pll2_p_ck) selected",
13163 ),
13164 value: 0,
13165 },
13166 EnumVariant {
13167 name: "PLL3_P",
13168 description: Some(
13169 "PLL3 P (pll3_p_ck) selected",
13170 ),
13171 value: 1,
13172 },
13173 EnumVariant {
13174 name: "PLL1_P",
13175 description: Some(
13176 "PLL1 P (pll1_p_ck) selected",
13177 ),
13178 value: 2,
13179 },
13180 EnumVariant {
13181 name: "AUDIOCLK",
13182 description: Some(
13183 "input pin AUDIOCLK selected",
13184 ),
13185 value: 3,
13186 },
13187 EnumVariant {
13188 name: "HSI",
13189 description: Some(
13190 "HSI clock selected",
13191 ),
13192 value: 4,
13193 },
13194 ],
13195 },
13196 Enum {
13197 name: "Sdmmcsel",
13198 description: None,
13199 bit_size: 1,
13200 variants: &[
13201 EnumVariant {
13202 name: "ICLK",
13203 description: Some(
13204 "ICLK clock selected",
13205 ),
13206 value: 0,
13207 },
13208 EnumVariant {
13209 name: "PLL1_P",
13210 description: Some(
13211 "PLL1 P (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode)",
13212 ),
13213 value: 1,
13214 },
13215 ],
13216 },
13217 Enum {
13218 name: "Security",
13219 description: None,
13220 bit_size: 1,
13221 variants: &[
13222 EnumVariant {
13223 name: "NON_SECURE",
13224 description: Some(
13225 "non secure",
13226 ),
13227 value: 0,
13228 },
13229 EnumVariant {
13230 name: "SECURE",
13231 description: Some(
13232 "secure",
13233 ),
13234 value: 1,
13235 },
13236 ],
13237 },
13238 Enum {
13239 name: "Spi1sel",
13240 description: None,
13241 bit_size: 2,
13242 variants: &[
13243 EnumVariant {
13244 name: "PCLK2",
13245 description: Some(
13246 "PCLK2 selected",
13247 ),
13248 value: 0,
13249 },
13250 EnumVariant {
13251 name: "SYS",
13252 description: Some(
13253 "SYSCLK selected",
13254 ),
13255 value: 1,
13256 },
13257 EnumVariant {
13258 name: "HSI",
13259 description: Some(
13260 "HSI selected",
13261 ),
13262 value: 2,
13263 },
13264 EnumVariant {
13265 name: "MSIK",
13266 description: Some(
13267 "MSIK selected",
13268 ),
13269 value: 3,
13270 },
13271 ],
13272 },
13273 Enum {
13274 name: "Spi2sel",
13275 description: None,
13276 bit_size: 2,
13277 variants: &[
13278 EnumVariant {
13279 name: "PCLK1",
13280 description: Some(
13281 "PCLK2 selected",
13282 ),
13283 value: 0,
13284 },
13285 EnumVariant {
13286 name: "SYS",
13287 description: Some(
13288 "SYSCLK selected",
13289 ),
13290 value: 1,
13291 },
13292 EnumVariant {
13293 name: "HSI",
13294 description: Some(
13295 "HSI selected",
13296 ),
13297 value: 2,
13298 },
13299 EnumVariant {
13300 name: "MSIK",
13301 description: Some(
13302 "MSIK selected",
13303 ),
13304 value: 3,
13305 },
13306 ],
13307 },
13308 Enum {
13309 name: "Spi3sel",
13310 description: None,
13311 bit_size: 2,
13312 variants: &[
13313 EnumVariant {
13314 name: "PCLK3",
13315 description: Some(
13316 "PCLK2 selected",
13317 ),
13318 value: 0,
13319 },
13320 EnumVariant {
13321 name: "SYS",
13322 description: Some(
13323 "SYSCLK selected",
13324 ),
13325 value: 1,
13326 },
13327 EnumVariant {
13328 name: "HSI",
13329 description: Some(
13330 "HSI selected",
13331 ),
13332 value: 2,
13333 },
13334 EnumVariant {
13335 name: "MSIK",
13336 description: Some(
13337 "MSIK selected",
13338 ),
13339 value: 3,
13340 },
13341 ],
13342 },
13343 Enum {
13344 name: "Stopkerwuck",
13345 description: None,
13346 bit_size: 1,
13347 variants: &[
13348 EnumVariant {
13349 name: "MSIK",
13350 description: Some(
13351 "MSIK oscillator automatically enabled when exiting Stop mode",
13352 ),
13353 value: 0,
13354 },
13355 EnumVariant {
13356 name: "HSI",
13357 description: Some(
13358 "HSI oscillator automatically enabled when exiting Stop mode",
13359 ),
13360 value: 1,
13361 },
13362 ],
13363 },
13364 Enum {
13365 name: "Stopwuck",
13366 description: None,
13367 bit_size: 1,
13368 variants: &[
13369 EnumVariant {
13370 name: "MSIS",
13371 description: Some(
13372 "MSIS oscillator selected as wakeup from stop clock and CSS backup clock",
13373 ),
13374 value: 0,
13375 },
13376 EnumVariant {
13377 name: "HSI",
13378 description: Some(
13379 "HSI oscillator selected as wakeup from stop clock and CSS backup clock",
13380 ),
13381 value: 1,
13382 },
13383 ],
13384 },
13385 Enum {
13386 name: "Sw",
13387 description: None,
13388 bit_size: 2,
13389 variants: &[
13390 EnumVariant {
13391 name: "MSIS",
13392 description: Some(
13393 "MSIS selected as system clock",
13394 ),
13395 value: 0,
13396 },
13397 EnumVariant {
13398 name: "HSI",
13399 description: Some(
13400 "HSI selected as system clock",
13401 ),
13402 value: 1,
13403 },
13404 EnumVariant {
13405 name: "HSE",
13406 description: Some(
13407 "HSE selected as system clock",
13408 ),
13409 value: 2,
13410 },
13411 EnumVariant {
13412 name: "PLL1_R",
13413 description: Some(
13414 "PLL pll1_r_ck selected as system clock",
13415 ),
13416 value: 3,
13417 },
13418 ],
13419 },
13420 Enum {
13421 name: "Systicksel",
13422 description: None,
13423 bit_size: 2,
13424 variants: &[
13425 EnumVariant {
13426 name: "HCLK1_DIV_8",
13427 description: Some(
13428 "HCLK/8 selected",
13429 ),
13430 value: 0,
13431 },
13432 EnumVariant {
13433 name: "LSI",
13434 description: Some(
13435 "LSI selected",
13436 ),
13437 value: 1,
13438 },
13439 EnumVariant {
13440 name: "LSE",
13441 description: Some(
13442 "LSE selected",
13443 ),
13444 value: 2,
13445 },
13446 ],
13447 },
13448 Enum {
13449 name: "Timicsel",
13450 description: None,
13451 bit_size: 3,
13452 variants: &[
13453 EnumVariant {
13454 name: "DISABLE",
13455 description: Some(
13456 "No sources can be selected by TIM16, TIM17 and LPTIM2 as internal input capture",
13457 ),
13458 value: 0,
13459 },
13460 EnumVariant {
13461 name: "HSI256_MSIS1024_MSIS4",
13462 description: Some(
13463 "HSI/256, MSIS/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture",
13464 ),
13465 value: 4,
13466 },
13467 EnumVariant {
13468 name: "HSI256_MSIS1024_MSIK4",
13469 description: Some(
13470 "HSI/256, MSIS/1024 and MSIK/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture",
13471 ),
13472 value: 5,
13473 },
13474 EnumVariant {
13475 name: "HSI256_MSIK1024_MSIS4",
13476 description: Some(
13477 "HSI/256, MSIK/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture",
13478 ),
13479 value: 6,
13480 },
13481 EnumVariant {
13482 name: "HSI256_MSIK1024_MSIK4",
13483 description: Some(
13484 "HSI/256, MSIK/1024 and MSIK/4 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture",
13485 ),
13486 value: 7,
13487 },
13488 ],
13489 },
13490 Enum {
13491 name: "Usart1sel",
13492 description: None,
13493 bit_size: 2,
13494 variants: &[
13495 EnumVariant {
13496 name: "PCLK2",
13497 description: Some(
13498 "PCLK2 selected",
13499 ),
13500 value: 0,
13501 },
13502 EnumVariant {
13503 name: "SYS",
13504 description: Some(
13505 "SYSCLK selected",
13506 ),
13507 value: 1,
13508 },
13509 EnumVariant {
13510 name: "HSI",
13511 description: Some(
13512 "HSI selected",
13513 ),
13514 value: 2,
13515 },
13516 EnumVariant {
13517 name: "LSE",
13518 description: Some(
13519 "LSE selected",
13520 ),
13521 value: 3,
13522 },
13523 ],
13524 },
13525 Enum {
13526 name: "Usartsel",
13527 description: None,
13528 bit_size: 2,
13529 variants: &[
13530 EnumVariant {
13531 name: "PCLK1",
13532 description: Some(
13533 "PCLK1 selected",
13534 ),
13535 value: 0,
13536 },
13537 EnumVariant {
13538 name: "SYS",
13539 description: Some(
13540 "SYSCLK selected",
13541 ),
13542 value: 1,
13543 },
13544 EnumVariant {
13545 name: "HSI",
13546 description: Some(
13547 "HSI selected",
13548 ),
13549 value: 2,
13550 },
13551 EnumVariant {
13552 name: "LSE",
13553 description: Some(
13554 "LSE selected",
13555 ),
13556 value: 3,
13557 },
13558 ],
13559 },
13560 ],
13561};
13562