1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Rng",
7 extends: None,
8 description: Some(
9 "Random number generator",
10 ),
11 items: &[
12 BlockItem {
13 name: "cr",
14 description: Some(
15 "control register",
16 ),
17 array: None,
18 byte_offset: 0x0,
19 inner: BlockItemInner::Register(
20 Register {
21 access: Access::ReadWrite,
22 bit_size: 32,
23 fieldset: Some(
24 "Cr",
25 ),
26 },
27 ),
28 },
29 BlockItem {
30 name: "sr",
31 description: Some(
32 "status register",
33 ),
34 array: None,
35 byte_offset: 0x4,
36 inner: BlockItemInner::Register(
37 Register {
38 access: Access::ReadWrite,
39 bit_size: 32,
40 fieldset: Some(
41 "Sr",
42 ),
43 },
44 ),
45 },
46 BlockItem {
47 name: "dr",
48 description: Some(
49 "data register",
50 ),
51 array: None,
52 byte_offset: 0x8,
53 inner: BlockItemInner::Register(
54 Register {
55 access: Access::Read,
56 bit_size: 32,
57 fieldset: None,
58 },
59 ),
60 },
61 BlockItem {
62 name: "htcr",
63 description: Some(
64 "health test control register",
65 ),
66 array: None,
67 byte_offset: 0x10,
68 inner: BlockItemInner::Register(
69 Register {
70 access: Access::ReadWrite,
71 bit_size: 32,
72 fieldset: Some(
73 "Htcr",
74 ),
75 },
76 ),
77 },
78 ],
79 },
80 ],
81 fieldsets: &[
82 FieldSet {
83 name: "Cr",
84 extends: None,
85 description: Some(
86 "control register",
87 ),
88 bit_size: 32,
89 fields: &[
90 Field {
91 name: "rngen",
92 description: Some(
93 "Random number generator enable",
94 ),
95 bit_offset: BitOffset::Regular(
96 RegularBitOffset {
97 offset: 2,
98 },
99 ),
100 bit_size: 1,
101 array: None,
102 enumm: None,
103 },
104 Field {
105 name: "ie",
106 description: Some(
107 "Interrupt enable",
108 ),
109 bit_offset: BitOffset::Regular(
110 RegularBitOffset {
111 offset: 3,
112 },
113 ),
114 bit_size: 1,
115 array: None,
116 enumm: None,
117 },
118 Field {
119 name: "ced",
120 description: Some(
121 "Clock error detection",
122 ),
123 bit_offset: BitOffset::Regular(
124 RegularBitOffset {
125 offset: 5,
126 },
127 ),
128 bit_size: 1,
129 array: None,
130 enumm: None,
131 },
132 Field {
133 name: "ardis",
134 description: Some(
135 "Auto reset disable",
136 ),
137 bit_offset: BitOffset::Regular(
138 RegularBitOffset {
139 offset: 7,
140 },
141 ),
142 bit_size: 1,
143 array: None,
144 enumm: None,
145 },
146 Field {
147 name: "rng_config3",
148 description: Some(
149 "RNG configuration 3",
150 ),
151 bit_offset: BitOffset::Regular(
152 RegularBitOffset {
153 offset: 8,
154 },
155 ),
156 bit_size: 4,
157 array: None,
158 enumm: Some(
159 "RngConfig3",
160 ),
161 },
162 Field {
163 name: "nistc",
164 description: Some(
165 "Non NIST compliant",
166 ),
167 bit_offset: BitOffset::Regular(
168 RegularBitOffset {
169 offset: 12,
170 },
171 ),
172 bit_size: 1,
173 array: None,
174 enumm: Some(
175 "Nistc",
176 ),
177 },
178 Field {
179 name: "rng_config2",
180 description: Some(
181 "RNG configuration 2",
182 ),
183 bit_offset: BitOffset::Regular(
184 RegularBitOffset {
185 offset: 13,
186 },
187 ),
188 bit_size: 3,
189 array: None,
190 enumm: Some(
191 "RngConfig2",
192 ),
193 },
194 Field {
195 name: "clkdiv",
196 description: Some(
197 "Clock divider factor",
198 ),
199 bit_offset: BitOffset::Regular(
200 RegularBitOffset {
201 offset: 16,
202 },
203 ),
204 bit_size: 4,
205 array: None,
206 enumm: Some(
207 "Clkdiv",
208 ),
209 },
210 Field {
211 name: "rng_config1",
212 description: Some(
213 "RNG configuration 1",
214 ),
215 bit_offset: BitOffset::Regular(
216 RegularBitOffset {
217 offset: 20,
218 },
219 ),
220 bit_size: 6,
221 array: None,
222 enumm: Some(
223 "RngConfig1",
224 ),
225 },
226 Field {
227 name: "condrst",
228 description: Some(
229 "Conditioning soft reset",
230 ),
231 bit_offset: BitOffset::Regular(
232 RegularBitOffset {
233 offset: 30,
234 },
235 ),
236 bit_size: 1,
237 array: None,
238 enumm: None,
239 },
240 Field {
241 name: "configlock",
242 description: Some(
243 "Config Lock",
244 ),
245 bit_offset: BitOffset::Regular(
246 RegularBitOffset {
247 offset: 31,
248 },
249 ),
250 bit_size: 1,
251 array: None,
252 enumm: None,
253 },
254 ],
255 },
256 FieldSet {
257 name: "Htcr",
258 extends: None,
259 description: Some(
260 "Health test control register",
261 ),
262 bit_size: 32,
263 fields: &[
264 Field {
265 name: "htcfg",
266 description: Some(
267 "Health test configuration",
268 ),
269 bit_offset: BitOffset::Regular(
270 RegularBitOffset {
271 offset: 0,
272 },
273 ),
274 bit_size: 32,
275 array: None,
276 enumm: Some(
277 "Htcfg",
278 ),
279 },
280 ],
281 },
282 FieldSet {
283 name: "Sr",
284 extends: None,
285 description: Some(
286 "status register",
287 ),
288 bit_size: 32,
289 fields: &[
290 Field {
291 name: "drdy",
292 description: Some(
293 "Data ready",
294 ),
295 bit_offset: BitOffset::Regular(
296 RegularBitOffset {
297 offset: 0,
298 },
299 ),
300 bit_size: 1,
301 array: None,
302 enumm: None,
303 },
304 Field {
305 name: "cecs",
306 description: Some(
307 "Clock error current status",
308 ),
309 bit_offset: BitOffset::Regular(
310 RegularBitOffset {
311 offset: 1,
312 },
313 ),
314 bit_size: 1,
315 array: None,
316 enumm: None,
317 },
318 Field {
319 name: "secs",
320 description: Some(
321 "Seed error current status",
322 ),
323 bit_offset: BitOffset::Regular(
324 RegularBitOffset {
325 offset: 2,
326 },
327 ),
328 bit_size: 1,
329 array: None,
330 enumm: None,
331 },
332 Field {
333 name: "ceis",
334 description: Some(
335 "Clock error interrupt status",
336 ),
337 bit_offset: BitOffset::Regular(
338 RegularBitOffset {
339 offset: 5,
340 },
341 ),
342 bit_size: 1,
343 array: None,
344 enumm: None,
345 },
346 Field {
347 name: "seis",
348 description: Some(
349 "Seed error interrupt status",
350 ),
351 bit_offset: BitOffset::Regular(
352 RegularBitOffset {
353 offset: 6,
354 },
355 ),
356 bit_size: 1,
357 array: None,
358 enumm: None,
359 },
360 ],
361 },
362 ],
363 enums: &[
364 Enum {
365 name: "Clkdiv",
366 description: None,
367 bit_size: 4,
368 variants: &[
369 EnumVariant {
370 name: "NO_DIV",
371 description: Some(
372 "Internal RNG clock after divider is similar to incoming RNG clock",
373 ),
374 value: 0,
375 },
376 EnumVariant {
377 name: "DIV_2_1",
378 description: Some(
379 "Divide RNG clock by 2^1",
380 ),
381 value: 1,
382 },
383 EnumVariant {
384 name: "DIV_2_2",
385 description: Some(
386 "Divide RNG clock by 2^2",
387 ),
388 value: 2,
389 },
390 EnumVariant {
391 name: "DIV_2_3",
392 description: Some(
393 "Divide RNG clock by 2^3",
394 ),
395 value: 3,
396 },
397 EnumVariant {
398 name: "DIV_2_4",
399 description: Some(
400 "Divide RNG clock by 2^4",
401 ),
402 value: 4,
403 },
404 EnumVariant {
405 name: "DIV_2_5",
406 description: Some(
407 "Divide RNG clock by 2^5",
408 ),
409 value: 5,
410 },
411 EnumVariant {
412 name: "DIV_2_6",
413 description: Some(
414 "Divide RNG clock by 2^6",
415 ),
416 value: 6,
417 },
418 EnumVariant {
419 name: "DIV_2_7",
420 description: Some(
421 "Divide RNG clock by 2^7",
422 ),
423 value: 7,
424 },
425 EnumVariant {
426 name: "DIV_2_8",
427 description: Some(
428 "Divide RNG clock by 2^8",
429 ),
430 value: 8,
431 },
432 EnumVariant {
433 name: "DIV_2_9",
434 description: Some(
435 "Divide RNG clock by 2^9",
436 ),
437 value: 9,
438 },
439 EnumVariant {
440 name: "DIV_2_10",
441 description: Some(
442 "Divide RNG clock by 2^10",
443 ),
444 value: 10,
445 },
446 EnumVariant {
447 name: "DIV_2_11",
448 description: Some(
449 "Divide RNG clock by 2^11",
450 ),
451 value: 11,
452 },
453 EnumVariant {
454 name: "DIV_2_12",
455 description: Some(
456 "Divide RNG clock by 2^12",
457 ),
458 value: 12,
459 },
460 EnumVariant {
461 name: "DIV_2_13",
462 description: Some(
463 "Divide RNG clock by 2^13",
464 ),
465 value: 13,
466 },
467 EnumVariant {
468 name: "DIV_2_14",
469 description: Some(
470 "Divide RNG clock by 2^14",
471 ),
472 value: 14,
473 },
474 EnumVariant {
475 name: "DIV_2_15",
476 description: Some(
477 "Divide RNG clock by 2^15",
478 ),
479 value: 15,
480 },
481 ],
482 },
483 Enum {
484 name: "Htcfg",
485 description: None,
486 bit_size: 32,
487 variants: &[
488 EnumVariant {
489 name: "RECOMMENDED",
490 description: Some(
491 "Recommended value for RNG certification (0x0000_AA74)",
492 ),
493 value: 43636,
494 },
495 EnumVariant {
496 name: "MAGIC",
497 description: Some(
498 "Magic number to be written before any write (0x1759_0ABC)",
499 ),
500 value: 391711420,
501 },
502 ],
503 },
504 Enum {
505 name: "Nistc",
506 description: None,
507 bit_size: 1,
508 variants: &[
509 EnumVariant {
510 name: "DEFAULT",
511 description: Some(
512 "Hardware default values for NIST compliant RNG. In this configuration per 128-bit output two conditioning loops are performed and 256 bits of noise source are used",
513 ),
514 value: 0,
515 },
516 EnumVariant {
517 name: "CUSTOM",
518 description: Some(
519 "Custom values for NIST compliant RNG",
520 ),
521 value: 1,
522 },
523 ],
524 },
525 Enum {
526 name: "RngConfig1",
527 description: None,
528 bit_size: 6,
529 variants: &[
530 EnumVariant {
531 name: "CONFIG_A",
532 description: Some(
533 "Recommended value for config A (NIST certifiable)",
534 ),
535 value: 15,
536 },
537 EnumVariant {
538 name: "CONFIG_B",
539 description: Some(
540 "Recommended value for config B (not NIST certifiable)",
541 ),
542 value: 24,
543 },
544 ],
545 },
546 Enum {
547 name: "RngConfig2",
548 description: None,
549 bit_size: 3,
550 variants: &[
551 EnumVariant {
552 name: "CONFIG_A_B",
553 description: Some(
554 "Recommended value for config A and B",
555 ),
556 value: 0,
557 },
558 ],
559 },
560 Enum {
561 name: "RngConfig3",
562 description: None,
563 bit_size: 4,
564 variants: &[
565 EnumVariant {
566 name: "CONFIG_B",
567 description: Some(
568 "Recommended value for config B (not NIST certifiable)",
569 ),
570 value: 0,
571 },
572 EnumVariant {
573 name: "CONFIG_A",
574 description: Some(
575 "Recommended value for config A (NIST certifiable)",
576 ),
577 value: 13,
578 },
579 ],
580 },
581 ],
582};
583