1 | |
2 | use crate::metadata::ir::*; |
3 | pub(crate) static REGISTERS: IR = IR { |
4 | blocks: &[ |
5 | Block { |
6 | name: "Rtc" , |
7 | extends: None, |
8 | description: Some( |
9 | "Real-time clock" , |
10 | ), |
11 | items: &[ |
12 | BlockItem { |
13 | name: "tr" , |
14 | description: Some( |
15 | "Time register" , |
16 | ), |
17 | array: None, |
18 | byte_offset: 0x0, |
19 | inner: BlockItemInner::Register( |
20 | Register { |
21 | access: Access::ReadWrite, |
22 | bit_size: 32, |
23 | fieldset: Some( |
24 | "Tr" , |
25 | ), |
26 | }, |
27 | ), |
28 | }, |
29 | BlockItem { |
30 | name: "dr" , |
31 | description: Some( |
32 | "Date register" , |
33 | ), |
34 | array: None, |
35 | byte_offset: 0x4, |
36 | inner: BlockItemInner::Register( |
37 | Register { |
38 | access: Access::ReadWrite, |
39 | bit_size: 32, |
40 | fieldset: Some( |
41 | "Dr" , |
42 | ), |
43 | }, |
44 | ), |
45 | }, |
46 | BlockItem { |
47 | name: "ssr" , |
48 | description: Some( |
49 | "Sub second register" , |
50 | ), |
51 | array: None, |
52 | byte_offset: 0x8, |
53 | inner: BlockItemInner::Register( |
54 | Register { |
55 | access: Access::Read, |
56 | bit_size: 32, |
57 | fieldset: Some( |
58 | "Ssr" , |
59 | ), |
60 | }, |
61 | ), |
62 | }, |
63 | BlockItem { |
64 | name: "icsr" , |
65 | description: Some( |
66 | "Initialization control and status register" , |
67 | ), |
68 | array: None, |
69 | byte_offset: 0xc, |
70 | inner: BlockItemInner::Register( |
71 | Register { |
72 | access: Access::ReadWrite, |
73 | bit_size: 32, |
74 | fieldset: Some( |
75 | "Icsr" , |
76 | ), |
77 | }, |
78 | ), |
79 | }, |
80 | BlockItem { |
81 | name: "prer" , |
82 | description: Some( |
83 | "Prescaler register" , |
84 | ), |
85 | array: None, |
86 | byte_offset: 0x10, |
87 | inner: BlockItemInner::Register( |
88 | Register { |
89 | access: Access::ReadWrite, |
90 | bit_size: 32, |
91 | fieldset: Some( |
92 | "Prer" , |
93 | ), |
94 | }, |
95 | ), |
96 | }, |
97 | BlockItem { |
98 | name: "wutr" , |
99 | description: Some( |
100 | "Wakeup timer register" , |
101 | ), |
102 | array: None, |
103 | byte_offset: 0x14, |
104 | inner: BlockItemInner::Register( |
105 | Register { |
106 | access: Access::ReadWrite, |
107 | bit_size: 32, |
108 | fieldset: Some( |
109 | "Wutr" , |
110 | ), |
111 | }, |
112 | ), |
113 | }, |
114 | BlockItem { |
115 | name: "cr" , |
116 | description: Some( |
117 | "Control register" , |
118 | ), |
119 | array: None, |
120 | byte_offset: 0x18, |
121 | inner: BlockItemInner::Register( |
122 | Register { |
123 | access: Access::ReadWrite, |
124 | bit_size: 32, |
125 | fieldset: Some( |
126 | "Cr" , |
127 | ), |
128 | }, |
129 | ), |
130 | }, |
131 | BlockItem { |
132 | name: "privcr" , |
133 | description: Some( |
134 | "Privilege mode control register" , |
135 | ), |
136 | array: None, |
137 | byte_offset: 0x1c, |
138 | inner: BlockItemInner::Register( |
139 | Register { |
140 | access: Access::ReadWrite, |
141 | bit_size: 32, |
142 | fieldset: Some( |
143 | "Privcr" , |
144 | ), |
145 | }, |
146 | ), |
147 | }, |
148 | BlockItem { |
149 | name: "seccfgr" , |
150 | description: Some( |
151 | "Secure mode control register" , |
152 | ), |
153 | array: None, |
154 | byte_offset: 0x20, |
155 | inner: BlockItemInner::Register( |
156 | Register { |
157 | access: Access::ReadWrite, |
158 | bit_size: 32, |
159 | fieldset: Some( |
160 | "Seccfgr" , |
161 | ), |
162 | }, |
163 | ), |
164 | }, |
165 | BlockItem { |
166 | name: "wpr" , |
167 | description: Some( |
168 | "Write protection register" , |
169 | ), |
170 | array: None, |
171 | byte_offset: 0x24, |
172 | inner: BlockItemInner::Register( |
173 | Register { |
174 | access: Access::Write, |
175 | bit_size: 32, |
176 | fieldset: Some( |
177 | "Wpr" , |
178 | ), |
179 | }, |
180 | ), |
181 | }, |
182 | BlockItem { |
183 | name: "calr" , |
184 | description: Some( |
185 | "Calibration register" , |
186 | ), |
187 | array: None, |
188 | byte_offset: 0x28, |
189 | inner: BlockItemInner::Register( |
190 | Register { |
191 | access: Access::ReadWrite, |
192 | bit_size: 32, |
193 | fieldset: Some( |
194 | "Calr" , |
195 | ), |
196 | }, |
197 | ), |
198 | }, |
199 | BlockItem { |
200 | name: "shiftr" , |
201 | description: Some( |
202 | "Shift control register" , |
203 | ), |
204 | array: None, |
205 | byte_offset: 0x2c, |
206 | inner: BlockItemInner::Register( |
207 | Register { |
208 | access: Access::Write, |
209 | bit_size: 32, |
210 | fieldset: Some( |
211 | "Shiftr" , |
212 | ), |
213 | }, |
214 | ), |
215 | }, |
216 | BlockItem { |
217 | name: "tstr" , |
218 | description: Some( |
219 | "Timestamp time register" , |
220 | ), |
221 | array: None, |
222 | byte_offset: 0x30, |
223 | inner: BlockItemInner::Register( |
224 | Register { |
225 | access: Access::Read, |
226 | bit_size: 32, |
227 | fieldset: Some( |
228 | "Tstr" , |
229 | ), |
230 | }, |
231 | ), |
232 | }, |
233 | BlockItem { |
234 | name: "tsdr" , |
235 | description: Some( |
236 | "Timestamp date register" , |
237 | ), |
238 | array: None, |
239 | byte_offset: 0x34, |
240 | inner: BlockItemInner::Register( |
241 | Register { |
242 | access: Access::Read, |
243 | bit_size: 32, |
244 | fieldset: Some( |
245 | "Tsdr" , |
246 | ), |
247 | }, |
248 | ), |
249 | }, |
250 | BlockItem { |
251 | name: "tsssr" , |
252 | description: Some( |
253 | "Timestamp sub second register" , |
254 | ), |
255 | array: None, |
256 | byte_offset: 0x38, |
257 | inner: BlockItemInner::Register( |
258 | Register { |
259 | access: Access::Read, |
260 | bit_size: 32, |
261 | fieldset: Some( |
262 | "Tsssr" , |
263 | ), |
264 | }, |
265 | ), |
266 | }, |
267 | BlockItem { |
268 | name: "alrmr" , |
269 | description: Some( |
270 | "Alarm register" , |
271 | ), |
272 | array: Some( |
273 | Array::Regular( |
274 | RegularArray { |
275 | len: 2, |
276 | stride: 8, |
277 | }, |
278 | ), |
279 | ), |
280 | byte_offset: 0x40, |
281 | inner: BlockItemInner::Register( |
282 | Register { |
283 | access: Access::ReadWrite, |
284 | bit_size: 32, |
285 | fieldset: Some( |
286 | "Alrmr" , |
287 | ), |
288 | }, |
289 | ), |
290 | }, |
291 | BlockItem { |
292 | name: "alrmssr" , |
293 | description: Some( |
294 | "Alarm sub second register" , |
295 | ), |
296 | array: Some( |
297 | Array::Regular( |
298 | RegularArray { |
299 | len: 2, |
300 | stride: 8, |
301 | }, |
302 | ), |
303 | ), |
304 | byte_offset: 0x44, |
305 | inner: BlockItemInner::Register( |
306 | Register { |
307 | access: Access::ReadWrite, |
308 | bit_size: 32, |
309 | fieldset: Some( |
310 | "Alrmssr" , |
311 | ), |
312 | }, |
313 | ), |
314 | }, |
315 | BlockItem { |
316 | name: "sr" , |
317 | description: Some( |
318 | "Status register" , |
319 | ), |
320 | array: None, |
321 | byte_offset: 0x50, |
322 | inner: BlockItemInner::Register( |
323 | Register { |
324 | access: Access::Read, |
325 | bit_size: 32, |
326 | fieldset: Some( |
327 | "Sr" , |
328 | ), |
329 | }, |
330 | ), |
331 | }, |
332 | BlockItem { |
333 | name: "misr" , |
334 | description: Some( |
335 | "Masked interrupt status register" , |
336 | ), |
337 | array: None, |
338 | byte_offset: 0x54, |
339 | inner: BlockItemInner::Register( |
340 | Register { |
341 | access: Access::Read, |
342 | bit_size: 32, |
343 | fieldset: Some( |
344 | "Misr" , |
345 | ), |
346 | }, |
347 | ), |
348 | }, |
349 | BlockItem { |
350 | name: "smisr" , |
351 | description: Some( |
352 | "Secure masked interrupt status register" , |
353 | ), |
354 | array: None, |
355 | byte_offset: 0x58, |
356 | inner: BlockItemInner::Register( |
357 | Register { |
358 | access: Access::Read, |
359 | bit_size: 32, |
360 | fieldset: Some( |
361 | "Smisr" , |
362 | ), |
363 | }, |
364 | ), |
365 | }, |
366 | BlockItem { |
367 | name: "scr" , |
368 | description: Some( |
369 | "Status clear register" , |
370 | ), |
371 | array: None, |
372 | byte_offset: 0x5c, |
373 | inner: BlockItemInner::Register( |
374 | Register { |
375 | access: Access::Write, |
376 | bit_size: 32, |
377 | fieldset: Some( |
378 | "Scr" , |
379 | ), |
380 | }, |
381 | ), |
382 | }, |
383 | BlockItem { |
384 | name: "alrbinr" , |
385 | description: Some( |
386 | "Alarm binary mode register" , |
387 | ), |
388 | array: Some( |
389 | Array::Regular( |
390 | RegularArray { |
391 | len: 2, |
392 | stride: 4, |
393 | }, |
394 | ), |
395 | ), |
396 | byte_offset: 0x70, |
397 | inner: BlockItemInner::Register( |
398 | Register { |
399 | access: Access::ReadWrite, |
400 | bit_size: 32, |
401 | fieldset: Some( |
402 | "Alrbinr" , |
403 | ), |
404 | }, |
405 | ), |
406 | }, |
407 | ], |
408 | }, |
409 | ], |
410 | fieldsets: &[ |
411 | FieldSet { |
412 | name: "Alrbinr" , |
413 | extends: None, |
414 | description: Some( |
415 | "RTC alarm A binary mode register" , |
416 | ), |
417 | bit_size: 32, |
418 | fields: &[ |
419 | Field { |
420 | name: "ss" , |
421 | description: Some( |
422 | "Synchronous counter alarm value in Binary mode" , |
423 | ), |
424 | bit_offset: BitOffset::Regular( |
425 | RegularBitOffset { |
426 | offset: 0, |
427 | }, |
428 | ), |
429 | bit_size: 32, |
430 | array: None, |
431 | enumm: None, |
432 | }, |
433 | ], |
434 | }, |
435 | FieldSet { |
436 | name: "Alrmr" , |
437 | extends: None, |
438 | description: Some( |
439 | "Alarm register" , |
440 | ), |
441 | bit_size: 32, |
442 | fields: &[ |
443 | Field { |
444 | name: "su" , |
445 | description: Some( |
446 | "Second units in BCD format" , |
447 | ), |
448 | bit_offset: BitOffset::Regular( |
449 | RegularBitOffset { |
450 | offset: 0, |
451 | }, |
452 | ), |
453 | bit_size: 4, |
454 | array: None, |
455 | enumm: None, |
456 | }, |
457 | Field { |
458 | name: "st" , |
459 | description: Some( |
460 | "Second tens in BCD format" , |
461 | ), |
462 | bit_offset: BitOffset::Regular( |
463 | RegularBitOffset { |
464 | offset: 4, |
465 | }, |
466 | ), |
467 | bit_size: 3, |
468 | array: None, |
469 | enumm: None, |
470 | }, |
471 | Field { |
472 | name: "msk1" , |
473 | description: Some( |
474 | "Alarm A seconds mask" , |
475 | ), |
476 | bit_offset: BitOffset::Regular( |
477 | RegularBitOffset { |
478 | offset: 7, |
479 | }, |
480 | ), |
481 | bit_size: 1, |
482 | array: None, |
483 | enumm: Some( |
484 | "AlrmrMsk" , |
485 | ), |
486 | }, |
487 | Field { |
488 | name: "mnu" , |
489 | description: Some( |
490 | "Minute units in BCD format" , |
491 | ), |
492 | bit_offset: BitOffset::Regular( |
493 | RegularBitOffset { |
494 | offset: 8, |
495 | }, |
496 | ), |
497 | bit_size: 4, |
498 | array: None, |
499 | enumm: None, |
500 | }, |
501 | Field { |
502 | name: "mnt" , |
503 | description: Some( |
504 | "Minute tens in BCD format" , |
505 | ), |
506 | bit_offset: BitOffset::Regular( |
507 | RegularBitOffset { |
508 | offset: 12, |
509 | }, |
510 | ), |
511 | bit_size: 3, |
512 | array: None, |
513 | enumm: None, |
514 | }, |
515 | Field { |
516 | name: "msk2" , |
517 | description: Some( |
518 | "Alarm A minutes mask" , |
519 | ), |
520 | bit_offset: BitOffset::Regular( |
521 | RegularBitOffset { |
522 | offset: 15, |
523 | }, |
524 | ), |
525 | bit_size: 1, |
526 | array: None, |
527 | enumm: Some( |
528 | "AlrmrMsk" , |
529 | ), |
530 | }, |
531 | Field { |
532 | name: "hu" , |
533 | description: Some( |
534 | "Hour units in BCD format" , |
535 | ), |
536 | bit_offset: BitOffset::Regular( |
537 | RegularBitOffset { |
538 | offset: 16, |
539 | }, |
540 | ), |
541 | bit_size: 4, |
542 | array: None, |
543 | enumm: None, |
544 | }, |
545 | Field { |
546 | name: "ht" , |
547 | description: Some( |
548 | "Hour tens in BCD format" , |
549 | ), |
550 | bit_offset: BitOffset::Regular( |
551 | RegularBitOffset { |
552 | offset: 20, |
553 | }, |
554 | ), |
555 | bit_size: 2, |
556 | array: None, |
557 | enumm: None, |
558 | }, |
559 | Field { |
560 | name: "pm" , |
561 | description: Some( |
562 | "AM/PM notation" , |
563 | ), |
564 | bit_offset: BitOffset::Regular( |
565 | RegularBitOffset { |
566 | offset: 22, |
567 | }, |
568 | ), |
569 | bit_size: 1, |
570 | array: None, |
571 | enumm: Some( |
572 | "AlrmrPm" , |
573 | ), |
574 | }, |
575 | Field { |
576 | name: "msk3" , |
577 | description: Some( |
578 | "Alarm A hours mask" , |
579 | ), |
580 | bit_offset: BitOffset::Regular( |
581 | RegularBitOffset { |
582 | offset: 23, |
583 | }, |
584 | ), |
585 | bit_size: 1, |
586 | array: None, |
587 | enumm: Some( |
588 | "AlrmrMsk" , |
589 | ), |
590 | }, |
591 | Field { |
592 | name: "du" , |
593 | description: Some( |
594 | "Date units or day in BCD format" , |
595 | ), |
596 | bit_offset: BitOffset::Regular( |
597 | RegularBitOffset { |
598 | offset: 24, |
599 | }, |
600 | ), |
601 | bit_size: 4, |
602 | array: None, |
603 | enumm: None, |
604 | }, |
605 | Field { |
606 | name: "dt" , |
607 | description: Some( |
608 | "Date tens in BCD format" , |
609 | ), |
610 | bit_offset: BitOffset::Regular( |
611 | RegularBitOffset { |
612 | offset: 28, |
613 | }, |
614 | ), |
615 | bit_size: 2, |
616 | array: None, |
617 | enumm: None, |
618 | }, |
619 | Field { |
620 | name: "wdsel" , |
621 | description: Some( |
622 | "Week day selection" , |
623 | ), |
624 | bit_offset: BitOffset::Regular( |
625 | RegularBitOffset { |
626 | offset: 30, |
627 | }, |
628 | ), |
629 | bit_size: 1, |
630 | array: None, |
631 | enumm: Some( |
632 | "AlrmrWdsel" , |
633 | ), |
634 | }, |
635 | Field { |
636 | name: "msk4" , |
637 | description: Some( |
638 | "Alarm A date mask" , |
639 | ), |
640 | bit_offset: BitOffset::Regular( |
641 | RegularBitOffset { |
642 | offset: 31, |
643 | }, |
644 | ), |
645 | bit_size: 1, |
646 | array: None, |
647 | enumm: Some( |
648 | "AlrmrMsk" , |
649 | ), |
650 | }, |
651 | ], |
652 | }, |
653 | FieldSet { |
654 | name: "Alrmssr" , |
655 | extends: None, |
656 | description: Some( |
657 | "Alarm sub second register" , |
658 | ), |
659 | bit_size: 32, |
660 | fields: &[ |
661 | Field { |
662 | name: "ss" , |
663 | description: Some( |
664 | "Sub seconds value" , |
665 | ), |
666 | bit_offset: BitOffset::Regular( |
667 | RegularBitOffset { |
668 | offset: 0, |
669 | }, |
670 | ), |
671 | bit_size: 15, |
672 | array: None, |
673 | enumm: None, |
674 | }, |
675 | Field { |
676 | name: "maskss" , |
677 | description: Some( |
678 | "Mask the most-significant bits starting at this bit" , |
679 | ), |
680 | bit_offset: BitOffset::Regular( |
681 | RegularBitOffset { |
682 | offset: 24, |
683 | }, |
684 | ), |
685 | bit_size: 6, |
686 | array: None, |
687 | enumm: None, |
688 | }, |
689 | Field { |
690 | name: "ssclr" , |
691 | description: Some( |
692 | "Clear synchronous counter on alarm (Binary mode only)" , |
693 | ), |
694 | bit_offset: BitOffset::Regular( |
695 | RegularBitOffset { |
696 | offset: 31, |
697 | }, |
698 | ), |
699 | bit_size: 1, |
700 | array: None, |
701 | enumm: Some( |
702 | "AlrmssrSsclr" , |
703 | ), |
704 | }, |
705 | ], |
706 | }, |
707 | FieldSet { |
708 | name: "Calr" , |
709 | extends: None, |
710 | description: Some( |
711 | "Calibration register" , |
712 | ), |
713 | bit_size: 32, |
714 | fields: &[ |
715 | Field { |
716 | name: "calm" , |
717 | description: Some( |
718 | "Calibration minus" , |
719 | ), |
720 | bit_offset: BitOffset::Regular( |
721 | RegularBitOffset { |
722 | offset: 0, |
723 | }, |
724 | ), |
725 | bit_size: 9, |
726 | array: None, |
727 | enumm: None, |
728 | }, |
729 | Field { |
730 | name: "lpcal" , |
731 | description: Some( |
732 | "Calibration low-power mode" , |
733 | ), |
734 | bit_offset: BitOffset::Regular( |
735 | RegularBitOffset { |
736 | offset: 12, |
737 | }, |
738 | ), |
739 | bit_size: 1, |
740 | array: None, |
741 | enumm: Some( |
742 | "Lpcal" , |
743 | ), |
744 | }, |
745 | Field { |
746 | name: "calw16" , |
747 | description: Some( |
748 | "Use a 16-second calibration cycle period" , |
749 | ), |
750 | bit_offset: BitOffset::Regular( |
751 | RegularBitOffset { |
752 | offset: 13, |
753 | }, |
754 | ), |
755 | bit_size: 1, |
756 | array: None, |
757 | enumm: Some( |
758 | "Calw16" , |
759 | ), |
760 | }, |
761 | Field { |
762 | name: "calw8" , |
763 | description: Some( |
764 | "Use an 8-second calibration cycle period" , |
765 | ), |
766 | bit_offset: BitOffset::Regular( |
767 | RegularBitOffset { |
768 | offset: 14, |
769 | }, |
770 | ), |
771 | bit_size: 1, |
772 | array: None, |
773 | enumm: Some( |
774 | "Calw8" , |
775 | ), |
776 | }, |
777 | Field { |
778 | name: "calp" , |
779 | description: Some( |
780 | "Increase frequency of RTC by 488.5 ppm" , |
781 | ), |
782 | bit_offset: BitOffset::Regular( |
783 | RegularBitOffset { |
784 | offset: 15, |
785 | }, |
786 | ), |
787 | bit_size: 1, |
788 | array: None, |
789 | enumm: Some( |
790 | "Calp" , |
791 | ), |
792 | }, |
793 | ], |
794 | }, |
795 | FieldSet { |
796 | name: "Cr" , |
797 | extends: None, |
798 | description: Some( |
799 | "Control register" , |
800 | ), |
801 | bit_size: 32, |
802 | fields: &[ |
803 | Field { |
804 | name: "wucksel" , |
805 | description: Some( |
806 | "Wakeup clock selection" , |
807 | ), |
808 | bit_offset: BitOffset::Regular( |
809 | RegularBitOffset { |
810 | offset: 0, |
811 | }, |
812 | ), |
813 | bit_size: 3, |
814 | array: None, |
815 | enumm: Some( |
816 | "Wucksel" , |
817 | ), |
818 | }, |
819 | Field { |
820 | name: "tsedge" , |
821 | description: Some( |
822 | "Timestamp event active edge" , |
823 | ), |
824 | bit_offset: BitOffset::Regular( |
825 | RegularBitOffset { |
826 | offset: 3, |
827 | }, |
828 | ), |
829 | bit_size: 1, |
830 | array: None, |
831 | enumm: Some( |
832 | "Tsedge" , |
833 | ), |
834 | }, |
835 | Field { |
836 | name: "refckon" , |
837 | description: Some( |
838 | "RTC_REFIN reference clock detection enable (50 or 60 Hz)" , |
839 | ), |
840 | bit_offset: BitOffset::Regular( |
841 | RegularBitOffset { |
842 | offset: 4, |
843 | }, |
844 | ), |
845 | bit_size: 1, |
846 | array: None, |
847 | enumm: None, |
848 | }, |
849 | Field { |
850 | name: "bypshad" , |
851 | description: Some( |
852 | "Bypass the shadow registers" , |
853 | ), |
854 | bit_offset: BitOffset::Regular( |
855 | RegularBitOffset { |
856 | offset: 5, |
857 | }, |
858 | ), |
859 | bit_size: 1, |
860 | array: None, |
861 | enumm: None, |
862 | }, |
863 | Field { |
864 | name: "fmt" , |
865 | description: Some( |
866 | "Hour format" , |
867 | ), |
868 | bit_offset: BitOffset::Regular( |
869 | RegularBitOffset { |
870 | offset: 6, |
871 | }, |
872 | ), |
873 | bit_size: 1, |
874 | array: None, |
875 | enumm: Some( |
876 | "Fmt" , |
877 | ), |
878 | }, |
879 | Field { |
880 | name: "ssruie" , |
881 | description: Some( |
882 | "SSR underflow interrupt enable" , |
883 | ), |
884 | bit_offset: BitOffset::Regular( |
885 | RegularBitOffset { |
886 | offset: 7, |
887 | }, |
888 | ), |
889 | bit_size: 1, |
890 | array: None, |
891 | enumm: None, |
892 | }, |
893 | Field { |
894 | name: "alre" , |
895 | description: Some( |
896 | "Alarm enable" , |
897 | ), |
898 | bit_offset: BitOffset::Regular( |
899 | RegularBitOffset { |
900 | offset: 8, |
901 | }, |
902 | ), |
903 | bit_size: 1, |
904 | array: Some( |
905 | Array::Regular( |
906 | RegularArray { |
907 | len: 2, |
908 | stride: 1, |
909 | }, |
910 | ), |
911 | ), |
912 | enumm: None, |
913 | }, |
914 | Field { |
915 | name: "wute" , |
916 | description: Some( |
917 | "Wakeup timer enable" , |
918 | ), |
919 | bit_offset: BitOffset::Regular( |
920 | RegularBitOffset { |
921 | offset: 10, |
922 | }, |
923 | ), |
924 | bit_size: 1, |
925 | array: None, |
926 | enumm: None, |
927 | }, |
928 | Field { |
929 | name: "tse" , |
930 | description: Some( |
931 | "Timestamp enable" , |
932 | ), |
933 | bit_offset: BitOffset::Regular( |
934 | RegularBitOffset { |
935 | offset: 11, |
936 | }, |
937 | ), |
938 | bit_size: 1, |
939 | array: None, |
940 | enumm: None, |
941 | }, |
942 | Field { |
943 | name: "alrie" , |
944 | description: Some( |
945 | "Alarm interrupt enable" , |
946 | ), |
947 | bit_offset: BitOffset::Regular( |
948 | RegularBitOffset { |
949 | offset: 12, |
950 | }, |
951 | ), |
952 | bit_size: 1, |
953 | array: Some( |
954 | Array::Regular( |
955 | RegularArray { |
956 | len: 2, |
957 | stride: 1, |
958 | }, |
959 | ), |
960 | ), |
961 | enumm: None, |
962 | }, |
963 | Field { |
964 | name: "wutie" , |
965 | description: Some( |
966 | "Wakeup timer interrupt enable" , |
967 | ), |
968 | bit_offset: BitOffset::Regular( |
969 | RegularBitOffset { |
970 | offset: 14, |
971 | }, |
972 | ), |
973 | bit_size: 1, |
974 | array: None, |
975 | enumm: None, |
976 | }, |
977 | Field { |
978 | name: "tsie" , |
979 | description: Some( |
980 | "Timestamp interrupt enable" , |
981 | ), |
982 | bit_offset: BitOffset::Regular( |
983 | RegularBitOffset { |
984 | offset: 15, |
985 | }, |
986 | ), |
987 | bit_size: 1, |
988 | array: None, |
989 | enumm: None, |
990 | }, |
991 | Field { |
992 | name: "add1h" , |
993 | description: Some( |
994 | "Add 1 hour (summer time change)" , |
995 | ), |
996 | bit_offset: BitOffset::Regular( |
997 | RegularBitOffset { |
998 | offset: 16, |
999 | }, |
1000 | ), |
1001 | bit_size: 1, |
1002 | array: None, |
1003 | enumm: None, |
1004 | }, |
1005 | Field { |
1006 | name: "sub1h" , |
1007 | description: Some( |
1008 | "Subtract 1 hour (winter time change)" , |
1009 | ), |
1010 | bit_offset: BitOffset::Regular( |
1011 | RegularBitOffset { |
1012 | offset: 17, |
1013 | }, |
1014 | ), |
1015 | bit_size: 1, |
1016 | array: None, |
1017 | enumm: None, |
1018 | }, |
1019 | Field { |
1020 | name: "bkp" , |
1021 | description: Some( |
1022 | "Backup" , |
1023 | ), |
1024 | bit_offset: BitOffset::Regular( |
1025 | RegularBitOffset { |
1026 | offset: 18, |
1027 | }, |
1028 | ), |
1029 | bit_size: 1, |
1030 | array: None, |
1031 | enumm: None, |
1032 | }, |
1033 | Field { |
1034 | name: "cosel" , |
1035 | description: Some( |
1036 | "Calibration output selection" , |
1037 | ), |
1038 | bit_offset: BitOffset::Regular( |
1039 | RegularBitOffset { |
1040 | offset: 19, |
1041 | }, |
1042 | ), |
1043 | bit_size: 1, |
1044 | array: None, |
1045 | enumm: Some( |
1046 | "Cosel" , |
1047 | ), |
1048 | }, |
1049 | Field { |
1050 | name: "pol" , |
1051 | description: Some( |
1052 | "Output polarity" , |
1053 | ), |
1054 | bit_offset: BitOffset::Regular( |
1055 | RegularBitOffset { |
1056 | offset: 20, |
1057 | }, |
1058 | ), |
1059 | bit_size: 1, |
1060 | array: None, |
1061 | enumm: Some( |
1062 | "Pol" , |
1063 | ), |
1064 | }, |
1065 | Field { |
1066 | name: "osel" , |
1067 | description: Some( |
1068 | "Output selection" , |
1069 | ), |
1070 | bit_offset: BitOffset::Regular( |
1071 | RegularBitOffset { |
1072 | offset: 21, |
1073 | }, |
1074 | ), |
1075 | bit_size: 2, |
1076 | array: None, |
1077 | enumm: Some( |
1078 | "Osel" , |
1079 | ), |
1080 | }, |
1081 | Field { |
1082 | name: "coe" , |
1083 | description: Some( |
1084 | "Calibration output enable" , |
1085 | ), |
1086 | bit_offset: BitOffset::Regular( |
1087 | RegularBitOffset { |
1088 | offset: 23, |
1089 | }, |
1090 | ), |
1091 | bit_size: 1, |
1092 | array: None, |
1093 | enumm: None, |
1094 | }, |
1095 | Field { |
1096 | name: "itse" , |
1097 | description: Some( |
1098 | "Timestamp on internal event enable" , |
1099 | ), |
1100 | bit_offset: BitOffset::Regular( |
1101 | RegularBitOffset { |
1102 | offset: 24, |
1103 | }, |
1104 | ), |
1105 | bit_size: 1, |
1106 | array: None, |
1107 | enumm: None, |
1108 | }, |
1109 | Field { |
1110 | name: "tampts" , |
1111 | description: Some( |
1112 | "Activate timestamp on tamper detection event" , |
1113 | ), |
1114 | bit_offset: BitOffset::Regular( |
1115 | RegularBitOffset { |
1116 | offset: 25, |
1117 | }, |
1118 | ), |
1119 | bit_size: 1, |
1120 | array: None, |
1121 | enumm: None, |
1122 | }, |
1123 | Field { |
1124 | name: "tampoe" , |
1125 | description: Some( |
1126 | "Tamper detection output enable on TAMPALRM" , |
1127 | ), |
1128 | bit_offset: BitOffset::Regular( |
1129 | RegularBitOffset { |
1130 | offset: 26, |
1131 | }, |
1132 | ), |
1133 | bit_size: 1, |
1134 | array: None, |
1135 | enumm: None, |
1136 | }, |
1137 | Field { |
1138 | name: "alrfclr" , |
1139 | description: Some( |
1140 | "ALRFCLR" , |
1141 | ), |
1142 | bit_offset: BitOffset::Regular( |
1143 | RegularBitOffset { |
1144 | offset: 27, |
1145 | }, |
1146 | ), |
1147 | bit_size: 1, |
1148 | array: Some( |
1149 | Array::Regular( |
1150 | RegularArray { |
1151 | len: 2, |
1152 | stride: 1, |
1153 | }, |
1154 | ), |
1155 | ), |
1156 | enumm: None, |
1157 | }, |
1158 | Field { |
1159 | name: "tampalrm_pu" , |
1160 | description: Some( |
1161 | "TAMPALRM pull-up enable" , |
1162 | ), |
1163 | bit_offset: BitOffset::Regular( |
1164 | RegularBitOffset { |
1165 | offset: 29, |
1166 | }, |
1167 | ), |
1168 | bit_size: 1, |
1169 | array: None, |
1170 | enumm: None, |
1171 | }, |
1172 | Field { |
1173 | name: "tampalrm_type" , |
1174 | description: Some( |
1175 | "TAMPALRM output type" , |
1176 | ), |
1177 | bit_offset: BitOffset::Regular( |
1178 | RegularBitOffset { |
1179 | offset: 30, |
1180 | }, |
1181 | ), |
1182 | bit_size: 1, |
1183 | array: None, |
1184 | enumm: Some( |
1185 | "TampalrmType" , |
1186 | ), |
1187 | }, |
1188 | Field { |
1189 | name: "out2en" , |
1190 | description: Some( |
1191 | "RTC_OUT2 output enable" , |
1192 | ), |
1193 | bit_offset: BitOffset::Regular( |
1194 | RegularBitOffset { |
1195 | offset: 31, |
1196 | }, |
1197 | ), |
1198 | bit_size: 1, |
1199 | array: None, |
1200 | enumm: None, |
1201 | }, |
1202 | ], |
1203 | }, |
1204 | FieldSet { |
1205 | name: "Dr" , |
1206 | extends: None, |
1207 | description: Some( |
1208 | "Date register" , |
1209 | ), |
1210 | bit_size: 32, |
1211 | fields: &[ |
1212 | Field { |
1213 | name: "du" , |
1214 | description: Some( |
1215 | "Date units in BCD format" , |
1216 | ), |
1217 | bit_offset: BitOffset::Regular( |
1218 | RegularBitOffset { |
1219 | offset: 0, |
1220 | }, |
1221 | ), |
1222 | bit_size: 4, |
1223 | array: None, |
1224 | enumm: None, |
1225 | }, |
1226 | Field { |
1227 | name: "dt" , |
1228 | description: Some( |
1229 | "Date tens in BCD format" , |
1230 | ), |
1231 | bit_offset: BitOffset::Regular( |
1232 | RegularBitOffset { |
1233 | offset: 4, |
1234 | }, |
1235 | ), |
1236 | bit_size: 2, |
1237 | array: None, |
1238 | enumm: None, |
1239 | }, |
1240 | Field { |
1241 | name: "mu" , |
1242 | description: Some( |
1243 | "Month units in BCD format" , |
1244 | ), |
1245 | bit_offset: BitOffset::Regular( |
1246 | RegularBitOffset { |
1247 | offset: 8, |
1248 | }, |
1249 | ), |
1250 | bit_size: 4, |
1251 | array: None, |
1252 | enumm: None, |
1253 | }, |
1254 | Field { |
1255 | name: "mt" , |
1256 | description: Some( |
1257 | "Month tens in BCD format" , |
1258 | ), |
1259 | bit_offset: BitOffset::Regular( |
1260 | RegularBitOffset { |
1261 | offset: 12, |
1262 | }, |
1263 | ), |
1264 | bit_size: 1, |
1265 | array: None, |
1266 | enumm: None, |
1267 | }, |
1268 | Field { |
1269 | name: "wdu" , |
1270 | description: Some( |
1271 | "Week day units" , |
1272 | ), |
1273 | bit_offset: BitOffset::Regular( |
1274 | RegularBitOffset { |
1275 | offset: 13, |
1276 | }, |
1277 | ), |
1278 | bit_size: 3, |
1279 | array: None, |
1280 | enumm: None, |
1281 | }, |
1282 | Field { |
1283 | name: "yu" , |
1284 | description: Some( |
1285 | "Year units in BCD format" , |
1286 | ), |
1287 | bit_offset: BitOffset::Regular( |
1288 | RegularBitOffset { |
1289 | offset: 16, |
1290 | }, |
1291 | ), |
1292 | bit_size: 4, |
1293 | array: None, |
1294 | enumm: None, |
1295 | }, |
1296 | Field { |
1297 | name: "yt" , |
1298 | description: Some( |
1299 | "Year tens in BCD format" , |
1300 | ), |
1301 | bit_offset: BitOffset::Regular( |
1302 | RegularBitOffset { |
1303 | offset: 20, |
1304 | }, |
1305 | ), |
1306 | bit_size: 4, |
1307 | array: None, |
1308 | enumm: None, |
1309 | }, |
1310 | ], |
1311 | }, |
1312 | FieldSet { |
1313 | name: "Icsr" , |
1314 | extends: None, |
1315 | description: Some( |
1316 | "Initialization control and status register" , |
1317 | ), |
1318 | bit_size: 32, |
1319 | fields: &[ |
1320 | Field { |
1321 | name: "wutwf" , |
1322 | description: Some( |
1323 | "Wakeup timer write enabled" , |
1324 | ), |
1325 | bit_offset: BitOffset::Regular( |
1326 | RegularBitOffset { |
1327 | offset: 2, |
1328 | }, |
1329 | ), |
1330 | bit_size: 1, |
1331 | array: None, |
1332 | enumm: None, |
1333 | }, |
1334 | Field { |
1335 | name: "shpf" , |
1336 | description: Some( |
1337 | "Shift operation pending" , |
1338 | ), |
1339 | bit_offset: BitOffset::Regular( |
1340 | RegularBitOffset { |
1341 | offset: 3, |
1342 | }, |
1343 | ), |
1344 | bit_size: 1, |
1345 | array: None, |
1346 | enumm: None, |
1347 | }, |
1348 | Field { |
1349 | name: "inits" , |
1350 | description: Some( |
1351 | "Initialization status flag" , |
1352 | ), |
1353 | bit_offset: BitOffset::Regular( |
1354 | RegularBitOffset { |
1355 | offset: 4, |
1356 | }, |
1357 | ), |
1358 | bit_size: 1, |
1359 | array: None, |
1360 | enumm: None, |
1361 | }, |
1362 | Field { |
1363 | name: "rsf" , |
1364 | description: Some( |
1365 | "Registers synchronization flag" , |
1366 | ), |
1367 | bit_offset: BitOffset::Regular( |
1368 | RegularBitOffset { |
1369 | offset: 5, |
1370 | }, |
1371 | ), |
1372 | bit_size: 1, |
1373 | array: None, |
1374 | enumm: None, |
1375 | }, |
1376 | Field { |
1377 | name: "initf" , |
1378 | description: Some( |
1379 | "Initialization flag" , |
1380 | ), |
1381 | bit_offset: BitOffset::Regular( |
1382 | RegularBitOffset { |
1383 | offset: 6, |
1384 | }, |
1385 | ), |
1386 | bit_size: 1, |
1387 | array: None, |
1388 | enumm: None, |
1389 | }, |
1390 | Field { |
1391 | name: "init" , |
1392 | description: Some( |
1393 | "Enter Initialization mode" , |
1394 | ), |
1395 | bit_offset: BitOffset::Regular( |
1396 | RegularBitOffset { |
1397 | offset: 7, |
1398 | }, |
1399 | ), |
1400 | bit_size: 1, |
1401 | array: None, |
1402 | enumm: None, |
1403 | }, |
1404 | Field { |
1405 | name: "bin" , |
1406 | description: Some( |
1407 | "Binary mode" , |
1408 | ), |
1409 | bit_offset: BitOffset::Regular( |
1410 | RegularBitOffset { |
1411 | offset: 8, |
1412 | }, |
1413 | ), |
1414 | bit_size: 2, |
1415 | array: None, |
1416 | enumm: Some( |
1417 | "Bin" , |
1418 | ), |
1419 | }, |
1420 | Field { |
1421 | name: "bcdu" , |
1422 | description: Some( |
1423 | "BCD update" , |
1424 | ), |
1425 | bit_offset: BitOffset::Regular( |
1426 | RegularBitOffset { |
1427 | offset: 10, |
1428 | }, |
1429 | ), |
1430 | bit_size: 3, |
1431 | array: None, |
1432 | enumm: Some( |
1433 | "Bcdu" , |
1434 | ), |
1435 | }, |
1436 | Field { |
1437 | name: "recalpf" , |
1438 | description: Some( |
1439 | "Recalibration pending Flag" , |
1440 | ), |
1441 | bit_offset: BitOffset::Regular( |
1442 | RegularBitOffset { |
1443 | offset: 16, |
1444 | }, |
1445 | ), |
1446 | bit_size: 1, |
1447 | array: None, |
1448 | enumm: Some( |
1449 | "Recalpf" , |
1450 | ), |
1451 | }, |
1452 | ], |
1453 | }, |
1454 | FieldSet { |
1455 | name: "Misr" , |
1456 | extends: None, |
1457 | description: Some( |
1458 | "Masked interrupt status register" , |
1459 | ), |
1460 | bit_size: 32, |
1461 | fields: &[ |
1462 | Field { |
1463 | name: "alrmf" , |
1464 | description: Some( |
1465 | "Alarm masked flag" , |
1466 | ), |
1467 | bit_offset: BitOffset::Regular( |
1468 | RegularBitOffset { |
1469 | offset: 0, |
1470 | }, |
1471 | ), |
1472 | bit_size: 1, |
1473 | array: Some( |
1474 | Array::Regular( |
1475 | RegularArray { |
1476 | len: 2, |
1477 | stride: 1, |
1478 | }, |
1479 | ), |
1480 | ), |
1481 | enumm: Some( |
1482 | "Alrmf" , |
1483 | ), |
1484 | }, |
1485 | Field { |
1486 | name: "wutmf" , |
1487 | description: Some( |
1488 | "Wakeup timer masked flag" , |
1489 | ), |
1490 | bit_offset: BitOffset::Regular( |
1491 | RegularBitOffset { |
1492 | offset: 2, |
1493 | }, |
1494 | ), |
1495 | bit_size: 1, |
1496 | array: None, |
1497 | enumm: Some( |
1498 | "Wutmf" , |
1499 | ), |
1500 | }, |
1501 | Field { |
1502 | name: "tsmf" , |
1503 | description: Some( |
1504 | "Timestamp masked flag" , |
1505 | ), |
1506 | bit_offset: BitOffset::Regular( |
1507 | RegularBitOffset { |
1508 | offset: 3, |
1509 | }, |
1510 | ), |
1511 | bit_size: 1, |
1512 | array: None, |
1513 | enumm: Some( |
1514 | "Tsmf" , |
1515 | ), |
1516 | }, |
1517 | Field { |
1518 | name: "tsovmf" , |
1519 | description: Some( |
1520 | "Timestamp overflow masked flag" , |
1521 | ), |
1522 | bit_offset: BitOffset::Regular( |
1523 | RegularBitOffset { |
1524 | offset: 4, |
1525 | }, |
1526 | ), |
1527 | bit_size: 1, |
1528 | array: None, |
1529 | enumm: Some( |
1530 | "Tsovmf" , |
1531 | ), |
1532 | }, |
1533 | Field { |
1534 | name: "itsmf" , |
1535 | description: Some( |
1536 | "Internal timestamp masked flag" , |
1537 | ), |
1538 | bit_offset: BitOffset::Regular( |
1539 | RegularBitOffset { |
1540 | offset: 5, |
1541 | }, |
1542 | ), |
1543 | bit_size: 1, |
1544 | array: None, |
1545 | enumm: Some( |
1546 | "Itsmf" , |
1547 | ), |
1548 | }, |
1549 | Field { |
1550 | name: "ssrumf" , |
1551 | description: Some( |
1552 | "SSR underflow masked flag" , |
1553 | ), |
1554 | bit_offset: BitOffset::Regular( |
1555 | RegularBitOffset { |
1556 | offset: 6, |
1557 | }, |
1558 | ), |
1559 | bit_size: 1, |
1560 | array: None, |
1561 | enumm: Some( |
1562 | "Ssrumf" , |
1563 | ), |
1564 | }, |
1565 | ], |
1566 | }, |
1567 | FieldSet { |
1568 | name: "Prer" , |
1569 | extends: None, |
1570 | description: Some( |
1571 | "Prescaler register" , |
1572 | ), |
1573 | bit_size: 32, |
1574 | fields: &[ |
1575 | Field { |
1576 | name: "prediv_s" , |
1577 | description: Some( |
1578 | "Synchronous prescaler factor" , |
1579 | ), |
1580 | bit_offset: BitOffset::Regular( |
1581 | RegularBitOffset { |
1582 | offset: 0, |
1583 | }, |
1584 | ), |
1585 | bit_size: 15, |
1586 | array: None, |
1587 | enumm: None, |
1588 | }, |
1589 | Field { |
1590 | name: "prediv_a" , |
1591 | description: Some( |
1592 | "Asynchronous prescaler factor" , |
1593 | ), |
1594 | bit_offset: BitOffset::Regular( |
1595 | RegularBitOffset { |
1596 | offset: 16, |
1597 | }, |
1598 | ), |
1599 | bit_size: 7, |
1600 | array: None, |
1601 | enumm: None, |
1602 | }, |
1603 | ], |
1604 | }, |
1605 | FieldSet { |
1606 | name: "Privcr" , |
1607 | extends: None, |
1608 | description: Some( |
1609 | "Privilege mode control register" , |
1610 | ), |
1611 | bit_size: 32, |
1612 | fields: &[ |
1613 | Field { |
1614 | name: "alrpriv" , |
1615 | description: Some( |
1616 | "ALRPRIV" , |
1617 | ), |
1618 | bit_offset: BitOffset::Regular( |
1619 | RegularBitOffset { |
1620 | offset: 0, |
1621 | }, |
1622 | ), |
1623 | bit_size: 1, |
1624 | array: Some( |
1625 | Array::Regular( |
1626 | RegularArray { |
1627 | len: 2, |
1628 | stride: 1, |
1629 | }, |
1630 | ), |
1631 | ), |
1632 | enumm: None, |
1633 | }, |
1634 | Field { |
1635 | name: "wutpriv" , |
1636 | description: Some( |
1637 | "WUTPRIV" , |
1638 | ), |
1639 | bit_offset: BitOffset::Regular( |
1640 | RegularBitOffset { |
1641 | offset: 2, |
1642 | }, |
1643 | ), |
1644 | bit_size: 1, |
1645 | array: None, |
1646 | enumm: None, |
1647 | }, |
1648 | Field { |
1649 | name: "tspriv" , |
1650 | description: Some( |
1651 | "TSPRIV" , |
1652 | ), |
1653 | bit_offset: BitOffset::Regular( |
1654 | RegularBitOffset { |
1655 | offset: 3, |
1656 | }, |
1657 | ), |
1658 | bit_size: 1, |
1659 | array: None, |
1660 | enumm: None, |
1661 | }, |
1662 | Field { |
1663 | name: "calpriv" , |
1664 | description: Some( |
1665 | "CALPRIV" , |
1666 | ), |
1667 | bit_offset: BitOffset::Regular( |
1668 | RegularBitOffset { |
1669 | offset: 13, |
1670 | }, |
1671 | ), |
1672 | bit_size: 1, |
1673 | array: None, |
1674 | enumm: None, |
1675 | }, |
1676 | Field { |
1677 | name: "initpriv" , |
1678 | description: Some( |
1679 | "INITPRIV" , |
1680 | ), |
1681 | bit_offset: BitOffset::Regular( |
1682 | RegularBitOffset { |
1683 | offset: 14, |
1684 | }, |
1685 | ), |
1686 | bit_size: 1, |
1687 | array: None, |
1688 | enumm: None, |
1689 | }, |
1690 | Field { |
1691 | name: "priv_" , |
1692 | description: Some( |
1693 | "PRIV" , |
1694 | ), |
1695 | bit_offset: BitOffset::Regular( |
1696 | RegularBitOffset { |
1697 | offset: 15, |
1698 | }, |
1699 | ), |
1700 | bit_size: 1, |
1701 | array: None, |
1702 | enumm: None, |
1703 | }, |
1704 | ], |
1705 | }, |
1706 | FieldSet { |
1707 | name: "Scr" , |
1708 | extends: None, |
1709 | description: Some( |
1710 | "Status clear register" , |
1711 | ), |
1712 | bit_size: 32, |
1713 | fields: &[ |
1714 | Field { |
1715 | name: "calrf" , |
1716 | description: Some( |
1717 | "Clear alarm x flag" , |
1718 | ), |
1719 | bit_offset: BitOffset::Regular( |
1720 | RegularBitOffset { |
1721 | offset: 0, |
1722 | }, |
1723 | ), |
1724 | bit_size: 1, |
1725 | array: Some( |
1726 | Array::Regular( |
1727 | RegularArray { |
1728 | len: 2, |
1729 | stride: 1, |
1730 | }, |
1731 | ), |
1732 | ), |
1733 | enumm: Some( |
1734 | "Calrf" , |
1735 | ), |
1736 | }, |
1737 | Field { |
1738 | name: "cwutf" , |
1739 | description: Some( |
1740 | "Clear wakeup timer flag" , |
1741 | ), |
1742 | bit_offset: BitOffset::Regular( |
1743 | RegularBitOffset { |
1744 | offset: 2, |
1745 | }, |
1746 | ), |
1747 | bit_size: 1, |
1748 | array: None, |
1749 | enumm: Some( |
1750 | "Calrf" , |
1751 | ), |
1752 | }, |
1753 | Field { |
1754 | name: "ctsf" , |
1755 | description: Some( |
1756 | "Clear timestamp flag" , |
1757 | ), |
1758 | bit_offset: BitOffset::Regular( |
1759 | RegularBitOffset { |
1760 | offset: 3, |
1761 | }, |
1762 | ), |
1763 | bit_size: 1, |
1764 | array: None, |
1765 | enumm: Some( |
1766 | "Calrf" , |
1767 | ), |
1768 | }, |
1769 | Field { |
1770 | name: "ctsovf" , |
1771 | description: Some( |
1772 | "Clear timestamp overflow flag" , |
1773 | ), |
1774 | bit_offset: BitOffset::Regular( |
1775 | RegularBitOffset { |
1776 | offset: 4, |
1777 | }, |
1778 | ), |
1779 | bit_size: 1, |
1780 | array: None, |
1781 | enumm: Some( |
1782 | "Calrf" , |
1783 | ), |
1784 | }, |
1785 | Field { |
1786 | name: "citsf" , |
1787 | description: Some( |
1788 | "Clear internal timestamp flag" , |
1789 | ), |
1790 | bit_offset: BitOffset::Regular( |
1791 | RegularBitOffset { |
1792 | offset: 5, |
1793 | }, |
1794 | ), |
1795 | bit_size: 1, |
1796 | array: None, |
1797 | enumm: Some( |
1798 | "Calrf" , |
1799 | ), |
1800 | }, |
1801 | Field { |
1802 | name: "cssruf" , |
1803 | description: Some( |
1804 | "Clear SSR underflow flag" , |
1805 | ), |
1806 | bit_offset: BitOffset::Regular( |
1807 | RegularBitOffset { |
1808 | offset: 6, |
1809 | }, |
1810 | ), |
1811 | bit_size: 1, |
1812 | array: None, |
1813 | enumm: Some( |
1814 | "Calrf" , |
1815 | ), |
1816 | }, |
1817 | ], |
1818 | }, |
1819 | FieldSet { |
1820 | name: "Seccfgr" , |
1821 | extends: None, |
1822 | description: Some( |
1823 | "Secure mode control register" , |
1824 | ), |
1825 | bit_size: 32, |
1826 | fields: &[ |
1827 | Field { |
1828 | name: "alrasec" , |
1829 | description: Some( |
1830 | "ALRASEC" , |
1831 | ), |
1832 | bit_offset: BitOffset::Regular( |
1833 | RegularBitOffset { |
1834 | offset: 0, |
1835 | }, |
1836 | ), |
1837 | bit_size: 1, |
1838 | array: None, |
1839 | enumm: None, |
1840 | }, |
1841 | Field { |
1842 | name: "alrbsec" , |
1843 | description: Some( |
1844 | "ALRBSEC" , |
1845 | ), |
1846 | bit_offset: BitOffset::Regular( |
1847 | RegularBitOffset { |
1848 | offset: 1, |
1849 | }, |
1850 | ), |
1851 | bit_size: 1, |
1852 | array: None, |
1853 | enumm: None, |
1854 | }, |
1855 | Field { |
1856 | name: "wutsec" , |
1857 | description: Some( |
1858 | "WUTSEC" , |
1859 | ), |
1860 | bit_offset: BitOffset::Regular( |
1861 | RegularBitOffset { |
1862 | offset: 2, |
1863 | }, |
1864 | ), |
1865 | bit_size: 1, |
1866 | array: None, |
1867 | enumm: None, |
1868 | }, |
1869 | Field { |
1870 | name: "tssec" , |
1871 | description: Some( |
1872 | "TSSEC" , |
1873 | ), |
1874 | bit_offset: BitOffset::Regular( |
1875 | RegularBitOffset { |
1876 | offset: 3, |
1877 | }, |
1878 | ), |
1879 | bit_size: 1, |
1880 | array: None, |
1881 | enumm: None, |
1882 | }, |
1883 | Field { |
1884 | name: "calsec" , |
1885 | description: Some( |
1886 | "CALSEC" , |
1887 | ), |
1888 | bit_offset: BitOffset::Regular( |
1889 | RegularBitOffset { |
1890 | offset: 13, |
1891 | }, |
1892 | ), |
1893 | bit_size: 1, |
1894 | array: None, |
1895 | enumm: None, |
1896 | }, |
1897 | Field { |
1898 | name: "initsec" , |
1899 | description: Some( |
1900 | "INITSEC" , |
1901 | ), |
1902 | bit_offset: BitOffset::Regular( |
1903 | RegularBitOffset { |
1904 | offset: 14, |
1905 | }, |
1906 | ), |
1907 | bit_size: 1, |
1908 | array: None, |
1909 | enumm: None, |
1910 | }, |
1911 | Field { |
1912 | name: "sec" , |
1913 | description: Some( |
1914 | "SEC" , |
1915 | ), |
1916 | bit_offset: BitOffset::Regular( |
1917 | RegularBitOffset { |
1918 | offset: 15, |
1919 | }, |
1920 | ), |
1921 | bit_size: 1, |
1922 | array: None, |
1923 | enumm: None, |
1924 | }, |
1925 | ], |
1926 | }, |
1927 | FieldSet { |
1928 | name: "Shiftr" , |
1929 | extends: None, |
1930 | description: Some( |
1931 | "Shift control register" , |
1932 | ), |
1933 | bit_size: 32, |
1934 | fields: &[ |
1935 | Field { |
1936 | name: "subfs" , |
1937 | description: Some( |
1938 | "Subtract a fraction of a second" , |
1939 | ), |
1940 | bit_offset: BitOffset::Regular( |
1941 | RegularBitOffset { |
1942 | offset: 0, |
1943 | }, |
1944 | ), |
1945 | bit_size: 15, |
1946 | array: None, |
1947 | enumm: None, |
1948 | }, |
1949 | Field { |
1950 | name: "add1s" , |
1951 | description: Some( |
1952 | "Add one second" , |
1953 | ), |
1954 | bit_offset: BitOffset::Regular( |
1955 | RegularBitOffset { |
1956 | offset: 31, |
1957 | }, |
1958 | ), |
1959 | bit_size: 1, |
1960 | array: None, |
1961 | enumm: None, |
1962 | }, |
1963 | ], |
1964 | }, |
1965 | FieldSet { |
1966 | name: "Smisr" , |
1967 | extends: None, |
1968 | description: Some( |
1969 | "Secure masked interrupt status register" , |
1970 | ), |
1971 | bit_size: 32, |
1972 | fields: &[ |
1973 | Field { |
1974 | name: "alrmf" , |
1975 | description: Some( |
1976 | "Alarm x interrupt secure masked flag" , |
1977 | ), |
1978 | bit_offset: BitOffset::Regular( |
1979 | RegularBitOffset { |
1980 | offset: 0, |
1981 | }, |
1982 | ), |
1983 | bit_size: 1, |
1984 | array: Some( |
1985 | Array::Regular( |
1986 | RegularArray { |
1987 | len: 2, |
1988 | stride: 1, |
1989 | }, |
1990 | ), |
1991 | ), |
1992 | enumm: None, |
1993 | }, |
1994 | Field { |
1995 | name: "wutmf" , |
1996 | description: Some( |
1997 | "WUTMF" , |
1998 | ), |
1999 | bit_offset: BitOffset::Regular( |
2000 | RegularBitOffset { |
2001 | offset: 2, |
2002 | }, |
2003 | ), |
2004 | bit_size: 1, |
2005 | array: None, |
2006 | enumm: None, |
2007 | }, |
2008 | Field { |
2009 | name: "tsmf" , |
2010 | description: Some( |
2011 | "TSMF" , |
2012 | ), |
2013 | bit_offset: BitOffset::Regular( |
2014 | RegularBitOffset { |
2015 | offset: 3, |
2016 | }, |
2017 | ), |
2018 | bit_size: 1, |
2019 | array: None, |
2020 | enumm: None, |
2021 | }, |
2022 | Field { |
2023 | name: "tsovmf" , |
2024 | description: Some( |
2025 | "TSOVMF" , |
2026 | ), |
2027 | bit_offset: BitOffset::Regular( |
2028 | RegularBitOffset { |
2029 | offset: 4, |
2030 | }, |
2031 | ), |
2032 | bit_size: 1, |
2033 | array: None, |
2034 | enumm: None, |
2035 | }, |
2036 | Field { |
2037 | name: "itsmf" , |
2038 | description: Some( |
2039 | "ITSMF" , |
2040 | ), |
2041 | bit_offset: BitOffset::Regular( |
2042 | RegularBitOffset { |
2043 | offset: 5, |
2044 | }, |
2045 | ), |
2046 | bit_size: 1, |
2047 | array: None, |
2048 | enumm: None, |
2049 | }, |
2050 | Field { |
2051 | name: "ssrumf" , |
2052 | description: Some( |
2053 | "SSRUMF" , |
2054 | ), |
2055 | bit_offset: BitOffset::Regular( |
2056 | RegularBitOffset { |
2057 | offset: 6, |
2058 | }, |
2059 | ), |
2060 | bit_size: 1, |
2061 | array: None, |
2062 | enumm: None, |
2063 | }, |
2064 | ], |
2065 | }, |
2066 | FieldSet { |
2067 | name: "Sr" , |
2068 | extends: None, |
2069 | description: Some( |
2070 | "Status register" , |
2071 | ), |
2072 | bit_size: 32, |
2073 | fields: &[ |
2074 | Field { |
2075 | name: "alrf" , |
2076 | description: Some( |
2077 | "Alarm flag" , |
2078 | ), |
2079 | bit_offset: BitOffset::Regular( |
2080 | RegularBitOffset { |
2081 | offset: 0, |
2082 | }, |
2083 | ), |
2084 | bit_size: 1, |
2085 | array: Some( |
2086 | Array::Regular( |
2087 | RegularArray { |
2088 | len: 2, |
2089 | stride: 1, |
2090 | }, |
2091 | ), |
2092 | ), |
2093 | enumm: Some( |
2094 | "Alrf" , |
2095 | ), |
2096 | }, |
2097 | Field { |
2098 | name: "wutf" , |
2099 | description: Some( |
2100 | "Wakeup timer flag" , |
2101 | ), |
2102 | bit_offset: BitOffset::Regular( |
2103 | RegularBitOffset { |
2104 | offset: 2, |
2105 | }, |
2106 | ), |
2107 | bit_size: 1, |
2108 | array: None, |
2109 | enumm: Some( |
2110 | "Wutf" , |
2111 | ), |
2112 | }, |
2113 | Field { |
2114 | name: "tsf" , |
2115 | description: Some( |
2116 | "Timestamp flag" , |
2117 | ), |
2118 | bit_offset: BitOffset::Regular( |
2119 | RegularBitOffset { |
2120 | offset: 3, |
2121 | }, |
2122 | ), |
2123 | bit_size: 1, |
2124 | array: None, |
2125 | enumm: Some( |
2126 | "Tsf" , |
2127 | ), |
2128 | }, |
2129 | Field { |
2130 | name: "tsovf" , |
2131 | description: Some( |
2132 | "Timestamp overflow flag" , |
2133 | ), |
2134 | bit_offset: BitOffset::Regular( |
2135 | RegularBitOffset { |
2136 | offset: 4, |
2137 | }, |
2138 | ), |
2139 | bit_size: 1, |
2140 | array: None, |
2141 | enumm: Some( |
2142 | "Tsovf" , |
2143 | ), |
2144 | }, |
2145 | Field { |
2146 | name: "itsf" , |
2147 | description: Some( |
2148 | "Internal timestamp flag" , |
2149 | ), |
2150 | bit_offset: BitOffset::Regular( |
2151 | RegularBitOffset { |
2152 | offset: 5, |
2153 | }, |
2154 | ), |
2155 | bit_size: 1, |
2156 | array: None, |
2157 | enumm: Some( |
2158 | "Itsf" , |
2159 | ), |
2160 | }, |
2161 | Field { |
2162 | name: "ssruf" , |
2163 | description: Some( |
2164 | "SSR underflow flag" , |
2165 | ), |
2166 | bit_offset: BitOffset::Regular( |
2167 | RegularBitOffset { |
2168 | offset: 6, |
2169 | }, |
2170 | ), |
2171 | bit_size: 1, |
2172 | array: None, |
2173 | enumm: Some( |
2174 | "Ssruf" , |
2175 | ), |
2176 | }, |
2177 | ], |
2178 | }, |
2179 | FieldSet { |
2180 | name: "Ssr" , |
2181 | extends: None, |
2182 | description: Some( |
2183 | "Sub second register" , |
2184 | ), |
2185 | bit_size: 32, |
2186 | fields: &[ |
2187 | Field { |
2188 | name: "ss" , |
2189 | description: Some( |
2190 | "Synchronous binary counter" , |
2191 | ), |
2192 | bit_offset: BitOffset::Regular( |
2193 | RegularBitOffset { |
2194 | offset: 0, |
2195 | }, |
2196 | ), |
2197 | bit_size: 32, |
2198 | array: None, |
2199 | enumm: None, |
2200 | }, |
2201 | ], |
2202 | }, |
2203 | FieldSet { |
2204 | name: "Tr" , |
2205 | extends: None, |
2206 | description: Some( |
2207 | "Time register" , |
2208 | ), |
2209 | bit_size: 32, |
2210 | fields: &[ |
2211 | Field { |
2212 | name: "su" , |
2213 | description: Some( |
2214 | "Second units in BCD format" , |
2215 | ), |
2216 | bit_offset: BitOffset::Regular( |
2217 | RegularBitOffset { |
2218 | offset: 0, |
2219 | }, |
2220 | ), |
2221 | bit_size: 4, |
2222 | array: None, |
2223 | enumm: None, |
2224 | }, |
2225 | Field { |
2226 | name: "st" , |
2227 | description: Some( |
2228 | "Second tens in BCD format" , |
2229 | ), |
2230 | bit_offset: BitOffset::Regular( |
2231 | RegularBitOffset { |
2232 | offset: 4, |
2233 | }, |
2234 | ), |
2235 | bit_size: 3, |
2236 | array: None, |
2237 | enumm: None, |
2238 | }, |
2239 | Field { |
2240 | name: "mnu" , |
2241 | description: Some( |
2242 | "Minute units in BCD format" , |
2243 | ), |
2244 | bit_offset: BitOffset::Regular( |
2245 | RegularBitOffset { |
2246 | offset: 8, |
2247 | }, |
2248 | ), |
2249 | bit_size: 4, |
2250 | array: None, |
2251 | enumm: None, |
2252 | }, |
2253 | Field { |
2254 | name: "mnt" , |
2255 | description: Some( |
2256 | "Minute tens in BCD format" , |
2257 | ), |
2258 | bit_offset: BitOffset::Regular( |
2259 | RegularBitOffset { |
2260 | offset: 12, |
2261 | }, |
2262 | ), |
2263 | bit_size: 3, |
2264 | array: None, |
2265 | enumm: None, |
2266 | }, |
2267 | Field { |
2268 | name: "hu" , |
2269 | description: Some( |
2270 | "Hour units in BCD format" , |
2271 | ), |
2272 | bit_offset: BitOffset::Regular( |
2273 | RegularBitOffset { |
2274 | offset: 16, |
2275 | }, |
2276 | ), |
2277 | bit_size: 4, |
2278 | array: None, |
2279 | enumm: None, |
2280 | }, |
2281 | Field { |
2282 | name: "ht" , |
2283 | description: Some( |
2284 | "Hour tens in BCD format" , |
2285 | ), |
2286 | bit_offset: BitOffset::Regular( |
2287 | RegularBitOffset { |
2288 | offset: 20, |
2289 | }, |
2290 | ), |
2291 | bit_size: 2, |
2292 | array: None, |
2293 | enumm: None, |
2294 | }, |
2295 | Field { |
2296 | name: "pm" , |
2297 | description: Some( |
2298 | "AM/PM notation" , |
2299 | ), |
2300 | bit_offset: BitOffset::Regular( |
2301 | RegularBitOffset { |
2302 | offset: 22, |
2303 | }, |
2304 | ), |
2305 | bit_size: 1, |
2306 | array: None, |
2307 | enumm: Some( |
2308 | "Ampm" , |
2309 | ), |
2310 | }, |
2311 | ], |
2312 | }, |
2313 | FieldSet { |
2314 | name: "Tsdr" , |
2315 | extends: None, |
2316 | description: Some( |
2317 | "Timestamp date register" , |
2318 | ), |
2319 | bit_size: 32, |
2320 | fields: &[ |
2321 | Field { |
2322 | name: "du" , |
2323 | description: Some( |
2324 | "Date units in BCD format" , |
2325 | ), |
2326 | bit_offset: BitOffset::Regular( |
2327 | RegularBitOffset { |
2328 | offset: 0, |
2329 | }, |
2330 | ), |
2331 | bit_size: 4, |
2332 | array: None, |
2333 | enumm: None, |
2334 | }, |
2335 | Field { |
2336 | name: "dt" , |
2337 | description: Some( |
2338 | "Date tens in BCD format" , |
2339 | ), |
2340 | bit_offset: BitOffset::Regular( |
2341 | RegularBitOffset { |
2342 | offset: 4, |
2343 | }, |
2344 | ), |
2345 | bit_size: 2, |
2346 | array: None, |
2347 | enumm: None, |
2348 | }, |
2349 | Field { |
2350 | name: "mu" , |
2351 | description: Some( |
2352 | "Month units in BCD format" , |
2353 | ), |
2354 | bit_offset: BitOffset::Regular( |
2355 | RegularBitOffset { |
2356 | offset: 8, |
2357 | }, |
2358 | ), |
2359 | bit_size: 4, |
2360 | array: None, |
2361 | enumm: None, |
2362 | }, |
2363 | Field { |
2364 | name: "mt" , |
2365 | description: Some( |
2366 | "Month tens in BCD format" , |
2367 | ), |
2368 | bit_offset: BitOffset::Regular( |
2369 | RegularBitOffset { |
2370 | offset: 12, |
2371 | }, |
2372 | ), |
2373 | bit_size: 1, |
2374 | array: None, |
2375 | enumm: None, |
2376 | }, |
2377 | Field { |
2378 | name: "wdu" , |
2379 | description: Some( |
2380 | "Week day units" , |
2381 | ), |
2382 | bit_offset: BitOffset::Regular( |
2383 | RegularBitOffset { |
2384 | offset: 13, |
2385 | }, |
2386 | ), |
2387 | bit_size: 3, |
2388 | array: None, |
2389 | enumm: None, |
2390 | }, |
2391 | ], |
2392 | }, |
2393 | FieldSet { |
2394 | name: "Tsssr" , |
2395 | extends: None, |
2396 | description: Some( |
2397 | "Timestamp sub second register" , |
2398 | ), |
2399 | bit_size: 32, |
2400 | fields: &[ |
2401 | Field { |
2402 | name: "ss" , |
2403 | description: Some( |
2404 | "Sub second value" , |
2405 | ), |
2406 | bit_offset: BitOffset::Regular( |
2407 | RegularBitOffset { |
2408 | offset: 0, |
2409 | }, |
2410 | ), |
2411 | bit_size: 32, |
2412 | array: None, |
2413 | enumm: None, |
2414 | }, |
2415 | ], |
2416 | }, |
2417 | FieldSet { |
2418 | name: "Tstr" , |
2419 | extends: None, |
2420 | description: Some( |
2421 | "Timestamp time register" , |
2422 | ), |
2423 | bit_size: 32, |
2424 | fields: &[ |
2425 | Field { |
2426 | name: "su" , |
2427 | description: Some( |
2428 | "Second units in BCD format" , |
2429 | ), |
2430 | bit_offset: BitOffset::Regular( |
2431 | RegularBitOffset { |
2432 | offset: 0, |
2433 | }, |
2434 | ), |
2435 | bit_size: 4, |
2436 | array: None, |
2437 | enumm: None, |
2438 | }, |
2439 | Field { |
2440 | name: "st" , |
2441 | description: Some( |
2442 | "Second tens in BCD format" , |
2443 | ), |
2444 | bit_offset: BitOffset::Regular( |
2445 | RegularBitOffset { |
2446 | offset: 4, |
2447 | }, |
2448 | ), |
2449 | bit_size: 3, |
2450 | array: None, |
2451 | enumm: None, |
2452 | }, |
2453 | Field { |
2454 | name: "mnu" , |
2455 | description: Some( |
2456 | "Minute units in BCD format" , |
2457 | ), |
2458 | bit_offset: BitOffset::Regular( |
2459 | RegularBitOffset { |
2460 | offset: 8, |
2461 | }, |
2462 | ), |
2463 | bit_size: 4, |
2464 | array: None, |
2465 | enumm: None, |
2466 | }, |
2467 | Field { |
2468 | name: "mnt" , |
2469 | description: Some( |
2470 | "Minute tens in BCD format" , |
2471 | ), |
2472 | bit_offset: BitOffset::Regular( |
2473 | RegularBitOffset { |
2474 | offset: 12, |
2475 | }, |
2476 | ), |
2477 | bit_size: 3, |
2478 | array: None, |
2479 | enumm: None, |
2480 | }, |
2481 | Field { |
2482 | name: "hu" , |
2483 | description: Some( |
2484 | "Hour units in BCD format" , |
2485 | ), |
2486 | bit_offset: BitOffset::Regular( |
2487 | RegularBitOffset { |
2488 | offset: 16, |
2489 | }, |
2490 | ), |
2491 | bit_size: 4, |
2492 | array: None, |
2493 | enumm: None, |
2494 | }, |
2495 | Field { |
2496 | name: "ht" , |
2497 | description: Some( |
2498 | "Hour tens in BCD format" , |
2499 | ), |
2500 | bit_offset: BitOffset::Regular( |
2501 | RegularBitOffset { |
2502 | offset: 20, |
2503 | }, |
2504 | ), |
2505 | bit_size: 2, |
2506 | array: None, |
2507 | enumm: None, |
2508 | }, |
2509 | Field { |
2510 | name: "pm" , |
2511 | description: Some( |
2512 | "AM/PM notation" , |
2513 | ), |
2514 | bit_offset: BitOffset::Regular( |
2515 | RegularBitOffset { |
2516 | offset: 22, |
2517 | }, |
2518 | ), |
2519 | bit_size: 1, |
2520 | array: None, |
2521 | enumm: None, |
2522 | }, |
2523 | ], |
2524 | }, |
2525 | FieldSet { |
2526 | name: "Wpr" , |
2527 | extends: None, |
2528 | description: Some( |
2529 | "Write protection register" , |
2530 | ), |
2531 | bit_size: 32, |
2532 | fields: &[ |
2533 | Field { |
2534 | name: "key" , |
2535 | description: Some( |
2536 | "Write protection key" , |
2537 | ), |
2538 | bit_offset: BitOffset::Regular( |
2539 | RegularBitOffset { |
2540 | offset: 0, |
2541 | }, |
2542 | ), |
2543 | bit_size: 8, |
2544 | array: None, |
2545 | enumm: Some( |
2546 | "Key" , |
2547 | ), |
2548 | }, |
2549 | ], |
2550 | }, |
2551 | FieldSet { |
2552 | name: "Wutr" , |
2553 | extends: None, |
2554 | description: Some( |
2555 | "Wakeup timer register" , |
2556 | ), |
2557 | bit_size: 32, |
2558 | fields: &[ |
2559 | Field { |
2560 | name: "wut" , |
2561 | description: Some( |
2562 | "Wakeup auto-reload value bits" , |
2563 | ), |
2564 | bit_offset: BitOffset::Regular( |
2565 | RegularBitOffset { |
2566 | offset: 0, |
2567 | }, |
2568 | ), |
2569 | bit_size: 16, |
2570 | array: None, |
2571 | enumm: None, |
2572 | }, |
2573 | Field { |
2574 | name: "wutoclr" , |
2575 | description: Some( |
2576 | "Wakeup auto-reload output clear value" , |
2577 | ), |
2578 | bit_offset: BitOffset::Regular( |
2579 | RegularBitOffset { |
2580 | offset: 16, |
2581 | }, |
2582 | ), |
2583 | bit_size: 16, |
2584 | array: None, |
2585 | enumm: None, |
2586 | }, |
2587 | ], |
2588 | }, |
2589 | ], |
2590 | enums: &[ |
2591 | Enum { |
2592 | name: "Alrf" , |
2593 | description: None, |
2594 | bit_size: 1, |
2595 | variants: &[ |
2596 | EnumVariant { |
2597 | name: "MATCH" , |
2598 | description: Some( |
2599 | "This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)" , |
2600 | ), |
2601 | value: 1, |
2602 | }, |
2603 | ], |
2604 | }, |
2605 | Enum { |
2606 | name: "Alrmf" , |
2607 | description: None, |
2608 | bit_size: 1, |
2609 | variants: &[ |
2610 | EnumVariant { |
2611 | name: "MATCH" , |
2612 | description: Some( |
2613 | "This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)" , |
2614 | ), |
2615 | value: 1, |
2616 | }, |
2617 | ], |
2618 | }, |
2619 | Enum { |
2620 | name: "AlrmrMsk" , |
2621 | description: None, |
2622 | bit_size: 1, |
2623 | variants: &[ |
2624 | EnumVariant { |
2625 | name: "TO_MATCH" , |
2626 | description: Some( |
2627 | "Alarm set if the date/day match" , |
2628 | ), |
2629 | value: 0, |
2630 | }, |
2631 | EnumVariant { |
2632 | name: "NOT_MATCH" , |
2633 | description: Some( |
2634 | "Date/day don’t care in Alarm comparison" , |
2635 | ), |
2636 | value: 1, |
2637 | }, |
2638 | ], |
2639 | }, |
2640 | Enum { |
2641 | name: "AlrmrPm" , |
2642 | description: None, |
2643 | bit_size: 1, |
2644 | variants: &[ |
2645 | EnumVariant { |
2646 | name: "AM" , |
2647 | description: Some( |
2648 | "AM or 24-hour format" , |
2649 | ), |
2650 | value: 0, |
2651 | }, |
2652 | EnumVariant { |
2653 | name: "PM" , |
2654 | description: Some( |
2655 | "PM" , |
2656 | ), |
2657 | value: 1, |
2658 | }, |
2659 | ], |
2660 | }, |
2661 | Enum { |
2662 | name: "AlrmrWdsel" , |
2663 | description: None, |
2664 | bit_size: 1, |
2665 | variants: &[ |
2666 | EnumVariant { |
2667 | name: "DATE_UNITS" , |
2668 | description: Some( |
2669 | "DU[3:0] represents the date units" , |
2670 | ), |
2671 | value: 0, |
2672 | }, |
2673 | EnumVariant { |
2674 | name: "WEEK_DAY" , |
2675 | description: Some( |
2676 | "DU[3:0] represents the week day. DT[1:0] is don’t care." , |
2677 | ), |
2678 | value: 1, |
2679 | }, |
2680 | ], |
2681 | }, |
2682 | Enum { |
2683 | name: "AlrmssrSsclr" , |
2684 | description: None, |
2685 | bit_size: 1, |
2686 | variants: &[ |
2687 | EnumVariant { |
2688 | name: "FREE_RUNNING" , |
2689 | description: Some( |
2690 | "The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running" , |
2691 | ), |
2692 | value: 0, |
2693 | }, |
2694 | EnumVariant { |
2695 | name: "ALRMBINR" , |
2696 | description: Some( |
2697 | "The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR → SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR → SS[31:0]" , |
2698 | ), |
2699 | value: 1, |
2700 | }, |
2701 | ], |
2702 | }, |
2703 | Enum { |
2704 | name: "Ampm" , |
2705 | description: None, |
2706 | bit_size: 1, |
2707 | variants: &[ |
2708 | EnumVariant { |
2709 | name: "AM" , |
2710 | description: Some( |
2711 | "AM or 24-hour format" , |
2712 | ), |
2713 | value: 0, |
2714 | }, |
2715 | EnumVariant { |
2716 | name: "PM" , |
2717 | description: Some( |
2718 | "PM" , |
2719 | ), |
2720 | value: 1, |
2721 | }, |
2722 | ], |
2723 | }, |
2724 | Enum { |
2725 | name: "Bcdu" , |
2726 | description: None, |
2727 | bit_size: 3, |
2728 | variants: &[ |
2729 | EnumVariant { |
2730 | name: "BIT7" , |
2731 | description: Some( |
2732 | "1s increment each time SS[7:0]=0" , |
2733 | ), |
2734 | value: 0, |
2735 | }, |
2736 | EnumVariant { |
2737 | name: "BIT8" , |
2738 | description: Some( |
2739 | "1s increment each time SS[8:0]=0" , |
2740 | ), |
2741 | value: 1, |
2742 | }, |
2743 | EnumVariant { |
2744 | name: "BIT9" , |
2745 | description: Some( |
2746 | "1s increment each time SS[9:0]=0" , |
2747 | ), |
2748 | value: 2, |
2749 | }, |
2750 | EnumVariant { |
2751 | name: "BIT10" , |
2752 | description: Some( |
2753 | "1s increment each time SS[10:0]=0" , |
2754 | ), |
2755 | value: 3, |
2756 | }, |
2757 | EnumVariant { |
2758 | name: "BIT11" , |
2759 | description: Some( |
2760 | "1s increment each time SS[11:0]=0" , |
2761 | ), |
2762 | value: 4, |
2763 | }, |
2764 | EnumVariant { |
2765 | name: "BIT12" , |
2766 | description: Some( |
2767 | "1s increment each time SS[12:0]=0" , |
2768 | ), |
2769 | value: 5, |
2770 | }, |
2771 | EnumVariant { |
2772 | name: "BIT13" , |
2773 | description: Some( |
2774 | "1s increment each time SS[13:0]=0" , |
2775 | ), |
2776 | value: 6, |
2777 | }, |
2778 | EnumVariant { |
2779 | name: "BIT14" , |
2780 | description: Some( |
2781 | "1s increment each time SS[14:0]=0" , |
2782 | ), |
2783 | value: 7, |
2784 | }, |
2785 | ], |
2786 | }, |
2787 | Enum { |
2788 | name: "Bin" , |
2789 | description: None, |
2790 | bit_size: 2, |
2791 | variants: &[ |
2792 | EnumVariant { |
2793 | name: "BCD" , |
2794 | description: Some( |
2795 | "Free running BCD calendar mode (Binary mode disabled)" , |
2796 | ), |
2797 | value: 0, |
2798 | }, |
2799 | EnumVariant { |
2800 | name: "BINARY" , |
2801 | description: Some( |
2802 | "Free running Binary mode (BCD mode disabled)" , |
2803 | ), |
2804 | value: 1, |
2805 | }, |
2806 | EnumVariant { |
2807 | name: "BIN_BCD" , |
2808 | description: Some( |
2809 | "Free running BCD calendar and Binary modes" , |
2810 | ), |
2811 | value: 2, |
2812 | }, |
2813 | EnumVariant { |
2814 | name: "BIN_BCD2" , |
2815 | description: Some( |
2816 | "Free running BCD calendar and Binary modes" , |
2817 | ), |
2818 | value: 3, |
2819 | }, |
2820 | ], |
2821 | }, |
2822 | Enum { |
2823 | name: "Calp" , |
2824 | description: None, |
2825 | bit_size: 1, |
2826 | variants: &[ |
2827 | EnumVariant { |
2828 | name: "NO_CHANGE" , |
2829 | description: Some( |
2830 | "No RTCCLK pulses are added" , |
2831 | ), |
2832 | value: 0, |
2833 | }, |
2834 | EnumVariant { |
2835 | name: "INCREASE_FREQ" , |
2836 | description: Some( |
2837 | "One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)" , |
2838 | ), |
2839 | value: 1, |
2840 | }, |
2841 | ], |
2842 | }, |
2843 | Enum { |
2844 | name: "Calrf" , |
2845 | description: None, |
2846 | bit_size: 1, |
2847 | variants: &[ |
2848 | EnumVariant { |
2849 | name: "CLEAR" , |
2850 | description: Some( |
2851 | "Clear interrupt flag by writing 1" , |
2852 | ), |
2853 | value: 1, |
2854 | }, |
2855 | ], |
2856 | }, |
2857 | Enum { |
2858 | name: "Calw16" , |
2859 | description: None, |
2860 | bit_size: 1, |
2861 | variants: &[ |
2862 | EnumVariant { |
2863 | name: "SIXTEEN_SECONDS" , |
2864 | description: Some( |
2865 | "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" , |
2866 | ), |
2867 | value: 1, |
2868 | }, |
2869 | ], |
2870 | }, |
2871 | Enum { |
2872 | name: "Calw8" , |
2873 | description: None, |
2874 | bit_size: 1, |
2875 | variants: &[ |
2876 | EnumVariant { |
2877 | name: "EIGHT_SECONDS" , |
2878 | description: Some( |
2879 | "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" , |
2880 | ), |
2881 | value: 1, |
2882 | }, |
2883 | ], |
2884 | }, |
2885 | Enum { |
2886 | name: "Cosel" , |
2887 | description: None, |
2888 | bit_size: 1, |
2889 | variants: &[ |
2890 | EnumVariant { |
2891 | name: "CAL_FREQ_512HZ" , |
2892 | description: Some( |
2893 | "Calibration output is 512 Hz (with default prescaler setting)" , |
2894 | ), |
2895 | value: 0, |
2896 | }, |
2897 | EnumVariant { |
2898 | name: "CAL_FREQ_1HZ" , |
2899 | description: Some( |
2900 | "Calibration output is 1 Hz (with default prescaler setting)" , |
2901 | ), |
2902 | value: 1, |
2903 | }, |
2904 | ], |
2905 | }, |
2906 | Enum { |
2907 | name: "Fmt" , |
2908 | description: None, |
2909 | bit_size: 1, |
2910 | variants: &[ |
2911 | EnumVariant { |
2912 | name: "TWENTY_FOUR_HOUR" , |
2913 | description: Some( |
2914 | "24 hour/day format" , |
2915 | ), |
2916 | value: 0, |
2917 | }, |
2918 | EnumVariant { |
2919 | name: "AM_PM" , |
2920 | description: Some( |
2921 | "AM/PM hour format" , |
2922 | ), |
2923 | value: 1, |
2924 | }, |
2925 | ], |
2926 | }, |
2927 | Enum { |
2928 | name: "Itsf" , |
2929 | description: None, |
2930 | bit_size: 1, |
2931 | variants: &[ |
2932 | EnumVariant { |
2933 | name: "TIMESTAMP_EVENT" , |
2934 | description: Some( |
2935 | "This flag is set by hardware when a timestamp on the internal event occurs" , |
2936 | ), |
2937 | value: 1, |
2938 | }, |
2939 | ], |
2940 | }, |
2941 | Enum { |
2942 | name: "Itsmf" , |
2943 | description: None, |
2944 | bit_size: 1, |
2945 | variants: &[ |
2946 | EnumVariant { |
2947 | name: "TIMESTAMP_EVENT" , |
2948 | description: Some( |
2949 | "This flag is set by hardware when a timestamp on the internal event occurs" , |
2950 | ), |
2951 | value: 1, |
2952 | }, |
2953 | ], |
2954 | }, |
2955 | Enum { |
2956 | name: "Key" , |
2957 | description: None, |
2958 | bit_size: 8, |
2959 | variants: &[ |
2960 | EnumVariant { |
2961 | name: "ACTIVATE" , |
2962 | description: Some( |
2963 | "Activate write protection (any value that is not the keys)" , |
2964 | ), |
2965 | value: 0, |
2966 | }, |
2967 | EnumVariant { |
2968 | name: "DEACTIVATE2" , |
2969 | description: Some( |
2970 | "Key 2" , |
2971 | ), |
2972 | value: 83, |
2973 | }, |
2974 | EnumVariant { |
2975 | name: "DEACTIVATE1" , |
2976 | description: Some( |
2977 | "Key 1" , |
2978 | ), |
2979 | value: 202, |
2980 | }, |
2981 | ], |
2982 | }, |
2983 | Enum { |
2984 | name: "Lpcal" , |
2985 | description: None, |
2986 | bit_size: 1, |
2987 | variants: &[ |
2988 | EnumVariant { |
2989 | name: "RTCCLK" , |
2990 | description: Some( |
2991 | "Calibration window is 220 RTCCLK, which is a high-consumption mode. This mode should be set only when less than 32s calibration window is required" , |
2992 | ), |
2993 | value: 0, |
2994 | }, |
2995 | EnumVariant { |
2996 | name: "CK_APRE" , |
2997 | description: Some( |
2998 | "Calibration window is 220 ck_apre, which is the required configuration for ultra-low consumption mode" , |
2999 | ), |
3000 | value: 1, |
3001 | }, |
3002 | ], |
3003 | }, |
3004 | Enum { |
3005 | name: "Osel" , |
3006 | description: None, |
3007 | bit_size: 2, |
3008 | variants: &[ |
3009 | EnumVariant { |
3010 | name: "DISABLED" , |
3011 | description: Some( |
3012 | "Output disabled" , |
3013 | ), |
3014 | value: 0, |
3015 | }, |
3016 | EnumVariant { |
3017 | name: "ALARM_A" , |
3018 | description: Some( |
3019 | "Alarm A output enabled" , |
3020 | ), |
3021 | value: 1, |
3022 | }, |
3023 | EnumVariant { |
3024 | name: "ALARM_B" , |
3025 | description: Some( |
3026 | "Alarm B output enabled" , |
3027 | ), |
3028 | value: 2, |
3029 | }, |
3030 | EnumVariant { |
3031 | name: "WAKEUP" , |
3032 | description: Some( |
3033 | "Wakeup output enabled" , |
3034 | ), |
3035 | value: 3, |
3036 | }, |
3037 | ], |
3038 | }, |
3039 | Enum { |
3040 | name: "Pol" , |
3041 | description: None, |
3042 | bit_size: 1, |
3043 | variants: &[ |
3044 | EnumVariant { |
3045 | name: "HIGH" , |
3046 | description: Some( |
3047 | "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" , |
3048 | ), |
3049 | value: 0, |
3050 | }, |
3051 | EnumVariant { |
3052 | name: "LOW" , |
3053 | description: Some( |
3054 | "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" , |
3055 | ), |
3056 | value: 1, |
3057 | }, |
3058 | ], |
3059 | }, |
3060 | Enum { |
3061 | name: "Recalpf" , |
3062 | description: None, |
3063 | bit_size: 1, |
3064 | variants: &[ |
3065 | EnumVariant { |
3066 | name: "PENDING" , |
3067 | description: Some( |
3068 | "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" , |
3069 | ), |
3070 | value: 1, |
3071 | }, |
3072 | ], |
3073 | }, |
3074 | Enum { |
3075 | name: "Ssruf" , |
3076 | description: None, |
3077 | bit_size: 1, |
3078 | variants: &[ |
3079 | EnumVariant { |
3080 | name: "UNDERFLOW" , |
3081 | description: Some( |
3082 | "This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1" , |
3083 | ), |
3084 | value: 1, |
3085 | }, |
3086 | ], |
3087 | }, |
3088 | Enum { |
3089 | name: "Ssrumf" , |
3090 | description: None, |
3091 | bit_size: 1, |
3092 | variants: &[ |
3093 | EnumVariant { |
3094 | name: "UNDERFLOW" , |
3095 | description: Some( |
3096 | "This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1" , |
3097 | ), |
3098 | value: 1, |
3099 | }, |
3100 | ], |
3101 | }, |
3102 | Enum { |
3103 | name: "TampalrmType" , |
3104 | description: None, |
3105 | bit_size: 1, |
3106 | variants: &[ |
3107 | EnumVariant { |
3108 | name: "PUSH_PULL" , |
3109 | description: Some( |
3110 | "TAMPALRM is push-pull output" , |
3111 | ), |
3112 | value: 0, |
3113 | }, |
3114 | EnumVariant { |
3115 | name: "OPEN_DRAIN" , |
3116 | description: Some( |
3117 | "TAMPALRM is open-drain output" , |
3118 | ), |
3119 | value: 1, |
3120 | }, |
3121 | ], |
3122 | }, |
3123 | Enum { |
3124 | name: "Tsedge" , |
3125 | description: None, |
3126 | bit_size: 1, |
3127 | variants: &[ |
3128 | EnumVariant { |
3129 | name: "RISING_EDGE" , |
3130 | description: Some( |
3131 | "RTC_TS input rising edge generates a time-stamp event" , |
3132 | ), |
3133 | value: 0, |
3134 | }, |
3135 | EnumVariant { |
3136 | name: "FALLING_EDGE" , |
3137 | description: Some( |
3138 | "RTC_TS input falling edge generates a time-stamp event" , |
3139 | ), |
3140 | value: 1, |
3141 | }, |
3142 | ], |
3143 | }, |
3144 | Enum { |
3145 | name: "Tsf" , |
3146 | description: None, |
3147 | bit_size: 1, |
3148 | variants: &[ |
3149 | EnumVariant { |
3150 | name: "TIMESTAMP_EVENT" , |
3151 | description: Some( |
3152 | "This flag is set by hardware when a time-stamp event occurs" , |
3153 | ), |
3154 | value: 1, |
3155 | }, |
3156 | ], |
3157 | }, |
3158 | Enum { |
3159 | name: "Tsmf" , |
3160 | description: None, |
3161 | bit_size: 1, |
3162 | variants: &[ |
3163 | EnumVariant { |
3164 | name: "TIMESTAMP_EVENT" , |
3165 | description: Some( |
3166 | "This flag is set by hardware when a time-stamp event occurs" , |
3167 | ), |
3168 | value: 1, |
3169 | }, |
3170 | ], |
3171 | }, |
3172 | Enum { |
3173 | name: "Tsovf" , |
3174 | description: None, |
3175 | bit_size: 1, |
3176 | variants: &[ |
3177 | EnumVariant { |
3178 | name: "OVERFLOW" , |
3179 | description: Some( |
3180 | "This flag is set by hardware when a time-stamp event occurs while TSF is already set" , |
3181 | ), |
3182 | value: 1, |
3183 | }, |
3184 | ], |
3185 | }, |
3186 | Enum { |
3187 | name: "Tsovmf" , |
3188 | description: None, |
3189 | bit_size: 1, |
3190 | variants: &[ |
3191 | EnumVariant { |
3192 | name: "OVERFLOW" , |
3193 | description: Some( |
3194 | "This flag is set by hardware when a time-stamp event occurs while TSF is already set" , |
3195 | ), |
3196 | value: 1, |
3197 | }, |
3198 | ], |
3199 | }, |
3200 | Enum { |
3201 | name: "Wucksel" , |
3202 | description: None, |
3203 | bit_size: 3, |
3204 | variants: &[ |
3205 | EnumVariant { |
3206 | name: "DIV16" , |
3207 | description: Some( |
3208 | "RTC/16 clock is selected" , |
3209 | ), |
3210 | value: 0, |
3211 | }, |
3212 | EnumVariant { |
3213 | name: "DIV8" , |
3214 | description: Some( |
3215 | "RTC/8 clock is selected" , |
3216 | ), |
3217 | value: 1, |
3218 | }, |
3219 | EnumVariant { |
3220 | name: "DIV4" , |
3221 | description: Some( |
3222 | "RTC/4 clock is selected" , |
3223 | ), |
3224 | value: 2, |
3225 | }, |
3226 | EnumVariant { |
3227 | name: "DIV2" , |
3228 | description: Some( |
3229 | "RTC/2 clock is selected" , |
3230 | ), |
3231 | value: 3, |
3232 | }, |
3233 | EnumVariant { |
3234 | name: "CLOCK_SPARE" , |
3235 | description: Some( |
3236 | "ck_spre (usually 1 Hz) clock is selected" , |
3237 | ), |
3238 | value: 4, |
3239 | }, |
3240 | EnumVariant { |
3241 | name: "CLOCK_SPARE_WITH_OFFSET" , |
3242 | description: Some( |
3243 | "ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value" , |
3244 | ), |
3245 | value: 6, |
3246 | }, |
3247 | ], |
3248 | }, |
3249 | Enum { |
3250 | name: "Wutf" , |
3251 | description: None, |
3252 | bit_size: 1, |
3253 | variants: &[ |
3254 | EnumVariant { |
3255 | name: "ZERO" , |
3256 | description: Some( |
3257 | "This flag is set by hardware when the wakeup auto-reload counter reaches 0" , |
3258 | ), |
3259 | value: 1, |
3260 | }, |
3261 | ], |
3262 | }, |
3263 | Enum { |
3264 | name: "Wutmf" , |
3265 | description: None, |
3266 | bit_size: 1, |
3267 | variants: &[ |
3268 | EnumVariant { |
3269 | name: "ZERO" , |
3270 | description: Some( |
3271 | "This flag is set by hardware when the wakeup auto-reload counter reaches 0" , |
3272 | ), |
3273 | value: 1, |
3274 | }, |
3275 | ], |
3276 | }, |
3277 | ], |
3278 | }; |
3279 | |