1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Saes",
7 extends: None,
8 description: Some(
9 "Secure advanced encryption standard hardware accelerator.",
10 ),
11 items: &[
12 BlockItem {
13 name: "cr",
14 description: Some(
15 "SAES control register.",
16 ),
17 array: None,
18 byte_offset: 0x0,
19 inner: BlockItemInner::Register(
20 Register {
21 access: Access::ReadWrite,
22 bit_size: 32,
23 fieldset: Some(
24 "Cr",
25 ),
26 },
27 ),
28 },
29 BlockItem {
30 name: "sr",
31 description: Some(
32 "SAES status register.",
33 ),
34 array: None,
35 byte_offset: 0x4,
36 inner: BlockItemInner::Register(
37 Register {
38 access: Access::ReadWrite,
39 bit_size: 32,
40 fieldset: Some(
41 "Sr",
42 ),
43 },
44 ),
45 },
46 BlockItem {
47 name: "dinr",
48 description: Some(
49 "SAES data input register.",
50 ),
51 array: None,
52 byte_offset: 0x8,
53 inner: BlockItemInner::Register(
54 Register {
55 access: Access::ReadWrite,
56 bit_size: 32,
57 fieldset: None,
58 },
59 ),
60 },
61 BlockItem {
62 name: "doutr",
63 description: Some(
64 "SAES data output register.",
65 ),
66 array: None,
67 byte_offset: 0xc,
68 inner: BlockItemInner::Register(
69 Register {
70 access: Access::ReadWrite,
71 bit_size: 32,
72 fieldset: None,
73 },
74 ),
75 },
76 BlockItem {
77 name: "keyr",
78 description: Some(
79 "SAES key register 0.",
80 ),
81 array: Some(
82 Array::Cursed(
83 CursedArray {
84 offsets: &[
85 0,
86 4,
87 8,
88 12,
89 32,
90 36,
91 40,
92 44,
93 ],
94 },
95 ),
96 ),
97 byte_offset: 0x10,
98 inner: BlockItemInner::Register(
99 Register {
100 access: Access::ReadWrite,
101 bit_size: 32,
102 fieldset: None,
103 },
104 ),
105 },
106 BlockItem {
107 name: "ivr",
108 description: Some(
109 "SAES initialization vector register 0.",
110 ),
111 array: Some(
112 Array::Regular(
113 RegularArray {
114 len: 4,
115 stride: 4,
116 },
117 ),
118 ),
119 byte_offset: 0x20,
120 inner: BlockItemInner::Register(
121 Register {
122 access: Access::ReadWrite,
123 bit_size: 32,
124 fieldset: None,
125 },
126 ),
127 },
128 BlockItem {
129 name: "suspr",
130 description: Some(
131 "SAES suspend registers.",
132 ),
133 array: Some(
134 Array::Regular(
135 RegularArray {
136 len: 8,
137 stride: 4,
138 },
139 ),
140 ),
141 byte_offset: 0x40,
142 inner: BlockItemInner::Register(
143 Register {
144 access: Access::ReadWrite,
145 bit_size: 32,
146 fieldset: None,
147 },
148 ),
149 },
150 BlockItem {
151 name: "ier",
152 description: Some(
153 "SAES interrupt enable register.",
154 ),
155 array: None,
156 byte_offset: 0x300,
157 inner: BlockItemInner::Register(
158 Register {
159 access: Access::ReadWrite,
160 bit_size: 32,
161 fieldset: Some(
162 "Ier",
163 ),
164 },
165 ),
166 },
167 BlockItem {
168 name: "isr",
169 description: Some(
170 "SAES interrupt status register.",
171 ),
172 array: None,
173 byte_offset: 0x304,
174 inner: BlockItemInner::Register(
175 Register {
176 access: Access::ReadWrite,
177 bit_size: 32,
178 fieldset: Some(
179 "Isr",
180 ),
181 },
182 ),
183 },
184 BlockItem {
185 name: "icr",
186 description: Some(
187 "SAES interrupt clear register.",
188 ),
189 array: None,
190 byte_offset: 0x308,
191 inner: BlockItemInner::Register(
192 Register {
193 access: Access::ReadWrite,
194 bit_size: 32,
195 fieldset: Some(
196 "Icr",
197 ),
198 },
199 ),
200 },
201 ],
202 },
203 ],
204 fieldsets: &[
205 FieldSet {
206 name: "Cr",
207 extends: None,
208 description: Some(
209 "SAES control register.",
210 ),
211 bit_size: 32,
212 fields: &[
213 Field {
214 name: "en",
215 description: Some(
216 "SAES enable This bit enables/disables the SAES peripheral: At any moment, clearing then setting the bit re-initializes the SAES peripheral. This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2) and upon the completion of GCM/GMAC/CCM initial phase. The bit cannot be set as long as KEYVALID = 0 nor along with the following settings: KMOD = 01 + CHMOD = 011 and KMOD = 01 + CHMOD = 010 + MODE = 00. Note: With KMOD[1:0] other than 00, use the IPRST bit rather than the bit EN.",
217 ),
218 bit_offset: BitOffset::Regular(
219 RegularBitOffset {
220 offset: 0,
221 },
222 ),
223 bit_size: 1,
224 array: None,
225 enumm: None,
226 },
227 Field {
228 name: "datatype",
229 description: Some(
230 "Data type selection This bitfield defines the format of data written in the SAES_DINR register or read from the SAES_DOUTR register, through selecting the mode of data swapping: For more details, refer to . Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.",
231 ),
232 bit_offset: BitOffset::Regular(
233 RegularBitOffset {
234 offset: 1,
235 },
236 ),
237 bit_size: 2,
238 array: None,
239 enumm: Some(
240 "Datatype",
241 ),
242 },
243 Field {
244 name: "mode",
245 description: Some(
246 "SAES operating mode This bitfield selects the SAES operating mode: Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.",
247 ),
248 bit_offset: BitOffset::Regular(
249 RegularBitOffset {
250 offset: 3,
251 },
252 ),
253 bit_size: 2,
254 array: None,
255 enumm: Some(
256 "Mode",
257 ),
258 },
259 Field {
260 name: "chmod",
261 description: Some(
262 "Chaining mode selection This bitfield selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.",
263 ),
264 bit_offset: BitOffset::Cursed(
265 CursedBitOffset {
266 ranges: &[
267 5..=6,
268 16..=16,
269 ],
270 },
271 ),
272 bit_size: 3,
273 array: None,
274 enumm: Some(
275 "Chmod",
276 ),
277 },
278 Field {
279 name: "dmainen",
280 description: Some(
281 "DMA input enable This bit enables/disables data transferring with DMA, in the input phase: When the bit is set, DMA requests are automatically generated by SAES during the input data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation).",
282 ),
283 bit_offset: BitOffset::Regular(
284 RegularBitOffset {
285 offset: 11,
286 },
287 ),
288 bit_size: 1,
289 array: None,
290 enumm: None,
291 },
292 Field {
293 name: "dmaouten",
294 description: Some(
295 "DMA output enable This bit enables/disables data transferring with DMA, in the output phase: When the bit is set, DMA requests are automatically generated by SAES during the output data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation).",
296 ),
297 bit_offset: BitOffset::Regular(
298 RegularBitOffset {
299 offset: 12,
300 },
301 ),
302 bit_size: 1,
303 array: None,
304 enumm: None,
305 },
306 Field {
307 name: "keysize",
308 description: Some(
309 "Key size selection This bitfield defines the length of the key used in the SAES cryptographic core, in bits: When KMOD[1:0]=01 or 10 KEYSIZE also defines the length of the key to encrypt or decrypt. Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.",
310 ),
311 bit_offset: BitOffset::Regular(
312 RegularBitOffset {
313 offset: 18,
314 },
315 ),
316 bit_size: 1,
317 array: None,
318 enumm: Some(
319 "Keysize",
320 ),
321 },
322 Field {
323 name: "keyprot",
324 description: Some(
325 "Key protection When set, hardware-based key protection is enabled. Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.",
326 ),
327 bit_offset: BitOffset::Regular(
328 RegularBitOffset {
329 offset: 19,
330 },
331 ),
332 bit_size: 1,
333 array: None,
334 enumm: None,
335 },
336 Field {
337 name: "kmod",
338 description: Some(
339 "Key mode selection The bitfield defines how the SAES key can be used by the application: Others: Reserved With normal key selection, the key registers are freely usable, no specific usage or protection applies to SAES_DIN and SAES_DOUT registers. With wrapped key selection, the key loaded in key registers can only be used to encrypt or decrypt AES keys. Hence, when a decryption is selected in Wrapped-key mode read-as-zero SAES_DOUT register is automatically loaded into SAES key registers after a successful decryption process. With shared key selection, after a successful decryption process, SAES key registers are shared with the peripheral described in KSHAREID(1:0] bitfield. This sharing is valid only while KMOD[1:0]=10 and KEYVALID = 1. When a decryption is selected, read-as-zero SAES_DOUT register is automatically loaded into SAES key registers after a successful decryption process. With KMOD[1:0] other than zero, any attempt to configure the SAES peripheral for use by an application belonging to a different security domain (secure or non-secure) results in automatic key erasure and setting of the KEIF flag.\\nAttempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.",
340 ),
341 bit_offset: BitOffset::Regular(
342 RegularBitOffset {
343 offset: 24,
344 },
345 ),
346 bit_size: 2,
347 array: None,
348 enumm: Some(
349 "Kmod",
350 ),
351 },
352 Field {
353 name: "kshareid",
354 description: Some(
355 "Key share identification This bitfield defines, at the end of a decryption process with KMOD[1:0]=10 (shared key), which target can read the SAES key registers using a dedicated hardware bus. Others: Reserved Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.",
356 ),
357 bit_offset: BitOffset::Regular(
358 RegularBitOffset {
359 offset: 26,
360 },
361 ),
362 bit_size: 2,
363 array: None,
364 enumm: Some(
365 "Kshareid",
366 ),
367 },
368 Field {
369 name: "keysel",
370 description: Some(
371 "Key selection The bitfield defines the source of the key information to use in the AES cryptographic core. Others: Reserved (if used, unfreeze SAES with IPRST) When KEYSEL is different from zero, selected key value is available in key registers when BUSY bit is cleared and KEYVALID is set in the SAES_SR register. Otherwise, the key error flag KEIF is set. Repeated writing of KEYSEL[2:0] with the same non-zero value only triggers the loading of DHUK or BHK if KEYVALID = 0. When the application software changes the key selection by writing the KEYSEL[2:0] bitfield, the key registers are immediately erased and the KEYVALID flag cleared. At the end of the decryption process, if KMOD[1:0] is other than zero, KEYSEL[2:0] is cleared. With the bitfield value other than zero and KEYVALID set, the application cannot transfer the ownership of SAES with a loaded key to an application running in another security context (such as secure, non-secure). More specifically, when security of an access to any register does not match the information recorded by SAES, the KEIF flag is set. Attempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.",
372 ),
373 bit_offset: BitOffset::Regular(
374 RegularBitOffset {
375 offset: 28,
376 },
377 ),
378 bit_size: 3,
379 array: None,
380 enumm: Some(
381 "Keysel",
382 ),
383 },
384 Field {
385 name: "iprst",
386 description: Some(
387 "SAES peripheral software reset Setting the bit resets the SAES peripheral, putting all registers to their default values, except the IPRST bit itself and the SAES_DPACFG register. Hence, any key-relative data is lost. For this reason, it is recommended to set the bit before handing over the SAES to a less secure application. The bit must be low while writing any configuration registers.",
388 ),
389 bit_offset: BitOffset::Regular(
390 RegularBitOffset {
391 offset: 31,
392 },
393 ),
394 bit_size: 1,
395 array: None,
396 enumm: None,
397 },
398 ],
399 },
400 FieldSet {
401 name: "Icr",
402 extends: None,
403 description: Some(
404 "SAES interrupt clear register.",
405 ),
406 bit_size: 32,
407 fields: &[
408 Field {
409 name: "ccf",
410 description: Some(
411 "Computation complete flag clear Setting this bit clears the CCF status bit of the SAES_SR and SAES_ISR registers.",
412 ),
413 bit_offset: BitOffset::Regular(
414 RegularBitOffset {
415 offset: 0,
416 },
417 ),
418 bit_size: 1,
419 array: None,
420 enumm: None,
421 },
422 Field {
423 name: "rweif",
424 description: Some(
425 "Read or write error interrupt flag clear Setting this bit clears the RWEIF status bit of the SAES_ISR register, and both RDERR and WRERR flags in the SAES_SR register.",
426 ),
427 bit_offset: BitOffset::Regular(
428 RegularBitOffset {
429 offset: 1,
430 },
431 ),
432 bit_size: 1,
433 array: None,
434 enumm: None,
435 },
436 Field {
437 name: "keif",
438 description: Some(
439 "Key error interrupt flag clear Setting this bit clears the KEIF status bit of the SAES_ISR register.",
440 ),
441 bit_offset: BitOffset::Regular(
442 RegularBitOffset {
443 offset: 2,
444 },
445 ),
446 bit_size: 1,
447 array: None,
448 enumm: None,
449 },
450 Field {
451 name: "rngeif",
452 description: Some(
453 "RNG error interrupt flag clear Application must set this bit to clear the RNGEIF status bit in SAES_ISR register.",
454 ),
455 bit_offset: BitOffset::Regular(
456 RegularBitOffset {
457 offset: 3,
458 },
459 ),
460 bit_size: 1,
461 array: None,
462 enumm: None,
463 },
464 ],
465 },
466 FieldSet {
467 name: "Ier",
468 extends: None,
469 description: Some(
470 "SAES interrupt enable register.",
471 ),
472 bit_size: 32,
473 fields: &[
474 Field {
475 name: "ccfie",
476 description: Some(
477 "Computation complete flag interrupt enable This bit enables or disables (masks) the SAES interrupt generation when CCF (computation complete flag) is set.",
478 ),
479 bit_offset: BitOffset::Regular(
480 RegularBitOffset {
481 offset: 0,
482 },
483 ),
484 bit_size: 1,
485 array: None,
486 enumm: None,
487 },
488 Field {
489 name: "rweie",
490 description: Some(
491 "Read or write error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when RWEIF (read and/or write error flag) is set.",
492 ),
493 bit_offset: BitOffset::Regular(
494 RegularBitOffset {
495 offset: 1,
496 },
497 ),
498 bit_size: 1,
499 array: None,
500 enumm: None,
501 },
502 Field {
503 name: "keie",
504 description: Some(
505 "Key error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when KEIF (key error flag) is set.",
506 ),
507 bit_offset: BitOffset::Regular(
508 RegularBitOffset {
509 offset: 2,
510 },
511 ),
512 bit_size: 1,
513 array: None,
514 enumm: None,
515 },
516 Field {
517 name: "rngeie",
518 description: Some(
519 "RNG error interrupt enable This bit enables or disables (masks) the SAES interrupt generation when RNGEIF (RNG error flag) is set.",
520 ),
521 bit_offset: BitOffset::Regular(
522 RegularBitOffset {
523 offset: 3,
524 },
525 ),
526 bit_size: 1,
527 array: None,
528 enumm: None,
529 },
530 ],
531 },
532 FieldSet {
533 name: "Isr",
534 extends: None,
535 description: Some(
536 "SAES interrupt status register.",
537 ),
538 bit_size: 32,
539 fields: &[
540 Field {
541 name: "ccf",
542 description: Some(
543 "Computation complete flag This flag indicates whether the computation is completed: The flag is set by hardware upon the completion of the computation. It is cleared by software, upon setting the CCF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the SAES_IER register. The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1.",
544 ),
545 bit_offset: BitOffset::Regular(
546 RegularBitOffset {
547 offset: 0,
548 },
549 ),
550 bit_size: 1,
551 array: None,
552 enumm: None,
553 },
554 Field {
555 name: "rweif",
556 description: Some(
557 "Read or write error interrupt flag This read-only bit is set by hardware when a RDERR or a WRERR error flag is set in the SAES_SR register. RWEIF bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RWEIE bit has been previously set in the SAES_IER register. This flags has no meaning when key derivation mode is selected.",
558 ),
559 bit_offset: BitOffset::Regular(
560 RegularBitOffset {
561 offset: 1,
562 },
563 ),
564 bit_size: 1,
565 array: None,
566 enumm: None,
567 },
568 Field {
569 name: "keif",
570 description: Some(
571 "Key error interrupt flag This read-only bit is set by hardware when key information failed to load into key registers or key register usage is forbidden. Setting the corresponding bit of the SAES_ICR register clears the KEIF and generates interrupt if the KEIE bit of the SAES_IER register is set. KEIF is triggered upon any of the following errors: SAES fails to load the DHUK (KEYSEL = 001 or 100). SAES fails to load the BHK (KEYSEL = 010 or 100) respecting the correct order. AES fails to load the key shared by SAES peripheral (KMOD=10). When KEYVALID = 1 and (KEYPROT = 1 or KEYSEL is not 0x0), the security context of the application that loads the key (secure or non-secure) does not match the security attribute of the access to SAES_CR or SAES_DOUT. In this case, KEYVALID and EN bits are cleared. SAES_KEYRx register write does not respect the correct order. (For KEYSIZE = 0, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 register, or reverse. For KEYSIZE = 1, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 then SAES_KEYR4 then SAES_KEYR5 then SAES_KEYR6 then SAES_KEYR7, or reverse). KEIF must be cleared by the application software, otherwise KEYVALID cannot be set.",
572 ),
573 bit_offset: BitOffset::Regular(
574 RegularBitOffset {
575 offset: 2,
576 },
577 ),
578 bit_size: 1,
579 array: None,
580 enumm: None,
581 },
582 Field {
583 name: "rngeif",
584 description: Some(
585 "RNG error interrupt flag This read-only bit is set by hardware when an error is detected on RNG bus interface (e.g. bad entropy). RNGEIE bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RNGEIE bit has been previously set in the SAES_IER register. Clearing this bit triggers the reload of a new random number from RNG peripheral.",
586 ),
587 bit_offset: BitOffset::Regular(
588 RegularBitOffset {
589 offset: 3,
590 },
591 ),
592 bit_size: 1,
593 array: None,
594 enumm: None,
595 },
596 ],
597 },
598 FieldSet {
599 name: "Sr",
600 extends: None,
601 description: Some(
602 "SAES status register.",
603 ),
604 bit_size: 32,
605 fields: &[
606 Field {
607 name: "ccf",
608 description: Some(
609 "Computation completed flag. This bit mirrors the CCF bit of the SAES_ISR register.",
610 ),
611 bit_offset: BitOffset::Regular(
612 RegularBitOffset {
613 offset: 1,
614 },
615 ),
616 bit_size: 1,
617 array: None,
618 enumm: None,
619 },
620 Field {
621 name: "rderr",
622 description: Some(
623 "Read error flag This flag indicates the detection of an unexpected read operation from the SAES_DOUTR register (during computation or data input phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. The flag setting has no impact on the SAES operation. Unexpected read returns zero.",
624 ),
625 bit_offset: BitOffset::Regular(
626 RegularBitOffset {
627 offset: 1,
628 },
629 ),
630 bit_size: 1,
631 array: None,
632 enumm: None,
633 },
634 Field {
635 name: "wrerr",
636 description: Some(
637 "Write error This flag indicates the detection of an unexpected write operation to the SAES_DINR register (during computation or data output phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. The flag setting has no impact on the SAES operation. Unexpected write is ignored.",
638 ),
639 bit_offset: BitOffset::Regular(
640 RegularBitOffset {
641 offset: 2,
642 },
643 ),
644 bit_size: 1,
645 array: None,
646 enumm: None,
647 },
648 Field {
649 name: "busy",
650 description: Some(
651 "Busy This flag indicates whether SAES is idle or busy during GCM payload encryption phase: The flag is set upon SAES initialization, upon fetching random number from the RNG, or upon transferring a shared key to a target peripheral. When GCM encryption is selected, the flag must be at zero before selecting the GCM final phase.",
652 ),
653 bit_offset: BitOffset::Regular(
654 RegularBitOffset {
655 offset: 3,
656 },
657 ),
658 bit_size: 1,
659 array: None,
660 enumm: None,
661 },
662 Field {
663 name: "keyvalid",
664 description: Some(
665 "Key Valid flag This bit is set by hardware when the amount of key information defined by KEYSIZE in SAES_CR has been loaded in SAES_KEYx key registers. In normal mode when KEYSEL equals to zero, the application must write the key registers in the correct sequence, otherwise the KEIF flag of the SAES_ISR register is set and KEYVALID stays at zero. When KEYSEL is different from zero the BUSY flag is automatically set by SAES. When key is loaded successfully, the BUSY flag is cleared and KEYVALID set. Upon an error, the KEIF flag of the SAES_ISR register is set, the BUSY flag cleared and KEYVALID kept at zero. When the KEIF flag is set, the application must clear it through the SAES_ICR register, otherwise KEYVALID cannot be set. See the KEIF bit description for more details. For more information on key loading please refer to.",
666 ),
667 bit_offset: BitOffset::Regular(
668 RegularBitOffset {
669 offset: 7,
670 },
671 ),
672 bit_size: 1,
673 array: None,
674 enumm: None,
675 },
676 ],
677 },
678 ],
679 enums: &[
680 Enum {
681 name: "Chmod",
682 description: None,
683 bit_size: 3,
684 variants: &[
685 EnumVariant {
686 name: "ECB",
687 description: Some(
688 "Electronic codebook",
689 ),
690 value: 0,
691 },
692 EnumVariant {
693 name: "CBC",
694 description: Some(
695 "Cipher-block chaining",
696 ),
697 value: 1,
698 },
699 EnumVariant {
700 name: "CTR",
701 description: Some(
702 "Counter mode",
703 ),
704 value: 2,
705 },
706 EnumVariant {
707 name: "GCM_GMAC",
708 description: Some(
709 "Galois counter mode and Galois message authentication code",
710 ),
711 value: 3,
712 },
713 EnumVariant {
714 name: "CCM",
715 description: Some(
716 "Counter with CBC-MAC",
717 ),
718 value: 4,
719 },
720 ],
721 },
722 Enum {
723 name: "Datatype",
724 description: None,
725 bit_size: 2,
726 variants: &[
727 EnumVariant {
728 name: "NONE",
729 description: Some(
730 "No swapping (32-bit data).",
731 ),
732 value: 0,
733 },
734 EnumVariant {
735 name: "HALF_WORD",
736 description: Some(
737 "Half-word swapping (16-bit data)",
738 ),
739 value: 1,
740 },
741 EnumVariant {
742 name: "BYTE",
743 description: Some(
744 "Byte swapping (8-bit data)",
745 ),
746 value: 2,
747 },
748 EnumVariant {
749 name: "BIT",
750 description: Some(
751 "Bit-level swapping",
752 ),
753 value: 3,
754 },
755 ],
756 },
757 Enum {
758 name: "Keysel",
759 description: None,
760 bit_size: 3,
761 variants: &[
762 EnumVariant {
763 name: "SOFTWARE_KEY",
764 description: Some(
765 "Software key, loaded in key registers SAES_KEYx",
766 ),
767 value: 0,
768 },
769 EnumVariant {
770 name: "DHUK",
771 description: Some(
772 "Derived hardware unique key",
773 ),
774 value: 1,
775 },
776 EnumVariant {
777 name: "BHK",
778 description: Some(
779 "Boot hardware key",
780 ),
781 value: 2,
782 },
783 EnumVariant {
784 name: "XOR_DHUK_BHK",
785 description: Some(
786 "XOR of DHUK and BHK",
787 ),
788 value: 4,
789 },
790 ],
791 },
792 Enum {
793 name: "Keysize",
794 description: None,
795 bit_size: 1,
796 variants: &[
797 EnumVariant {
798 name: "BITS128",
799 description: Some(
800 "128-bit",
801 ),
802 value: 0,
803 },
804 EnumVariant {
805 name: "BITS256",
806 description: Some(
807 "256-bit",
808 ),
809 value: 1,
810 },
811 ],
812 },
813 Enum {
814 name: "Kmod",
815 description: None,
816 bit_size: 2,
817 variants: &[
818 EnumVariant {
819 name: "NORMAL",
820 description: Some(
821 "AES peripheral",
822 ),
823 value: 0,
824 },
825 EnumVariant {
826 name: "WRAPPED_KEY",
827 description: Some(
828 "Wrapped key for SAES mode. Key loaded in key registers can only be used to encrypt or\ndecrypt AES keys. Hence, when a decryption is selected, read-as-zero SAES_DOUTR register is\nautomatically loaded into SAES key registers after a successful decryption process.",
829 ),
830 value: 1,
831 },
832 EnumVariant {
833 name: "SHARED_KEY",
834 description: Some(
835 "Shared key mode. After a successful decryption process (unwrapping), SAES key registers are\nshared with the peripheral described in KSHAREID[1:0] bitfield. This sharing is valid only while\nKMOD[1:0] at 0x2 and KEYVALID=1. When a decryption is selected, read-as-zero SAES_DOUTR\nregister is automatically loaded into SAES key registers after a successful decryption process.",
836 ),
837 value: 2,
838 },
839 ],
840 },
841 Enum {
842 name: "Kshareid",
843 description: None,
844 bit_size: 2,
845 variants: &[
846 EnumVariant {
847 name: "AES",
848 description: Some(
849 "AES peripheral",
850 ),
851 value: 0,
852 },
853 ],
854 },
855 Enum {
856 name: "Mode",
857 description: None,
858 bit_size: 2,
859 variants: &[
860 EnumVariant {
861 name: "ENCRYPTION",
862 description: None,
863 value: 0,
864 },
865 EnumVariant {
866 name: "KEY_DERIVATION",
867 description: Some(
868 "Key derivation (or key preparation), for ECB/CBC decryption only",
869 ),
870 value: 1,
871 },
872 EnumVariant {
873 name: "DECRYPTION",
874 description: None,
875 value: 2,
876 },
877 ],
878 },
879 ],
880};
881