1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Ch",
7 extends: None,
8 description: Some(
9 "Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR",
10 ),
11 items: &[
12 BlockItem {
13 name: "cr1",
14 description: Some(
15 "Configuration register 1",
16 ),
17 array: None,
18 byte_offset: 0x0,
19 inner: BlockItemInner::Register(
20 Register {
21 access: Access::ReadWrite,
22 bit_size: 32,
23 fieldset: Some(
24 "Cr1",
25 ),
26 },
27 ),
28 },
29 BlockItem {
30 name: "cr2",
31 description: Some(
32 "Configuration register 2",
33 ),
34 array: None,
35 byte_offset: 0x4,
36 inner: BlockItemInner::Register(
37 Register {
38 access: Access::ReadWrite,
39 bit_size: 32,
40 fieldset: Some(
41 "Cr2",
42 ),
43 },
44 ),
45 },
46 BlockItem {
47 name: "frcr",
48 description: Some(
49 "This register has no meaning in AC97 and SPDIF audio protocol",
50 ),
51 array: None,
52 byte_offset: 0x8,
53 inner: BlockItemInner::Register(
54 Register {
55 access: Access::ReadWrite,
56 bit_size: 32,
57 fieldset: Some(
58 "Frcr",
59 ),
60 },
61 ),
62 },
63 BlockItem {
64 name: "slotr",
65 description: Some(
66 "This register has no meaning in AC97 and SPDIF audio protocol",
67 ),
68 array: None,
69 byte_offset: 0xc,
70 inner: BlockItemInner::Register(
71 Register {
72 access: Access::ReadWrite,
73 bit_size: 32,
74 fieldset: Some(
75 "Slotr",
76 ),
77 },
78 ),
79 },
80 BlockItem {
81 name: "im",
82 description: Some(
83 "Interrupt mask register 2",
84 ),
85 array: None,
86 byte_offset: 0x10,
87 inner: BlockItemInner::Register(
88 Register {
89 access: Access::ReadWrite,
90 bit_size: 32,
91 fieldset: Some(
92 "Im",
93 ),
94 },
95 ),
96 },
97 BlockItem {
98 name: "sr",
99 description: Some(
100 "Status register",
101 ),
102 array: None,
103 byte_offset: 0x14,
104 inner: BlockItemInner::Register(
105 Register {
106 access: Access::Read,
107 bit_size: 32,
108 fieldset: Some(
109 "Sr",
110 ),
111 },
112 ),
113 },
114 BlockItem {
115 name: "clrfr",
116 description: Some(
117 "Clear flag register",
118 ),
119 array: None,
120 byte_offset: 0x18,
121 inner: BlockItemInner::Register(
122 Register {
123 access: Access::Write,
124 bit_size: 32,
125 fieldset: Some(
126 "Clrfr",
127 ),
128 },
129 ),
130 },
131 BlockItem {
132 name: "dr",
133 description: Some(
134 "Data register",
135 ),
136 array: None,
137 byte_offset: 0x1c,
138 inner: BlockItemInner::Register(
139 Register {
140 access: Access::ReadWrite,
141 bit_size: 32,
142 fieldset: Some(
143 "Dr",
144 ),
145 },
146 ),
147 },
148 ],
149 },
150 Block {
151 name: "Sai",
152 extends: None,
153 description: Some(
154 "Serial audio interface",
155 ),
156 items: &[
157 BlockItem {
158 name: "gcr",
159 description: Some(
160 "Global configuration register",
161 ),
162 array: None,
163 byte_offset: 0x0,
164 inner: BlockItemInner::Register(
165 Register {
166 access: Access::ReadWrite,
167 bit_size: 32,
168 fieldset: Some(
169 "Gcr",
170 ),
171 },
172 ),
173 },
174 BlockItem {
175 name: "ch",
176 description: Some(
177 "Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR",
178 ),
179 array: Some(
180 Array::Regular(
181 RegularArray {
182 len: 2,
183 stride: 32,
184 },
185 ),
186 ),
187 byte_offset: 0x4,
188 inner: BlockItemInner::Block(
189 BlockItemBlock {
190 block: "Ch",
191 },
192 ),
193 },
194 BlockItem {
195 name: "pdmcr",
196 description: Some(
197 "PDM control register",
198 ),
199 array: None,
200 byte_offset: 0x44,
201 inner: BlockItemInner::Register(
202 Register {
203 access: Access::ReadWrite,
204 bit_size: 32,
205 fieldset: Some(
206 "Pdmcr",
207 ),
208 },
209 ),
210 },
211 BlockItem {
212 name: "pdmdly",
213 description: Some(
214 "PDM delay register",
215 ),
216 array: None,
217 byte_offset: 0x48,
218 inner: BlockItemInner::Register(
219 Register {
220 access: Access::ReadWrite,
221 bit_size: 32,
222 fieldset: Some(
223 "Pdmdly",
224 ),
225 },
226 ),
227 },
228 ],
229 },
230 ],
231 fieldsets: &[
232 FieldSet {
233 name: "Clrfr",
234 extends: None,
235 description: Some(
236 "Clear flag register",
237 ),
238 bit_size: 32,
239 fields: &[
240 Field {
241 name: "covrudr",
242 description: Some(
243 "Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0.",
244 ),
245 bit_offset: BitOffset::Regular(
246 RegularBitOffset {
247 offset: 0,
248 },
249 ),
250 bit_size: 1,
251 array: None,
252 enumm: None,
253 },
254 Field {
255 name: "cmutedet",
256 description: Some(
257 "Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0.",
258 ),
259 bit_offset: BitOffset::Regular(
260 RegularBitOffset {
261 offset: 1,
262 },
263 ),
264 bit_size: 1,
265 array: None,
266 enumm: None,
267 },
268 Field {
269 name: "cwckcfg",
270 description: Some(
271 "Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0.",
272 ),
273 bit_offset: BitOffset::Regular(
274 RegularBitOffset {
275 offset: 2,
276 },
277 ),
278 bit_size: 1,
279 array: None,
280 enumm: None,
281 },
282 Field {
283 name: "ccnrdy",
284 description: Some(
285 "Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0.",
286 ),
287 bit_offset: BitOffset::Regular(
288 RegularBitOffset {
289 offset: 4,
290 },
291 ),
292 bit_size: 1,
293 array: None,
294 enumm: None,
295 },
296 Field {
297 name: "cafsdet",
298 description: Some(
299 "Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0.",
300 ),
301 bit_offset: BitOffset::Regular(
302 RegularBitOffset {
303 offset: 5,
304 },
305 ),
306 bit_size: 1,
307 array: None,
308 enumm: None,
309 },
310 Field {
311 name: "clfsdet",
312 description: Some(
313 "Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0.",
314 ),
315 bit_offset: BitOffset::Regular(
316 RegularBitOffset {
317 offset: 6,
318 },
319 ),
320 bit_size: 1,
321 array: None,
322 enumm: None,
323 },
324 ],
325 },
326 FieldSet {
327 name: "Cr1",
328 extends: None,
329 description: Some(
330 "Configuration register 1",
331 ),
332 bit_size: 32,
333 fields: &[
334 Field {
335 name: "mode",
336 description: Some(
337 "SAIx audio block mode immediately",
338 ),
339 bit_offset: BitOffset::Regular(
340 RegularBitOffset {
341 offset: 0,
342 },
343 ),
344 bit_size: 2,
345 array: None,
346 enumm: Some(
347 "Mode",
348 ),
349 },
350 Field {
351 name: "prtcfg",
352 description: Some(
353 "Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled.",
354 ),
355 bit_offset: BitOffset::Regular(
356 RegularBitOffset {
357 offset: 2,
358 },
359 ),
360 bit_size: 2,
361 array: None,
362 enumm: Some(
363 "Prtcfg",
364 ),
365 },
366 Field {
367 name: "ds",
368 description: Some(
369 "Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled.",
370 ),
371 bit_offset: BitOffset::Regular(
372 RegularBitOffset {
373 offset: 5,
374 },
375 ),
376 bit_size: 3,
377 array: None,
378 enumm: Some(
379 "Ds",
380 ),
381 },
382 Field {
383 name: "lsbfirst",
384 description: Some(
385 "Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first.",
386 ),
387 bit_offset: BitOffset::Regular(
388 RegularBitOffset {
389 offset: 8,
390 },
391 ),
392 bit_size: 1,
393 array: None,
394 enumm: Some(
395 "Lsbfirst",
396 ),
397 },
398 Field {
399 name: "ckstr",
400 description: Some(
401 "Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol.",
402 ),
403 bit_offset: BitOffset::Regular(
404 RegularBitOffset {
405 offset: 9,
406 },
407 ),
408 bit_size: 1,
409 array: None,
410 enumm: Some(
411 "Ckstr",
412 ),
413 },
414 Field {
415 name: "syncen",
416 description: Some(
417 "Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled.",
418 ),
419 bit_offset: BitOffset::Regular(
420 RegularBitOffset {
421 offset: 10,
422 },
423 ),
424 bit_size: 2,
425 array: None,
426 enumm: Some(
427 "Syncen",
428 ),
429 },
430 Field {
431 name: "mono",
432 description: Some(
433 "Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details.",
434 ),
435 bit_offset: BitOffset::Regular(
436 RegularBitOffset {
437 offset: 12,
438 },
439 ),
440 bit_size: 1,
441 array: None,
442 enumm: Some(
443 "Mono",
444 ),
445 },
446 Field {
447 name: "outdriv",
448 description: Some(
449 "Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration.",
450 ),
451 bit_offset: BitOffset::Regular(
452 RegularBitOffset {
453 offset: 13,
454 },
455 ),
456 bit_size: 1,
457 array: None,
458 enumm: Some(
459 "Outdriv",
460 ),
461 },
462 Field {
463 name: "saien",
464 description: Some(
465 "Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit.",
466 ),
467 bit_offset: BitOffset::Regular(
468 RegularBitOffset {
469 offset: 16,
470 },
471 ),
472 bit_size: 1,
473 array: None,
474 enumm: None,
475 },
476 Field {
477 name: "dmaen",
478 description: Some(
479 "DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode.",
480 ),
481 bit_offset: BitOffset::Regular(
482 RegularBitOffset {
483 offset: 17,
484 },
485 ),
486 bit_size: 1,
487 array: None,
488 enumm: None,
489 },
490 Field {
491 name: "nodiv",
492 description: Some(
493 "No fixed divider between MCLK and FS",
494 ),
495 bit_offset: BitOffset::Regular(
496 RegularBitOffset {
497 offset: 19,
498 },
499 ),
500 bit_size: 1,
501 array: None,
502 enumm: Some(
503 "Nodiv",
504 ),
505 },
506 Field {
507 name: "mckdiv",
508 description: Some(
509 "Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula:",
510 ),
511 bit_offset: BitOffset::Regular(
512 RegularBitOffset {
513 offset: 20,
514 },
515 ),
516 bit_size: 6,
517 array: None,
518 enumm: None,
519 },
520 Field {
521 name: "osr",
522 description: Some(
523 "Oversampling ratio for master clock",
524 ),
525 bit_offset: BitOffset::Regular(
526 RegularBitOffset {
527 offset: 26,
528 },
529 ),
530 bit_size: 1,
531 array: None,
532 enumm: None,
533 },
534 Field {
535 name: "mcken",
536 description: Some(
537 "Master clock generation enable",
538 ),
539 bit_offset: BitOffset::Regular(
540 RegularBitOffset {
541 offset: 27,
542 },
543 ),
544 bit_size: 1,
545 array: None,
546 enumm: None,
547 },
548 ],
549 },
550 FieldSet {
551 name: "Cr2",
552 extends: None,
553 description: Some(
554 "Configuration register 2",
555 ),
556 bit_size: 32,
557 fields: &[
558 Field {
559 name: "fth",
560 description: Some(
561 "FIFO threshold. This bit is set and cleared by software.",
562 ),
563 bit_offset: BitOffset::Regular(
564 RegularBitOffset {
565 offset: 0,
566 },
567 ),
568 bit_size: 3,
569 array: None,
570 enumm: Some(
571 "Fth",
572 ),
573 },
574 Field {
575 name: "fflush",
576 description: Some(
577 "FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled.",
578 ),
579 bit_offset: BitOffset::Regular(
580 RegularBitOffset {
581 offset: 3,
582 },
583 ),
584 bit_size: 1,
585 array: None,
586 enumm: None,
587 },
588 Field {
589 name: "tris",
590 description: Some(
591 "Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details.",
592 ),
593 bit_offset: BitOffset::Regular(
594 RegularBitOffset {
595 offset: 4,
596 },
597 ),
598 bit_size: 1,
599 array: None,
600 enumm: None,
601 },
602 Field {
603 name: "mute",
604 description: Some(
605 "Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks.",
606 ),
607 bit_offset: BitOffset::Regular(
608 RegularBitOffset {
609 offset: 5,
610 },
611 ),
612 bit_size: 1,
613 array: None,
614 enumm: None,
615 },
616 Field {
617 name: "muteval",
618 description: Some(
619 "Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks.",
620 ),
621 bit_offset: BitOffset::Regular(
622 RegularBitOffset {
623 offset: 6,
624 },
625 ),
626 bit_size: 1,
627 array: None,
628 enumm: Some(
629 "Muteval",
630 ),
631 },
632 Field {
633 name: "mutecnt",
634 description: Some(
635 "Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details.",
636 ),
637 bit_offset: BitOffset::Regular(
638 RegularBitOffset {
639 offset: 7,
640 },
641 ),
642 bit_size: 6,
643 array: None,
644 enumm: None,
645 },
646 Field {
647 name: "cpl",
648 description: Some(
649 "Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm.",
650 ),
651 bit_offset: BitOffset::Regular(
652 RegularBitOffset {
653 offset: 13,
654 },
655 ),
656 bit_size: 1,
657 array: None,
658 enumm: Some(
659 "Cpl",
660 ),
661 },
662 Field {
663 name: "comp",
664 description: Some(
665 "Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected.",
666 ),
667 bit_offset: BitOffset::Regular(
668 RegularBitOffset {
669 offset: 14,
670 },
671 ),
672 bit_size: 2,
673 array: None,
674 enumm: Some(
675 "Comp",
676 ),
677 },
678 ],
679 },
680 FieldSet {
681 name: "Dr",
682 extends: None,
683 description: Some(
684 "Data register",
685 ),
686 bit_size: 32,
687 fields: &[
688 Field {
689 name: "data",
690 description: Some(
691 "Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty.",
692 ),
693 bit_offset: BitOffset::Regular(
694 RegularBitOffset {
695 offset: 0,
696 },
697 ),
698 bit_size: 32,
699 array: None,
700 enumm: None,
701 },
702 ],
703 },
704 FieldSet {
705 name: "Frcr",
706 extends: None,
707 description: Some(
708 "This register has no meaning in AC97 and SPDIF audio protocol",
709 ),
710 bit_size: 32,
711 fields: &[
712 Field {
713 name: "frl",
714 description: Some(
715 "Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration.",
716 ),
717 bit_offset: BitOffset::Regular(
718 RegularBitOffset {
719 offset: 0,
720 },
721 ),
722 bit_size: 8,
723 array: None,
724 enumm: None,
725 },
726 Field {
727 name: "fsall",
728 description: Some(
729 "Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled.",
730 ),
731 bit_offset: BitOffset::Regular(
732 RegularBitOffset {
733 offset: 8,
734 },
735 ),
736 bit_size: 7,
737 array: None,
738 enumm: None,
739 },
740 Field {
741 name: "fsdef",
742 description: Some(
743 "Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled.",
744 ),
745 bit_offset: BitOffset::Regular(
746 RegularBitOffset {
747 offset: 16,
748 },
749 ),
750 bit_size: 1,
751 array: None,
752 enumm: None,
753 },
754 Field {
755 name: "fspol",
756 description: Some(
757 "Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled.",
758 ),
759 bit_offset: BitOffset::Regular(
760 RegularBitOffset {
761 offset: 17,
762 },
763 ),
764 bit_size: 1,
765 array: None,
766 enumm: Some(
767 "Fspol",
768 ),
769 },
770 Field {
771 name: "fsoff",
772 description: Some(
773 "Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled.",
774 ),
775 bit_offset: BitOffset::Regular(
776 RegularBitOffset {
777 offset: 18,
778 },
779 ),
780 bit_size: 1,
781 array: None,
782 enumm: Some(
783 "Fsoff",
784 ),
785 },
786 ],
787 },
788 FieldSet {
789 name: "Gcr",
790 extends: None,
791 description: Some(
792 "Global configuration register",
793 ),
794 bit_size: 32,
795 fields: &[
796 Field {
797 name: "syncin",
798 description: Some(
799 "Synchronization inputs",
800 ),
801 bit_offset: BitOffset::Regular(
802 RegularBitOffset {
803 offset: 0,
804 },
805 ),
806 bit_size: 2,
807 array: None,
808 enumm: None,
809 },
810 Field {
811 name: "syncout",
812 description: Some(
813 "Synchronization outputs These bits are set and cleared by software.",
814 ),
815 bit_offset: BitOffset::Regular(
816 RegularBitOffset {
817 offset: 4,
818 },
819 ),
820 bit_size: 2,
821 array: None,
822 enumm: None,
823 },
824 ],
825 },
826 FieldSet {
827 name: "Im",
828 extends: None,
829 description: Some(
830 "Interrupt mask register 2",
831 ),
832 bit_size: 32,
833 fields: &[
834 Field {
835 name: "ovrudrie",
836 description: Some(
837 "Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set.",
838 ),
839 bit_offset: BitOffset::Regular(
840 RegularBitOffset {
841 offset: 0,
842 },
843 ),
844 bit_size: 1,
845 array: None,
846 enumm: None,
847 },
848 Field {
849 name: "mutedetie",
850 description: Some(
851 "Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode.",
852 ),
853 bit_offset: BitOffset::Regular(
854 RegularBitOffset {
855 offset: 1,
856 },
857 ),
858 bit_size: 1,
859 array: None,
860 enumm: None,
861 },
862 Field {
863 name: "wckcfgie",
864 description: Some(
865 "Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes.",
866 ),
867 bit_offset: BitOffset::Regular(
868 RegularBitOffset {
869 offset: 2,
870 },
871 ),
872 bit_size: 1,
873 array: None,
874 enumm: None,
875 },
876 Field {
877 name: "freqie",
878 description: Some(
879 "FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode,",
880 ),
881 bit_offset: BitOffset::Regular(
882 RegularBitOffset {
883 offset: 3,
884 },
885 ),
886 bit_size: 1,
887 array: None,
888 enumm: None,
889 },
890 Field {
891 name: "cnrdyie",
892 description: Some(
893 "Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver.",
894 ),
895 bit_offset: BitOffset::Regular(
896 RegularBitOffset {
897 offset: 4,
898 },
899 ),
900 bit_size: 1,
901 array: None,
902 enumm: None,
903 },
904 Field {
905 name: "afsdetie",
906 description: Some(
907 "Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master.",
908 ),
909 bit_offset: BitOffset::Regular(
910 RegularBitOffset {
911 offset: 5,
912 },
913 ),
914 bit_size: 1,
915 array: None,
916 enumm: None,
917 },
918 Field {
919 name: "lfsdetie",
920 description: Some(
921 "Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master.",
922 ),
923 bit_offset: BitOffset::Regular(
924 RegularBitOffset {
925 offset: 6,
926 },
927 ),
928 bit_size: 1,
929 array: None,
930 enumm: None,
931 },
932 ],
933 },
934 FieldSet {
935 name: "Pdmcr",
936 extends: None,
937 description: Some(
938 "PDM control register",
939 ),
940 bit_size: 32,
941 fields: &[
942 Field {
943 name: "pdmen",
944 description: Some(
945 "PDM enable",
946 ),
947 bit_offset: BitOffset::Regular(
948 RegularBitOffset {
949 offset: 0,
950 },
951 ),
952 bit_size: 1,
953 array: None,
954 enumm: None,
955 },
956 Field {
957 name: "micnbr",
958 description: Some(
959 "Number of microphones",
960 ),
961 bit_offset: BitOffset::Regular(
962 RegularBitOffset {
963 offset: 4,
964 },
965 ),
966 bit_size: 2,
967 array: None,
968 enumm: None,
969 },
970 Field {
971 name: "cken",
972 description: Some(
973 "Clock enable of bitstream clock number 1",
974 ),
975 bit_offset: BitOffset::Regular(
976 RegularBitOffset {
977 offset: 8,
978 },
979 ),
980 bit_size: 1,
981 array: Some(
982 Array::Regular(
983 RegularArray {
984 len: 2,
985 stride: 1,
986 },
987 ),
988 ),
989 enumm: None,
990 },
991 ],
992 },
993 FieldSet {
994 name: "Pdmdly",
995 extends: None,
996 description: Some(
997 "PDM delay register",
998 ),
999 bit_size: 32,
1000 fields: &[
1001 Field {
1002 name: "dlyml",
1003 description: Some(
1004 "Delay line adjust for first microphone of pair 1",
1005 ),
1006 bit_offset: BitOffset::Regular(
1007 RegularBitOffset {
1008 offset: 0,
1009 },
1010 ),
1011 bit_size: 3,
1012 array: Some(
1013 Array::Regular(
1014 RegularArray {
1015 len: 4,
1016 stride: 8,
1017 },
1018 ),
1019 ),
1020 enumm: None,
1021 },
1022 Field {
1023 name: "dlymr",
1024 description: Some(
1025 "Delay line adjust for second microphone of pair 1",
1026 ),
1027 bit_offset: BitOffset::Regular(
1028 RegularBitOffset {
1029 offset: 4,
1030 },
1031 ),
1032 bit_size: 3,
1033 array: Some(
1034 Array::Regular(
1035 RegularArray {
1036 len: 4,
1037 stride: 8,
1038 },
1039 ),
1040 ),
1041 enumm: None,
1042 },
1043 ],
1044 },
1045 FieldSet {
1046 name: "Slotr",
1047 extends: None,
1048 description: Some(
1049 "This register has no meaning in AC97 and SPDIF audio protocol",
1050 ),
1051 bit_size: 32,
1052 fields: &[
1053 Field {
1054 name: "fboff",
1055 description: Some(
1056 "First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode.",
1057 ),
1058 bit_offset: BitOffset::Regular(
1059 RegularBitOffset {
1060 offset: 0,
1061 },
1062 ),
1063 bit_size: 5,
1064 array: None,
1065 enumm: None,
1066 },
1067 Field {
1068 name: "slotsz",
1069 description: Some(
1070 "Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode.",
1071 ),
1072 bit_offset: BitOffset::Regular(
1073 RegularBitOffset {
1074 offset: 6,
1075 },
1076 ),
1077 bit_size: 2,
1078 array: None,
1079 enumm: Some(
1080 "Slotsz",
1081 ),
1082 },
1083 Field {
1084 name: "nbslot",
1085 description: Some(
1086 "Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode.",
1087 ),
1088 bit_offset: BitOffset::Regular(
1089 RegularBitOffset {
1090 offset: 8,
1091 },
1092 ),
1093 bit_size: 4,
1094 array: None,
1095 enumm: None,
1096 },
1097 Field {
1098 name: "sloten",
1099 description: Some(
1100 "Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode.",
1101 ),
1102 bit_offset: BitOffset::Regular(
1103 RegularBitOffset {
1104 offset: 16,
1105 },
1106 ),
1107 bit_size: 16,
1108 array: None,
1109 enumm: Some(
1110 "Sloten",
1111 ),
1112 },
1113 ],
1114 },
1115 FieldSet {
1116 name: "Sr",
1117 extends: None,
1118 description: Some(
1119 "Status register",
1120 ),
1121 bit_size: 32,
1122 fields: &[
1123 Field {
1124 name: "ovrudr",
1125 description: Some(
1126 "Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register.",
1127 ),
1128 bit_offset: BitOffset::Regular(
1129 RegularBitOffset {
1130 offset: 0,
1131 },
1132 ),
1133 bit_size: 1,
1134 array: None,
1135 enumm: None,
1136 },
1137 Field {
1138 name: "mutedet",
1139 description: Some(
1140 "Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register.",
1141 ),
1142 bit_offset: BitOffset::Regular(
1143 RegularBitOffset {
1144 offset: 1,
1145 },
1146 ),
1147 bit_size: 1,
1148 array: None,
1149 enumm: None,
1150 },
1151 Field {
1152 name: "wckcfg",
1153 description: Some(
1154 "Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register.",
1155 ),
1156 bit_offset: BitOffset::Regular(
1157 RegularBitOffset {
1158 offset: 2,
1159 },
1160 ),
1161 bit_size: 1,
1162 array: None,
1163 enumm: Some(
1164 "Wckcfg",
1165 ),
1166 },
1167 Field {
1168 name: "freq",
1169 description: Some(
1170 "FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register.",
1171 ),
1172 bit_offset: BitOffset::Regular(
1173 RegularBitOffset {
1174 offset: 3,
1175 },
1176 ),
1177 bit_size: 1,
1178 array: None,
1179 enumm: None,
1180 },
1181 Field {
1182 name: "cnrdy",
1183 description: Some(
1184 "Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register.",
1185 ),
1186 bit_offset: BitOffset::Regular(
1187 RegularBitOffset {
1188 offset: 4,
1189 },
1190 ),
1191 bit_size: 1,
1192 array: None,
1193 enumm: Some(
1194 "Cnrdy",
1195 ),
1196 },
1197 Field {
1198 name: "afsdet",
1199 description: Some(
1200 "Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register.",
1201 ),
1202 bit_offset: BitOffset::Regular(
1203 RegularBitOffset {
1204 offset: 5,
1205 },
1206 ),
1207 bit_size: 1,
1208 array: None,
1209 enumm: None,
1210 },
1211 Field {
1212 name: "lfsdet",
1213 description: Some(
1214 "Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register",
1215 ),
1216 bit_offset: BitOffset::Regular(
1217 RegularBitOffset {
1218 offset: 6,
1219 },
1220 ),
1221 bit_size: 1,
1222 array: None,
1223 enumm: None,
1224 },
1225 Field {
1226 name: "flvl",
1227 description: Some(
1228 "FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:",
1229 ),
1230 bit_offset: BitOffset::Regular(
1231 RegularBitOffset {
1232 offset: 16,
1233 },
1234 ),
1235 bit_size: 3,
1236 array: None,
1237 enumm: Some(
1238 "Flvl",
1239 ),
1240 },
1241 ],
1242 },
1243 ],
1244 enums: &[
1245 Enum {
1246 name: "Ckstr",
1247 description: None,
1248 bit_size: 1,
1249 variants: &[
1250 EnumVariant {
1251 name: "FALLING_EDGE",
1252 description: Some(
1253 "Data strobing edge is falling edge of SCK",
1254 ),
1255 value: 0,
1256 },
1257 EnumVariant {
1258 name: "RISING_EDGE",
1259 description: Some(
1260 "Data strobing edge is rising edge of SCK",
1261 ),
1262 value: 1,
1263 },
1264 ],
1265 },
1266 Enum {
1267 name: "Cnrdy",
1268 description: None,
1269 bit_size: 1,
1270 variants: &[
1271 EnumVariant {
1272 name: "READY",
1273 description: Some(
1274 "External AC’97 Codec is ready",
1275 ),
1276 value: 0,
1277 },
1278 EnumVariant {
1279 name: "NOT_READY",
1280 description: Some(
1281 "External AC’97 Codec is not ready",
1282 ),
1283 value: 1,
1284 },
1285 ],
1286 },
1287 Enum {
1288 name: "Comp",
1289 description: None,
1290 bit_size: 2,
1291 variants: &[
1292 EnumVariant {
1293 name: "NO_COMPANDING",
1294 description: Some(
1295 "No companding algorithm",
1296 ),
1297 value: 0,
1298 },
1299 EnumVariant {
1300 name: "MU_LAW",
1301 description: Some(
1302 "μ-Law algorithm",
1303 ),
1304 value: 2,
1305 },
1306 EnumVariant {
1307 name: "ALAW",
1308 description: Some(
1309 "A-Law algorithm",
1310 ),
1311 value: 3,
1312 },
1313 ],
1314 },
1315 Enum {
1316 name: "Cpl",
1317 description: None,
1318 bit_size: 1,
1319 variants: &[
1320 EnumVariant {
1321 name: "ONES_COMPLEMENT",
1322 description: Some(
1323 "1’s complement representation",
1324 ),
1325 value: 0,
1326 },
1327 EnumVariant {
1328 name: "TWOS_COMPLEMENT",
1329 description: Some(
1330 "2’s complement representation",
1331 ),
1332 value: 1,
1333 },
1334 ],
1335 },
1336 Enum {
1337 name: "Ds",
1338 description: None,
1339 bit_size: 3,
1340 variants: &[
1341 EnumVariant {
1342 name: "BIT8",
1343 description: Some(
1344 "8 bits",
1345 ),
1346 value: 2,
1347 },
1348 EnumVariant {
1349 name: "BIT10",
1350 description: Some(
1351 "10 bits",
1352 ),
1353 value: 3,
1354 },
1355 EnumVariant {
1356 name: "BIT16",
1357 description: Some(
1358 "16 bits",
1359 ),
1360 value: 4,
1361 },
1362 EnumVariant {
1363 name: "BIT20",
1364 description: Some(
1365 "20 bits",
1366 ),
1367 value: 5,
1368 },
1369 EnumVariant {
1370 name: "BIT24",
1371 description: Some(
1372 "24 bits",
1373 ),
1374 value: 6,
1375 },
1376 EnumVariant {
1377 name: "BIT32",
1378 description: Some(
1379 "32 bits",
1380 ),
1381 value: 7,
1382 },
1383 ],
1384 },
1385 Enum {
1386 name: "Flvl",
1387 description: None,
1388 bit_size: 3,
1389 variants: &[
1390 EnumVariant {
1391 name: "EMPTY",
1392 description: Some(
1393 "FIFO empty",
1394 ),
1395 value: 0,
1396 },
1397 EnumVariant {
1398 name: "QUARTER1",
1399 description: Some(
1400 "FIFO <= 1⁄4 but not empty",
1401 ),
1402 value: 1,
1403 },
1404 EnumVariant {
1405 name: "QUARTER2",
1406 description: Some(
1407 "1⁄4 < FIFO <= 1⁄2",
1408 ),
1409 value: 2,
1410 },
1411 EnumVariant {
1412 name: "QUARTER3",
1413 description: Some(
1414 "1⁄2 < FIFO <= 3⁄4",
1415 ),
1416 value: 3,
1417 },
1418 EnumVariant {
1419 name: "QUARTER4",
1420 description: Some(
1421 "3⁄4 < FIFO but not full",
1422 ),
1423 value: 4,
1424 },
1425 EnumVariant {
1426 name: "FULL",
1427 description: Some(
1428 "FIFO full",
1429 ),
1430 value: 5,
1431 },
1432 ],
1433 },
1434 Enum {
1435 name: "Fsoff",
1436 description: None,
1437 bit_size: 1,
1438 variants: &[
1439 EnumVariant {
1440 name: "ON_FIRST",
1441 description: Some(
1442 "FS is asserted on the first bit of the slot 0",
1443 ),
1444 value: 0,
1445 },
1446 EnumVariant {
1447 name: "BEFORE_FIRST",
1448 description: Some(
1449 "FS is asserted one bit before the first bit of the slot 0",
1450 ),
1451 value: 1,
1452 },
1453 ],
1454 },
1455 Enum {
1456 name: "Fspol",
1457 description: None,
1458 bit_size: 1,
1459 variants: &[
1460 EnumVariant {
1461 name: "FALLING_EDGE",
1462 description: Some(
1463 "FS is active low (falling edge)",
1464 ),
1465 value: 0,
1466 },
1467 EnumVariant {
1468 name: "RISING_EDGE",
1469 description: Some(
1470 "FS is active high (rising edge)",
1471 ),
1472 value: 1,
1473 },
1474 ],
1475 },
1476 Enum {
1477 name: "Fth",
1478 description: None,
1479 bit_size: 3,
1480 variants: &[
1481 EnumVariant {
1482 name: "EMPTY",
1483 description: Some(
1484 "FIFO empty",
1485 ),
1486 value: 0,
1487 },
1488 EnumVariant {
1489 name: "QUARTER1",
1490 description: Some(
1491 "1⁄4 FIFO",
1492 ),
1493 value: 1,
1494 },
1495 EnumVariant {
1496 name: "QUARTER2",
1497 description: Some(
1498 "1⁄2 FIFO",
1499 ),
1500 value: 2,
1501 },
1502 EnumVariant {
1503 name: "QUARTER3",
1504 description: Some(
1505 "3⁄4 FIFO",
1506 ),
1507 value: 3,
1508 },
1509 EnumVariant {
1510 name: "FULL",
1511 description: Some(
1512 "FIFO full",
1513 ),
1514 value: 4,
1515 },
1516 ],
1517 },
1518 Enum {
1519 name: "Lsbfirst",
1520 description: None,
1521 bit_size: 1,
1522 variants: &[
1523 EnumVariant {
1524 name: "MSB_FIRST",
1525 description: Some(
1526 "Data are transferred with MSB first",
1527 ),
1528 value: 0,
1529 },
1530 EnumVariant {
1531 name: "LSB_FIRST",
1532 description: Some(
1533 "Data are transferred with LSB first",
1534 ),
1535 value: 1,
1536 },
1537 ],
1538 },
1539 Enum {
1540 name: "Mode",
1541 description: None,
1542 bit_size: 2,
1543 variants: &[
1544 EnumVariant {
1545 name: "MASTER_TX",
1546 description: Some(
1547 "Master transmitter",
1548 ),
1549 value: 0,
1550 },
1551 EnumVariant {
1552 name: "MASTER_RX",
1553 description: Some(
1554 "Master receiver",
1555 ),
1556 value: 1,
1557 },
1558 EnumVariant {
1559 name: "SLAVE_TX",
1560 description: Some(
1561 "Slave transmitter",
1562 ),
1563 value: 2,
1564 },
1565 EnumVariant {
1566 name: "SLAVE_RX",
1567 description: Some(
1568 "Slave receiver",
1569 ),
1570 value: 3,
1571 },
1572 ],
1573 },
1574 Enum {
1575 name: "Mono",
1576 description: None,
1577 bit_size: 1,
1578 variants: &[
1579 EnumVariant {
1580 name: "STEREO",
1581 description: Some(
1582 "Stereo mode",
1583 ),
1584 value: 0,
1585 },
1586 EnumVariant {
1587 name: "MONO",
1588 description: Some(
1589 "Mono mode",
1590 ),
1591 value: 1,
1592 },
1593 ],
1594 },
1595 Enum {
1596 name: "Muteval",
1597 description: None,
1598 bit_size: 1,
1599 variants: &[
1600 EnumVariant {
1601 name: "SEND_ZERO",
1602 description: Some(
1603 "Bit value 0 is sent during the mute mode",
1604 ),
1605 value: 0,
1606 },
1607 EnumVariant {
1608 name: "SEND_LAST",
1609 description: Some(
1610 "Last values are sent during the mute mode",
1611 ),
1612 value: 1,
1613 },
1614 ],
1615 },
1616 Enum {
1617 name: "Nodiv",
1618 description: None,
1619 bit_size: 1,
1620 variants: &[
1621 EnumVariant {
1622 name: "MASTER_CLOCK",
1623 description: Some(
1624 "MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value",
1625 ),
1626 value: 0,
1627 },
1628 EnumVariant {
1629 name: "NO_DIV",
1630 description: Some(
1631 "MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.",
1632 ),
1633 value: 1,
1634 },
1635 ],
1636 },
1637 Enum {
1638 name: "Outdriv",
1639 description: None,
1640 bit_size: 1,
1641 variants: &[
1642 EnumVariant {
1643 name: "ON_START",
1644 description: Some(
1645 "Audio block output driven when SAIEN is set",
1646 ),
1647 value: 0,
1648 },
1649 EnumVariant {
1650 name: "IMMEDIATELY",
1651 description: Some(
1652 "Audio block output driven immediately after the setting of this bit",
1653 ),
1654 value: 1,
1655 },
1656 ],
1657 },
1658 Enum {
1659 name: "Prtcfg",
1660 description: None,
1661 bit_size: 2,
1662 variants: &[
1663 EnumVariant {
1664 name: "FREE",
1665 description: Some(
1666 "Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol",
1667 ),
1668 value: 0,
1669 },
1670 EnumVariant {
1671 name: "SPDIF",
1672 description: Some(
1673 "SPDIF protocol",
1674 ),
1675 value: 1,
1676 },
1677 EnumVariant {
1678 name: "AC97",
1679 description: Some(
1680 "AC’97 protocol",
1681 ),
1682 value: 2,
1683 },
1684 ],
1685 },
1686 Enum {
1687 name: "Sloten",
1688 description: None,
1689 bit_size: 16,
1690 variants: &[
1691 EnumVariant {
1692 name: "INACTIVE",
1693 description: Some(
1694 "Inactive slot",
1695 ),
1696 value: 0,
1697 },
1698 EnumVariant {
1699 name: "ACTIVE",
1700 description: Some(
1701 "Active slot",
1702 ),
1703 value: 1,
1704 },
1705 ],
1706 },
1707 Enum {
1708 name: "Slotsz",
1709 description: None,
1710 bit_size: 2,
1711 variants: &[
1712 EnumVariant {
1713 name: "DATA_SIZE",
1714 description: Some(
1715 "The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)",
1716 ),
1717 value: 0,
1718 },
1719 EnumVariant {
1720 name: "BIT16",
1721 description: Some(
1722 "16-bit",
1723 ),
1724 value: 1,
1725 },
1726 EnumVariant {
1727 name: "BIT32",
1728 description: Some(
1729 "32-bit",
1730 ),
1731 value: 2,
1732 },
1733 ],
1734 },
1735 Enum {
1736 name: "Syncen",
1737 description: None,
1738 bit_size: 2,
1739 variants: &[
1740 EnumVariant {
1741 name: "ASYNCHRONOUS",
1742 description: Some(
1743 "audio sub-block in asynchronous mode",
1744 ),
1745 value: 0,
1746 },
1747 EnumVariant {
1748 name: "INTERNAL",
1749 description: Some(
1750 "audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode",
1751 ),
1752 value: 1,
1753 },
1754 EnumVariant {
1755 name: "EXTERNAL",
1756 description: Some(
1757 "audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode",
1758 ),
1759 value: 2,
1760 },
1761 ],
1762 },
1763 Enum {
1764 name: "Wckcfg",
1765 description: None,
1766 bit_size: 1,
1767 variants: &[
1768 EnumVariant {
1769 name: "CORRECT",
1770 description: Some(
1771 "Clock configuration is correct",
1772 ),
1773 value: 0,
1774 },
1775 EnumVariant {
1776 name: "WRONG",
1777 description: Some(
1778 "Clock configuration does not respect the rule concerning the frame length specification",
1779 ),
1780 value: 1,
1781 },
1782 ],
1783 },
1784 ],
1785};
1786