1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Sdmmc",
7 extends: None,
8 description: Some(
9 "SDMMC",
10 ),
11 items: &[
12 BlockItem {
13 name: "power",
14 description: Some(
15 "SDMMC power control register",
16 ),
17 array: None,
18 byte_offset: 0x0,
19 inner: BlockItemInner::Register(
20 Register {
21 access: Access::ReadWrite,
22 bit_size: 32,
23 fieldset: Some(
24 "Power",
25 ),
26 },
27 ),
28 },
29 BlockItem {
30 name: "clkcr",
31 description: Some(
32 "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width.",
33 ),
34 array: None,
35 byte_offset: 0x4,
36 inner: BlockItemInner::Register(
37 Register {
38 access: Access::ReadWrite,
39 bit_size: 32,
40 fieldset: Some(
41 "Clkcr",
42 ),
43 },
44 ),
45 },
46 BlockItem {
47 name: "argr",
48 description: Some(
49 "The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message.",
50 ),
51 array: None,
52 byte_offset: 0x8,
53 inner: BlockItemInner::Register(
54 Register {
55 access: Access::ReadWrite,
56 bit_size: 32,
57 fieldset: Some(
58 "Argr",
59 ),
60 },
61 ),
62 },
63 BlockItem {
64 name: "cmdr",
65 description: Some(
66 "The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM).",
67 ),
68 array: None,
69 byte_offset: 0xc,
70 inner: BlockItemInner::Register(
71 Register {
72 access: Access::ReadWrite,
73 bit_size: 32,
74 fieldset: Some(
75 "Cmdr",
76 ),
77 },
78 ),
79 },
80 BlockItem {
81 name: "respcmdr",
82 description: Some(
83 "SDMMC command response register",
84 ),
85 array: None,
86 byte_offset: 0x10,
87 inner: BlockItemInner::Register(
88 Register {
89 access: Access::Read,
90 bit_size: 32,
91 fieldset: Some(
92 "Respcmdr",
93 ),
94 },
95 ),
96 },
97 BlockItem {
98 name: "respr",
99 description: Some(
100 "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.",
101 ),
102 array: Some(
103 Array::Regular(
104 RegularArray {
105 len: 4,
106 stride: 4,
107 },
108 ),
109 ),
110 byte_offset: 0x14,
111 inner: BlockItemInner::Register(
112 Register {
113 access: Access::Read,
114 bit_size: 32,
115 fieldset: Some(
116 "RespxR",
117 ),
118 },
119 ),
120 },
121 BlockItem {
122 name: "dtimer",
123 description: Some(
124 "The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set.",
125 ),
126 array: None,
127 byte_offset: 0x24,
128 inner: BlockItemInner::Register(
129 Register {
130 access: Access::ReadWrite,
131 bit_size: 32,
132 fieldset: Some(
133 "Dtimer",
134 ),
135 },
136 ),
137 },
138 BlockItem {
139 name: "dlenr",
140 description: Some(
141 "The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts.",
142 ),
143 array: None,
144 byte_offset: 0x28,
145 inner: BlockItemInner::Register(
146 Register {
147 access: Access::ReadWrite,
148 bit_size: 32,
149 fieldset: Some(
150 "Dlenr",
151 ),
152 },
153 ),
154 },
155 BlockItem {
156 name: "dctrl",
157 description: Some(
158 "The SDMMC_DCTRL register control the data path state machine (DPSM).",
159 ),
160 array: None,
161 byte_offset: 0x2c,
162 inner: BlockItemInner::Register(
163 Register {
164 access: Access::ReadWrite,
165 bit_size: 32,
166 fieldset: Some(
167 "Dctrl",
168 ),
169 },
170 ),
171 },
172 BlockItem {
173 name: "dcntr",
174 description: Some(
175 "The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set.",
176 ),
177 array: None,
178 byte_offset: 0x30,
179 inner: BlockItemInner::Register(
180 Register {
181 access: Access::Read,
182 bit_size: 32,
183 fieldset: Some(
184 "Dcntr",
185 ),
186 },
187 ),
188 },
189 BlockItem {
190 name: "star",
191 description: Some(
192 "The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)",
193 ),
194 array: None,
195 byte_offset: 0x34,
196 inner: BlockItemInner::Register(
197 Register {
198 access: Access::Read,
199 bit_size: 32,
200 fieldset: Some(
201 "Star",
202 ),
203 },
204 ),
205 },
206 BlockItem {
207 name: "icr",
208 description: Some(
209 "The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register.",
210 ),
211 array: None,
212 byte_offset: 0x38,
213 inner: BlockItemInner::Register(
214 Register {
215 access: Access::ReadWrite,
216 bit_size: 32,
217 fieldset: Some(
218 "Icr",
219 ),
220 },
221 ),
222 },
223 BlockItem {
224 name: "maskr",
225 description: Some(
226 "The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1.",
227 ),
228 array: None,
229 byte_offset: 0x3c,
230 inner: BlockItemInner::Register(
231 Register {
232 access: Access::ReadWrite,
233 bit_size: 32,
234 fieldset: Some(
235 "Maskr",
236 ),
237 },
238 ),
239 },
240 BlockItem {
241 name: "acktimer",
242 description: Some(
243 "The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set.",
244 ),
245 array: None,
246 byte_offset: 0x40,
247 inner: BlockItemInner::Register(
248 Register {
249 access: Access::ReadWrite,
250 bit_size: 32,
251 fieldset: Some(
252 "Acktimer",
253 ),
254 },
255 ),
256 },
257 BlockItem {
258 name: "idmactrlr",
259 description: Some(
260 "The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.",
261 ),
262 array: None,
263 byte_offset: 0x50,
264 inner: BlockItemInner::Register(
265 Register {
266 access: Access::ReadWrite,
267 bit_size: 32,
268 fieldset: Some(
269 "Idmactrlr",
270 ),
271 },
272 ),
273 },
274 BlockItem {
275 name: "idmabsizer",
276 description: Some(
277 "The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration.",
278 ),
279 array: None,
280 byte_offset: 0x54,
281 inner: BlockItemInner::Register(
282 Register {
283 access: Access::ReadWrite,
284 bit_size: 32,
285 fieldset: Some(
286 "Idmabsizer",
287 ),
288 },
289 ),
290 },
291 BlockItem {
292 name: "idmabase0r",
293 description: Some(
294 "The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration.",
295 ),
296 array: None,
297 byte_offset: 0x58,
298 inner: BlockItemInner::Register(
299 Register {
300 access: Access::ReadWrite,
301 bit_size: 32,
302 fieldset: Some(
303 "Idmabase0r",
304 ),
305 },
306 ),
307 },
308 BlockItem {
309 name: "idmabase1r",
310 description: Some(
311 "The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address.",
312 ),
313 array: None,
314 byte_offset: 0x5c,
315 inner: BlockItemInner::Register(
316 Register {
317 access: Access::ReadWrite,
318 bit_size: 32,
319 fieldset: Some(
320 "Idmabase1r",
321 ),
322 },
323 ),
324 },
325 BlockItem {
326 name: "fifor",
327 description: Some(
328 "The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.",
329 ),
330 array: None,
331 byte_offset: 0x80,
332 inner: BlockItemInner::Register(
333 Register {
334 access: Access::ReadWrite,
335 bit_size: 32,
336 fieldset: Some(
337 "Fifor",
338 ),
339 },
340 ),
341 },
342 BlockItem {
343 name: "ver",
344 description: Some(
345 "SDMMC IP version register",
346 ),
347 array: None,
348 byte_offset: 0x3f4,
349 inner: BlockItemInner::Register(
350 Register {
351 access: Access::Read,
352 bit_size: 32,
353 fieldset: Some(
354 "Ver",
355 ),
356 },
357 ),
358 },
359 BlockItem {
360 name: "id",
361 description: Some(
362 "SDMMC IP identification register",
363 ),
364 array: None,
365 byte_offset: 0x3f8,
366 inner: BlockItemInner::Register(
367 Register {
368 access: Access::Read,
369 bit_size: 32,
370 fieldset: Some(
371 "Id",
372 ),
373 },
374 ),
375 },
376 ],
377 },
378 ],
379 fieldsets: &[
380 FieldSet {
381 name: "Acktimer",
382 extends: None,
383 description: Some(
384 "The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set.",
385 ),
386 bit_size: 32,
387 fields: &[
388 Field {
389 name: "acktime",
390 description: Some(
391 "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods.",
392 ),
393 bit_offset: BitOffset::Regular(
394 RegularBitOffset {
395 offset: 0,
396 },
397 ),
398 bit_size: 25,
399 array: None,
400 enumm: None,
401 },
402 ],
403 },
404 FieldSet {
405 name: "Argr",
406 extends: None,
407 description: Some(
408 "The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message.",
409 ),
410 bit_size: 32,
411 fields: &[
412 Field {
413 name: "cmdarg",
414 description: Some(
415 "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register.",
416 ),
417 bit_offset: BitOffset::Regular(
418 RegularBitOffset {
419 offset: 0,
420 },
421 ),
422 bit_size: 32,
423 array: None,
424 enumm: None,
425 },
426 ],
427 },
428 FieldSet {
429 name: "Clkcr",
430 extends: None,
431 description: Some(
432 "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width.",
433 ),
434 bit_size: 32,
435 fields: &[
436 Field {
437 name: "clkdiv",
438 description: Some(
439 "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc..",
440 ),
441 bit_offset: BitOffset::Regular(
442 RegularBitOffset {
443 offset: 0,
444 },
445 ),
446 bit_size: 10,
447 array: None,
448 enumm: None,
449 },
450 Field {
451 name: "pwrsav",
452 description: Some(
453 "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:",
454 ),
455 bit_offset: BitOffset::Regular(
456 RegularBitOffset {
457 offset: 12,
458 },
459 ),
460 bit_size: 1,
461 array: None,
462 enumm: None,
463 },
464 Field {
465 name: "widbus",
466 description: Some(
467 "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)",
468 ),
469 bit_offset: BitOffset::Regular(
470 RegularBitOffset {
471 offset: 14,
472 },
473 ),
474 bit_size: 2,
475 array: None,
476 enumm: None,
477 },
478 Field {
479 name: "negedge",
480 description: Some(
481 "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge.",
482 ),
483 bit_offset: BitOffset::Regular(
484 RegularBitOffset {
485 offset: 16,
486 },
487 ),
488 bit_size: 1,
489 array: None,
490 enumm: None,
491 },
492 Field {
493 name: "hwfc_en",
494 description: Some(
495 "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11.",
496 ),
497 bit_offset: BitOffset::Regular(
498 RegularBitOffset {
499 offset: 17,
500 },
501 ),
502 bit_size: 1,
503 array: None,
504 enumm: None,
505 },
506 Field {
507 name: "ddr",
508 description: Some(
509 "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0)",
510 ),
511 bit_offset: BitOffset::Regular(
512 RegularBitOffset {
513 offset: 18,
514 },
515 ),
516 bit_size: 1,
517 array: None,
518 enumm: None,
519 },
520 Field {
521 name: "busspeed",
522 description: Some(
523 "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)",
524 ),
525 bit_offset: BitOffset::Regular(
526 RegularBitOffset {
527 offset: 19,
528 },
529 ),
530 bit_size: 1,
531 array: None,
532 enumm: None,
533 },
534 Field {
535 name: "selclkrx",
536 description: Some(
537 "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)",
538 ),
539 bit_offset: BitOffset::Regular(
540 RegularBitOffset {
541 offset: 20,
542 },
543 ),
544 bit_size: 2,
545 array: None,
546 enumm: None,
547 },
548 ],
549 },
550 FieldSet {
551 name: "Cmdr",
552 extends: None,
553 description: Some(
554 "The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM).",
555 ),
556 bit_size: 32,
557 fields: &[
558 Field {
559 name: "cmdindex",
560 description: Some(
561 "Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message.",
562 ),
563 bit_offset: BitOffset::Regular(
564 RegularBitOffset {
565 offset: 0,
566 },
567 ),
568 bit_size: 6,
569 array: None,
570 enumm: None,
571 },
572 Field {
573 name: "cmdtrans",
574 description: Some(
575 "The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent.",
576 ),
577 bit_offset: BitOffset::Regular(
578 RegularBitOffset {
579 offset: 6,
580 },
581 ),
582 bit_size: 1,
583 array: None,
584 enumm: None,
585 },
586 Field {
587 name: "cmdstop",
588 description: Some(
589 "The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent.",
590 ),
591 bit_offset: BitOffset::Regular(
592 RegularBitOffset {
593 offset: 7,
594 },
595 ),
596 bit_size: 1,
597 array: None,
598 enumm: None,
599 },
600 Field {
601 name: "waitresp",
602 description: Some(
603 "Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response.",
604 ),
605 bit_offset: BitOffset::Regular(
606 RegularBitOffset {
607 offset: 8,
608 },
609 ),
610 bit_size: 2,
611 array: None,
612 enumm: None,
613 },
614 Field {
615 name: "waitint",
616 description: Some(
617 "CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode.",
618 ),
619 bit_offset: BitOffset::Regular(
620 RegularBitOffset {
621 offset: 10,
622 },
623 ),
624 bit_size: 1,
625 array: None,
626 enumm: None,
627 },
628 Field {
629 name: "waitpend",
630 description: Some(
631 "CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card.",
632 ),
633 bit_offset: BitOffset::Regular(
634 RegularBitOffset {
635 offset: 11,
636 },
637 ),
638 bit_size: 1,
639 array: None,
640 enumm: None,
641 },
642 Field {
643 name: "cpsmen",
644 description: Some(
645 "Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0.",
646 ),
647 bit_offset: BitOffset::Regular(
648 RegularBitOffset {
649 offset: 12,
650 },
651 ),
652 bit_size: 1,
653 array: None,
654 enumm: None,
655 },
656 Field {
657 name: "dthold",
658 description: Some(
659 "Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state.",
660 ),
661 bit_offset: BitOffset::Regular(
662 RegularBitOffset {
663 offset: 13,
664 },
665 ),
666 bit_size: 1,
667 array: None,
668 enumm: None,
669 },
670 Field {
671 name: "bootmode",
672 description: Some(
673 "Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)",
674 ),
675 bit_offset: BitOffset::Regular(
676 RegularBitOffset {
677 offset: 14,
678 },
679 ),
680 bit_size: 1,
681 array: None,
682 enumm: None,
683 },
684 Field {
685 name: "booten",
686 description: Some(
687 "Enable boot mode procedure.",
688 ),
689 bit_offset: BitOffset::Regular(
690 RegularBitOffset {
691 offset: 15,
692 },
693 ),
694 bit_size: 1,
695 array: None,
696 enumm: None,
697 },
698 Field {
699 name: "cmdsuspend",
700 description: Some(
701 "The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1.",
702 ),
703 bit_offset: BitOffset::Regular(
704 RegularBitOffset {
705 offset: 16,
706 },
707 ),
708 bit_size: 1,
709 array: None,
710 enumm: None,
711 },
712 ],
713 },
714 FieldSet {
715 name: "Dcntr",
716 extends: None,
717 description: Some(
718 "The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set.",
719 ),
720 bit_size: 32,
721 fields: &[
722 Field {
723 name: "datacount",
724 description: Some(
725 "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect.",
726 ),
727 bit_offset: BitOffset::Regular(
728 RegularBitOffset {
729 offset: 0,
730 },
731 ),
732 bit_size: 25,
733 array: None,
734 enumm: None,
735 },
736 ],
737 },
738 FieldSet {
739 name: "Dctrl",
740 extends: None,
741 description: Some(
742 "The SDMMC_DCTRL register control the data path state machine (DPSM).",
743 ),
744 bit_size: 32,
745 fields: &[
746 Field {
747 name: "dten",
748 description: Some(
749 "Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards.",
750 ),
751 bit_offset: BitOffset::Regular(
752 RegularBitOffset {
753 offset: 0,
754 },
755 ),
756 bit_size: 1,
757 array: None,
758 enumm: None,
759 },
760 Field {
761 name: "dtdir",
762 description: Some(
763 "Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).",
764 ),
765 bit_offset: BitOffset::Regular(
766 RegularBitOffset {
767 offset: 1,
768 },
769 ),
770 bit_size: 1,
771 array: None,
772 enumm: None,
773 },
774 Field {
775 name: "dtmode",
776 description: Some(
777 "Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).",
778 ),
779 bit_offset: BitOffset::Regular(
780 RegularBitOffset {
781 offset: 2,
782 },
783 ),
784 bit_size: 2,
785 array: None,
786 enumm: None,
787 },
788 Field {
789 name: "dblocksize",
790 description: Some(
791 "Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)",
792 ),
793 bit_offset: BitOffset::Regular(
794 RegularBitOffset {
795 offset: 4,
796 },
797 ),
798 bit_size: 4,
799 array: None,
800 enumm: None,
801 },
802 Field {
803 name: "rwstart",
804 description: Some(
805 "Read wait start. If this bit is set, read wait operation starts.",
806 ),
807 bit_offset: BitOffset::Regular(
808 RegularBitOffset {
809 offset: 8,
810 },
811 ),
812 bit_size: 1,
813 array: None,
814 enumm: None,
815 },
816 Field {
817 name: "rwstop",
818 description: Some(
819 "Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state.",
820 ),
821 bit_offset: BitOffset::Regular(
822 RegularBitOffset {
823 offset: 9,
824 },
825 ),
826 bit_size: 1,
827 array: None,
828 enumm: None,
829 },
830 Field {
831 name: "rwmod",
832 description: Some(
833 "Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).",
834 ),
835 bit_offset: BitOffset::Regular(
836 RegularBitOffset {
837 offset: 10,
838 },
839 ),
840 bit_size: 1,
841 array: None,
842 enumm: None,
843 },
844 Field {
845 name: "sdioen",
846 description: Some(
847 "SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation.",
848 ),
849 bit_offset: BitOffset::Regular(
850 RegularBitOffset {
851 offset: 11,
852 },
853 ),
854 bit_size: 1,
855 array: None,
856 enumm: None,
857 },
858 Field {
859 name: "bootacken",
860 description: Some(
861 "Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).",
862 ),
863 bit_offset: BitOffset::Regular(
864 RegularBitOffset {
865 offset: 12,
866 },
867 ),
868 bit_size: 1,
869 array: None,
870 enumm: None,
871 },
872 Field {
873 name: "fiforst",
874 description: Some(
875 "FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs.",
876 ),
877 bit_offset: BitOffset::Regular(
878 RegularBitOffset {
879 offset: 13,
880 },
881 ),
882 bit_size: 1,
883 array: None,
884 enumm: None,
885 },
886 ],
887 },
888 FieldSet {
889 name: "Dlenr",
890 extends: None,
891 description: Some(
892 "The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts.",
893 ),
894 bit_size: 32,
895 fields: &[
896 Field {
897 name: "datalength",
898 description: Some(
899 "Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0.",
900 ),
901 bit_offset: BitOffset::Regular(
902 RegularBitOffset {
903 offset: 0,
904 },
905 ),
906 bit_size: 25,
907 array: None,
908 enumm: None,
909 },
910 ],
911 },
912 FieldSet {
913 name: "Dtimer",
914 extends: None,
915 description: Some(
916 "The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set.",
917 ),
918 bit_size: 32,
919 fields: &[
920 Field {
921 name: "datatime",
922 description: Some(
923 "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods.",
924 ),
925 bit_offset: BitOffset::Regular(
926 RegularBitOffset {
927 offset: 0,
928 },
929 ),
930 bit_size: 32,
931 array: None,
932 enumm: None,
933 },
934 ],
935 },
936 FieldSet {
937 name: "Fifor",
938 extends: None,
939 description: Some(
940 "The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.",
941 ),
942 bit_size: 32,
943 fields: &[
944 Field {
945 name: "fifodata",
946 description: Some(
947 "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words.",
948 ),
949 bit_offset: BitOffset::Regular(
950 RegularBitOffset {
951 offset: 0,
952 },
953 ),
954 bit_size: 32,
955 array: None,
956 enumm: None,
957 },
958 ],
959 },
960 FieldSet {
961 name: "Icr",
962 extends: None,
963 description: Some(
964 "The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register.",
965 ),
966 bit_size: 32,
967 fields: &[
968 Field {
969 name: "ccrcfailc",
970 description: Some(
971 "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag.",
972 ),
973 bit_offset: BitOffset::Regular(
974 RegularBitOffset {
975 offset: 0,
976 },
977 ),
978 bit_size: 1,
979 array: None,
980 enumm: None,
981 },
982 Field {
983 name: "dcrcfailc",
984 description: Some(
985 "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag.",
986 ),
987 bit_offset: BitOffset::Regular(
988 RegularBitOffset {
989 offset: 1,
990 },
991 ),
992 bit_size: 1,
993 array: None,
994 enumm: None,
995 },
996 Field {
997 name: "ctimeoutc",
998 description: Some(
999 "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag.",
1000 ),
1001 bit_offset: BitOffset::Regular(
1002 RegularBitOffset {
1003 offset: 2,
1004 },
1005 ),
1006 bit_size: 1,
1007 array: None,
1008 enumm: None,
1009 },
1010 Field {
1011 name: "dtimeoutc",
1012 description: Some(
1013 "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag.",
1014 ),
1015 bit_offset: BitOffset::Regular(
1016 RegularBitOffset {
1017 offset: 3,
1018 },
1019 ),
1020 bit_size: 1,
1021 array: None,
1022 enumm: None,
1023 },
1024 Field {
1025 name: "txunderrc",
1026 description: Some(
1027 "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag.",
1028 ),
1029 bit_offset: BitOffset::Regular(
1030 RegularBitOffset {
1031 offset: 4,
1032 },
1033 ),
1034 bit_size: 1,
1035 array: None,
1036 enumm: None,
1037 },
1038 Field {
1039 name: "rxoverrc",
1040 description: Some(
1041 "RXOVERR flag clear bit Set by software to clear the RXOVERR flag.",
1042 ),
1043 bit_offset: BitOffset::Regular(
1044 RegularBitOffset {
1045 offset: 5,
1046 },
1047 ),
1048 bit_size: 1,
1049 array: None,
1050 enumm: None,
1051 },
1052 Field {
1053 name: "cmdrendc",
1054 description: Some(
1055 "CMDREND flag clear bit Set by software to clear the CMDREND flag.",
1056 ),
1057 bit_offset: BitOffset::Regular(
1058 RegularBitOffset {
1059 offset: 6,
1060 },
1061 ),
1062 bit_size: 1,
1063 array: None,
1064 enumm: None,
1065 },
1066 Field {
1067 name: "cmdsentc",
1068 description: Some(
1069 "CMDSENT flag clear bit Set by software to clear the CMDSENT flag.",
1070 ),
1071 bit_offset: BitOffset::Regular(
1072 RegularBitOffset {
1073 offset: 7,
1074 },
1075 ),
1076 bit_size: 1,
1077 array: None,
1078 enumm: None,
1079 },
1080 Field {
1081 name: "dataendc",
1082 description: Some(
1083 "DATAEND flag clear bit Set by software to clear the DATAEND flag.",
1084 ),
1085 bit_offset: BitOffset::Regular(
1086 RegularBitOffset {
1087 offset: 8,
1088 },
1089 ),
1090 bit_size: 1,
1091 array: None,
1092 enumm: None,
1093 },
1094 Field {
1095 name: "dholdc",
1096 description: Some(
1097 "DHOLD flag clear bit Set by software to clear the DHOLD flag.",
1098 ),
1099 bit_offset: BitOffset::Regular(
1100 RegularBitOffset {
1101 offset: 9,
1102 },
1103 ),
1104 bit_size: 1,
1105 array: None,
1106 enumm: None,
1107 },
1108 Field {
1109 name: "dbckendc",
1110 description: Some(
1111 "DBCKEND flag clear bit Set by software to clear the DBCKEND flag.",
1112 ),
1113 bit_offset: BitOffset::Regular(
1114 RegularBitOffset {
1115 offset: 10,
1116 },
1117 ),
1118 bit_size: 1,
1119 array: None,
1120 enumm: None,
1121 },
1122 Field {
1123 name: "dabortc",
1124 description: Some(
1125 "DABORT flag clear bit Set by software to clear the DABORT flag.",
1126 ),
1127 bit_offset: BitOffset::Regular(
1128 RegularBitOffset {
1129 offset: 11,
1130 },
1131 ),
1132 bit_size: 1,
1133 array: None,
1134 enumm: None,
1135 },
1136 Field {
1137 name: "busyd0endc",
1138 description: Some(
1139 "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag.",
1140 ),
1141 bit_offset: BitOffset::Regular(
1142 RegularBitOffset {
1143 offset: 21,
1144 },
1145 ),
1146 bit_size: 1,
1147 array: None,
1148 enumm: None,
1149 },
1150 Field {
1151 name: "sdioitc",
1152 description: Some(
1153 "SDIOIT flag clear bit Set by software to clear the SDIOIT flag.",
1154 ),
1155 bit_offset: BitOffset::Regular(
1156 RegularBitOffset {
1157 offset: 22,
1158 },
1159 ),
1160 bit_size: 1,
1161 array: None,
1162 enumm: None,
1163 },
1164 Field {
1165 name: "ackfailc",
1166 description: Some(
1167 "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag.",
1168 ),
1169 bit_offset: BitOffset::Regular(
1170 RegularBitOffset {
1171 offset: 23,
1172 },
1173 ),
1174 bit_size: 1,
1175 array: None,
1176 enumm: None,
1177 },
1178 Field {
1179 name: "acktimeoutc",
1180 description: Some(
1181 "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag.",
1182 ),
1183 bit_offset: BitOffset::Regular(
1184 RegularBitOffset {
1185 offset: 24,
1186 },
1187 ),
1188 bit_size: 1,
1189 array: None,
1190 enumm: None,
1191 },
1192 Field {
1193 name: "vswendc",
1194 description: Some(
1195 "VSWEND flag clear bit Set by software to clear the VSWEND flag.",
1196 ),
1197 bit_offset: BitOffset::Regular(
1198 RegularBitOffset {
1199 offset: 25,
1200 },
1201 ),
1202 bit_size: 1,
1203 array: None,
1204 enumm: None,
1205 },
1206 Field {
1207 name: "ckstopc",
1208 description: Some(
1209 "CKSTOP flag clear bit Set by software to clear the CKSTOP flag.",
1210 ),
1211 bit_offset: BitOffset::Regular(
1212 RegularBitOffset {
1213 offset: 26,
1214 },
1215 ),
1216 bit_size: 1,
1217 array: None,
1218 enumm: None,
1219 },
1220 Field {
1221 name: "idmatec",
1222 description: Some(
1223 "IDMA transfer error clear bit Set by software to clear the IDMATE flag.",
1224 ),
1225 bit_offset: BitOffset::Regular(
1226 RegularBitOffset {
1227 offset: 27,
1228 },
1229 ),
1230 bit_size: 1,
1231 array: None,
1232 enumm: None,
1233 },
1234 Field {
1235 name: "idmabtcc",
1236 description: Some(
1237 "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag.",
1238 ),
1239 bit_offset: BitOffset::Regular(
1240 RegularBitOffset {
1241 offset: 28,
1242 },
1243 ),
1244 bit_size: 1,
1245 array: None,
1246 enumm: None,
1247 },
1248 ],
1249 },
1250 FieldSet {
1251 name: "Id",
1252 extends: None,
1253 description: Some(
1254 "SDMMC IP identification register",
1255 ),
1256 bit_size: 32,
1257 fields: &[
1258 Field {
1259 name: "ip_id",
1260 description: Some(
1261 "SDMMC IP identification.",
1262 ),
1263 bit_offset: BitOffset::Regular(
1264 RegularBitOffset {
1265 offset: 0,
1266 },
1267 ),
1268 bit_size: 32,
1269 array: None,
1270 enumm: None,
1271 },
1272 ],
1273 },
1274 FieldSet {
1275 name: "Idmabase0r",
1276 extends: None,
1277 description: Some(
1278 "The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration.",
1279 ),
1280 bit_size: 32,
1281 fields: &[
1282 Field {
1283 name: "idmabase0",
1284 description: Some(
1285 "Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1).",
1286 ),
1287 bit_offset: BitOffset::Regular(
1288 RegularBitOffset {
1289 offset: 0,
1290 },
1291 ),
1292 bit_size: 32,
1293 array: None,
1294 enumm: None,
1295 },
1296 ],
1297 },
1298 FieldSet {
1299 name: "Idmabase1r",
1300 extends: None,
1301 description: Some(
1302 "The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address.",
1303 ),
1304 bit_size: 32,
1305 fields: &[
1306 Field {
1307 name: "idmabase1",
1308 description: Some(
1309 "Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0).",
1310 ),
1311 bit_offset: BitOffset::Regular(
1312 RegularBitOffset {
1313 offset: 0,
1314 },
1315 ),
1316 bit_size: 32,
1317 array: None,
1318 enumm: None,
1319 },
1320 ],
1321 },
1322 FieldSet {
1323 name: "Idmabsizer",
1324 extends: None,
1325 description: Some(
1326 "The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration.",
1327 ),
1328 bit_size: 32,
1329 fields: &[
1330 Field {
1331 name: "idmabndt",
1332 description: Some(
1333 "Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0).",
1334 ),
1335 bit_offset: BitOffset::Regular(
1336 RegularBitOffset {
1337 offset: 5,
1338 },
1339 ),
1340 bit_size: 8,
1341 array: None,
1342 enumm: None,
1343 },
1344 ],
1345 },
1346 FieldSet {
1347 name: "Idmactrlr",
1348 extends: None,
1349 description: Some(
1350 "The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.",
1351 ),
1352 bit_size: 32,
1353 fields: &[
1354 Field {
1355 name: "idmaen",
1356 description: Some(
1357 "IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).",
1358 ),
1359 bit_offset: BitOffset::Regular(
1360 RegularBitOffset {
1361 offset: 0,
1362 },
1363 ),
1364 bit_size: 1,
1365 array: None,
1366 enumm: None,
1367 },
1368 Field {
1369 name: "idmabmode",
1370 description: Some(
1371 "Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).",
1372 ),
1373 bit_offset: BitOffset::Regular(
1374 RegularBitOffset {
1375 offset: 1,
1376 },
1377 ),
1378 bit_size: 1,
1379 array: None,
1380 enumm: None,
1381 },
1382 Field {
1383 name: "idmabact",
1384 description: Some(
1385 "Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware.",
1386 ),
1387 bit_offset: BitOffset::Regular(
1388 RegularBitOffset {
1389 offset: 2,
1390 },
1391 ),
1392 bit_size: 1,
1393 array: None,
1394 enumm: None,
1395 },
1396 ],
1397 },
1398 FieldSet {
1399 name: "Maskr",
1400 extends: None,
1401 description: Some(
1402 "The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1.",
1403 ),
1404 bit_size: 32,
1405 fields: &[
1406 Field {
1407 name: "ccrcfailie",
1408 description: Some(
1409 "Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure.",
1410 ),
1411 bit_offset: BitOffset::Regular(
1412 RegularBitOffset {
1413 offset: 0,
1414 },
1415 ),
1416 bit_size: 1,
1417 array: None,
1418 enumm: None,
1419 },
1420 Field {
1421 name: "dcrcfailie",
1422 description: Some(
1423 "Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure.",
1424 ),
1425 bit_offset: BitOffset::Regular(
1426 RegularBitOffset {
1427 offset: 1,
1428 },
1429 ),
1430 bit_size: 1,
1431 array: None,
1432 enumm: None,
1433 },
1434 Field {
1435 name: "ctimeoutie",
1436 description: Some(
1437 "Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout.",
1438 ),
1439 bit_offset: BitOffset::Regular(
1440 RegularBitOffset {
1441 offset: 2,
1442 },
1443 ),
1444 bit_size: 1,
1445 array: None,
1446 enumm: None,
1447 },
1448 Field {
1449 name: "dtimeoutie",
1450 description: Some(
1451 "Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout.",
1452 ),
1453 bit_offset: BitOffset::Regular(
1454 RegularBitOffset {
1455 offset: 3,
1456 },
1457 ),
1458 bit_size: 1,
1459 array: None,
1460 enumm: None,
1461 },
1462 Field {
1463 name: "txunderrie",
1464 description: Some(
1465 "Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error.",
1466 ),
1467 bit_offset: BitOffset::Regular(
1468 RegularBitOffset {
1469 offset: 4,
1470 },
1471 ),
1472 bit_size: 1,
1473 array: None,
1474 enumm: None,
1475 },
1476 Field {
1477 name: "rxoverrie",
1478 description: Some(
1479 "Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error.",
1480 ),
1481 bit_offset: BitOffset::Regular(
1482 RegularBitOffset {
1483 offset: 5,
1484 },
1485 ),
1486 bit_size: 1,
1487 array: None,
1488 enumm: None,
1489 },
1490 Field {
1491 name: "cmdrendie",
1492 description: Some(
1493 "Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response.",
1494 ),
1495 bit_offset: BitOffset::Regular(
1496 RegularBitOffset {
1497 offset: 6,
1498 },
1499 ),
1500 bit_size: 1,
1501 array: None,
1502 enumm: None,
1503 },
1504 Field {
1505 name: "cmdsentie",
1506 description: Some(
1507 "Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command.",
1508 ),
1509 bit_offset: BitOffset::Regular(
1510 RegularBitOffset {
1511 offset: 7,
1512 },
1513 ),
1514 bit_size: 1,
1515 array: None,
1516 enumm: None,
1517 },
1518 Field {
1519 name: "dataendie",
1520 description: Some(
1521 "Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end.",
1522 ),
1523 bit_offset: BitOffset::Regular(
1524 RegularBitOffset {
1525 offset: 8,
1526 },
1527 ),
1528 bit_size: 1,
1529 array: None,
1530 enumm: None,
1531 },
1532 Field {
1533 name: "dholdie",
1534 description: Some(
1535 "Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state.",
1536 ),
1537 bit_offset: BitOffset::Regular(
1538 RegularBitOffset {
1539 offset: 9,
1540 },
1541 ),
1542 bit_size: 1,
1543 array: None,
1544 enumm: None,
1545 },
1546 Field {
1547 name: "dbckendie",
1548 description: Some(
1549 "Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end.",
1550 ),
1551 bit_offset: BitOffset::Regular(
1552 RegularBitOffset {
1553 offset: 10,
1554 },
1555 ),
1556 bit_size: 1,
1557 array: None,
1558 enumm: None,
1559 },
1560 Field {
1561 name: "dabortie",
1562 description: Some(
1563 "Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted.",
1564 ),
1565 bit_offset: BitOffset::Regular(
1566 RegularBitOffset {
1567 offset: 11,
1568 },
1569 ),
1570 bit_size: 1,
1571 array: None,
1572 enumm: None,
1573 },
1574 Field {
1575 name: "txfifoheie",
1576 description: Some(
1577 "Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty.",
1578 ),
1579 bit_offset: BitOffset::Regular(
1580 RegularBitOffset {
1581 offset: 14,
1582 },
1583 ),
1584 bit_size: 1,
1585 array: None,
1586 enumm: None,
1587 },
1588 Field {
1589 name: "rxfifohfie",
1590 description: Some(
1591 "Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full.",
1592 ),
1593 bit_offset: BitOffset::Regular(
1594 RegularBitOffset {
1595 offset: 15,
1596 },
1597 ),
1598 bit_size: 1,
1599 array: None,
1600 enumm: None,
1601 },
1602 Field {
1603 name: "rxfifofie",
1604 description: Some(
1605 "Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full.",
1606 ),
1607 bit_offset: BitOffset::Regular(
1608 RegularBitOffset {
1609 offset: 17,
1610 },
1611 ),
1612 bit_size: 1,
1613 array: None,
1614 enumm: None,
1615 },
1616 Field {
1617 name: "txfifoeie",
1618 description: Some(
1619 "Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty.",
1620 ),
1621 bit_offset: BitOffset::Regular(
1622 RegularBitOffset {
1623 offset: 18,
1624 },
1625 ),
1626 bit_size: 1,
1627 array: None,
1628 enumm: None,
1629 },
1630 Field {
1631 name: "busyd0endie",
1632 description: Some(
1633 "BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response.",
1634 ),
1635 bit_offset: BitOffset::Regular(
1636 RegularBitOffset {
1637 offset: 21,
1638 },
1639 ),
1640 bit_size: 1,
1641 array: None,
1642 enumm: None,
1643 },
1644 Field {
1645 name: "sdioitie",
1646 description: Some(
1647 "SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt.",
1648 ),
1649 bit_offset: BitOffset::Regular(
1650 RegularBitOffset {
1651 offset: 22,
1652 },
1653 ),
1654 bit_size: 1,
1655 array: None,
1656 enumm: None,
1657 },
1658 Field {
1659 name: "ackfailie",
1660 description: Some(
1661 "Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail.",
1662 ),
1663 bit_offset: BitOffset::Regular(
1664 RegularBitOffset {
1665 offset: 23,
1666 },
1667 ),
1668 bit_size: 1,
1669 array: None,
1670 enumm: None,
1671 },
1672 Field {
1673 name: "acktimeoutie",
1674 description: Some(
1675 "Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout.",
1676 ),
1677 bit_offset: BitOffset::Regular(
1678 RegularBitOffset {
1679 offset: 24,
1680 },
1681 ),
1682 bit_size: 1,
1683 array: None,
1684 enumm: None,
1685 },
1686 Field {
1687 name: "vswendie",
1688 description: Some(
1689 "Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion.",
1690 ),
1691 bit_offset: BitOffset::Regular(
1692 RegularBitOffset {
1693 offset: 25,
1694 },
1695 ),
1696 bit_size: 1,
1697 array: None,
1698 enumm: None,
1699 },
1700 Field {
1701 name: "ckstopie",
1702 description: Some(
1703 "Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped.",
1704 ),
1705 bit_offset: BitOffset::Regular(
1706 RegularBitOffset {
1707 offset: 26,
1708 },
1709 ),
1710 bit_size: 1,
1711 array: None,
1712 enumm: None,
1713 },
1714 Field {
1715 name: "idmabtcie",
1716 description: Some(
1717 "IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer.",
1718 ),
1719 bit_offset: BitOffset::Regular(
1720 RegularBitOffset {
1721 offset: 28,
1722 },
1723 ),
1724 bit_size: 1,
1725 array: None,
1726 enumm: None,
1727 },
1728 ],
1729 },
1730 FieldSet {
1731 name: "Power",
1732 extends: None,
1733 description: Some(
1734 "SDMMC power control register",
1735 ),
1736 bit_size: 32,
1737 fields: &[
1738 Field {
1739 name: "pwrctrl",
1740 description: Some(
1741 "SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11.",
1742 ),
1743 bit_offset: BitOffset::Regular(
1744 RegularBitOffset {
1745 offset: 0,
1746 },
1747 ),
1748 bit_size: 2,
1749 array: None,
1750 enumm: None,
1751 },
1752 Field {
1753 name: "vswitch",
1754 description: Some(
1755 "Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:",
1756 ),
1757 bit_offset: BitOffset::Regular(
1758 RegularBitOffset {
1759 offset: 2,
1760 },
1761 ),
1762 bit_size: 1,
1763 array: None,
1764 enumm: None,
1765 },
1766 Field {
1767 name: "vswitchen",
1768 description: Some(
1769 "Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:",
1770 ),
1771 bit_offset: BitOffset::Regular(
1772 RegularBitOffset {
1773 offset: 3,
1774 },
1775 ),
1776 bit_size: 1,
1777 array: None,
1778 enumm: None,
1779 },
1780 Field {
1781 name: "dirpol",
1782 description: Some(
1783 "Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00).",
1784 ),
1785 bit_offset: BitOffset::Regular(
1786 RegularBitOffset {
1787 offset: 4,
1788 },
1789 ),
1790 bit_size: 1,
1791 array: None,
1792 enumm: None,
1793 },
1794 ],
1795 },
1796 FieldSet {
1797 name: "Respcmdr",
1798 extends: None,
1799 description: Some(
1800 "SDMMC command response register",
1801 ),
1802 bit_size: 32,
1803 fields: &[
1804 Field {
1805 name: "respcmd",
1806 description: Some(
1807 "Response command index",
1808 ),
1809 bit_offset: BitOffset::Regular(
1810 RegularBitOffset {
1811 offset: 0,
1812 },
1813 ),
1814 bit_size: 6,
1815 array: None,
1816 enumm: None,
1817 },
1818 ],
1819 },
1820 FieldSet {
1821 name: "RespxR",
1822 extends: None,
1823 description: Some(
1824 "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.",
1825 ),
1826 bit_size: 32,
1827 fields: &[
1828 Field {
1829 name: "cardstatus",
1830 description: Some(
1831 "see Table 432",
1832 ),
1833 bit_offset: BitOffset::Regular(
1834 RegularBitOffset {
1835 offset: 0,
1836 },
1837 ),
1838 bit_size: 32,
1839 array: None,
1840 enumm: None,
1841 },
1842 ],
1843 },
1844 FieldSet {
1845 name: "Star",
1846 extends: None,
1847 description: Some(
1848 "The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)",
1849 ),
1850 bit_size: 32,
1851 fields: &[
1852 Field {
1853 name: "ccrcfail",
1854 description: Some(
1855 "Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.",
1856 ),
1857 bit_offset: BitOffset::Regular(
1858 RegularBitOffset {
1859 offset: 0,
1860 },
1861 ),
1862 bit_size: 1,
1863 array: None,
1864 enumm: None,
1865 },
1866 Field {
1867 name: "dcrcfail",
1868 description: Some(
1869 "Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.",
1870 ),
1871 bit_offset: BitOffset::Regular(
1872 RegularBitOffset {
1873 offset: 1,
1874 },
1875 ),
1876 bit_size: 1,
1877 array: None,
1878 enumm: None,
1879 },
1880 Field {
1881 name: "ctimeout",
1882 description: Some(
1883 "Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods.",
1884 ),
1885 bit_offset: BitOffset::Regular(
1886 RegularBitOffset {
1887 offset: 2,
1888 },
1889 ),
1890 bit_size: 1,
1891 array: None,
1892 enumm: None,
1893 },
1894 Field {
1895 name: "dtimeout",
1896 description: Some(
1897 "Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.",
1898 ),
1899 bit_offset: BitOffset::Regular(
1900 RegularBitOffset {
1901 offset: 3,
1902 },
1903 ),
1904 bit_size: 1,
1905 array: None,
1906 enumm: None,
1907 },
1908 Field {
1909 name: "txunderr",
1910 description: Some(
1911 "Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.",
1912 ),
1913 bit_offset: BitOffset::Regular(
1914 RegularBitOffset {
1915 offset: 4,
1916 },
1917 ),
1918 bit_size: 1,
1919 array: None,
1920 enumm: None,
1921 },
1922 Field {
1923 name: "rxoverr",
1924 description: Some(
1925 "Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.",
1926 ),
1927 bit_offset: BitOffset::Regular(
1928 RegularBitOffset {
1929 offset: 5,
1930 },
1931 ),
1932 bit_size: 1,
1933 array: None,
1934 enumm: None,
1935 },
1936 Field {
1937 name: "cmdrend",
1938 description: Some(
1939 "Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.",
1940 ),
1941 bit_offset: BitOffset::Regular(
1942 RegularBitOffset {
1943 offset: 6,
1944 },
1945 ),
1946 bit_size: 1,
1947 array: None,
1948 enumm: None,
1949 },
1950 Field {
1951 name: "cmdsent",
1952 description: Some(
1953 "Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.",
1954 ),
1955 bit_offset: BitOffset::Regular(
1956 RegularBitOffset {
1957 offset: 7,
1958 },
1959 ),
1960 bit_size: 1,
1961 array: None,
1962 enumm: None,
1963 },
1964 Field {
1965 name: "dataend",
1966 description: Some(
1967 "Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.",
1968 ),
1969 bit_offset: BitOffset::Regular(
1970 RegularBitOffset {
1971 offset: 8,
1972 },
1973 ),
1974 bit_size: 1,
1975 array: None,
1976 enumm: None,
1977 },
1978 Field {
1979 name: "dhold",
1980 description: Some(
1981 "Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.",
1982 ),
1983 bit_offset: BitOffset::Regular(
1984 RegularBitOffset {
1985 offset: 9,
1986 },
1987 ),
1988 bit_size: 1,
1989 array: None,
1990 enumm: None,
1991 },
1992 Field {
1993 name: "dbckend",
1994 description: Some(
1995 "Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.",
1996 ),
1997 bit_offset: BitOffset::Regular(
1998 RegularBitOffset {
1999 offset: 10,
2000 },
2001 ),
2002 bit_size: 1,
2003 array: None,
2004 enumm: None,
2005 },
2006 Field {
2007 name: "dabort",
2008 description: Some(
2009 "Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.",
2010 ),
2011 bit_offset: BitOffset::Regular(
2012 RegularBitOffset {
2013 offset: 11,
2014 },
2015 ),
2016 bit_size: 1,
2017 array: None,
2018 enumm: None,
2019 },
2020 Field {
2021 name: "dpsmact",
2022 description: Some(
2023 "Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt.",
2024 ),
2025 bit_offset: BitOffset::Regular(
2026 RegularBitOffset {
2027 offset: 12,
2028 },
2029 ),
2030 bit_size: 1,
2031 array: None,
2032 enumm: None,
2033 },
2034 Field {
2035 name: "cpsmact",
2036 description: Some(
2037 "Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt.",
2038 ),
2039 bit_offset: BitOffset::Regular(
2040 RegularBitOffset {
2041 offset: 13,
2042 },
2043 ),
2044 bit_size: 1,
2045 array: None,
2046 enumm: None,
2047 },
2048 Field {
2049 name: "txfifohe",
2050 description: Some(
2051 "Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full.",
2052 ),
2053 bit_offset: BitOffset::Regular(
2054 RegularBitOffset {
2055 offset: 14,
2056 },
2057 ),
2058 bit_size: 1,
2059 array: None,
2060 enumm: None,
2061 },
2062 Field {
2063 name: "rxfifohf",
2064 description: Some(
2065 "Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty.",
2066 ),
2067 bit_offset: BitOffset::Regular(
2068 RegularBitOffset {
2069 offset: 15,
2070 },
2071 ),
2072 bit_size: 1,
2073 array: None,
2074 enumm: None,
2075 },
2076 Field {
2077 name: "txfifof",
2078 description: Some(
2079 "Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty.",
2080 ),
2081 bit_offset: BitOffset::Regular(
2082 RegularBitOffset {
2083 offset: 16,
2084 },
2085 ),
2086 bit_size: 1,
2087 array: None,
2088 enumm: None,
2089 },
2090 Field {
2091 name: "rxfifof",
2092 description: Some(
2093 "Receive FIFO full This bit is cleared when one FIFO location becomes empty.",
2094 ),
2095 bit_offset: BitOffset::Regular(
2096 RegularBitOffset {
2097 offset: 17,
2098 },
2099 ),
2100 bit_size: 1,
2101 array: None,
2102 enumm: None,
2103 },
2104 Field {
2105 name: "txfifoe",
2106 description: Some(
2107 "Transmit FIFO empty This bit is cleared when one FIFO location becomes full.",
2108 ),
2109 bit_offset: BitOffset::Regular(
2110 RegularBitOffset {
2111 offset: 18,
2112 },
2113 ),
2114 bit_size: 1,
2115 array: None,
2116 enumm: None,
2117 },
2118 Field {
2119 name: "rxfifoe",
2120 description: Some(
2121 "Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full.",
2122 ),
2123 bit_offset: BitOffset::Regular(
2124 RegularBitOffset {
2125 offset: 19,
2126 },
2127 ),
2128 bit_size: 1,
2129 array: None,
2130 enumm: None,
2131 },
2132 Field {
2133 name: "busyd0",
2134 description: Some(
2135 "Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt.",
2136 ),
2137 bit_offset: BitOffset::Regular(
2138 RegularBitOffset {
2139 offset: 20,
2140 },
2141 ),
2142 bit_size: 1,
2143 array: None,
2144 enumm: None,
2145 },
2146 Field {
2147 name: "busyd0end",
2148 description: Some(
2149 "end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.",
2150 ),
2151 bit_offset: BitOffset::Regular(
2152 RegularBitOffset {
2153 offset: 21,
2154 },
2155 ),
2156 bit_size: 1,
2157 array: None,
2158 enumm: None,
2159 },
2160 Field {
2161 name: "sdioit",
2162 description: Some(
2163 "SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.",
2164 ),
2165 bit_offset: BitOffset::Regular(
2166 RegularBitOffset {
2167 offset: 22,
2168 },
2169 ),
2170 bit_size: 1,
2171 array: None,
2172 enumm: None,
2173 },
2174 Field {
2175 name: "ackfail",
2176 description: Some(
2177 "Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.",
2178 ),
2179 bit_offset: BitOffset::Regular(
2180 RegularBitOffset {
2181 offset: 23,
2182 },
2183 ),
2184 bit_size: 1,
2185 array: None,
2186 enumm: None,
2187 },
2188 Field {
2189 name: "acktimeout",
2190 description: Some(
2191 "Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.",
2192 ),
2193 bit_offset: BitOffset::Regular(
2194 RegularBitOffset {
2195 offset: 24,
2196 },
2197 ),
2198 bit_size: 1,
2199 array: None,
2200 enumm: None,
2201 },
2202 Field {
2203 name: "vswend",
2204 description: Some(
2205 "Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.",
2206 ),
2207 bit_offset: BitOffset::Regular(
2208 RegularBitOffset {
2209 offset: 25,
2210 },
2211 ),
2212 bit_size: 1,
2213 array: None,
2214 enumm: None,
2215 },
2216 Field {
2217 name: "ckstop",
2218 description: Some(
2219 "SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.",
2220 ),
2221 bit_offset: BitOffset::Regular(
2222 RegularBitOffset {
2223 offset: 26,
2224 },
2225 ),
2226 bit_size: 1,
2227 array: None,
2228 enumm: None,
2229 },
2230 Field {
2231 name: "idmate",
2232 description: Some(
2233 "IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.",
2234 ),
2235 bit_offset: BitOffset::Regular(
2236 RegularBitOffset {
2237 offset: 27,
2238 },
2239 ),
2240 bit_size: 1,
2241 array: None,
2242 enumm: None,
2243 },
2244 Field {
2245 name: "idmabtc",
2246 description: Some(
2247 "IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR.",
2248 ),
2249 bit_offset: BitOffset::Regular(
2250 RegularBitOffset {
2251 offset: 28,
2252 },
2253 ),
2254 bit_size: 1,
2255 array: None,
2256 enumm: None,
2257 },
2258 ],
2259 },
2260 FieldSet {
2261 name: "Ver",
2262 extends: None,
2263 description: Some(
2264 "SDMMC IP version register",
2265 ),
2266 bit_size: 32,
2267 fields: &[
2268 Field {
2269 name: "minrev",
2270 description: Some(
2271 "IP minor revision number.",
2272 ),
2273 bit_offset: BitOffset::Regular(
2274 RegularBitOffset {
2275 offset: 0,
2276 },
2277 ),
2278 bit_size: 4,
2279 array: None,
2280 enumm: None,
2281 },
2282 Field {
2283 name: "majrev",
2284 description: Some(
2285 "IP major revision number.",
2286 ),
2287 bit_offset: BitOffset::Regular(
2288 RegularBitOffset {
2289 offset: 4,
2290 },
2291 ),
2292 bit_size: 4,
2293 array: None,
2294 enumm: None,
2295 },
2296 ],
2297 },
2298 ],
2299 enums: &[],
2300};
2301