1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Spi",
7 extends: None,
8 description: Some(
9 "Serial peripheral interface",
10 ),
11 items: &[
12 BlockItem {
13 name: "cr1",
14 description: Some(
15 "control register 1",
16 ),
17 array: None,
18 byte_offset: 0x0,
19 inner: BlockItemInner::Register(
20 Register {
21 access: Access::ReadWrite,
22 bit_size: 32,
23 fieldset: Some(
24 "Cr1",
25 ),
26 },
27 ),
28 },
29 BlockItem {
30 name: "cr2",
31 description: Some(
32 "control register 2",
33 ),
34 array: None,
35 byte_offset: 0x4,
36 inner: BlockItemInner::Register(
37 Register {
38 access: Access::ReadWrite,
39 bit_size: 32,
40 fieldset: Some(
41 "Cr2",
42 ),
43 },
44 ),
45 },
46 BlockItem {
47 name: "cfg1",
48 description: Some(
49 "configuration register 1",
50 ),
51 array: None,
52 byte_offset: 0x8,
53 inner: BlockItemInner::Register(
54 Register {
55 access: Access::ReadWrite,
56 bit_size: 32,
57 fieldset: Some(
58 "Cfg1",
59 ),
60 },
61 ),
62 },
63 BlockItem {
64 name: "cfg2",
65 description: Some(
66 "configuration register 2",
67 ),
68 array: None,
69 byte_offset: 0xc,
70 inner: BlockItemInner::Register(
71 Register {
72 access: Access::ReadWrite,
73 bit_size: 32,
74 fieldset: Some(
75 "Cfg2",
76 ),
77 },
78 ),
79 },
80 BlockItem {
81 name: "ier",
82 description: Some(
83 "Interrupt Enable Register",
84 ),
85 array: None,
86 byte_offset: 0x10,
87 inner: BlockItemInner::Register(
88 Register {
89 access: Access::ReadWrite,
90 bit_size: 32,
91 fieldset: Some(
92 "Ier",
93 ),
94 },
95 ),
96 },
97 BlockItem {
98 name: "sr",
99 description: Some(
100 "Status Register",
101 ),
102 array: None,
103 byte_offset: 0x14,
104 inner: BlockItemInner::Register(
105 Register {
106 access: Access::Read,
107 bit_size: 32,
108 fieldset: Some(
109 "Sr",
110 ),
111 },
112 ),
113 },
114 BlockItem {
115 name: "ifcr",
116 description: Some(
117 "Interrupt/Status Flags Clear Register",
118 ),
119 array: None,
120 byte_offset: 0x18,
121 inner: BlockItemInner::Register(
122 Register {
123 access: Access::Write,
124 bit_size: 32,
125 fieldset: Some(
126 "Ifcr",
127 ),
128 },
129 ),
130 },
131 BlockItem {
132 name: "autocr",
133 description: None,
134 array: None,
135 byte_offset: 0x1c,
136 inner: BlockItemInner::Register(
137 Register {
138 access: Access::ReadWrite,
139 bit_size: 32,
140 fieldset: Some(
141 "Autocr",
142 ),
143 },
144 ),
145 },
146 BlockItem {
147 name: "txdr16",
148 description: Some(
149 "Transmit Data Register - half-word sized",
150 ),
151 array: None,
152 byte_offset: 0x20,
153 inner: BlockItemInner::Register(
154 Register {
155 access: Access::Write,
156 bit_size: 16,
157 fieldset: None,
158 },
159 ),
160 },
161 BlockItem {
162 name: "txdr32",
163 description: Some(
164 "Transmit Data Register",
165 ),
166 array: None,
167 byte_offset: 0x20,
168 inner: BlockItemInner::Register(
169 Register {
170 access: Access::Write,
171 bit_size: 32,
172 fieldset: None,
173 },
174 ),
175 },
176 BlockItem {
177 name: "txdr8",
178 description: Some(
179 "Transmit Data Register - byte sized",
180 ),
181 array: None,
182 byte_offset: 0x20,
183 inner: BlockItemInner::Register(
184 Register {
185 access: Access::Write,
186 bit_size: 8,
187 fieldset: None,
188 },
189 ),
190 },
191 BlockItem {
192 name: "rxdr16",
193 description: Some(
194 "Receive Data Register - half-word sized",
195 ),
196 array: None,
197 byte_offset: 0x30,
198 inner: BlockItemInner::Register(
199 Register {
200 access: Access::Read,
201 bit_size: 16,
202 fieldset: None,
203 },
204 ),
205 },
206 BlockItem {
207 name: "rxdr32",
208 description: Some(
209 "Receive Data Register",
210 ),
211 array: None,
212 byte_offset: 0x30,
213 inner: BlockItemInner::Register(
214 Register {
215 access: Access::Read,
216 bit_size: 32,
217 fieldset: None,
218 },
219 ),
220 },
221 BlockItem {
222 name: "rxdr8",
223 description: Some(
224 "Receive Data Register - byte sized",
225 ),
226 array: None,
227 byte_offset: 0x30,
228 inner: BlockItemInner::Register(
229 Register {
230 access: Access::Read,
231 bit_size: 8,
232 fieldset: None,
233 },
234 ),
235 },
236 BlockItem {
237 name: "crcpoly",
238 description: Some(
239 "Polynomial Register",
240 ),
241 array: None,
242 byte_offset: 0x40,
243 inner: BlockItemInner::Register(
244 Register {
245 access: Access::ReadWrite,
246 bit_size: 32,
247 fieldset: Some(
248 "Crcpoly",
249 ),
250 },
251 ),
252 },
253 BlockItem {
254 name: "txcrc",
255 description: Some(
256 "Transmitter CRC Register",
257 ),
258 array: None,
259 byte_offset: 0x44,
260 inner: BlockItemInner::Register(
261 Register {
262 access: Access::ReadWrite,
263 bit_size: 32,
264 fieldset: Some(
265 "Txcrc",
266 ),
267 },
268 ),
269 },
270 BlockItem {
271 name: "rxcrc",
272 description: Some(
273 "Receiver CRC Register",
274 ),
275 array: None,
276 byte_offset: 0x48,
277 inner: BlockItemInner::Register(
278 Register {
279 access: Access::ReadWrite,
280 bit_size: 32,
281 fieldset: Some(
282 "Rxcrc",
283 ),
284 },
285 ),
286 },
287 BlockItem {
288 name: "udrdr",
289 description: Some(
290 "Underrun Data Register",
291 ),
292 array: None,
293 byte_offset: 0x4c,
294 inner: BlockItemInner::Register(
295 Register {
296 access: Access::ReadWrite,
297 bit_size: 32,
298 fieldset: Some(
299 "Udrdr",
300 ),
301 },
302 ),
303 },
304 ],
305 },
306 ],
307 fieldsets: &[
308 FieldSet {
309 name: "Autocr",
310 extends: None,
311 description: None,
312 bit_size: 32,
313 fields: &[
314 Field {
315 name: "trigsel",
316 description: Some(
317 "trigger selection (refer ).\n ...\n Note: these bits can be written only when SPE = 0.",
318 ),
319 bit_offset: BitOffset::Regular(
320 RegularBitOffset {
321 offset: 16,
322 },
323 ),
324 bit_size: 4,
325 array: None,
326 enumm: None,
327 },
328 Field {
329 name: "trigpol",
330 description: Some(
331 "trigger polarity\n Note: This bit can be written only when SPE = 0.",
332 ),
333 bit_offset: BitOffset::Regular(
334 RegularBitOffset {
335 offset: 20,
336 },
337 ),
338 bit_size: 1,
339 array: None,
340 enumm: Some(
341 "Trigpol",
342 ),
343 },
344 Field {
345 name: "trigen",
346 description: Some(
347 "trigger of CSTART control enable\n Note: if user can't prevent trigger event during write, the TRIGEN has to be changed when SPI is disabled",
348 ),
349 bit_offset: BitOffset::Regular(
350 RegularBitOffset {
351 offset: 21,
352 },
353 ),
354 bit_size: 1,
355 array: None,
356 enumm: None,
357 },
358 ],
359 },
360 FieldSet {
361 name: "Cfg1",
362 extends: None,
363 description: Some(
364 "configuration register 1",
365 ),
366 bit_size: 32,
367 fields: &[
368 Field {
369 name: "dsize",
370 description: Some(
371 "Number of bits in at single SPI data frame",
372 ),
373 bit_offset: BitOffset::Regular(
374 RegularBitOffset {
375 offset: 0,
376 },
377 ),
378 bit_size: 5,
379 array: None,
380 enumm: None,
381 },
382 Field {
383 name: "fthlv",
384 description: Some(
385 "threshold level",
386 ),
387 bit_offset: BitOffset::Regular(
388 RegularBitOffset {
389 offset: 5,
390 },
391 ),
392 bit_size: 4,
393 array: None,
394 enumm: Some(
395 "Fthlv",
396 ),
397 },
398 Field {
399 name: "udrcfg",
400 description: Some(
401 "Behavior of slave transmitter at underrun condition",
402 ),
403 bit_offset: BitOffset::Regular(
404 RegularBitOffset {
405 offset: 9,
406 },
407 ),
408 bit_size: 2,
409 array: None,
410 enumm: Some(
411 "Udrcfg",
412 ),
413 },
414 Field {
415 name: "rxdmaen",
416 description: Some(
417 "Rx DMA stream enable",
418 ),
419 bit_offset: BitOffset::Regular(
420 RegularBitOffset {
421 offset: 14,
422 },
423 ),
424 bit_size: 1,
425 array: None,
426 enumm: None,
427 },
428 Field {
429 name: "txdmaen",
430 description: Some(
431 "Tx DMA stream enable",
432 ),
433 bit_offset: BitOffset::Regular(
434 RegularBitOffset {
435 offset: 15,
436 },
437 ),
438 bit_size: 1,
439 array: None,
440 enumm: None,
441 },
442 Field {
443 name: "crcsize",
444 description: Some(
445 "Length of CRC frame to be transacted and compared",
446 ),
447 bit_offset: BitOffset::Regular(
448 RegularBitOffset {
449 offset: 16,
450 },
451 ),
452 bit_size: 5,
453 array: None,
454 enumm: None,
455 },
456 Field {
457 name: "crcen",
458 description: Some(
459 "Hardware CRC computation enable",
460 ),
461 bit_offset: BitOffset::Regular(
462 RegularBitOffset {
463 offset: 22,
464 },
465 ),
466 bit_size: 1,
467 array: None,
468 enumm: None,
469 },
470 Field {
471 name: "mbr",
472 description: Some(
473 "Master baud rate",
474 ),
475 bit_offset: BitOffset::Regular(
476 RegularBitOffset {
477 offset: 28,
478 },
479 ),
480 bit_size: 3,
481 array: None,
482 enumm: Some(
483 "Mbr",
484 ),
485 },
486 Field {
487 name: "bpass",
488 description: Some(
489 "bypass of the prescaler at master baud rate clock generator",
490 ),
491 bit_offset: BitOffset::Regular(
492 RegularBitOffset {
493 offset: 31,
494 },
495 ),
496 bit_size: 1,
497 array: None,
498 enumm: None,
499 },
500 ],
501 },
502 FieldSet {
503 name: "Cfg2",
504 extends: None,
505 description: Some(
506 "configuration register 2",
507 ),
508 bit_size: 32,
509 fields: &[
510 Field {
511 name: "mssi",
512 description: Some(
513 "Master SS Idleness",
514 ),
515 bit_offset: BitOffset::Regular(
516 RegularBitOffset {
517 offset: 0,
518 },
519 ),
520 bit_size: 4,
521 array: None,
522 enumm: None,
523 },
524 Field {
525 name: "midi",
526 description: Some(
527 "Master Inter-Data Idleness",
528 ),
529 bit_offset: BitOffset::Regular(
530 RegularBitOffset {
531 offset: 4,
532 },
533 ),
534 bit_size: 4,
535 array: None,
536 enumm: None,
537 },
538 Field {
539 name: "rdiom",
540 description: Some(
541 "RDY signal input/output management\n Note: When DSIZE at the CFG1 register is configured shorter than 8-bit, the RDIOM bit has to be kept at zero.",
542 ),
543 bit_offset: BitOffset::Regular(
544 RegularBitOffset {
545 offset: 13,
546 },
547 ),
548 bit_size: 1,
549 array: None,
550 enumm: Some(
551 "Rdiom",
552 ),
553 },
554 Field {
555 name: "rdiop",
556 description: Some(
557 "RDY signal input/output polarity",
558 ),
559 bit_offset: BitOffset::Regular(
560 RegularBitOffset {
561 offset: 14,
562 },
563 ),
564 bit_size: 1,
565 array: None,
566 enumm: Some(
567 "Rdiop",
568 ),
569 },
570 Field {
571 name: "ioswp",
572 description: Some(
573 "Swap functionality of MISO and MOSI pins",
574 ),
575 bit_offset: BitOffset::Regular(
576 RegularBitOffset {
577 offset: 15,
578 },
579 ),
580 bit_size: 1,
581 array: None,
582 enumm: None,
583 },
584 Field {
585 name: "comm",
586 description: Some(
587 "SPI Communication Mode",
588 ),
589 bit_offset: BitOffset::Regular(
590 RegularBitOffset {
591 offset: 17,
592 },
593 ),
594 bit_size: 2,
595 array: None,
596 enumm: Some(
597 "Comm",
598 ),
599 },
600 Field {
601 name: "sp",
602 description: Some(
603 "Serial Protocol",
604 ),
605 bit_offset: BitOffset::Regular(
606 RegularBitOffset {
607 offset: 19,
608 },
609 ),
610 bit_size: 3,
611 array: None,
612 enumm: Some(
613 "Sp",
614 ),
615 },
616 Field {
617 name: "master",
618 description: Some(
619 "SPI Master",
620 ),
621 bit_offset: BitOffset::Regular(
622 RegularBitOffset {
623 offset: 22,
624 },
625 ),
626 bit_size: 1,
627 array: None,
628 enumm: Some(
629 "Master",
630 ),
631 },
632 Field {
633 name: "lsbfirst",
634 description: Some(
635 "Data frame format",
636 ),
637 bit_offset: BitOffset::Regular(
638 RegularBitOffset {
639 offset: 23,
640 },
641 ),
642 bit_size: 1,
643 array: None,
644 enumm: Some(
645 "Lsbfirst",
646 ),
647 },
648 Field {
649 name: "cpha",
650 description: Some(
651 "Clock phase",
652 ),
653 bit_offset: BitOffset::Regular(
654 RegularBitOffset {
655 offset: 24,
656 },
657 ),
658 bit_size: 1,
659 array: None,
660 enumm: Some(
661 "Cpha",
662 ),
663 },
664 Field {
665 name: "cpol",
666 description: Some(
667 "Clock polarity",
668 ),
669 bit_offset: BitOffset::Regular(
670 RegularBitOffset {
671 offset: 25,
672 },
673 ),
674 bit_size: 1,
675 array: None,
676 enumm: Some(
677 "Cpol",
678 ),
679 },
680 Field {
681 name: "ssm",
682 description: Some(
683 "Software management of SS signal input",
684 ),
685 bit_offset: BitOffset::Regular(
686 RegularBitOffset {
687 offset: 26,
688 },
689 ),
690 bit_size: 1,
691 array: None,
692 enumm: None,
693 },
694 Field {
695 name: "ssiop",
696 description: Some(
697 "SS input/output polarity",
698 ),
699 bit_offset: BitOffset::Regular(
700 RegularBitOffset {
701 offset: 28,
702 },
703 ),
704 bit_size: 1,
705 array: None,
706 enumm: Some(
707 "Ssiop",
708 ),
709 },
710 Field {
711 name: "ssoe",
712 description: Some(
713 "SS output enable",
714 ),
715 bit_offset: BitOffset::Regular(
716 RegularBitOffset {
717 offset: 29,
718 },
719 ),
720 bit_size: 1,
721 array: None,
722 enumm: None,
723 },
724 Field {
725 name: "ssom",
726 description: Some(
727 "SS output management in master mode",
728 ),
729 bit_offset: BitOffset::Regular(
730 RegularBitOffset {
731 offset: 30,
732 },
733 ),
734 bit_size: 1,
735 array: None,
736 enumm: Some(
737 "Ssom",
738 ),
739 },
740 Field {
741 name: "afcntr",
742 description: Some(
743 "Alternate function always control GPIOs",
744 ),
745 bit_offset: BitOffset::Regular(
746 RegularBitOffset {
747 offset: 31,
748 },
749 ),
750 bit_size: 1,
751 array: None,
752 enumm: None,
753 },
754 ],
755 },
756 FieldSet {
757 name: "Cr1",
758 extends: None,
759 description: Some(
760 "control register 1",
761 ),
762 bit_size: 32,
763 fields: &[
764 Field {
765 name: "spe",
766 description: Some(
767 "Serial Peripheral Enable",
768 ),
769 bit_offset: BitOffset::Regular(
770 RegularBitOffset {
771 offset: 0,
772 },
773 ),
774 bit_size: 1,
775 array: None,
776 enumm: None,
777 },
778 Field {
779 name: "masrx",
780 description: Some(
781 "Master automatic SUSP in Receive mode",
782 ),
783 bit_offset: BitOffset::Regular(
784 RegularBitOffset {
785 offset: 8,
786 },
787 ),
788 bit_size: 1,
789 array: None,
790 enumm: None,
791 },
792 Field {
793 name: "cstart",
794 description: Some(
795 "Master transfer start",
796 ),
797 bit_offset: BitOffset::Regular(
798 RegularBitOffset {
799 offset: 9,
800 },
801 ),
802 bit_size: 1,
803 array: None,
804 enumm: None,
805 },
806 Field {
807 name: "csusp",
808 description: Some(
809 "Master SUSPend request",
810 ),
811 bit_offset: BitOffset::Regular(
812 RegularBitOffset {
813 offset: 10,
814 },
815 ),
816 bit_size: 1,
817 array: None,
818 enumm: None,
819 },
820 Field {
821 name: "hddir",
822 description: Some(
823 "Rx/Tx direction at Half-duplex mode",
824 ),
825 bit_offset: BitOffset::Regular(
826 RegularBitOffset {
827 offset: 11,
828 },
829 ),
830 bit_size: 1,
831 array: None,
832 enumm: Some(
833 "Hddir",
834 ),
835 },
836 Field {
837 name: "ssi",
838 description: Some(
839 "Internal SS signal input level",
840 ),
841 bit_offset: BitOffset::Regular(
842 RegularBitOffset {
843 offset: 12,
844 },
845 ),
846 bit_size: 1,
847 array: None,
848 enumm: None,
849 },
850 Field {
851 name: "crc33_17",
852 description: Some(
853 "Full size (33-bit or 17-bit) CRC polynomial is used",
854 ),
855 bit_offset: BitOffset::Regular(
856 RegularBitOffset {
857 offset: 13,
858 },
859 ),
860 bit_size: 1,
861 array: None,
862 enumm: None,
863 },
864 Field {
865 name: "rcrcini",
866 description: Some(
867 "CRC calculation initialization pattern control for receiver",
868 ),
869 bit_offset: BitOffset::Regular(
870 RegularBitOffset {
871 offset: 14,
872 },
873 ),
874 bit_size: 1,
875 array: None,
876 enumm: Some(
877 "Rcrcini",
878 ),
879 },
880 Field {
881 name: "tcrcini",
882 description: Some(
883 "CRC calculation initialization pattern control for transmitter",
884 ),
885 bit_offset: BitOffset::Regular(
886 RegularBitOffset {
887 offset: 15,
888 },
889 ),
890 bit_size: 1,
891 array: None,
892 enumm: Some(
893 "Tcrcini",
894 ),
895 },
896 Field {
897 name: "iolock",
898 description: Some(
899 "Locking the AF configuration of associated IOs",
900 ),
901 bit_offset: BitOffset::Regular(
902 RegularBitOffset {
903 offset: 16,
904 },
905 ),
906 bit_size: 1,
907 array: None,
908 enumm: None,
909 },
910 ],
911 },
912 FieldSet {
913 name: "Cr2",
914 extends: None,
915 description: Some(
916 "control register 2",
917 ),
918 bit_size: 32,
919 fields: &[
920 Field {
921 name: "tsize",
922 description: Some(
923 "Number of data at current transfer",
924 ),
925 bit_offset: BitOffset::Regular(
926 RegularBitOffset {
927 offset: 0,
928 },
929 ),
930 bit_size: 16,
931 array: None,
932 enumm: None,
933 },
934 ],
935 },
936 FieldSet {
937 name: "Crcpoly",
938 extends: None,
939 description: Some(
940 "Polynomial Register",
941 ),
942 bit_size: 32,
943 fields: &[
944 Field {
945 name: "crcpoly",
946 description: Some(
947 "CRC polynomial register",
948 ),
949 bit_offset: BitOffset::Regular(
950 RegularBitOffset {
951 offset: 0,
952 },
953 ),
954 bit_size: 32,
955 array: None,
956 enumm: None,
957 },
958 ],
959 },
960 FieldSet {
961 name: "Ier",
962 extends: None,
963 description: Some(
964 "Interrupt Enable Register",
965 ),
966 bit_size: 32,
967 fields: &[
968 Field {
969 name: "rxpie",
970 description: Some(
971 "RXP Interrupt Enable",
972 ),
973 bit_offset: BitOffset::Regular(
974 RegularBitOffset {
975 offset: 0,
976 },
977 ),
978 bit_size: 1,
979 array: None,
980 enumm: None,
981 },
982 Field {
983 name: "txpie",
984 description: Some(
985 "TXP interrupt enable",
986 ),
987 bit_offset: BitOffset::Regular(
988 RegularBitOffset {
989 offset: 1,
990 },
991 ),
992 bit_size: 1,
993 array: None,
994 enumm: None,
995 },
996 Field {
997 name: "dxpie",
998 description: Some(
999 "DXP interrupt enabled",
1000 ),
1001 bit_offset: BitOffset::Regular(
1002 RegularBitOffset {
1003 offset: 2,
1004 },
1005 ),
1006 bit_size: 1,
1007 array: None,
1008 enumm: None,
1009 },
1010 Field {
1011 name: "eotie",
1012 description: Some(
1013 "EOT, SUSP and TXC interrupt enable",
1014 ),
1015 bit_offset: BitOffset::Regular(
1016 RegularBitOffset {
1017 offset: 3,
1018 },
1019 ),
1020 bit_size: 1,
1021 array: None,
1022 enumm: None,
1023 },
1024 Field {
1025 name: "txtfie",
1026 description: Some(
1027 "TXTFIE interrupt enable",
1028 ),
1029 bit_offset: BitOffset::Regular(
1030 RegularBitOffset {
1031 offset: 4,
1032 },
1033 ),
1034 bit_size: 1,
1035 array: None,
1036 enumm: None,
1037 },
1038 Field {
1039 name: "udrie",
1040 description: Some(
1041 "UDR interrupt enable",
1042 ),
1043 bit_offset: BitOffset::Regular(
1044 RegularBitOffset {
1045 offset: 5,
1046 },
1047 ),
1048 bit_size: 1,
1049 array: None,
1050 enumm: None,
1051 },
1052 Field {
1053 name: "ovrie",
1054 description: Some(
1055 "OVR interrupt enable",
1056 ),
1057 bit_offset: BitOffset::Regular(
1058 RegularBitOffset {
1059 offset: 6,
1060 },
1061 ),
1062 bit_size: 1,
1063 array: None,
1064 enumm: None,
1065 },
1066 Field {
1067 name: "crceie",
1068 description: Some(
1069 "CRC Interrupt enable",
1070 ),
1071 bit_offset: BitOffset::Regular(
1072 RegularBitOffset {
1073 offset: 7,
1074 },
1075 ),
1076 bit_size: 1,
1077 array: None,
1078 enumm: None,
1079 },
1080 Field {
1081 name: "tifreie",
1082 description: Some(
1083 "TIFRE interrupt enable",
1084 ),
1085 bit_offset: BitOffset::Regular(
1086 RegularBitOffset {
1087 offset: 8,
1088 },
1089 ),
1090 bit_size: 1,
1091 array: None,
1092 enumm: None,
1093 },
1094 Field {
1095 name: "modfie",
1096 description: Some(
1097 "Mode Fault interrupt enable",
1098 ),
1099 bit_offset: BitOffset::Regular(
1100 RegularBitOffset {
1101 offset: 9,
1102 },
1103 ),
1104 bit_size: 1,
1105 array: None,
1106 enumm: None,
1107 },
1108 ],
1109 },
1110 FieldSet {
1111 name: "Ifcr",
1112 extends: None,
1113 description: Some(
1114 "Interrupt/Status Flags Clear Register",
1115 ),
1116 bit_size: 32,
1117 fields: &[
1118 Field {
1119 name: "eotc",
1120 description: Some(
1121 "End Of Transfer flag clear",
1122 ),
1123 bit_offset: BitOffset::Regular(
1124 RegularBitOffset {
1125 offset: 3,
1126 },
1127 ),
1128 bit_size: 1,
1129 array: None,
1130 enumm: None,
1131 },
1132 Field {
1133 name: "txtfc",
1134 description: Some(
1135 "Transmission Transfer Filled flag clear",
1136 ),
1137 bit_offset: BitOffset::Regular(
1138 RegularBitOffset {
1139 offset: 4,
1140 },
1141 ),
1142 bit_size: 1,
1143 array: None,
1144 enumm: None,
1145 },
1146 Field {
1147 name: "udrc",
1148 description: Some(
1149 "Underrun flag clear",
1150 ),
1151 bit_offset: BitOffset::Regular(
1152 RegularBitOffset {
1153 offset: 5,
1154 },
1155 ),
1156 bit_size: 1,
1157 array: None,
1158 enumm: None,
1159 },
1160 Field {
1161 name: "ovrc",
1162 description: Some(
1163 "Overrun flag clear",
1164 ),
1165 bit_offset: BitOffset::Regular(
1166 RegularBitOffset {
1167 offset: 6,
1168 },
1169 ),
1170 bit_size: 1,
1171 array: None,
1172 enumm: None,
1173 },
1174 Field {
1175 name: "crcec",
1176 description: Some(
1177 "CRC Error flag clear",
1178 ),
1179 bit_offset: BitOffset::Regular(
1180 RegularBitOffset {
1181 offset: 7,
1182 },
1183 ),
1184 bit_size: 1,
1185 array: None,
1186 enumm: None,
1187 },
1188 Field {
1189 name: "tifrec",
1190 description: Some(
1191 "TI frame format error flag clear",
1192 ),
1193 bit_offset: BitOffset::Regular(
1194 RegularBitOffset {
1195 offset: 8,
1196 },
1197 ),
1198 bit_size: 1,
1199 array: None,
1200 enumm: None,
1201 },
1202 Field {
1203 name: "modfc",
1204 description: Some(
1205 "Mode Fault flag clear",
1206 ),
1207 bit_offset: BitOffset::Regular(
1208 RegularBitOffset {
1209 offset: 9,
1210 },
1211 ),
1212 bit_size: 1,
1213 array: None,
1214 enumm: None,
1215 },
1216 Field {
1217 name: "suspc",
1218 description: Some(
1219 "SUSPend flag clear",
1220 ),
1221 bit_offset: BitOffset::Regular(
1222 RegularBitOffset {
1223 offset: 11,
1224 },
1225 ),
1226 bit_size: 1,
1227 array: None,
1228 enumm: None,
1229 },
1230 ],
1231 },
1232 FieldSet {
1233 name: "Rxcrc",
1234 extends: None,
1235 description: Some(
1236 "Receiver CRC Register",
1237 ),
1238 bit_size: 32,
1239 fields: &[
1240 Field {
1241 name: "rxcrc",
1242 description: Some(
1243 "CRC register for receiver",
1244 ),
1245 bit_offset: BitOffset::Regular(
1246 RegularBitOffset {
1247 offset: 0,
1248 },
1249 ),
1250 bit_size: 32,
1251 array: None,
1252 enumm: None,
1253 },
1254 ],
1255 },
1256 FieldSet {
1257 name: "Sr",
1258 extends: None,
1259 description: Some(
1260 "Status Register",
1261 ),
1262 bit_size: 32,
1263 fields: &[
1264 Field {
1265 name: "rxp",
1266 description: Some(
1267 "Rx-Packet available",
1268 ),
1269 bit_offset: BitOffset::Regular(
1270 RegularBitOffset {
1271 offset: 0,
1272 },
1273 ),
1274 bit_size: 1,
1275 array: None,
1276 enumm: None,
1277 },
1278 Field {
1279 name: "txp",
1280 description: Some(
1281 "Tx-Packet space available",
1282 ),
1283 bit_offset: BitOffset::Regular(
1284 RegularBitOffset {
1285 offset: 1,
1286 },
1287 ),
1288 bit_size: 1,
1289 array: None,
1290 enumm: None,
1291 },
1292 Field {
1293 name: "dxp",
1294 description: Some(
1295 "Duplex Packet",
1296 ),
1297 bit_offset: BitOffset::Regular(
1298 RegularBitOffset {
1299 offset: 2,
1300 },
1301 ),
1302 bit_size: 1,
1303 array: None,
1304 enumm: None,
1305 },
1306 Field {
1307 name: "eot",
1308 description: Some(
1309 "End Of Transfer",
1310 ),
1311 bit_offset: BitOffset::Regular(
1312 RegularBitOffset {
1313 offset: 3,
1314 },
1315 ),
1316 bit_size: 1,
1317 array: None,
1318 enumm: None,
1319 },
1320 Field {
1321 name: "txtf",
1322 description: Some(
1323 "Transmission Transfer Filled",
1324 ),
1325 bit_offset: BitOffset::Regular(
1326 RegularBitOffset {
1327 offset: 4,
1328 },
1329 ),
1330 bit_size: 1,
1331 array: None,
1332 enumm: None,
1333 },
1334 Field {
1335 name: "udr",
1336 description: Some(
1337 "Underrun at slave transmission mode",
1338 ),
1339 bit_offset: BitOffset::Regular(
1340 RegularBitOffset {
1341 offset: 5,
1342 },
1343 ),
1344 bit_size: 1,
1345 array: None,
1346 enumm: None,
1347 },
1348 Field {
1349 name: "ovr",
1350 description: Some(
1351 "Overrun",
1352 ),
1353 bit_offset: BitOffset::Regular(
1354 RegularBitOffset {
1355 offset: 6,
1356 },
1357 ),
1358 bit_size: 1,
1359 array: None,
1360 enumm: None,
1361 },
1362 Field {
1363 name: "crce",
1364 description: Some(
1365 "CRC Error",
1366 ),
1367 bit_offset: BitOffset::Regular(
1368 RegularBitOffset {
1369 offset: 7,
1370 },
1371 ),
1372 bit_size: 1,
1373 array: None,
1374 enumm: None,
1375 },
1376 Field {
1377 name: "tifre",
1378 description: Some(
1379 "TI frame format error",
1380 ),
1381 bit_offset: BitOffset::Regular(
1382 RegularBitOffset {
1383 offset: 8,
1384 },
1385 ),
1386 bit_size: 1,
1387 array: None,
1388 enumm: None,
1389 },
1390 Field {
1391 name: "modf",
1392 description: Some(
1393 "Mode Fault",
1394 ),
1395 bit_offset: BitOffset::Regular(
1396 RegularBitOffset {
1397 offset: 9,
1398 },
1399 ),
1400 bit_size: 1,
1401 array: None,
1402 enumm: None,
1403 },
1404 Field {
1405 name: "susp",
1406 description: Some(
1407 "SUSPend",
1408 ),
1409 bit_offset: BitOffset::Regular(
1410 RegularBitOffset {
1411 offset: 11,
1412 },
1413 ),
1414 bit_size: 1,
1415 array: None,
1416 enumm: None,
1417 },
1418 Field {
1419 name: "txc",
1420 description: Some(
1421 "TxFIFO transmission complete",
1422 ),
1423 bit_offset: BitOffset::Regular(
1424 RegularBitOffset {
1425 offset: 12,
1426 },
1427 ),
1428 bit_size: 1,
1429 array: None,
1430 enumm: None,
1431 },
1432 Field {
1433 name: "rxplvl",
1434 description: Some(
1435 "RxFIFO Packing LeVeL",
1436 ),
1437 bit_offset: BitOffset::Regular(
1438 RegularBitOffset {
1439 offset: 13,
1440 },
1441 ),
1442 bit_size: 2,
1443 array: None,
1444 enumm: Some(
1445 "Rxplvl",
1446 ),
1447 },
1448 Field {
1449 name: "rxwne",
1450 description: Some(
1451 "RxFIFO Word Not Empty",
1452 ),
1453 bit_offset: BitOffset::Regular(
1454 RegularBitOffset {
1455 offset: 15,
1456 },
1457 ),
1458 bit_size: 1,
1459 array: None,
1460 enumm: Some(
1461 "Rxwne",
1462 ),
1463 },
1464 Field {
1465 name: "ctsize",
1466 description: Some(
1467 "Number of data frames remaining in current TSIZE session",
1468 ),
1469 bit_offset: BitOffset::Regular(
1470 RegularBitOffset {
1471 offset: 16,
1472 },
1473 ),
1474 bit_size: 16,
1475 array: None,
1476 enumm: None,
1477 },
1478 ],
1479 },
1480 FieldSet {
1481 name: "Txcrc",
1482 extends: None,
1483 description: Some(
1484 "Transmitter CRC Register",
1485 ),
1486 bit_size: 32,
1487 fields: &[
1488 Field {
1489 name: "txcrc",
1490 description: Some(
1491 "CRC register for transmitter",
1492 ),
1493 bit_offset: BitOffset::Regular(
1494 RegularBitOffset {
1495 offset: 0,
1496 },
1497 ),
1498 bit_size: 32,
1499 array: None,
1500 enumm: None,
1501 },
1502 ],
1503 },
1504 FieldSet {
1505 name: "Udrdr",
1506 extends: None,
1507 description: Some(
1508 "Underrun Data Register",
1509 ),
1510 bit_size: 32,
1511 fields: &[
1512 Field {
1513 name: "udrdr",
1514 description: Some(
1515 "Data at slave underrun condition",
1516 ),
1517 bit_offset: BitOffset::Regular(
1518 RegularBitOffset {
1519 offset: 0,
1520 },
1521 ),
1522 bit_size: 32,
1523 array: None,
1524 enumm: None,
1525 },
1526 ],
1527 },
1528 ],
1529 enums: &[
1530 Enum {
1531 name: "Comm",
1532 description: None,
1533 bit_size: 2,
1534 variants: &[
1535 EnumVariant {
1536 name: "FULL_DUPLEX",
1537 description: Some(
1538 "Full duplex",
1539 ),
1540 value: 0,
1541 },
1542 EnumVariant {
1543 name: "TRANSMITTER",
1544 description: Some(
1545 "Simplex transmitter only",
1546 ),
1547 value: 1,
1548 },
1549 EnumVariant {
1550 name: "RECEIVER",
1551 description: Some(
1552 "Simplex receiver only",
1553 ),
1554 value: 2,
1555 },
1556 EnumVariant {
1557 name: "HALF_DUPLEX",
1558 description: Some(
1559 "Half duplex",
1560 ),
1561 value: 3,
1562 },
1563 ],
1564 },
1565 Enum {
1566 name: "Cpha",
1567 description: None,
1568 bit_size: 1,
1569 variants: &[
1570 EnumVariant {
1571 name: "FIRST_EDGE",
1572 description: Some(
1573 "The first clock transition is the first data capture edge",
1574 ),
1575 value: 0,
1576 },
1577 EnumVariant {
1578 name: "SECOND_EDGE",
1579 description: Some(
1580 "The second clock transition is the first data capture edge",
1581 ),
1582 value: 1,
1583 },
1584 ],
1585 },
1586 Enum {
1587 name: "Cpol",
1588 description: None,
1589 bit_size: 1,
1590 variants: &[
1591 EnumVariant {
1592 name: "IDLE_LOW",
1593 description: Some(
1594 "CK to 0 when idle",
1595 ),
1596 value: 0,
1597 },
1598 EnumVariant {
1599 name: "IDLE_HIGH",
1600 description: Some(
1601 "CK to 1 when idle",
1602 ),
1603 value: 1,
1604 },
1605 ],
1606 },
1607 Enum {
1608 name: "Fthlv",
1609 description: None,
1610 bit_size: 4,
1611 variants: &[
1612 EnumVariant {
1613 name: "ONE_FRAME",
1614 description: Some(
1615 "1 frame",
1616 ),
1617 value: 0,
1618 },
1619 EnumVariant {
1620 name: "TWO_FRAMES",
1621 description: Some(
1622 "2 frames",
1623 ),
1624 value: 1,
1625 },
1626 EnumVariant {
1627 name: "THREE_FRAMES",
1628 description: Some(
1629 "3 frames",
1630 ),
1631 value: 2,
1632 },
1633 EnumVariant {
1634 name: "FOUR_FRAMES",
1635 description: Some(
1636 "4 frames",
1637 ),
1638 value: 3,
1639 },
1640 EnumVariant {
1641 name: "FIVE_FRAMES",
1642 description: Some(
1643 "5 frames",
1644 ),
1645 value: 4,
1646 },
1647 EnumVariant {
1648 name: "SIX_FRAMES",
1649 description: Some(
1650 "6 frames",
1651 ),
1652 value: 5,
1653 },
1654 EnumVariant {
1655 name: "SEVEN_FRAMES",
1656 description: Some(
1657 "7 frames",
1658 ),
1659 value: 6,
1660 },
1661 EnumVariant {
1662 name: "EIGHT_FRAMES",
1663 description: Some(
1664 "8 frames",
1665 ),
1666 value: 7,
1667 },
1668 EnumVariant {
1669 name: "NINE_FRAMES",
1670 description: Some(
1671 "9 frames",
1672 ),
1673 value: 8,
1674 },
1675 EnumVariant {
1676 name: "TEN_FRAMES",
1677 description: Some(
1678 "10 frames",
1679 ),
1680 value: 9,
1681 },
1682 EnumVariant {
1683 name: "ELEVEN_FRAMES",
1684 description: Some(
1685 "11 frames",
1686 ),
1687 value: 10,
1688 },
1689 EnumVariant {
1690 name: "TWELVE_FRAMES",
1691 description: Some(
1692 "12 frames",
1693 ),
1694 value: 11,
1695 },
1696 EnumVariant {
1697 name: "THIRTEEN_FRAMES",
1698 description: Some(
1699 "13 frames",
1700 ),
1701 value: 12,
1702 },
1703 EnumVariant {
1704 name: "FOURTEEN_FRAMES",
1705 description: Some(
1706 "14 frames",
1707 ),
1708 value: 13,
1709 },
1710 EnumVariant {
1711 name: "FIFTEEN_FRAMES",
1712 description: Some(
1713 "15 frames",
1714 ),
1715 value: 14,
1716 },
1717 EnumVariant {
1718 name: "SIXTEEN_FRAMES",
1719 description: Some(
1720 "16 frames",
1721 ),
1722 value: 15,
1723 },
1724 ],
1725 },
1726 Enum {
1727 name: "Hddir",
1728 description: None,
1729 bit_size: 1,
1730 variants: &[
1731 EnumVariant {
1732 name: "RECEIVER",
1733 description: Some(
1734 "Receiver in half duplex mode",
1735 ),
1736 value: 0,
1737 },
1738 EnumVariant {
1739 name: "TRANSMITTER",
1740 description: Some(
1741 "Transmitter in half duplex mode",
1742 ),
1743 value: 1,
1744 },
1745 ],
1746 },
1747 Enum {
1748 name: "Lsbfirst",
1749 description: None,
1750 bit_size: 1,
1751 variants: &[
1752 EnumVariant {
1753 name: "MSBFIRST",
1754 description: Some(
1755 "Data is transmitted/received with the MSB first",
1756 ),
1757 value: 0,
1758 },
1759 EnumVariant {
1760 name: "LSBFIRST",
1761 description: Some(
1762 "Data is transmitted/received with the LSB first",
1763 ),
1764 value: 1,
1765 },
1766 ],
1767 },
1768 Enum {
1769 name: "Master",
1770 description: None,
1771 bit_size: 1,
1772 variants: &[
1773 EnumVariant {
1774 name: "SLAVE",
1775 description: Some(
1776 "Slave configuration",
1777 ),
1778 value: 0,
1779 },
1780 EnumVariant {
1781 name: "MASTER",
1782 description: Some(
1783 "Master configuration",
1784 ),
1785 value: 1,
1786 },
1787 ],
1788 },
1789 Enum {
1790 name: "Mbr",
1791 description: None,
1792 bit_size: 3,
1793 variants: &[
1794 EnumVariant {
1795 name: "DIV2",
1796 description: Some(
1797 "f_spi_ker_ck / 2",
1798 ),
1799 value: 0,
1800 },
1801 EnumVariant {
1802 name: "DIV4",
1803 description: Some(
1804 "f_spi_ker_ck / 4",
1805 ),
1806 value: 1,
1807 },
1808 EnumVariant {
1809 name: "DIV8",
1810 description: Some(
1811 "f_spi_ker_ck / 8",
1812 ),
1813 value: 2,
1814 },
1815 EnumVariant {
1816 name: "DIV16",
1817 description: Some(
1818 "f_spi_ker_ck / 16",
1819 ),
1820 value: 3,
1821 },
1822 EnumVariant {
1823 name: "DIV32",
1824 description: Some(
1825 "f_spi_ker_ck / 32",
1826 ),
1827 value: 4,
1828 },
1829 EnumVariant {
1830 name: "DIV64",
1831 description: Some(
1832 "f_spi_ker_ck / 64",
1833 ),
1834 value: 5,
1835 },
1836 EnumVariant {
1837 name: "DIV128",
1838 description: Some(
1839 "f_spi_ker_ck / 128",
1840 ),
1841 value: 6,
1842 },
1843 EnumVariant {
1844 name: "DIV256",
1845 description: Some(
1846 "f_spi_ker_ck / 256",
1847 ),
1848 value: 7,
1849 },
1850 ],
1851 },
1852 Enum {
1853 name: "Rcrcini",
1854 description: None,
1855 bit_size: 1,
1856 variants: &[
1857 EnumVariant {
1858 name: "ALL_ZEROS",
1859 description: Some(
1860 "All zeros RX CRC initialization pattern",
1861 ),
1862 value: 0,
1863 },
1864 EnumVariant {
1865 name: "ALL_ONES",
1866 description: Some(
1867 "All ones RX CRC initialization pattern",
1868 ),
1869 value: 1,
1870 },
1871 ],
1872 },
1873 Enum {
1874 name: "Rdiom",
1875 description: None,
1876 bit_size: 1,
1877 variants: &[
1878 EnumVariant {
1879 name: "PERMANENTLY_ACTIVE",
1880 description: Some(
1881 "RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect)",
1882 ),
1883 value: 0,
1884 },
1885 EnumVariant {
1886 name: "FROM_INPUT",
1887 description: Some(
1888 "RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect)",
1889 ),
1890 value: 1,
1891 },
1892 ],
1893 },
1894 Enum {
1895 name: "Rdiop",
1896 description: None,
1897 bit_size: 1,
1898 variants: &[
1899 EnumVariant {
1900 name: "READY_HIGH",
1901 description: Some(
1902 "high level of the signal means the slave is ready for communication",
1903 ),
1904 value: 0,
1905 },
1906 EnumVariant {
1907 name: "READY_LOW",
1908 description: Some(
1909 "low level of the signal means the slave is ready for communication",
1910 ),
1911 value: 1,
1912 },
1913 ],
1914 },
1915 Enum {
1916 name: "Rxplvl",
1917 description: None,
1918 bit_size: 2,
1919 variants: &[
1920 EnumVariant {
1921 name: "ZERO_FRAMES",
1922 description: Some(
1923 "Zero frames beyond packing ratio available",
1924 ),
1925 value: 0,
1926 },
1927 EnumVariant {
1928 name: "ONE_FRAME",
1929 description: Some(
1930 "One frame beyond packing ratio available",
1931 ),
1932 value: 1,
1933 },
1934 EnumVariant {
1935 name: "TWO_FRAMES",
1936 description: Some(
1937 "Two frame beyond packing ratio available",
1938 ),
1939 value: 2,
1940 },
1941 EnumVariant {
1942 name: "THREE_FRAMES",
1943 description: Some(
1944 "Three frame beyond packing ratio available",
1945 ),
1946 value: 3,
1947 },
1948 ],
1949 },
1950 Enum {
1951 name: "Rxwne",
1952 description: None,
1953 bit_size: 1,
1954 variants: &[
1955 EnumVariant {
1956 name: "LESS_THAN32",
1957 description: Some(
1958 "Less than 32-bit data frame received",
1959 ),
1960 value: 0,
1961 },
1962 EnumVariant {
1963 name: "AT_LEAST32",
1964 description: Some(
1965 "At least 32-bit data frame received",
1966 ),
1967 value: 1,
1968 },
1969 ],
1970 },
1971 Enum {
1972 name: "Sp",
1973 description: None,
1974 bit_size: 3,
1975 variants: &[
1976 EnumVariant {
1977 name: "MOTOROLA",
1978 description: Some(
1979 "Motorola SPI protocol",
1980 ),
1981 value: 0,
1982 },
1983 EnumVariant {
1984 name: "TI",
1985 description: Some(
1986 "TI SPI protocol",
1987 ),
1988 value: 1,
1989 },
1990 ],
1991 },
1992 Enum {
1993 name: "Ssiop",
1994 description: None,
1995 bit_size: 1,
1996 variants: &[
1997 EnumVariant {
1998 name: "ACTIVE_LOW",
1999 description: Some(
2000 "Low level is active for SS signal",
2001 ),
2002 value: 0,
2003 },
2004 EnumVariant {
2005 name: "ACTIVE_HIGH",
2006 description: Some(
2007 "High level is active for SS signal",
2008 ),
2009 value: 1,
2010 },
2011 ],
2012 },
2013 Enum {
2014 name: "Ssom",
2015 description: None,
2016 bit_size: 1,
2017 variants: &[
2018 EnumVariant {
2019 name: "ASSERTED",
2020 description: Some(
2021 "SS is asserted until data transfer complete",
2022 ),
2023 value: 0,
2024 },
2025 EnumVariant {
2026 name: "NOT_ASSERTED",
2027 description: Some(
2028 "Data frames interleaved with SS not asserted during MIDI",
2029 ),
2030 value: 1,
2031 },
2032 ],
2033 },
2034 Enum {
2035 name: "Tcrcini",
2036 description: None,
2037 bit_size: 1,
2038 variants: &[
2039 EnumVariant {
2040 name: "ALL_ZEROS",
2041 description: Some(
2042 "All zeros TX CRC initialization pattern",
2043 ),
2044 value: 0,
2045 },
2046 EnumVariant {
2047 name: "ALL_ONES",
2048 description: Some(
2049 "All ones TX CRC initialization pattern",
2050 ),
2051 value: 1,
2052 },
2053 ],
2054 },
2055 Enum {
2056 name: "Trigpol",
2057 description: None,
2058 bit_size: 1,
2059 variants: &[
2060 EnumVariant {
2061 name: "RISING_EDGE",
2062 description: Some(
2063 "trigger is active on raising edge",
2064 ),
2065 value: 0,
2066 },
2067 EnumVariant {
2068 name: "FALLING_EDGE",
2069 description: Some(
2070 "trigger is active on falling edge",
2071 ),
2072 value: 1,
2073 },
2074 ],
2075 },
2076 Enum {
2077 name: "Udrcfg",
2078 description: None,
2079 bit_size: 2,
2080 variants: &[
2081 EnumVariant {
2082 name: "CONSTANT",
2083 description: Some(
2084 "Slave sends a constant underrun pattern",
2085 ),
2086 value: 0,
2087 },
2088 EnumVariant {
2089 name: "REPEAT_RECEIVED",
2090 description: Some(
2091 "Slave repeats last received data frame from master",
2092 ),
2093 value: 1,
2094 },
2095 EnumVariant {
2096 name: "REPEAT_TRANSMITTED",
2097 description: Some(
2098 "Slave repeats last transmitted data frame",
2099 ),
2100 value: 2,
2101 },
2102 ],
2103 },
2104 ],
2105};
2106