1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[Block {
5 name: "Syscfg",
6 extends: None,
7 description: Some("System configuration controller"),
8 items: &[
9 BlockItem {
10 name: "seccfgr",
11 description: Some("SYSCFG secure configuration\r register"),
12 array: None,
13 byte_offset: 0x0,
14 inner: BlockItemInner::Register(Register {
15 access: Access::ReadWrite,
16 bit_size: 32,
17 fieldset: Some("Seccfgr"),
18 }),
19 },
20 BlockItem {
21 name: "cfgr1",
22 description: Some("configuration register 1"),
23 array: None,
24 byte_offset: 0x4,
25 inner: BlockItemInner::Register(Register {
26 access: Access::ReadWrite,
27 bit_size: 32,
28 fieldset: Some("Cfgr1"),
29 }),
30 },
31 BlockItem {
32 name: "fpuimr",
33 description: Some("FPU interrupt mask register"),
34 array: None,
35 byte_offset: 0x8,
36 inner: BlockItemInner::Register(Register {
37 access: Access::ReadWrite,
38 bit_size: 32,
39 fieldset: Some("Fpuimr"),
40 }),
41 },
42 BlockItem {
43 name: "cnslckr",
44 description: Some("SYSCFG CPU non-secure lock\r register"),
45 array: None,
46 byte_offset: 0xc,
47 inner: BlockItemInner::Register(Register {
48 access: Access::ReadWrite,
49 bit_size: 32,
50 fieldset: Some("Cnslckr"),
51 }),
52 },
53 BlockItem {
54 name: "cslockr",
55 description: Some("SYSCFG CPU secure lock\r register"),
56 array: None,
57 byte_offset: 0x10,
58 inner: BlockItemInner::Register(Register {
59 access: Access::ReadWrite,
60 bit_size: 32,
61 fieldset: Some("Cslockr"),
62 }),
63 },
64 BlockItem {
65 name: "cfgr2",
66 description: Some("configuration register 2"),
67 array: None,
68 byte_offset: 0x14,
69 inner: BlockItemInner::Register(Register {
70 access: Access::ReadWrite,
71 bit_size: 32,
72 fieldset: Some("Cfgr2"),
73 }),
74 },
75 BlockItem {
76 name: "mesr",
77 description: Some("memory erase status register"),
78 array: None,
79 byte_offset: 0x18,
80 inner: BlockItemInner::Register(Register {
81 access: Access::ReadWrite,
82 bit_size: 32,
83 fieldset: Some("Mesr"),
84 }),
85 },
86 BlockItem {
87 name: "cccsr",
88 description: Some("compensation cell control/status register"),
89 array: None,
90 byte_offset: 0x1c,
91 inner: BlockItemInner::Register(Register {
92 access: Access::ReadWrite,
93 bit_size: 32,
94 fieldset: Some("Cccsr"),
95 }),
96 },
97 BlockItem {
98 name: "ccvr",
99 description: Some("compensation cell value register"),
100 array: None,
101 byte_offset: 0x20,
102 inner: BlockItemInner::Register(Register {
103 access: Access::Read,
104 bit_size: 32,
105 fieldset: Some("Ccvr"),
106 }),
107 },
108 BlockItem {
109 name: "cccr",
110 description: Some("compensation cell code register"),
111 array: None,
112 byte_offset: 0x24,
113 inner: BlockItemInner::Register(Register {
114 access: Access::ReadWrite,
115 bit_size: 32,
116 fieldset: Some("Cccr"),
117 }),
118 },
119 BlockItem {
120 name: "rsscmdr",
121 description: Some("RSS command register"),
122 array: None,
123 byte_offset: 0x2c,
124 inner: BlockItemInner::Register(Register {
125 access: Access::ReadWrite,
126 bit_size: 32,
127 fieldset: Some("Rsscmdr"),
128 }),
129 },
130 BlockItem {
131 name: "ucpdr",
132 description: Some("USB Type C and Power Delivery register"),
133 array: None,
134 byte_offset: 0x70,
135 inner: BlockItemInner::Register(Register {
136 access: Access::ReadWrite,
137 bit_size: 32,
138 fieldset: Some("Ucpdr"),
139 }),
140 },
141 BlockItem {
142 name: "otghsphycr",
143 description: Some("OTG_HS PHY register"),
144 array: None,
145 byte_offset: 0x74,
146 inner: BlockItemInner::Register(Register {
147 access: Access::ReadWrite,
148 bit_size: 32,
149 fieldset: Some("Otghsphycr"),
150 }),
151 },
152 BlockItem {
153 name: "otghsphytuner2",
154 description: Some("OTG_HS PHY tune register 2"),
155 array: None,
156 byte_offset: 0x7c,
157 inner: BlockItemInner::Register(Register {
158 access: Access::ReadWrite,
159 bit_size: 32,
160 fieldset: Some("Otghsphytuner2"),
161 }),
162 },
163 ],
164 }],
165 fieldsets: &[
166 FieldSet {
167 name: "Cccr",
168 extends: None,
169 description: Some("compensation cell code register"),
170 bit_size: 32,
171 fields: &[
172 Field {
173 name: "ncc1",
174 description: Some("NCC1"),
175 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
176 bit_size: 4,
177 array: None,
178 enumm: None,
179 },
180 Field {
181 name: "pcc1",
182 description: Some("PCC1"),
183 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
184 bit_size: 4,
185 array: None,
186 enumm: None,
187 },
188 Field {
189 name: "ncc2",
190 description: Some("NCC2"),
191 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
192 bit_size: 4,
193 array: None,
194 enumm: None,
195 },
196 Field {
197 name: "pcc2",
198 description: Some("PCC2"),
199 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
200 bit_size: 4,
201 array: None,
202 enumm: None,
203 },
204 ],
205 },
206 FieldSet {
207 name: "Cccsr",
208 extends: None,
209 description: Some("compensation cell control/status register"),
210 bit_size: 32,
211 fields: &[
212 Field {
213 name: "en1",
214 description: Some("EN1"),
215 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
216 bit_size: 1,
217 array: None,
218 enumm: None,
219 },
220 Field {
221 name: "cs1",
222 description: Some("CS1"),
223 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
224 bit_size: 1,
225 array: None,
226 enumm: None,
227 },
228 Field {
229 name: "en2",
230 description: Some("EN2"),
231 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
232 bit_size: 1,
233 array: None,
234 enumm: None,
235 },
236 Field {
237 name: "cs2",
238 description: Some("CS2"),
239 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
240 bit_size: 1,
241 array: None,
242 enumm: None,
243 },
244 Field {
245 name: "rdy1",
246 description: Some("RDY1"),
247 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
248 bit_size: 1,
249 array: None,
250 enumm: None,
251 },
252 Field {
253 name: "rdy2",
254 description: Some("RDY2"),
255 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
256 bit_size: 1,
257 array: None,
258 enumm: None,
259 },
260 ],
261 },
262 FieldSet {
263 name: "Ccvr",
264 extends: None,
265 description: Some("compensation cell value register"),
266 bit_size: 32,
267 fields: &[
268 Field {
269 name: "ncv1",
270 description: Some("NCV1"),
271 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
272 bit_size: 4,
273 array: None,
274 enumm: None,
275 },
276 Field {
277 name: "pcv1",
278 description: Some("PCV1"),
279 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
280 bit_size: 4,
281 array: None,
282 enumm: None,
283 },
284 Field {
285 name: "ncv2",
286 description: Some("NCV2"),
287 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
288 bit_size: 4,
289 array: None,
290 enumm: None,
291 },
292 Field {
293 name: "pcv2",
294 description: Some("PCV2"),
295 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
296 bit_size: 4,
297 array: None,
298 enumm: None,
299 },
300 ],
301 },
302 FieldSet {
303 name: "Cfgr1",
304 extends: None,
305 description: Some("configuration register 1"),
306 bit_size: 32,
307 fields: &[
308 Field {
309 name: "boosten",
310 description: Some("I/O analog switch voltage booster\r enable"),
311 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
312 bit_size: 1,
313 array: None,
314 enumm: None,
315 },
316 Field {
317 name: "anaswvdd",
318 description: Some("GPIO analog switch control voltage\r selection"),
319 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
320 bit_size: 1,
321 array: None,
322 enumm: None,
323 },
324 Field {
325 name: "pb6_fmp",
326 description: Some("PB6_FMP"),
327 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
328 bit_size: 1,
329 array: None,
330 enumm: None,
331 },
332 Field {
333 name: "pb7_fmp",
334 description: Some("PB7_FMP"),
335 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 17 }),
336 bit_size: 1,
337 array: None,
338 enumm: None,
339 },
340 Field {
341 name: "pb8_fmp",
342 description: Some("PB8_FMP"),
343 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }),
344 bit_size: 1,
345 array: None,
346 enumm: None,
347 },
348 Field {
349 name: "pb9_fmp",
350 description: Some("PB9_FMP"),
351 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 19 }),
352 bit_size: 1,
353 array: None,
354 enumm: None,
355 },
356 ],
357 },
358 FieldSet {
359 name: "Cfgr2",
360 extends: None,
361 description: Some("configuration register 2"),
362 bit_size: 32,
363 fields: &[
364 Field {
365 name: "cll",
366 description: Some("LOCKUP (hardfault) output enable\r bit"),
367 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
368 bit_size: 1,
369 array: None,
370 enumm: None,
371 },
372 Field {
373 name: "spl",
374 description: Some("SRAM ECC lock bit"),
375 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
376 bit_size: 1,
377 array: None,
378 enumm: None,
379 },
380 Field {
381 name: "pvdl",
382 description: Some("PVD lock enable bit"),
383 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
384 bit_size: 1,
385 array: None,
386 enumm: None,
387 },
388 Field {
389 name: "eccl",
390 description: Some("ECC Lock"),
391 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
392 bit_size: 1,
393 array: None,
394 enumm: None,
395 },
396 ],
397 },
398 FieldSet {
399 name: "Cnslckr",
400 extends: None,
401 description: Some("SYSCFG CPU non-secure lock\r register"),
402 bit_size: 32,
403 fields: &[
404 Field {
405 name: "locknsvtor",
406 description: Some("VTOR_NS register lock"),
407 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
408 bit_size: 1,
409 array: None,
410 enumm: None,
411 },
412 Field {
413 name: "locknsmpu",
414 description: Some("Non-secure MPU registers\r lock"),
415 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
416 bit_size: 1,
417 array: None,
418 enumm: None,
419 },
420 ],
421 },
422 FieldSet {
423 name: "Cslockr",
424 extends: None,
425 description: Some("SYSCFG CPU secure lock\r register"),
426 bit_size: 32,
427 fields: &[
428 Field {
429 name: "locksvtaircr",
430 description: Some("LOCKSVTAIRCR"),
431 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
432 bit_size: 1,
433 array: None,
434 enumm: None,
435 },
436 Field {
437 name: "locksmpu",
438 description: Some("LOCKSMPU"),
439 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
440 bit_size: 1,
441 array: None,
442 enumm: None,
443 },
444 Field {
445 name: "locksau",
446 description: Some("LOCKSAU"),
447 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
448 bit_size: 1,
449 array: None,
450 enumm: None,
451 },
452 ],
453 },
454 FieldSet {
455 name: "Fpuimr",
456 extends: None,
457 description: Some("FPU interrupt mask register"),
458 bit_size: 32,
459 fields: &[Field {
460 name: "fpu_ie",
461 description: Some("Floating point unit interrupts enable\r bits"),
462 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
463 bit_size: 6,
464 array: None,
465 enumm: None,
466 }],
467 },
468 FieldSet {
469 name: "Mesr",
470 extends: None,
471 description: Some("memory erase status register"),
472 bit_size: 32,
473 fields: &[
474 Field {
475 name: "mclr",
476 description: Some("MCLR"),
477 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
478 bit_size: 1,
479 array: None,
480 enumm: None,
481 },
482 Field {
483 name: "ipmee",
484 description: Some("IPMEE"),
485 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
486 bit_size: 1,
487 array: None,
488 enumm: None,
489 },
490 ],
491 },
492 FieldSet {
493 name: "Otghsphycr",
494 extends: None,
495 description: Some("OTG_HS PHY register"),
496 bit_size: 32,
497 fields: &[
498 Field {
499 name: "en",
500 description: Some("PHY Enable"),
501 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
502 bit_size: 1,
503 array: None,
504 enumm: None,
505 },
506 Field {
507 name: "pdctrl",
508 description: Some("Common block power-down control"),
509 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
510 bit_size: 1,
511 array: None,
512 enumm: None,
513 },
514 Field {
515 name: "clksel",
516 description: Some("Reference clock frequency selection"),
517 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
518 bit_size: 4,
519 array: None,
520 enumm: Some("Usbrefcksel"),
521 },
522 ],
523 },
524 FieldSet {
525 name: "Otghsphytuner2",
526 extends: None,
527 description: Some("OTG_HS tune register 2"),
528 bit_size: 32,
529 fields: &[
530 Field {
531 name: "compdistune",
532 description: Some("Disconnect threshold adjustment"),
533 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
534 bit_size: 3,
535 array: None,
536 enumm: None,
537 },
538 Field {
539 name: "sqrxtune",
540 description: Some("Squelch threshold adjustment"),
541 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
542 bit_size: 3,
543 array: None,
544 enumm: None,
545 },
546 Field {
547 name: "txpreempamptune",
548 description: Some("HS transmitter preemphasis current control"),
549 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 13 }),
550 bit_size: 2,
551 array: None,
552 enumm: None,
553 },
554 ],
555 },
556 FieldSet {
557 name: "Rsscmdr",
558 extends: None,
559 description: Some("RSS command register"),
560 bit_size: 32,
561 fields: &[Field {
562 name: "rsscmd",
563 description: Some("RSS commands"),
564 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
565 bit_size: 16,
566 array: None,
567 enumm: None,
568 }],
569 },
570 FieldSet {
571 name: "Seccfgr",
572 extends: None,
573 description: Some("SYSCFG secure configuration\r register"),
574 bit_size: 32,
575 fields: &[
576 Field {
577 name: "syscfgsec",
578 description: Some("SYSCFG clock control\r security"),
579 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
580 bit_size: 1,
581 array: None,
582 enumm: None,
583 },
584 Field {
585 name: "classbsec",
586 description: Some("CLASSBSEC"),
587 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
588 bit_size: 1,
589 array: None,
590 enumm: None,
591 },
592 Field {
593 name: "fpusec",
594 description: Some("FPUSEC"),
595 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
596 bit_size: 1,
597 array: None,
598 enumm: None,
599 },
600 ],
601 },
602 FieldSet {
603 name: "Ucpdr",
604 extends: None,
605 description: Some("USB Type C and Power Delivery register"),
606 bit_size: 32,
607 fields: &[
608 Field {
609 name: "cc1enrxfilter",
610 description: Some("CC1ENRXFILTER"),
611 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
612 bit_size: 1,
613 array: None,
614 enumm: None,
615 },
616 Field {
617 name: "cc2enrxfilter",
618 description: Some("CC2ENRXFILTER"),
619 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
620 bit_size: 1,
621 array: None,
622 enumm: None,
623 },
624 ],
625 },
626 ],
627 enums: &[Enum {
628 name: "Usbrefcksel",
629 description: None,
630 bit_size: 4,
631 variants: &[
632 EnumVariant {
633 name: "MHZ16",
634 description: Some("The kernel clock frequency provided to the OTG_HS PHY is 16 MHz."),
635 value: 3,
636 },
637 EnumVariant {
638 name: "MHZ19_2",
639 description: Some("The kernel clock frequency provided to the OTG_HS PHY is 19.2 MHz."),
640 value: 8,
641 },
642 EnumVariant {
643 name: "MHZ20",
644 description: Some("The kernel clock frequency provided to the OTG_HS PHY is 20MHz."),
645 value: 9,
646 },
647 EnumVariant {
648 name: "MHZ24",
649 description: Some(
650 "The kernel clock frequency provided to the OTG_HS PHY is 24 MHz (default after reset).",
651 ),
652 value: 10,
653 },
654 EnumVariant {
655 name: "MHZ32",
656 description: Some("The kernel clock frequency provided to the OTG_HS PHY is 32 MHz."),
657 value: 11,
658 },
659 EnumVariant {
660 name: "MHZ26",
661 description: Some("The kernel clock frequency provided to the OTG_HS PHY is 26 MHz."),
662 value: 14,
663 },
664 ],
665 }],
666};
667